Compilation method, electronic device, and storage medium

Abstract

The present disclosure provides a compilation method, an electronic device, and a storage medium. The compilation method includes: obtaining a code skeleton template for processing a tensor object, wherein the code skeleton template includes a first container and at least one second container; inserting at least one tensor intermediate representation instruction for processing the tensor object into the code skeleton template to obtain a first code; converting the first code into a second code composed of machine intermediate representation instructions; and converting the second code into an assembly code composed of assembly instructions. The compilation method also includes: determining the indentation values ​​corresponding to the first container and the at least one second container respectively based on the parent-child relationship between the first container and the at least one second container, wherein the indentation values ​​are assigned to the assembly code during the conversion process from the first code to the assembly code. The present disclosure can realize automatic indentation of the assembly code format and improve the structural clarity and readability of the assembly code.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of processor technology, and more particularly, to a compilation method, an electronic device, and a storage medium. Background Art

[0002] With the development of new computing architectures, high-performance code generation technology for operators has become an important means of improving computing efficiency. In particular, in application scenarios involving Tensor Cores and related fused operators, higher requirements are placed on the performance, readability, and maintainability of the underlying assembly code. Summary of the Invention

[0003] Embodiments of the present disclosure provide a compilation method, an electronic device, and a storage medium.

[0004] According to a first aspect of the present disclosure, a compilation method is provided, comprising: obtaining a code skeleton template for processing a tensor object, wherein the code skeleton template comprises a first container and at least one second container; inserting at least one tensor intermediate representation instruction for processing the tensor object into the code skeleton template to obtain a first code; converting the first code into a second code composed of machine intermediate representation instructions; and converting the second code into an assembly code composed of assembly instructions, wherein the machine intermediate representation instructions and the assembly instructions have a one-to-one mapping relationship; the compilation method further comprises: determining the indentation values ​​corresponding to the first container and the at least one second container respectively according to the parent-child relationship between the first container and the at least one second container; wherein the indentation values ​​are assigned to the assembly code during the conversion process from the first code to the assembly code.

[0005] According to some embodiments of the present disclosure, at least one tensor intermediate representation instruction includes a structured control flow instruction, which is used to describe a control instruction flow of a nested loop or a conditional judgment. At least one tensor intermediate representation instruction for processing a tensor object is inserted into a code skeleton template to obtain a first code, including: inserting at least one tensor intermediate representation instruction into a first container; and in response to the tensor intermediate representation instruction in the first container including a first structured control flow instruction, determining a first target container for the first structured control flow instruction from at least one second container, and inserting the tensor intermediate representation instruction corresponding to the first structured control flow instruction into the first target container, wherein each structured control flow instruction in the first container corresponds to a second container in the code skeleton template.

[0006] According to some embodiments of the present disclosure, the above-mentioned compilation method also includes: in response to the tensor intermediate representation instruction in the first target container including the second structured control flow instruction, inserting the tensor intermediate representation instruction corresponding to the second structured control flow instruction into the first target container.

[0007] According to some embodiments of the present disclosure, the above-mentioned compilation method further includes: determining a tensor intermediate representation instruction corresponding to the first structured control flow instruction based on the control flow semantics of the first structured control flow instruction.

[0008] In some embodiments according to the present disclosure, tensor intermediate representation instructions included in the same container have the same indentation value, and the indentation value of the parent container is smaller than the indentation value of the child container.

[0009] According to some embodiments of the present disclosure, based on the parent-child relationship between a first container and at least one second container, determining the indentation values ​​corresponding to each of the first container and the at least one second container includes: in response to the tensor intermediate representation instruction in the first container including a first structured control flow instruction, and a first target container in the at least one second container is used to insert the tensor intermediate representation instruction corresponding to the first structured control flow instruction, determining that the first target container is a child container of the first container, wherein the tensor intermediate representation instruction included in the first container is set with a first indentation value, the tensor intermediate representation instruction included in the first target container is set with a second indentation value, and the second indentation value is greater than the first indentation value.

[0010] According to some embodiments of the present disclosure, the above-mentioned compilation method also includes: in response to the tensor intermediate representation instruction in the first target container including a second structured control flow instruction and a tensor intermediate representation instruction corresponding to the second structured control flow instruction, updating the second indentation value of the tensor intermediate representation instruction corresponding to the second structured control flow instruction to a third indentation value, wherein the third indentation value is greater than the second indentation value.

[0011] According to some embodiments of the present disclosure, converting a first code into a second code composed of machine intermediate representation instructions includes: performing an equivalent transformation on each tensor intermediate representation instruction in the first code to generate a corresponding machine intermediate representation instruction, wherein the indentation value of the machine intermediate representation instruction is equal to the indentation value of the corresponding tensor intermediate representation instruction.

[0012] According to some embodiments of the present disclosure, converting the second code into assembly code includes: printing machine intermediate representation instructions according to the instruction sequence of the machine intermediate representation instructions and according to the indentation values ​​of the machine intermediate representation instructions to obtain the assembly code.

[0013] According to a second aspect of the present disclosure, an electronic device is also provided, which includes at least one processor and at least one non-volatile memory, wherein the at least one non-volatile memory stores program code, and when the program code is executed by the at least one processor, the at least one processor performs the steps of the compilation method according to the present disclosure.

[0014] According to a third aspect of the present disclosure, a non-transitory computer-readable storage medium is further provided, on which computer-readable instructions are stored. When the computer-readable instructions are executed by a processor, the processor executes the steps of the compilation method according to the present disclosure.

[0015] The compilation method, electronic device, and storage medium provided by some embodiments of the present disclosure can structure the first code and improve the structural clarity and readability of the first code by writing the first code in a manner of inserting tensor intermediate representation instructions into the container included in the code skeleton template. At the same time, according to the parent-child relationship between the first container and the second container in the first code, automatic indentation of the assembly code can be achieved when converting into assembly code, thereby improving the readability and structural clarity of the assembly code and reflecting the actual execution logic and dependencies of the program (or instruction). In addition, the code skeleton template provided by the present disclosure can cover multiple types of operators or tensor objects. By inserting the tensor intermediate representation instructions for a certain operator into the code skeleton template, the operator can be designed and developed, thereby improving development efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 A schematic flowchart of a compilation method according to at least one embodiment of the present disclosure is shown;

[0018] Figure 2 A schematic diagram of a code skeleton template according to at least one embodiment of the present disclosure is shown;

[0019] Figure 3 A schematic diagram illustrating compiling a first code into an assembly code according to at least one embodiment of the present disclosure is shown;

[0020] Figure 4 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is shown;

[0021] Figure 5A schematic block diagram of another electronic device according to at least one embodiment of the present disclosure is shown;

[0022] Figure 6 A schematic block diagram of a storage medium according to at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0024] In addition, as shown in the present disclosure and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not specifically refer to the singular, but may also include the plural. "First", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects, that is, it can be understood as "at least including but not limited to". Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0025] Flowcharts are used herein to illustrate the steps of the methods according to embodiments of the present disclosure. It should be understood that the preceding or following steps do not necessarily need to be performed in exact order. Instead, the various steps may be performed in reverse order or simultaneously. Furthermore, other operations may be added to these processes.

[0026] It is understood that the professional terms, nouns, etc. used herein have meanings well known to those skilled in the art. To facilitate understanding of the disclosed solutions, the following explanations of terms that may be used in at least some embodiments of the present disclosure are provided.

[0027] A tensor is a multidimensional array data structure. In deep learning, the dimensions of input data, intermediate data processed during the deep learning process, and output data are flexible and not exact. Therefore, a flexible data format is needed to describe various types of data, which gave rise to the concept of tensors. In deep learning, all data to be calculated is stored and exists in the form of tensors. If the data is not in tensor form, it must first be converted into a tensor data structure.

[0028] Artificial Intelligence (AI) operators refer to the tensor calculations performed in the AI ​​framework. These calculations are called operators, which are core components of the AI ​​framework. As an example, it can be the attention operator in a neural network. Its calculation process involves the calculation operations of query tensor (QTensor), key tensor (K Tensor), and value tensor (V Tensor).

[0029] With the development of new computing architectures, high-performance code generation technology for operators has become an important means of improving computing efficiency. In particular, in application scenarios involving Tensor Cores and related fused operators, higher requirements are placed on the performance, readability, and maintainability of the underlying assembly code.

[0030] In related technologies, there are already hardware-architecture-oriented operator development tools that adopt a code generation-based technology route and aim to generate high-performance underlying assembly code for operators (for example, tensor cores and related fusion operators).

[0031] Currently, assembly code generation and formatting primarily rely on two techniques: First, employing the simple indentation rules of common assemblers (such as GCC ASM), which format assembly code based on a fixed grammatical structure (e.g., uniform indentation based on labels); and second, using code beautification tools (such as Clang-Format). However, these simple indentation rules fail to fully account for key hardware features in AI chips, such as parallel computing blocks and multi-level memory access. This leads to a mismatch between the code indentation format and actual hardware behavior, resulting in a semantic disconnect. Furthermore, these two techniques fail to effectively utilize the control flow graph (CFG) and data dependency graph (DDG) in the intermediate representation (IR) for control flow processing, making it difficult to accurately reflect the program's actual execution logic and dependencies. Furthermore, the generated assembly code still needs improvement in terms of structure, readability, and annotation information. This is particularly true when dealing with large-scale assembly code (e.g., thousands of lines of code). The lack of well-structured design and detailed annotations significantly impacts code readability, making manual review and problem identification more difficult.

[0032] The present disclosure provides a compilation method, an electronic device, and a storage medium. By writing a first code in a manner of inserting a tensor intermediate representation instruction into a container included in a code skeleton template, the first code can be structured, thereby improving the structural clarity and readability of the first code. At the same time, according to the parent-child relationship between the first container and the second container in the first code, automatic indentation of the assembly code can be achieved when converted into assembly code, thereby improving the readability and structural clarity of the assembly code, and reflecting the actual execution logic and dependency of the program (or instruction). In addition, the code skeleton template provided by the present disclosure can cover multiple types of operators or tensor objects. By inserting the tensor intermediate representation instruction for a certain operator into the code skeleton template, the operator can be designed and developed, thereby improving development efficiency.

[0033] Next, an implementation scheme for the compilation method according to an embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0034] Figure 1 FIG1 shows a schematic flow chart of a compilation method according to at least one embodiment of the present disclosure. Figure 1 As shown, the compiling method according to the embodiment of the present disclosure includes steps S110-S140.

[0035] As an example, the compilation method provided in the present disclosure can be applied to electronic devices that perform tensor calculations. As some examples, the electronic device can be implemented as a graphics processing unit (GPU). In addition, the electronic device can also be implemented in other forms, such as general-purpose graphics processing units (GPGPU), neural network processing units (NPU), tensor processing units (TPU), etc., which are not listed one by one here. It is understandable that the electronic devices mentioned in this article may also include other components required to implement the target processing function, such as a central processing unit (CPU), memory, communication interface, etc., which are not listed here.

[0036] In step S110 , a code skeleton template for processing a tensor object is obtained, wherein the code skeleton template includes a first container and at least one second container.

[0037] For example, a target code skeleton template applicable to a tensor object (or target operator) can be selected from multiple preset code skeleton templates based on the type of the tensor object (or target operator). Alternatively, the code skeleton template can be obtained by analyzing the structure and regularity of various types of operators or tensor objects, making the code skeleton template applicable to various types of operators or tensor objects. Here, "tensor object" is used to refer to a tensor that describes an object.

[0038] For example, a Region is a high-level abstract model built on top of an Intermediate Representation (IR) that supports nested structures and is used to describe how a group of related IR instructions are organized together. The first container (also called the "main container") is the backbone structure or top-level container of the entire code skeleton template. It is used to encapsulate (or insert) some IR instructions from a group of related IR instructions (for example, IR instructions related to operations such as data reading, variable initialization, main loops, and data writing) to describe the overall structure of the group of related IR instructions. Second containers can serve as child containers of the first container. Each second container is used to encapsulate (or insert) execution instructions (for example, instructions for the conditional branch body (i.e., "If body") and the branch end marker (i.e., "End if")) corresponding to specific IR instructions in the first container (for example, structured control instructions such as the conditional judgment instruction "If").

[0039] In step S120 , at least one tensor intermediate representation (TIR) ​​instruction for processing a tensor object is inserted into the code skeleton template to obtain a first code.

[0040] For example, the code skeleton template includes a first container and at least one second container. By inserting corresponding tensor intermediate representation instructions into the first container and at least one second container, a first code can be obtained, thereby realizing program design and development with high-level tensor abstraction. This is to cope with the design stage that cannot be completed by high-level languages ​​in the early stages of hardware development or in applications with demanding performance requirements, and at the same time avoid directly writing assembly code. As an application example, the above-mentioned program design and development can refer to kernel function design and development, which refers to a program executed on a processor such as a GPU or other dedicated processor.

[0041] In addition, by writing the first code in a way that inserts tensor intermediate representation instructions into the containers included in the code skeleton template, the first code can be structured such that the logical relationships between the instructions in the first code are clearer, and the tensor intermediate representation instructions can also be managed in a containerized manner, avoiding directly processing strings in a simple code generation method.

[0042] In some embodiments of the present disclosure, at least one tensor intermediate representation instruction includes a structured control flow instruction, which is used to describe a control instruction flow for nested loops or conditional judgments. For example, the structured control flow instruction can be a judgment instruction "If", an index loop instruction "Loop", or a conditional loop instruction "While", and the present disclosure does not limit this.

[0043] For example, the judgment instruction "If" includes a condition judgment part (i.e., "If condition"), a conditional branch body part (i.e., "If body"), and a branch end marker part (i.e., "End if"). The conditional loop instruction "While" includes a loop condition judgment part (i.e., "While condition"), a loop body part (i.e., "While body"), and a loop end marker part (i.e., "End while"). The index loop instruction "Loop" includes a loop boundary definition part (e.g., "loop idx <upper bound"), a loop body part (i.e., "Loop body"), a loop variable update part (e.g., "idx += loopstep"), and a loop end marker part (i.e., "End loop"). Each part of these structured control flow instructions corresponds to a corresponding tensor intermediate representation instruction.

[0044] For example, the above step S120 may include: inserting at least one tensor intermediate representation instruction into a first container; and in response to the tensor intermediate representation instruction in the first container including a first structured control flow instruction, determining a first target container for the first structured control flow instruction from at least one second container, and inserting the tensor intermediate representation instruction corresponding to the first structured control flow instruction into the first target container, where each structured control flow instruction in the first container corresponds to a second container in the code skeleton template.

[0045] For example, Figure 2 shows a schematic diagram of a code skeleton template according to at least one embodiment of the present disclosure.

[0046] As Figure 2As shown, the code skeleton template 200 includes a first container (Region_1) and multiple second containers (Region_20 to Region_2n). When writing the first code for a tensor object, first obtain the code skeleton template 200 suitable for processing the tensor object, and then insert at least one TIR instruction for processing the tensor object into the first container (Region_1) of the code skeleton template 200. In response to the TIR instruction currently inserted into the first container (Region_1) (for example, Figure 2 "TIR instruction 2 (Loop)") is a structured control flow instruction (i.e., an index loop instruction "Loop"), then an empty (i.e., no TIR instruction has been inserted) second container is selected from multiple second containers as the first target container for TIR instruction 2.

[0047] For example, when selecting Figure 2 When the second container (Region_20) in the Container is used as the first target container, the TIR instruction corresponding to TIR instruction 2 is inserted into the second container (Region_20). Figure 2 As shown, TIR instruction 5, TIR instruction 6, TIR instruction 7 and TIR instruction 8 included in the second container (Region_20) are the TIR instructions corresponding to TIR instruction 2 in the first container (Region_1).

[0048] It should be noted that in Figure 2 In the

[15] , all tensor intermediate representation instructions other than structured control flow instructions are denoted as "TIR instructions." For example, TIR instructions can include resource declaration instructions for declaring resource storage space, tensor operation instructions for performing computations on tensors, scalar computation instructions, and other miscellaneous instructions required by the design. For example, miscellaneous instructions can include order-preserving instructions (Fence). As an example, resource declaration instructions include tensor resource declaration instructions, scalar resource declaration instructions, and synchronization resource declaration instructions. Tensor operation instructions include tensor multiplication instructions, tensor convolution instructions, and tensor move instructions.

[0049] In some examples, in response to the TIR instruction inserted into the first container (Region_1) also including other structured control flow instructions (e.g., the conditional loop instruction "TIR instruction 4 (While)"), the TIR instruction corresponding to the conditional loop instruction is selected from the remaining empty second containers (Region_21 to Region_2n) and inserted, and so on. For example, TIR instructions 9 and TIR instructions 10 corresponding to "TIR instruction 4 (While)" can be inserted into the second container (Region_21).

[0050] In some examples, the second container may also include corresponding structured control flow instructions, and the structured control flow instructions in the second container and their corresponding tensor intermediate representation instructions are inserted into the same second container. Figure 2 As shown, in response to the TIR instruction in the first target container (i.e., the second container (Region_20)) including a structured control flow instruction, i.e., TIR instruction 6 in the second container (Region_20) belongs to the judgment instruction "If", the TIR instructions corresponding to TIR instruction 6 (i.e., TIR instruction 7 and TIR instruction 8) are inserted into the same second container (Region_20).

[0051] exist Figure 2 In the example shown, the first container (Region_1) and multiple second containers (Region_20 to Region_2n) are visually presented in a flat overall-specific structure and have a parent-child relationship in the logical structure. For example, the second container (Region_20) and the second container (Region_21) are both child containers of the first container (Region_1).

[0052] Some embodiments of the present disclosure provide a compilation method that further includes: determining, based on the control flow semantics of the first structured control flow instruction, a tensor intermediate representation instruction corresponding to the first structured control flow instruction. The "first structured control flow instruction" herein refers to any type of structured control flow instruction, and this disclosure does not impose any restrictions thereon.

[0053] For example, semantic recognition is performed on the first structured control flow instruction. In response to determining that the first structured control flow instruction is a judgment instruction "If", the tensor intermediate representation instructions corresponding to the "If body" part and the "End if" part of the judgment instruction "If" are determined to be the tensor intermediate representation instructions corresponding to the first structured control flow instruction.

[0054] For example, semantic recognition is performed on the first structured control flow instruction. In response to determining that the first structured control flow instruction is the conditional loop instruction "While", the tensor intermediate representation instructions corresponding to the "While body" part and the "Endwhile" part of the conditional loop instruction "While" are determined as the tensor intermediate representation instructions corresponding to the first structured control flow instruction.

[0055] For example, semantic recognition is performed on the first structured control flow instruction. In response to determining that the first structured control flow instruction is an index loop instruction "Loop", the tensor intermediate representation instructions corresponding to the "Loop body" part, the loop variable update part (for example, "idx += loop step") and the "End loop" part of the index loop instruction "Loop" are determined as the tensor intermediate representation instructions corresponding to the first structured control flow instruction.

[0056] In addition, in the compilation method provided in the embodiment of the present disclosure, in addition to the first container and the second container mentioned above, the code skeleton template may also include other containers to insert TIR instructions for setting the program header and performing variable initialization, and the present disclosure does not limit this.

[0057] In some examples, instructions for setting a program header, for executing variable initialization, and for executing TIR instructions of "Mbar initialization" may also be directly inserted into the first container, and the present disclosure does not limit this.

[0058] The first code is written according to the above-mentioned code skeleton template and in the form of containerized management so that the first code has a general-to-specific structure, so that the programmer can determine the block division of the first code and the execution order of the TIR instructions in the first container, and can also quickly locate the code block that needs to be viewed in detail (that is, the second container where the TIR instructions corresponding to the structured control flow instructions are located), thereby improving the programming efficiency and structural clarity of the first code, and being able to express nested loops and complex control flows of loops and judgments, which is conducive to more convenient and intuitive conversion of TIR instructions one by one into Machine Intermediate Representation (MIR) instructions in the subsequent compilation stage.

[0059] The compilation method provided by some embodiments of the present disclosure further includes: determining an indentation value corresponding to each of the first container and the at least one second container based on a parent-child relationship between the first container and the at least one second container, wherein the indentation value is assigned to the assembly code during the conversion process from the first code to the assembly code.

[0060] For example, tensor intermediate representation instructions included in the same container have the same indentation value, and the indentation value of the parent container is smaller than the indentation value of the child container.

[0061] For example, in Figure 2In the example shown, in response to the TIR instructions in the first container (Region_1) including a first structured control flow instruction (e.g., TIR instruction 2 (Loop)), and the first target container in at least one second container (e.g., second container (Region_20)) being used to insert the TIR instructions (TIR instructions 5 through TIR instructions 8) corresponding to the first structured control flow instruction (TIR instruction 2 (Loop)), the second container (Region_20) is determined to be a child container of the first container (Region_1). In this case, all TIR instructions (e.g., TIR instructions 1 through TIR instructions 4) included in the first container (Region_1) are set with a first indent value (e.g., 1 space unit), and all TIR instructions (e.g., TIR instructions 5 through TIR instructions 8) included in the second container (Region_20) are set with a second indent value (e.g., 3 space units). Correspondingly, the second container (Region_21) can also be determined as a child container of the first container (Region_1), and all TIR instructions included in the second container (Region_21) (such as TIR instruction 9 and TIR instruction 10) are also set with a second indent value (for example, indented by 3 space units), and so on.

[0062] Furthermore, in Figure 2 In the example shown, in response to the TIR instructions in the first target container (i.e., the second container (Region_20)) including the second structured control flow instruction (i.e., TIR instruction 6 (If)) and the TIR instructions corresponding to the second structured control flow instruction (TIR instruction 6 (If)) (i.e., TIR instruction 7 and TIR instruction 8), the second indentation value of the tensor intermediate representation instruction corresponding to the second structured control flow instruction is updated to the third indentation value. At this time, TIR instruction 7 and TIR instruction 8 in the second container (Region_20) are set with the third indentation value (e.g., indented by 5 space units), and the indentation values ​​of the remaining TIR instructions in the second container (Region_20) (i.e., TIR instruction 5 and TIR instruction 6) still remain at the second indentation value (e.g., indented by 3 space units).

[0063] In step S130, the first code is converted into a second code consisting of machine intermediate representation instructions (MIR instructions). It can be understood that in the compilation method disclosed herein, the instruction code has two abstraction levels. The first abstraction level is a first code designed and developed based on a high-level tensor abstraction, which includes TIR instructions for describing operations on Tensor objects. Then, the TIR instructions are converted into a second code of a second abstraction level, which includes the converted MIR instructions. Since the MIR instructions have a one-to-one mapping relationship with the instructions at the assembly level, the MIR instructions can be directly converted into assembly instructions in the subsequent process, and the multiple assembly instructions obtained by the conversion constitute the assembly code.

[0064] In some embodiments of the present disclosure, the above-mentioned step S130 may include: performing an equivalent transformation on each tensor intermediate representation instruction in the first code to generate a corresponding machine intermediate representation instruction, wherein the indentation value of the machine intermediate representation instruction is equal to the indentation value of the corresponding tensor intermediate representation instruction.

[0065] By utilizing the compilation method according to an embodiment of the present disclosure, TIR instructions in a first code written according to a code skeleton template can be converted into MIR instructions one by one. For example, a TIR instruction can generate one or more MIR-level instruction abstractions through mathematically equivalent transformations, and the generated MIR instructions are included in one or more Machine Basic Block (MBB) containers, wherein the MIR instructions organized in the MBB container have a one-to-one mapping relationship with the assembly language.

[0066] In addition, when converting TIR instructions into MIR instructions one by one, the indentation value of the TIR instruction is assigned to the corresponding MIR instruction (or the MBB container where the corresponding MIR instruction is located), so that after the MIR instruction is converted into assembly instructions, the obtained assembly code also has the corresponding indentation value, thereby improving the readability and structural clarity of the assembly code.

[0067] For ease of description, the process of converting the above-mentioned TIR-level instructions to MIR-level instructions is represented as the Lower() process. Each TIR instruction can pre-define its corresponding Lower() function. As an example, the Lower function can be described as Lower(MIR pointer). Therefore, the above-mentioned conversion process of converting TIR-level instructions to MIR-level instructions can be represented as the process of converting the TIR instruction to the MIR instruction using the pre-defined Lower() function corresponding to each TIR instruction.

[0068] As an example, Figure 3 FIG. 1 shows a schematic diagram of compiling a first code into an assembly code according to at least one embodiment of the present disclosure. Figure 3 In the figure, it is shown that Figure 2 The process of converting the TIR instructions in the first code (or the code skeleton template 200) into MIR instructions organized according to the MBB container structure is shown.

[0069] like Figure 3 As shown, TIR instruction 1 in the first container (Region_1) is converted to MIR instruction 1 in basic block container 1 (MBB_1), and the indent value of MIR instruction 1 is equal to the indent value of TIR instruction 1 (i.e., the "first indent value"). It should be noted that Figure 3 Only one MIR instruction 1 is schematically shown. In actual scenarios, the TIR instruction 1 (Instruction) can be converted into multiple MIR instructions 1, and multiple MIR instructions 1 can be included in the same MBB container or included in multiple different MBB containers. This disclosure does not limit this.

[0070] It is understandable that for each TIR instruction in the code skeleton template 200, a corresponding Lower function can be defined so as to convert it into a MIR instruction during the compilation phase. For other instructions in the first code, they can be converted into MIR instructions one by one in a similar manner.

[0071] For example, when converting a TIR instruction to a MIR instruction, the conversion can be performed in the order in which the TIR instructions are inserted in the first container. Furthermore, when the current TIR instruction to be converted (e.g., TIR instruction 2 (Loop)) is a structured control flow instruction, after converting the TIR instruction to a MIR instruction, the TIR instructions in the second container corresponding to the TIR instruction are first converted one by one (e.g., TIR instructions 5 to TIR instruction 8 in the second container (Region_20) corresponding to TIR instruction 2 (Loop)), and then the next TIR instruction in the first container corresponding to the TIR instruction is converted (e.g., TIR instruction 3 next to TIR instruction 2 (Loop)). This makes the structure and logical relationship of the second code obtained after the conversion clearer, which facilitates the subsequent step of converting the second code into assembly code.

[0072] For example, Figure 3As shown, TIR instruction 2 in the first container (Region_1) is converted to MIR instruction 2 in basic block container 1 (MBB_1). TIR instruction 3 and TIR instruction 4 in the first container (Region_1) are converted to MIR instruction 3 and MIR instruction 4 in basic block container 4 (MBB_4), respectively. Since TIR instruction 1, TIR instruction 2, TIR instruction 3, and TIR instruction 4 all belong to the first container (Region_1), the indentation values ​​of TIR instruction 1, TIR instruction 2, TIR instruction 3, and TIR instruction 4 are all the first indentation value (for example, indented by 1 space unit). Accordingly, the indentation values ​​of the converted MIR instruction 1, MIR instruction 2, MIR instruction 3, and MIR instruction 4 are also set to the first indentation value (for example, indented by 1 space unit).

[0073] For example, Figure 3 As shown, according to the above description, the second container (Region_20) is a child container of the first container (Region_1). TIR instructions 5 and 6 in the second container (Region_20) are set with the second indent value, and TIR instructions 7 and 8 corresponding to TIR instruction 6, which are structured control flow instructions, are set with the third indent value. The indent value of MIR instructions 5 and 6 (included in basic container block MBB_2) converted from TIR instructions 5 and 6 is also set to the second indent value (for example, indented by 3 space units), and the indent value of MIR instructions 7 and 8 (included in basic container block MBB_3) converted from TIR instructions 7 and 8 is also set to the third indent value (for example, indented by 5 space units).

[0074] Similarly, the second container (Region_21) is a child container of the first container (Region_1), and the indentation value of TIR instruction 9 and TIR instruction 10 in the second container (Region_21) is set to the second indentation value (for example, indented by 3 space units). Then, MIR instruction 9 and MIR instruction 10 converted from TIR instruction 9 and TIR instruction 10 are included in basic container block 5 (MBB_5), and the indentation value of MIR instruction 9 and MIR instruction 10 is also set to the second indentation value (for example, indented by 3 space units).

[0075] In the compilation method provided in the embodiment of the present disclosure, the TIR instructions in the first code are organized and managed in a container manner, so that the logical relationship of the TIR instructions in the first code is clear during the conversion into MIR-level instructions, and they can be quickly and one by one converted into machine intermediate representation instructions and assigned corresponding indentation values, thereby improving the compilation efficiency and the readability of the machine intermediate representation instructions.

[0076] In step S140, the second code is converted into assembly code consisting of assembly instructions, where the machine intermediate representation instructions have a one-to-one mapping relationship with the assembly instructions. Because the machine intermediate representation instructions in the second code have a one-to-one mapping relationship with the assembly instructions in the assembly code, the second code can be directly printed as assembly code (Assembly) for execution, for example, using the Print() function.

[0077] For example, when executing the above step S140, the machine intermediate representation instructions (MIR instructions) in the second code can be printed according to the instruction sequence and the indentation values ​​of the MIR instructions, thereby obtaining assembly code with high readability and structural clarity.

[0078] For example, for the generated assembly code, a machine code may be first generated by an assembler, and the generated file may be represented as an object file. A linker may then be used to convert the object file into an executable file for execution by an electronic device.

[0079] In the compilation method provided by the embodiment of the present disclosure, according to the semantics of each TIR instruction in the first code and the parent-child relationship between the first container and the second container, the automatic indentation of the assembly code can be achieved when converted into assembly code, thereby improving the readability of the assembly code, and the effect of code folding and unfolding can be achieved based on the indentation format of the assembly code, so that the user can quickly check the format correctness of the assembly code file. In addition, the compilation method provided by the embodiment of the present disclosure also supports user-defined indentation rules to adapt to different AI chip architecture instructions. For example, the user can assign specific indentation values ​​to some specific instructions.

[0080] An embodiment of the present disclosure also provides an electronic device.

[0081] For example, Figure 4 A schematic block diagram of an electronic device according to at least one embodiment of the present disclosure is shown.

[0082] like Figure 4 As shown, the electronic device 400 may include a processor 401 and a non-transitory memory 402. The non-transitory memory 402 stores program code, which, when executed by the processor 401, enables the processor 401 to perform the steps of the compilation method provided in any embodiment of the present disclosure.

[0083] For example, the processor 401 may be any one of a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU (Neural Network Processing Unit), a DPU (Deep Learning Processing Unit), an APU (Accelerated Processing Unit), and a GPGPU (General-Purpose Computing on Graphics Processing Unit). In addition, the processor 401 may be any conventional processor. For example, the processor herein may refer to a processor chip capable of performing parallel computing.

[0084] For example, non-transitory memory 402 stores computer-readable code that, when executed by processor 401, can cause the processor to implement the steps of the compilation method provided in any embodiment of the present disclosure. Non-transitory memory 402 can also be any suitable type of memory. As an example, by executing the computer-readable code in non-transitory memory 402, the processor can implement the steps of the compilation method described above in conjunction with the accompanying drawings.

[0085] It is understandable that the electronic device provided by the embodiment of the present disclosure can also be implemented as any form of computing device or processor for performing tensor calculations, etc., without limitation herein, and can compile the first code designed and developed with high-level tensor abstraction according to the compilation method described above, and obtain high-performance assembly code capable of parallel computing. The specific steps performed by the electronic device according to the embodiment of the present disclosure can refer to the above description of the compilation method according to the present disclosure, and will not be repeated here.

[0086] Figure 5 A schematic block diagram of another electronic device according to at least one embodiment of the present disclosure is shown. Figure 5 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0087] For example, Figure 5As shown, in some examples, electronic device 500 includes a processing device 501 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) 502 or programs loaded from storage device 508 into random access memory (RAM) 503. RAM 503 also stores various programs and data required for computer system operation. Processing device 501, ROM 502, and RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to bus 504.

[0088] For example, the following components may be connected to the I / O interface 505: an input device 506 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 507 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 508 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 509 including, for example, a network interface card, such as a LAN card, a modem, etc. The communication device 509 may allow the electronic device 500 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. A drive 510 is also connected to the I / O interface 505 as needed. Removable media 511, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive 510 as needed, so that the computer program read therefrom is installed into the storage device 508 as needed. Although Figure 5 The electronic device 500 is shown as including various devices, but it should be understood that it is not required to implement or include all of the devices shown. More or fewer devices may be implemented or included instead.

[0089] For example, the electronic device 500 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 509 may communicate with a network and other devices through wireless communication.

[0090] For example, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program.For example, an embodiment of the present disclosure includes a computer program product including a computer program carried on a non-transitory computer-readable medium.

[0091] An embodiment of the present disclosure further provides a non-transitory computer-readable storage medium having computer-readable instructions stored thereon. When the computer-readable instructions are executed by a processor, the processor executes the steps of the compilation method provided by any embodiment of the present disclosure.

[0092] Figure 6 Schematic block diagram of a storage medium according to an embodiment of the present disclosure is shown. Figure 6 As shown, a computer-readable storage medium 600 stores computer-readable instructions 601. When the computer-readable instructions 601 are executed by a processor, the compilation method described with reference to the above figures can be executed.

[0093] It should be noted that the computer-readable storage medium provided by the present disclosure may be, for example, (but not limited to) an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In embodiments of the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or component. The above-mentioned computer-readable medium may be included in the above-mentioned electronic device, or may exist independently without being incorporated into the electronic device.

[0094] For the compilation method, electronic device and storage medium provided by the present disclosure, by writing the first code in a manner of inserting tensor intermediate representation instructions into the container included in the code skeleton template, the first code can be structured, thereby improving the structural clarity and readability of the first code. At the same time, according to the parent-child relationship between the first container and the second container in the first code, automatic indentation of the assembly code can be achieved when converted into assembly code, thereby improving the readability and structural clarity of the assembly code, and reflecting the actual execution logic and dependency of the program (or instruction). In addition, the code skeleton template provided by the present disclosure can cover multiple types of operators or tensor objects. By inserting the tensor intermediate representation instructions for a certain operator into the code skeleton template, the operator can be designed and developed, thereby improving development efficiency.

[0095] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented through hardware, software, firmware, or a combination of some or all of the three.

[0096] Furthermore, although this disclosure makes various references to certain units in computing devices and electronic devices according to embodiments of the present disclosure, any number of different units may be used and run on the client and / or server. The units are illustrative only, and different aspects of the data transmission method, computing device, or electronic device may utilize different units.

[0097] Those skilled in the art will appreciate that all or part of the steps in the above-described data transmission method can be performed by instructing related hardware using a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps in the above-described embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above-described embodiment can be implemented in the form of hardware or in the form of software functional modules. The present disclosure is not limited to any particular combination of hardware and software.

[0098] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or highly formal sense unless expressly defined as such herein.

[0099] The above is an illustration of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure have been described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the above is an illustration of the present disclosure and should not be considered as limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A compilation method, characterized in that: The compilation method comprises: Obtaining a code skeleton template for processing a tensor object, wherein the code skeleton template includes a first container and at least one second container; Inserting at least one tensor intermediate representation instruction for processing the tensor object into the code skeleton template to obtain a first code; converting the first code into a second code consisting of machine intermediate representation instructions; and Converting the second code into assembly code consisting of assembly instructions, wherein the machine intermediate representation instructions have a one-to-one mapping relationship with the assembly instructions; The compiling method further includes: determining, based on a parent-child relationship between the first container and the at least one second container, respective indentation values ​​corresponding to the first container and the at least one second container, wherein the indentation values ​​are assigned to the assembly code during conversion from the first code to the assembly code; The converting the first code into a second code composed of machine intermediate representation instructions includes: Performing an equivalent transformation on each tensor intermediate representation instruction in the first code to generate a corresponding machine intermediate representation instruction, wherein an indentation value of the machine intermediate representation instruction is equal to an indentation value of the corresponding tensor intermediate representation instruction; The converting the second code into assembly code comprises: The machine intermediate representation instructions are printed according to the instruction sequence of the machine intermediate representation instructions and according to the indentation values ​​of the machine intermediate representation instructions to obtain the assembly code.

2. The compiling method according to claim 1, wherein: The at least one tensor intermediate representation instruction includes a structured control flow instruction, and the structured control flow instruction is used to describe a control instruction flow of a nested loop or a conditional judgment. Inserting at least one tensor intermediate representation instruction for processing the tensor object into the code skeleton template to obtain a first code includes: inserting the at least one tensor intermediate representation instruction into the first container; and In response to the tensor intermediate representation instructions in the first container including a first structured control flow instruction, determining a first target container for the first structured control flow instruction from the at least one second container, and inserting the tensor intermediate representation instructions corresponding to the first structured control flow instruction into the first target container, Each structured control flow instruction in the first container corresponds to a second container in the code skeleton template.

3. The compiling method according to claim 2, wherein: The compilation method further includes: In response to the tensor intermediate representation instruction in the first target container including a second structured control flow instruction, the tensor intermediate representation instruction corresponding to the second structured control flow instruction is inserted into the first target container.

4. The compiling method according to claim 2, wherein: The compilation method further includes: Determine a tensor intermediate representation instruction corresponding to the first structured control flow instruction based on the control flow semantics of the first structured control flow instruction.

5. The compiling method according to claim 1, wherein: The tensor intermediate representation instructions included in the same container have the same indentation value, and the indentation value of the parent container is smaller than that of the child container.

6. The compiling method according to claim 5, wherein: The determining, based on the parent-child relationship between the first container and the at least one second container, the indentation values ​​corresponding to the first container and the at least one second container, includes: In response to the tensor intermediate representation instructions in the first container including a first structured control flow instruction, and a first target container in the at least one second container being used to insert the tensor intermediate representation instructions corresponding to the first structured control flow instruction, determining the first target container as a child container of the first container, The tensor intermediate representation instructions included in the first container are set with a first indentation value, the tensor intermediate representation instructions included in the first target container are set with a second indentation value, and the second indentation value is greater than the first indentation value.

7. The compiling method according to claim 6, wherein: The compilation method further includes: In response to the tensor intermediate representation instruction in the first target container including a second structured control flow instruction and a tensor intermediate representation instruction corresponding to the second structured control flow instruction, the second indentation value of the tensor intermediate representation instruction corresponding to the second structured control flow instruction is updated to a third indentation value, wherein the third indentation value is greater than the second indentation value.

8. An electronic device, characterized in that: The electronic device includes at least one processor and at least one non-transitory memory, wherein the at least one non-transitory memory stores program code, and when the program code is executed by the at least one processor, the at least one processor performs the steps of the compilation method according to any one of claims 1-7.

9. A non-transitory computer-readable storage medium, characterized in that The non-transitory computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, enable the processor to perform the steps of the compilation method according to any one of claims 1 to 7.

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