A method for translating vector instructions of x86 programs in binary translation

Abstract

The application provides a vector instruction translation method for XMM registers of X86 programs in binary translation, comprising: dividing an X86 program in binary form into multiple translation blocks, and disassembling each translation block to obtain an assembly instruction set of each translation block; for an X86 vector instruction in a translation block, when the instruction execution speed of translating the X86 vector instruction into a floating point instruction of a RISC-V instruction set is higher than the instruction execution speed of translating the X86 vector instruction into a vector instruction of the RISC-V instruction set, the X86 vector instruction is translated into the floating point instruction of the RISC-V instruction set, otherwise, the X86 vector instruction is translated into the vector instruction of the RISC-V instruction set; for an X86 vector instruction in a translation block, whether a preset bit number of an operand of the instruction is used by a subsequent X86 vector instruction is judged, and when the preset bit number of the operand is not used, the preset bit number of the operand in the instruction is not translated. The translation method improves the execution performance of the translated instruction, and reduces the data synchronization instruction and improves the translation performance of the floating point operation by avoiding the translation of redundant operation instructions.

Description

Technical Field

[0001] This invention relates to the field of binary translation, specifically to the field of vector instruction optimization, and more specifically, to a method for vector instruction translation of the XMM register in an X86 program during binary translation. Background Technology

[0002] With the continuous development of information technology, the computing power requirements of processors are constantly increasing, and various new instruction set architecture (ISA) processor architectures have emerged, such as PowerPC architecture, X86 architecture, ARM architecture, RISC-V in reference [1], Loongarch architecture in reference [2] and Shenwei 64-bit instruction set (SW64) architecture in reference [3]. The program compatibility problem between different ISAs has become particularly prominent, especially for some closed-source programs. In order to achieve software compatibility and interoperability between different ISAs and meet the cross-platform operation requirements, binary translation technology has emerged. Binary translation technology is the core technology for cross-architecture virtual machine implementation. Binary translation technology can convert a binary executable program on one ISA into a binary executable program on another ISA (or a different version of the same ISA), as in reference [4].

[0003] Since Intel launched the x86 architecture, the application software ecosystem based on the x86 architecture has become quite rich. However, as mentioned in reference [5], RISC-V, as a completely new and open instruction set architecture, still lacks a software ecosystem compared to x86 and has not yet formed a good software ecosystem. Although in the long run, establishing and improving one's own software development environment is the fundamental way, in the short term, it is a feasible way to promote the growth of RISC-V by leveraging the mature x86 / ARM ecosystem. Therefore, binary translation technology from x86 architecture to RISC-V architecture is particularly important.

[0004] In an x86 environment, compilers typically translate floating-point operations in source code into x86 vector instructions. This is because floating-point operations are generally less efficient than vector operations on x86, and compiling to x86 vector instructions improves program performance. Binary translation software translates based on the input x86 binary program. Therefore, SSE (Streaming SIMD Extensions) vector instructions in the x86 architecture are translated into RISC-V vector instructions. SSE is a format of instructions in the x86 architecture. During the translation process, x86 XMM registers are mapped to RISC-V vector registers. However, most SSE vector instructions only operate on the lower 64 or lower 32 bits of data. To maintain the original semantics of the x86 vector instructions, the translator needs to issue redundant instructions to perform high-bit holding or clearing operations on the XMM registers. For example, the x86 instructions cvtsi2sd, cvtss2sd, and movlps, while satisfying the lower 64-bit semantics, require an additional IR2 instruction to ensure the higher 64 bits of the RISC-V vector register retain their original data. Similarly, the movq instruction, with all operands being XMM, requires an additional IR2 instruction to clear the higher 64 bits of the RISC-V vector register while satisfying the lower 64-bit semantics. If the binary translation system strictly adheres to the original x86 semantics, simulating the original semantics of a single x86 instruction requires issuing and executing multiple instructions on the RISC-V, resulting in a high instruction translation bloat rate. This negatively impacts the performance of the translated target program. The instruction translation bloat rate refers to the ratio of the number of target instructions to the number of source instructions.

[0005] However, not every extra operation of preserving or clearing the high-order bits of the XMM register in x86 will affect the correctness of program execution. For example, if an x86 program assigns a value to the lower 64 bits of the xmm1 register and then no longer uses the higher 64 bits of the xmm1 register, then clearing the higher 64 bits of the xmm1 register is redundant.

[0006] Furthermore, RISC-V native compilers typically compile floating-point operations in the source code into floating-point instructions. Binary translators (the systems that translate x86 instructions into RISC-V instructions, abbreviated as DBT) have two translation options when translating SSE vector instructions under the x86 architecture: one is to use a floating-point translation method to translate SSE vector instructions into RISC-V vector instruction implementations, and the other is to use a vector translation method to translate SSE vector instructions into RISC-V floating-point instruction implementations. Current methods uniformly translate x86 vector instructions into RISC-V vector instructions. However, the inventors discovered that in RISC-V, for some x86 vector instructions, the execution speed using the vector translation method is slower than the floating-point translation method under the same semantics.

[0007] Therefore, existing methods suffer from instruction redundancy when translating x86 vector instructions that perform floating-point operations in the x86 environment. In terms of the execution efficiency of the translated instructions, not all x86 vector instructions are suitable for translation using the RISC-V vector method. There is a problem that the execution efficiency of some x86 vector instructions using the vector translation method is lower than that using the floating-point translation method.

[0008] It should be noted that the background information presented here is only for illustrating relevant information about the present invention to aid in understanding the technical solution of the present invention, and does not imply that the relevant information is necessarily prior art. The relevant information was submitted and disclosed together with the present invention, and should not be considered prior art unless there is evidence that the relevant information was disclosed before the filing date of the present invention.

[0009] The references are as follows:

[0010] [1] Waterman, AndrewLee, YunsupPatterson, et al. The RISC-V InstructionSet Manual, Volume I: User-Level ISA, Version 2.0[J].[2024-12-19].

[0011] [2] Weiwu H, Wenxiang W, Ruiyang W, et al. Loongson instruction set architecture technology[J]. J. Comput. Res. Dev, 2023, 60(2): 16.

[0012] [3] Li W, Luo

[0013] [4] Cifuentes C , Malhotra V .Binary translation: static, dynamic,retargetable?[C] / / Software Maintenance 1996, Proceedings.InternationalConference on.IEEE, 2002.DOI:10.1109 / ICSM.1996.565037.

[0014] [5] E. Cui, T. Li and Q. Wei, "RISC-V Instruction Set ArchitectureExtensions: A Survey," in IEEE Access, vol. 11, pp. 24696-24711, 2023, doi:10.1109 / ACCESS.2023.3246491. Summary of the Invention

[0015] Therefore, the purpose of this invention is to overcome the shortcomings of the prior art and provide a vector instruction translation method for the XMM register of an X86 program in binary translation.

[0016] The objective of this invention is achieved through the following technical solution:

[0017] According to a first aspect of the present invention, a method for translating vector instructions of the XMM register of an X86 program in binary translation is provided, comprising: S1, dividing the binary X86 program into multiple translation blocks, and disassembling each translation block to obtain the assembly instruction set of each translation block; S2, obtaining translation indication information of each X86 vector instruction in the assembly instruction set of each translation block according to a preset analysis method, including translation type indication and translation identifier, wherein the analysis method includes: S21, for each X86 vector instruction, if the instruction execution speed after translating it into RISC-V floating-point instructions is better than the instruction execution speed after translating it into RISC-V vector instructions, the translation type indication is set to floating-point class to indicate that it is translated into floating-point instructions of the RISC-V instruction set; otherwise, the translation type indication is set to vector class to indicate that it is translated into vector instructions of the RISC-V instruction set; S21, ... 22. Obtain the usage information of the operands in the XMM register in each X86 vector instruction, including whether the number of bits in the XMM register is used by subsequent X86 vector instructions; S23. Generate a translation flag based on the operand usage information, including a cancellation flag indicating whether to translate a preset number of bits of the operands in the XMM register. When the translation of the preset number of bits is a redundant operation, the cancellation flag indicates no; S3. Translate each X86 vector instruction according to the translation indication information of each X86 vector instruction in the assembly instruction set of each translation block to obtain the RISC-V instruction set program S3.

[0018] In some embodiments of the present invention, in S23, the translation identifier further includes: a first synchronization instruction, indicating whether the operand of the current x86 vector instruction that is an XMM register is synchronized from floating point to vector, which indicates whether the data of the floating point register under the RISC-V architecture corresponding to the XMM register is copied to the vector register under the RISC-V architecture corresponding to the same XMM register; the first synchronization instruction is set to yes when the following first preset conditions are met, and set to no otherwise: the operand of the current x86 vector instruction that is an XMM register is written to the lower 64 bits, and the subsequent x86 vector instruction reads the lower 64 bits of the operand of the same XMM register; and the current x86 vector instruction is translated into a floating point instruction of the RISC-V instruction set, and the subsequent x86 vector instruction is translated into a vector instruction of the RISC-V instruction set.

[0019] In some embodiments of the present invention, in S23, the translation identifier further includes: a second synchronization instruction, indicating whether the operand of the current x86 vector instruction that is an XMM register is synchronized from vector to floating point, which indicates whether the data of the vector register under the RISC-V architecture corresponding to the XMM register is copied to the floating point register under the same RISC-V architecture corresponding to the XMM register; the second synchronization instruction is set to yes when the following second preset conditions are met, and set to no otherwise: the operand of the current x86 vector instruction that is an XMM register is written to the lower 64 bits, and the subsequent x86 vector instruction reads the lower 64 bits of the operand of the same XMM register; and the current x86 vector instruction is translated into a vector instruction of the RISC-V instruction set, and the subsequent x86 vector instruction is translated into a floating point instruction of the RISC-V instruction set.

[0020] In some embodiments of the present invention, in S23, the preset bit length is the high 64 bits. For the current X86 vector instruction, the elimination flag is set as follows: when the operand of the XMM register is written to the high 64 bits in the current X86 vector instruction and the subsequent X86 vector instruction reads the high 64 bits of the operand of the same XMM register, the elimination flag indicates yes, which means that the high 64 bits of the operand of the same XMM register are translated; when the high 64 bits of the operand of the same XMM register are not read in the subsequent X86 vector instruction, the translation of the high 64 bits of the operand of the same XMM register is a redundant operation, and the elimination flag indicates no, which means that the high 64 bits of the operand of the same XMM register are not translated.

[0021] In some embodiments of the present invention, in S22, the usage of the operand of the XMM register in the X86 vector instruction is obtained based on the read / write status of the operand of the XMM register in the X86 vector instruction, the read / write status of the operand of the XMM register in subsequent X86 vector instructions, and the translation type indication of subsequent X86 vector instructions. The usage is represented by a preset usage array, which includes: a first usage value, indicating whether the high 64 bits of the XMM register in the X86 vector instruction should be used by subsequent X86 vector instructions translated into RISC-V instruction set vector instructions; a second usage value, indicating... The first read / write state indicates whether the lower 64 bits of the XMM register in the x86 vector instruction should be used by the subsequent x86 vector instruction that is translated into a RISC-V instruction set vector instruction; the second read / write state is represented by a preset read / write array, which includes: a first write value indicating whether the higher 64 bits of the XMM register have been written and a first read value indicating whether they have been read; and a second write value indicating whether the lower 64 bits of the XMM register have been written and a second read value indicating whether they have been read.

[0022] In some embodiments of the present invention, step S22 includes constructing the initial usage of all XMM registers under the x86 architecture for each translation block; wherein, the initial usage is constructed by: performing data flow analysis on all subsequent translation blocks of the current translation block to obtain the initial usage of all XMM registers corresponding to each of the subsequent translation blocks; and obtaining the initial usage of all XMM registers corresponding to the current translation block based on the union of the initial usage of all XMM registers corresponding to all subsequent translation blocks.

[0023] In some embodiments of the present invention, in step S2, the preset analysis method includes: for each translation block, sequentially analyzing each X86 vector instruction backward from the last X86 vector instruction of the translation block to obtain translation instruction information for each X86 vector instruction. Specifically, when analyzing each X86 vector instruction, the operands of each XMM register under that instruction are analyzed in the following manner, and their current usage is updated to obtain the updated usage:

[0024] Based on the acquired read / write status of the current x86 vector instruction, the read / write status of the subsequent x86 vector instruction, and the translation type indicators of the current and subsequent x86 vector instructions, when it is the destination operand, the analysis method includes: if the high 64 bits of the operand are redundant operations, setting the elimination flag indicator to yes and updating the first used value indicator to no; otherwise, setting the elimination flag indicator to no; determining whether the first preset condition is met and updating the second used value indicator to no; if met, setting the first synchronization instruction indicator to yes; otherwise, setting the first synchronization instruction indicator to no; determining whether the second preset condition is met and updating the third used value indicator to no. If the value indicator is not specified, and the condition is met, the second synchronization instruction indicator is set to yes; otherwise, the second synchronization instruction indicator is set to no. When the value is the source operand, the analysis method includes: if the operand of the XMM register in the subsequent x86 vector instruction is read in the high 64 bits, the first use value indicator is updated to yes; if the subsequent x86 vector instruction is translated into a RISC-V instruction set vector instruction, and the operand of the XMM register is read in the low 64 bits, the second use value indicator is updated to yes; if the subsequent x86 vector instruction is translated into a RISC-V instruction set floating-point instruction, and the operand of the XMM register is read in the low 64 bits, the third use value indicator is updated to yes.

[0025] In each translation block, when the operands of the XMM register are analyzed for the first time, the current usage is the initial usage of the XMM register corresponding to that translation block. In subsequent analyses of the operands of the XMM register, the current usage of the operands is the usage after the previous update.

[0026] In some embodiments of the present invention, S21 includes: obtaining a pre-constructed record table, including a plurality of x86 vector instructions and a label classifying each instruction as either a Class I instruction or a Class II instruction; if the execution speed of an x86 vector instruction translated into RISC-V floating-point instructions is better than the execution speed of an instruction translated into RISC-V vector instructions, it is labeled as a Class I instruction, otherwise it is labeled as a Class II instruction; according to the record table, determining the label of the x86 vector instructions in the translation block, setting the translation type indicator of the x86 vector instructions labeled as Class I instructions to floating-point class, and setting the translation type indicator of the x86 vector instructions labeled as Class II instructions to vector class.

[0027] In some embodiments of the present invention, the x86 vector instructions in the record table, which are classified into one category, include any one or a combination of the following instructions: MULSD, SQRTSD, SUBSD, UNPCKLPD, ROUNDSD, CVTSS2SD, CVTSI2SD, CVTSD2SI, CVITSD2SI, VCVITSD2SI, ADDSD, DIVSD, UCOMISD, COMISD, VUCOMISD, VCOMISD, MAXSD, MINSD, CMPSD, VCVTSI2SD, VCVTSS2SI, VMOVSD, VMOVQ, VMULSD, VADDSD, VDIVSD, VSUBSD, VSORTSD, VMAXSD, VMINSD, MOVLPS, MOVLPD, MOVQ, and MOVSD instructions.

[0028] In some embodiments of the present invention, the method further includes constructing a mapping relationship between each XMM register under the x86 architecture and each floating-point register under the RISC-V architecture; wherein, when an x86 vector instruction is translated into a floating-point instruction of the RISC-V instruction set, based on the mapping relationship, operands that are XMM registers in the x86 vector instruction are translated into operands that are floating-point registers in the floating-point instruction of the RISC-V instruction set.

[0029] According to a second aspect of the present invention, a binary translation system for implementing the method of the first aspect of the present invention is provided. The system includes: a disassembly module for dividing a binary x86 program into multiple translation blocks and disassembling each translation block to obtain an assembly instruction set for each translation block; a backward data flow analysis module for obtaining translation indication information of each x86 vector instruction in the assembly instruction set of each translation block according to a preset analysis method, including translation type indication and translation identifier; and a translation module for translating each x86 vector instruction according to the translation indication information of each x86 vector instruction in the assembly instruction set of each translation block to obtain a RISC-V instruction set program.

[0030] According to a third aspect of the present invention, an electronic device is provided, comprising: one or more processors; and a memory for storing executable instructions; wherein the one or more processors are configured to implement the steps of the method of the first aspect of the present invention by executing the executable instructions.

[0031] Compared with the prior art, the advantages of the present invention are as follows:

[0032] On the one hand, the method of this invention targets x86 vector instructions. If the execution speed of translating them into floating-point instructions of the RISC-V instruction set is better than that of translating them into vector instructions of the RISC-V instruction set, then the instructions are translated into floating-point instructions of the RISC-V instruction set; otherwise, they are translated into vector instructions of the RISC-V instruction set, thus improving the execution performance of the translated instructions. On the other hand, for each x86 vector instruction, the method determines whether a preset number of bits for the operands of that instruction is used by a subsequent x86 vector instruction. If not, the preset number of bits for the operands in that instruction is not translated, eliminating redundant instructions corresponding to the operands of the XMM register. Simultaneously, it reduces data synchronization between x86 vector instructions implemented with floating-point instructions of the RISC-V instruction set and x86 vector instructions implemented with vector instructions of the RISC-V instruction set, thereby improving the translation performance of floating-point operations. Attached Figure Description

[0033] The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

[0034] Figure 1 This is a schematic diagram of the vector instruction translation method according to an embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram illustrating the complete analysis process for each translation block according to an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram illustrating the analysis process of the target operand according to an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the overall process for analyzing all translation blocks according to an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram illustrating the execution process of the _xmm_recent_use_of_succ() function according to an embodiment of the present invention;

[0039] Figure 6 This is a schematic diagram illustrating the execution process of the compute_xmm_recent_use() function according to an embodiment of the present invention;

[0040] Figure 7 This is a schematic diagram of a binary translation system architecture according to an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the invention.

[0042] As mentioned in the background section, existing methods suffer from instruction redundancy when translating x86 vector instructions that perform floating-point operations in the x86 environment. In terms of the execution efficiency of the translated instructions, not all x86 vector instructions are suitable for the RISC-V vector translation method, and some x86 vector instructions have lower execution efficiency when using the vector translation method than when using the floating-point translation method.

[0043] To address the aforementioned issues, the inventors propose a method for translating vector instructions in the XMM register of an x86 program during binary translation. On one hand, this method, for x86 vector instructions performing floating-point operations, prioritizes RISC-V instruction set floating-point instructions over RISC-V instruction set vector instructions. If the execution speed of translating these instructions to RISC-V instruction set floating-point instructions is faster than translating them to RISC-V instruction set vector instructions, then the instructions are translated to RISC-V instruction set floating-point instructions; otherwise, they are translated to RISC-V instruction set vector instructions, thus improving the execution performance of the translated instructions. On the other hand, for each x86 vector instruction, the method determines whether a preset number of bits for the operands of that instruction is used by a subsequent x86 vector instruction. If not, the preset number of bits for the operands in that instruction is not translated, eliminating redundant operation instructions corresponding to the operands in the XMM register. Simultaneously, it reduces data synchronization between x86 vector instructions implemented with RISC-V instruction set floating-point instructions and x86 vector instructions implemented with RISC-V instruction set vector instructions. In other words, this invention reduces data synchronization instructions and improves the translation performance of floating-point operations by avoiding the issuance and translation of redundant operation instructions.

[0044] The principle behind this invention's method, which reduces data synchronization instructions after eliminating redundant instructions, is as follows: For example, two consecutive x86 vector instructions are translated using floating-point instructions from the RISC-V instruction set and vector instructions from the RISC-V instruction set, respectively, but both x86 vector instructions use the same operand in the XMM register. Since floating-point instructions from the RISC-V instruction set use floating-point registers, and vector instructions from the RISC-V instruction set use vector registers, after the previous instruction is translated into a floating-point instruction from the RISC-V instruction set, the operand is translated into the floating-point register. To ensure that the subsequent x86 vector instruction, after being translated into a vector instruction from the RISC-V instruction set, can also use this operand from the vector register, all bits of the operand need to be synchronously translated into the vector register. However, after eliminating redundant instructions that translate a preset number of bits of the operand in the same XMM register, only the remaining bits of the operand need to be synchronously translated into the vector register, reducing the need to synchronously translate the preset number of bits of the operand into the vector register, thus reducing the number of data synchronization instructions.

[0045] According to one embodiment of the present invention, see Figure 1 This is a schematic flowchart of the vector instruction translation method of the present invention. The method includes steps S1, S2, and S3, and step S2 includes S21, S22, and S23. To better understand the present invention, each step will be described in detail below with reference to specific embodiments.

[0046] Step S1: Divide the binary X86 program into multiple translation blocks, and disassemble each translation block to obtain the assembly instruction set of each translation block.

[0047] According to an embodiment of the present invention, in step S1, the translation block is a program consisting of multiple sequentially executed instructions. The translation block division rules include: control flow can only enter from the first instruction of the translation block, not from intermediate instructions, and can only output from the last instruction of the translation block, without jumping out at intermediate instructions. Specifically, when a `call` instruction appears, it is used as the last instruction of the translation block. The division of translation blocks is usually done by jump instructions, such as `jmp`. The technical solution of this embodiment can achieve at least the following beneficial technical effects: due to the dynamic nature of control flow and the lack of binary semantics, when a `call` instruction is encountered, this instruction needs to be used as the end instruction of the translation block. This design ensures that the translator can correctly handle complex scenarios such as function calls, return addresses, and cross-architecture differences, while balancing performance and correctness.

[0048] According to one embodiment of the present invention, the x86 architecture includes multiple XMM registers. If the x86 program source code contains programs that use XMM registers for floating-point operations, then under the x86 architecture, programs that use XMM registers for floating-point operations will be compiled into XMM vector instructions (in this invention, XMM vector instructions are uniformly referred to as x86 vector instructions). If a translation block contains programs that use XMM registers for floating-point operations, then the assembly instruction set corresponding to that translation block contains x86 vector instructions.

[0049] Step S2: Obtain the translation instruction information of each X86 vector instruction in the assembly instruction set of each translation block according to the preset analysis method, including translation type indication and translation identifier.

[0050] According to an embodiment of the present invention, the preset analysis method includes the following steps S21, S22 and S23:

[0051] Step S21: For each x86 vector instruction, if the execution speed of the instruction after translating it into a RISC-V floating-point instruction is better than the execution speed of the instruction after translating it into a RISC-V vector instruction, the translation type indicator is set to floating-point class to indicate that it is translated into a floating-point instruction of the RISC-V instruction set; otherwise, the translation type indicator is set to vector class to indicate that it is translated into a vector instruction of the RISC-V instruction set.

[0052] During Dynamic Binary Translation (DBT), x86 vector instructions are translated into RISC-V instruction set vector instructions. The source code semantics of x86 programs are floating-point operations, but translating them into vector operations contradicts this semantics. Furthermore, in the RISC-V architecture, using floating-point registers for floating-point operations is generally faster than using vector registers. If the execution speed of the translated RISC-V floating-point instructions is better, then x86 vector instructions are translated into RISC-V instruction set floating-point instructions. Before translating to RISC-V instruction set floating-point instructions, it is necessary to obtain the mapping relationship from the x86 architecture's XMM registers to the RISC-V architecture's floating-point registers to achieve the translation. Therefore, according to an embodiment of the present invention, before analyzing each x86 vector instruction, the method further includes constructing a mapping relationship between each xMM register under the x86 architecture and each floating-point register under the RISC-V architecture. There are a total of 16 xmm registers in the x86 architecture, namely xmm0 to xmm15, and the corresponding mapping relationship is shown in Table 1 below.

[0053] Table 1

[0054]

[0055] According to one embodiment of the present invention, when an X86 vector instruction is translated into a floating-point instruction of the RISC-V instruction set, based on a constructed mapping relationship, operands that are XMM registers in the X86 vector instruction are translated into operands that are floating-point registers in the floating-point instruction of the RISC-V instruction set.

[0056] According to an embodiment of the present invention, step S21 includes: obtaining a pre-constructed record table, including a plurality of x86 vector instructions and a label for each instruction to be classified into a first-class instruction or a second-class instruction; if the execution speed of the x86 vector instruction after being translated into RISC-V floating-point instructions is better than the execution speed of the instruction after being translated into RISC-V vector instructions, it is labeled as a first-class instruction, otherwise it is labeled as a second-class instruction; according to the record table, determining the label of the x86 vector instructions in the translation block, setting the translation type indicator of the x86 vector instructions labeled as first-class instructions to floating-point class, and setting the translation type indicator of the x86 vector instructions labeled as second-class instructions to vector class.

[0057] According to one embodiment of the present invention, a class of instructions in the record table includes any one or a combination of the following instructions: MULSD, SQRTSD, SUBSD, UNPCKLPD, ROUNDSD, CVTSS2SD, CVTSI2SD, CVTSD2SI, CVITSD2SI, VCVITSD2SI, ADDSD, DIVSD, UCOMISD, COMISD, VUCOMISD, VCOMISD, MAXSD, MINSD, CMPSD, VCVTSI2SD, VCVTSS2SI, VMOVSD, VMOVQ, VMULSD, VADDSD, VDIVSD, VSUBSD, VSORTSD, VMAXSD, VMINSD, MOVLPS, MOVLPD, MOVQ, and MOVSD instructions.

[0058] The test results for a portion of the x86 vector instructions are shown in Table 2 below as an illustration:

[0059] Table 2

[0060]

[0061] In Table 2 above, the instruction execution speed (i.e., number of cycles) of CVTSS2SD, MULSD, DIVSD, and MOVSD after being translated into RISC-V floating-point instructions is better than that of their translation into RISC-V vector instructions. Here, v4, t5, fa6, s5, %0, and fa0 represent the operands of the instructions. The instructions MOVSD xmm6 (destination operand), m64 (destination operand, representing 64-bit memory) and MOVSD m64 (destination operand), xmm0 (source operand) represent different forms of the same MOVSD instruction. This means that different forms of the same instruction can be translated into RISC-V floating-point instructions using the method of this invention, thus achieving translation optimization.

[0062] Step S22: Obtain the usage information of the operands of the XMM register in each X86 vector instruction, including whether the bits of the XMM register are used by subsequent X86 vector instructions.

[0063] According to an embodiment of the present invention, in step S22, the usage of the operand of the XMM register in the X86 vector instruction is obtained based on the read / write status of the operand of the XMM register in the X86 vector instruction, the read / write status of the operand of the XMM register in subsequent X86 vector instructions, and the translation type indication of subsequent X86 vector instructions.

[0064] According to one embodiment of the present invention, the X86 vector instruction uses a preset read / write array to represent the read / write state (also known as the usedef state) of each XMM register. The preset read / write array includes: a first write value indicating whether the high 64 bits of the XMM register have been written and a first read value indicating whether they have been read; and a second write value indicating whether the low 64 bits of the XMM register have been written and a second read value indicating whether they have been read.

[0065] According to an embodiment of the present invention, the preset read / write array is represented by the following XMM_USEDEF structure, wherein the first write value, the first read value, the second write value, and the second read value are each 1 or 0, where 1 indicates yes and 0 indicates no.

[0066] Predefined read / write array: typedef struct1{

[0067] bool high64_use; / / Indicates the value read first.

[0068] bool high64_def; / / Indicates the first written value

[0069] bool low 64_use; / / Indicates the second read value

[0070] bool low 64_def; / / Indicates the second written value

[0071] }XMM_USEDEF

[0072] According to one embodiment of the present invention, a translation status record is performed for each x86 vector instruction. The translation status record includes recording the read / write status of the instruction with respect to the XMM register, and recording the translation type indicator of the instruction. The translation status record for each x86 vector instruction is represented using the following IR1_OPND_USEDEF structure:

[0073] typedef struct2{

[0074] bool is_xmm_translate; / / Translation type indicator

[0075] XMM_USEDEF opnd_xmm_usedef[4]; / / An x86 vector instruction can use up to 4 XMM registers, including the read and write status of each used XMM register.

[0076] }IR1_OPND_USEDEF

[0077] If is_xmm_translate is 1, it indicates that the translation type is floating-point, meaning the instruction is translated into a floating-point instruction of the RISC-V instruction set. If it is 0, it indicates that the translation type is vector, meaning the instruction is translated into a vector instruction of the RISC-V instruction set.

[0078] According to one embodiment of the present invention, the usage of operands in the XMM register in x86 vector instructions is represented by a preset usage array. The preset usage array includes: a first usage value, which indicates whether the high 64 bits of the XMM register in the x86 vector instruction are to be used by the subsequent x86 vector instruction translated into a RISC-V instruction set vector instruction; a second usage value, which indicates whether the low 64 bits of the XMM register in the x86 vector instruction are to be used by the subsequent x86 vector instruction translated into a RISC-V instruction set vector instruction; and a third usage value, which indicates whether the low 64 bits of the XMM register in the x86 vector instruction are to be used by the subsequent x86 vector instruction translated into a RISC-V instruction set floating-point instruction.

[0079] According to one embodiment of the present invention, the preset operands of each XMM register are represented using an array as follows:

[0080] _typedef struct3{

[0081] bool high64_vec_use; / / First value to use

[0082] bool low64_vec_use; / / Secondary value to use

[0083] bool low64_fp_use; / / Third-party value

[0084] }IR1_XMM_USE;

[0085] According to one embodiment of the present invention, IR1_XMM_USE_xmm_recent_use represents the usage of the operands of the 16 XMM registers, and xmm_recent_use includes the preset usage arrays corresponding to each of the 16 XMM registers.

[0086] The technical solution of the above embodiments can achieve at least the following beneficial technical effects: The read / write status of each XMM register used by x86 vector instructions is recorded using an XMM_USEDEF structure, along with a translation type indicator. An array IR1_XMM_USE is then used to record the usage of the XMM registers. This facilitates a better determination of whether the high 64 bits and low 64 bits of the XMM register require data synchronization. Furthermore, the high 64 bits and low 64 bits can be separately determined to determine whether data synchronization is required, thus providing a better reference basis for subsequent judgments regarding redundant operations on the high 64 bits.

[0087] According to one embodiment of the present invention, S22 includes constructing the initial usage of all XMM registers under the x86 architecture for each translation block; wherein, the initial usage construction method includes: performing data flow analysis on all subsequent translation blocks of the current translation block to obtain the initial usage of all XMM registers corresponding to each of the subsequent translation blocks; and obtaining the initial usage of all XMM registers corresponding to the current translation block based on the union of the initial usage of all XMM registers corresponding to all subsequent translation blocks. That is, the initial xmm_recent_use of the current translation block is the union of the initial xmm_recent_use of all subsequent translation blocks. Schematic, the initial usage of xmm0 recorded in the initial xmm_recent_use of one subsequent translation block is represented by a preset usage array (1, 0, 0), and the initial usage of xmm0 recorded in the initial xmm_recent_use of another subsequent translation block is represented by a preset usage array (0, 0, 1). Taking the union of these arrays yields a preset usage array of (1, 0, 1), which serves as the initial usage of xmm0 recorded in the initial xmm_recent_use of the current translation block. The usage information construction method in this embodiment is defined as the function _xmm_recent_use_of_succ().

[0088] The technical solution of the above-described embodiment for constructing the initial usage scenario can achieve at least the following beneficial technical effects: In existing translation block analysis, to ensure the correctness of the program algorithm, it is conservatively assumed that the high 64 bits and low 64 bits of all XMM registers will be used after the translation block, resulting in low data flow analysis accuracy for existing single translation blocks. However, this invention, when analyzing a translation block, performs recursive data flow analysis on these subsequent translation blocks, exploring as much as possible the usage of the operands of the 16 XMM registers by the subsequent translation blocks, thereby expanding the analysis scope of the translation block and obtaining a more accurate initial usage scenario corresponding to the current translation block, thus improving the data flow analysis accuracy of the translation block.

[0089] Step S23: Generate a translation flag based on the usage of the operand, including a cancellation flag indicating whether to translate a preset number of bits of the operand in the XMM register. When the translation of the preset number of bits is a redundant operation, the cancellation flag indicates no.

[0090] According to an embodiment of the present invention, in step S23, the translation identifier further includes a first synchronization instruction (represented by _fp_xmm_sync), a second synchronization instruction (represented by _xmm_fp_sync), and a cancellation flag (represented by _xmm_is_high_64_used). The first synchronization instruction, the second synchronization instruction, and the cancellation flag are described below:

[0091] 1) First synchronization instruction

[0092] According to one embodiment of the present invention, the first synchronization instruction indicates whether the operands of the XMM register in the current x86 vector instruction should be synchronized from floating-point to vector. Whether to perform floating-point to vector synchronization indicates whether to copy the data of the floating-point register under the RISC-V architecture corresponding to the XMM register to the vector register under the same RISC-V architecture corresponding to the XMM register.

[0093] Specifically, the first synchronization instruction is set to "Yes" when the following first preset conditions are met, and set to "No" otherwise. The first preset conditions include: the operand of the XMM register in the current X86 vector instruction is written to the lower 64 bits, and the operand of the same XMM register is read by the subsequent X86 vector instruction; and the current X86 vector instruction is translated into a floating-point instruction of the RISC-V instruction set, and the subsequent X86 vector instruction is translated into a vector instruction of the RISC-V instruction set.

[0094] 2) Second synchronization instruction

[0095] According to one embodiment of the present invention, the second synchronization instruction indicates whether the operand of the XMM register in the current x86 vector instruction should be synchronized from vector to floating point. Wherein, whether to perform vector-to-floating point synchronization indicates whether to copy the data of the vector register under the RISC-V architecture corresponding to the XMM register to the floating point register under the same RISC-V architecture corresponding to the same XMM register.

[0096] Specifically, the second synchronization instruction is set to "Yes" when the following second preset conditions are met, and set to "No" otherwise. The second preset conditions include: the operand of the XMM register in the current x86 vector instruction is written to the lower 64 bits, and the subsequent x86 vector instruction reads the lower 64 bits of the operand of the same XMM register; and the current x86 vector instruction is translated into a vector instruction of the RISC-V instruction set, and the subsequent x86 vector instruction is translated into a floating-point instruction of the RISC-V instruction set.

[0097] The following examples illustrate the setting of the first and second synchronization instructions:

[0098] Example 1: Taking the first XMM register xmm0 as an example. The translation block includes three x86 vector instructions, inst1, inst2, and inst3. These three x86 vector instructions perform the following operations on xmm0 in sequence: xmm0 is written to its lower 64 bits, xmm0 is read from its lower 64 bits, and xmm0 is read from its lower 64 bits. These three x86 vector instructions are then translated into RISC-V instruction set floating-point instructions, RISC-V instruction set floating-point instructions, and RISC-V instruction set vector instructions, respectively.

[0099] Based on Example 1 above, when analyzing the x86 vector instruction `inst1`, after `inst1` is translated, its execution will write the latest value originally written to the lower 64 bits of `xmm0` into the floating-point register `fa0` in the corresponding RISC-V architecture. After the subsequent instruction `inst2` is translated, its execution will read the lower 64 bits of the floating-point register `fa0` in the RISC-V architecture corresponding to `xmm0`, indicating that the value read is the latest value written to `fa0`. Therefore, for the subsequent `inst2`, it is determined that the translation of the `inst1` instruction does not require data synchronization, and both the first and second synchronization instructions for `xmm0` are set to "no". After the subsequent instruction `inst3` is translated, it will read the lower 64 bits of the vector register in the RISC-V architecture corresponding to `xmm0`, but it actually needs to read the latest value written to the floating-point register `fa0` by the translated instruction of `inst1`. Therefore, for the subsequent inst3, it is determined that the translation of the inst1 instruction requires floating-point to vector synchronization, and the first synchronization instruction for XMM0 is set to yes. This is to copy the data of the floating-point register fa0 under the RISC-V architecture corresponding to xmm0 to the vector register under the RISC-V architecture corresponding to xmm0.

[0100] Example 2: Similar to Example 1, only the translation type indications for the three x86 vector instructions are changed. For example, the three x86 vector instructions are sequentially translated into RISC-V instruction set vector instructions, RISC-V instruction set floating-point instructions, and RISC-V instruction set vector instructions. When analyzing inst1, it is determined that the translation of the inst1 instruction requires vector-to-floating-point synchronization. The second synchronization instruction for xmm0 is set to "Yes," and the first synchronization instruction is set to "No."

[0101] The technical solutions in the above embodiments can achieve at least the following beneficial technical effects: Because two translation methods are performed, some data is written to the vector register and some data is written to the floating-point register, leading to problems such as the inability to read the latest data, which may cause translation errors. This invention uses a designed first synchronization instruction and a second synchronization instruction to indicate whether data needs to be synchronized to the corresponding register, thus achieving the synchronization of the latest data.

[0102] 3) Eliminate signs

[0103] According to an embodiment of the present invention, in step S23, the preset bit depth is the high 64 bits. For the current X86 vector instruction, the elimination flag is set as follows: when the operand of the XMM register is written to the high 64 bits in the current X86 vector instruction and the subsequent X86 vector instruction reads the high 64 bits of the operand of the same XMM register, the elimination flag is set to yes, indicating that the high 64 bits of the operand of the same XMM register are translated; when the high 64 bits of the operand of the same XMM register are not read in the subsequent X86 vector instruction, the translation of the high 64 bits of the operand of the same XMM register is a redundant operation, and the elimination flag is set to no, indicating that the high 64 bits of the operand of the same XMM register are not translated.

[0104] According to one embodiment of the present invention, if the high 64 bits of the operand in the subsequent x86 vector instruction are not read into the same XMM register, then the instruction operation of clearing or maintaining the high 64 bits of the operand in the XMM register is a redundant operation. Furthermore, when using the method of the present invention to translate some floating-point instructions and some vector instructions into the RISC-V instruction set, if the translation of the high 64 bits of the operand in the XMM register is a redundant operation, then data synchronization of the high 64 bits is not required. The technical solution of this embodiment can achieve at least the following beneficial technical effects: effectively eliminating the redundant instruction translation of clearing and maintaining the high bits of the XMM register, and eliminating the need for high 64-bit data synchronization, thus improving translation performance by eliminating the need to issue additional data synchronization instructions during translation.

[0105] According to one embodiment of the present invention, the first synchronization instruction (_fp_xmm_sync), the second synchronization instruction (_xmm_fp_sync), and the cancellation flag (_xmm_is_high_64_used) are each set to 1 or 0, where 1 indicates yes and 0 indicates no.

[0106] According to an embodiment of the present invention, based on the analysis process for each X86 vector instruction in steps S21-S23 described above, the overall analysis process for each translation block is described below: In step S2, the preset analysis method includes: for each translation block, analyzing each X86 vector instruction sequentially from the last X86 vector instruction of the translation block backwards to obtain the translation instruction information for each X86 vector instruction. Specifically, when analyzing each X86 vector instruction, the operands of each XMM register under that instruction are analyzed in the following manner, and their current usage is updated to obtain the updated usage:

[0107] Based on the read / write status of the current X86 vector instruction, the read / write status of the subsequent X86 vector instruction, and the translation type indications of the current and subsequent X86 vector instructions;

[0108] When the operand is the destination operand, the analysis method includes: if the high 64 bits of the operand are redundant operations, set the elimination flag to yes and update the first used value indicator to no; otherwise, set the elimination flag to no; determine whether the first preset condition is met and update the second used value indicator to no; if met, set the first synchronization instruction indicator to yes; otherwise, set the first synchronization instruction indicator to no; determine whether the second preset condition is met and update the third used value indicator to no; if met, set the second synchronization instruction indicator to yes; otherwise, set the second synchronization instruction indicator to no.

[0109] When the operand is the source operand, the analysis method includes: if the high 64 bits of the operand in the subsequent x86 vector instruction are read from the XMM register, update the first use value indicator to "Yes"; if the subsequent x86 vector instruction uses vector instruction translation of the RISC-V instruction set and the low 64 bits of the operand in the XMM register are read, update the second use value indicator to "Yes"; if the subsequent x86 vector instruction uses floating-point instruction translation of the RISC-V instruction set and the low 64 bits of the operand in the XMM register are read, update the third use value indicator to "Yes".

[0110] In the overall analysis of each translation block as described in the above embodiment, for each operand of the XMM register under each X86 vector instruction, when the operand of the XMM register is analyzed for the first time, the current usage is the initial usage corresponding to the translation block. After the first analysis, each time the operand of the XMM register is analyzed, the current usage of the operand of the XMM register adopts the usage after the previous update.

[0111] According to one embodiment of the present invention, the overall analysis process for each translation block is denoted as the `xmm_lazy_sync_analysis()` function. When an x86 vector instruction is encountered, the read / write status of the corresponding XMM register is read. The first read value and the second read value are stored in `xmm_curr_use`, and the first write value and the second write value are stored in `xmm_curr_def`. The first read value and the second read value represent the read status of the high 64 bits and low 64 bits of the XMM register, respectively, and the first write value and the second write value represent the write status of the high 64 bits and low 64 bits of the XMM register, respectively. In this way, `xmm_curr_use` and `xmm_curr_def` are constructed for each x86 vector instruction, where `xmm_curr_use` includes the read status of the instruction on 16 XMM registers, and `xmm_curr_def` includes the write status of the instruction on the 16 XMM registers.

[0112] According to one embodiment of the present invention, see Figure 2 This is a schematic diagram illustrating the complete analysis process for each translation block. It includes the following steps a1-a9:

[0113] a1. At the beginning, initialize pir1 to point to the last x86 vector instruction of the current translation block;

[0114] a2. Initialize xmm_curr_opnd to point to the first operand of the current x86 vector instruction;

[0115] a3. Determine if the operand pointed to by xmm_curr_opnd is the XMM register. If it is, jump to a4; otherwise, jump to a8.

[0116] a4. Read the static table, which includes the read and write status of each X86 vector instruction in the translation block to each XMM register. Obtain the read and write status of the XMM register pointed to by xmm_curr_opnd from the static table, store the first read value and the second read value in the read and write status into xmm_curr_use, and store the first write value and the second write value into xmm_curr_def.

[0117] a5. Determine if the XMM register pointed to by xmm_curr_opnd is the destination operand. If yes, jump to a6; otherwise, if it is the source operand, jump to a7.

[0118] a6. The analysis method adopted in the above embodiment when it is the destination operand includes: calling the xmm_flag_analysis() function, setting the first synchronization instruction (_fp_xmm_sync), the second synchronization instruction (_xmm_fp_sync), and the elimination flag (_xmm_is_high_64_used) according to the read / write status of the XMM register pointed to by the current X86 vector instruction, the read / write status of the XMM register pointed to by the subsequent X86 vector instruction, and the translation type indications of the current X86 vector instruction and the subsequent X86 vector instruction, and updating the current usage of the XMM register to obtain the updated _xmm_recent_use of the current translation block;

[0119] a7. The analysis method adopted in the above embodiment when it is the source operand includes: updating the current usage of the XMM register according to the xmm_curr_use corresponding to the pointed XMM register, the translation type indication of the current X86 vector instruction and the subsequent X86 vector instruction, to obtain the updated _xmm_recent_use of the current translation block, and jumping to a8.

[0120] a8. Determine if the operand pointed to by xmm_curr_opnd is the last operand of the current x86 vector instruction. If not, xmm_curr_opnd points to the next operand of the current x86 vector instruction and jumps to a3. If it is, jump to a9.

[0121] a9. Determine if pir1 points to the first x86 vector instruction of the current translation block. If not, pir1 points to the previous x86 vector instruction and jumps to a2. If yes, end the overall analysis of the translation block.

[0122] Specifically, for the same XMM register, each execution of the a5-a7 process on the XMM register represents one analysis of the XMM register and one update of its usage status.

[0123] According to one embodiment of the present invention, see Figure 3 This is a schematic diagram illustrating the analysis process of the destination operand. The diagram shows the execution principle of the xmm_flag_analysis() function called in a6 of the above embodiment. The execution process of this function includes the following steps b1-b8:

[0124] b1. Determine whether the current XMM register has only been written to (def indicates) the lower 64 bits, and whether the subsequent X86 vector instruction reads (uses) the lower 64 bits of the XMM register; if yes, jump to b2; otherwise, jump to b5.

[0125] b2. Determine whether the current X86 vector instruction needs data synchronization. If yes, jump to b3; otherwise, jump to b4.

[0126] b3. Determine whether vector-to-floating-point synchronization is needed. If yes, set _xmm_fp_sync to 1 and jump to b4. Otherwise, floating-point-to-vector synchronization is needed, set _fp_xmm_sync to 1, and jump to b4.

[0127] b4. Update the usage status of the corresponding XMM register, including: set the second and third usage values ​​in the current XMM register usage status recorded in xmm_recent_use to 0, and jump to b;

[0128] b5. Determine whether the high 64 bits of the current XMM register have been written (def) and whether the high 64 bits of the XMM register have been read (use) by subsequent X86 vector instructions. If yes, jump to b6; otherwise, jump to b8.

[0129] b6. Set the elimination flag (_xmm_is_high_64_used) to 1, and set the first used value in the current XMM register usage recorded by xmm_recent_use to 0, then jump to b7;

[0130] b7. Has the lower 64 bits of the XMM register been written to (def) and then the lower 64 bits of the XMM register were subsequently read (use) by the X86 vector instruction? If yes, jump to b2; otherwise, jump to b8.

[0131] b8. End and return.

[0132] According to one embodiment of the present invention, all translation blocks are analyzed based on the aforementioned _xmm_recent_use_of_succ() and xmm_flag_analysis() functions. See also Figure 4 This is a schematic diagram of the overall process for analyzing all translation blocks. The overall process is denoted as the xmm_sync_reduction() function, which includes the following c1-c5:

[0133] c1. At the beginning, determine whether the translation block has been analyzed. If so, jump to c5; otherwise, continue to execute c2.

[0134] c2. Mark the translation block as being analyzed and disassemble it;

[0135] c3. Call the _xmm_recent_use_of_succ() function to obtain the initial _xmm_recent_use of the subsequent translation block, construct the initial usage of each XMM register under the X86 architecture for the translation block, and obtain the initial usage of all XMM registers of the translation block in terms of _xmm_recent_use.

[0136] c4. Call the xmm_lazy_sync_analysis() function to analyze the translation block and update the initial _xmm_recent_use of the translation block;

[0137] c5. Mark the translated block as analyzed and return.

[0138] According to one embodiment of the present invention, see Figure 5 This is a diagram illustrating the execution process of the _xmm_recent_use_of_succ() function, which includes the following processes d1-d8:

[0139] d1. At the beginning, determine whether the current translation block ends with a conditional jump. If yes, jump to d2; otherwise, jump to d3. Translation blocks that end with a conditional jump include two or more subsequent translation blocks.

[0140] d2. Obtain all subsequent translation blocks of the current translation block. Each subsequent translation block calls the compute_xmm_recent_use() function to obtain the initial usage state _xmm_recent_use of each subsequent translation block. Perform a bitwise logical OR operation on the initial usage states _xmm_recent_use of all subsequent translation blocks to obtain the initial _xmm_recent_use of the current translation block, and then jump to d8.

[0141] d3. Determine if the translation block ends directly. If yes, jump to d4; otherwise, jump to d5. Direct jump indicates that the translation block has only one successor translation block.

[0142] d4. Obtain a successor translation block of the translation block. The successor translation block calls the compute_xmm_recent_use() function to obtain the initial usage state _xmm_recent_use of the successor translation block, and use it as the initial usage state _xmm_recent_use of the current translation block. Then jump to d8.

[0143] d5. Determine if the translation block ends with an indirect jump. If yes, jump to d6; otherwise, jump to d7. The jump position cannot be determined for blocks ending with indirect jumps.

[0144] d6. Set all initial usage states of the current translation block, _xmm_recent_use, to 1, and then jump to d8;

[0145] d7. Determine if the translation block ends with a call instruction. If so, set the initial usage state of the current translation block _xmm_recent_use according to the Application Binary Interface (ABI) and then jump to d8. If not, set the initial usage state of the current translation block _xmm_recent_use according to the ABI function calling convention and then jump to d8.

[0146] d8. Mark the current translation block as being analyzed.

[0147] In the process of classifying and discussing the type of jump at the end of the translation block, the _xmm_recent_use_of_succ() function assumes that the subsequent translation block uses all bits of the XMM registers if it is an indirect jump. Conservatively speaking, all elements of _xmm_recent_use are 1.

[0148] According to one embodiment of the present invention, see Figure 6 This is a diagram illustrating the execution process of the compute_xmm_recent_use() function, which includes the following processes e1-e6:

[0149] e1. At the beginning, determine whether the current translation block has been analyzed. If not, disassemble the translation block and jump to e2; otherwise, jump to e7.

[0150] e2. Determine if the current translation block is being analyzed. If not, jump to e3; if so, jump to e6.

[0151] e3. Call the _xmm_recent_use_of_succ() function to get the initial _xmm_recent_use of the current translation block, and then jump to e4.

[0152] e4. Based on the initial _xmm_recent_use of the current translation block, call the xmm_lazy_sync_analysis() function to analyze the current translation block, update the initial _xmm_recent_use of the current translation block, and jump to e5;

[0153] e5. Mark the translated block as analyzed and jump to e7;

[0154] e6. Instead of obtaining the initial _xmm_recent_use of the subsequent translation block, directly use the latest updated _xmm_recent_use of the current translation block, call the xmm_lazy_sync_analysis() function to analyze the current translation block based on the latest updated _xmm_recent_use, update the latest updated _xmm_recent_use of the current translation block again, and jump to e7;

[0155] e7. End and return.

[0156] Each time the `compute_xmm_recent_use()` function is called, the translation block checks if it is currently being analyzed. If so, it doesn't search for the initial `_xmm_recent_use` of the subsequent translation block; instead, it uses the latest updated `_xmm_recent_use` of the current translation block for analysis and then returns E7. In other words, while the translation block is being analyzed, for each XMM register under each x86 vector instruction in the translation block, the first analysis of the XMM register is based on the initial usage `_xmm_recent_use` corresponding to that translation block. Subsequent analyses of the XMM register are based on its previous updated usage.

[0157] Step S3: Translate each X86 vector instruction according to the translation instruction information of each X86 vector instruction in the assembly instruction set of each translation block to obtain the RISC-V instruction set program.

[0158] According to one embodiment of the present invention, the x86 vector instruction is translated into a RISC-V instruction set vector instruction or a RISC-V instruction set floating-point instruction based on the translation type indication. At the same time, based on the first synchronization instruction (_fp_xmm_sync), the second synchronization instruction (_xmm_fp_sync), and the cancellation flag (_xmm_is_high_64_used) in the translation identifier, it is determined whether data synchronization between the floating-point register and the vector register is required during the translation process, and whether the preset high 64-bit related instruction operations are translated.

[0159] According to an embodiment of the present invention, a binary translation system for implementing the method of the above embodiments is provided, see [link to documentation]. Figure 7This is a schematic diagram of a binary translation system architecture. The system includes: a disassembly module, used to divide the binary x86 program into multiple translation blocks and disassemble each translation block to obtain the assembly instruction set of each translation block; a backward data flow analysis module, used to obtain translation indication information of each x86 vector instruction in the assembly instruction set of each translation block according to a preset analysis method, including translation type indication and translation identifier; and a translation module, used to translate each x86 vector instruction according to the translation indication information of each x86 vector instruction in the assembly instruction set of each translation block to obtain a RISC-V instruction set program. The RISC-V instruction set program represents the target ISA instruction set program. Specifically, the disassembly module executes step S1 of the above embodiment, the backward data flow analysis module executes step S2 of the above embodiment, and its output translation indication information guides the elimination of redundant data synchronization instructions and unnecessary high-order operation instructions; the translation module executes step S3 of the above embodiment.

[0160] In addition, the backward data flow analysis module is also used to call the disassembly module to execute the _xmm_recent_use_of_succ() function before analyzing each translation block according to the preset analysis method. This enables data flow analysis of all subsequent translation blocks of the current translation block, obtaining the initial usage of each XMM register corresponding to the current translation block. This further expands the number of translation blocks analyzed, thereby improving the analysis accuracy.

[0161] It should be noted that although the steps are described in a specific order above, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently, or even in a different order, as long as the required function can be achieved.

[0162] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0163] Computer-readable storage media can be tangible devices that hold and store instructions for use by an instruction execution device. Computer-readable storage media can include, for example, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0164] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for vector instruction translation of the XMM register in an X86 program during binary translation, comprising: S1. Divide the binary form of the X86 program into multiple translation blocks, and disassemble each translation block to obtain the assembly instruction set of each translation block; S2. Obtain the translation instruction information of each X86 vector instruction in the assembly instruction set of each translation block according to the preset analysis method, including translation type indication and translation identifier. The analysis method includes: S21. For each x86 vector instruction, if the execution speed of the instruction after translating it into a RISC-V floating-point instruction is better than the execution speed of the instruction after translating it into a RISC-V vector instruction, the translation type indicator is set to floating-point class to indicate that it is translated into a floating-point instruction of the RISC-V instruction set; otherwise, the translation type indicator is set to vector class to indicate that it is translated into a vector instruction of the RISC-V instruction set. S22. Obtain the usage information of the operands of the XMM register in each X86 vector instruction, including whether the bits of the XMM register are used by subsequent X86 vector instructions; S23. Based on the usage of the operands, generate a translation identifier, including a cancellation flag indicating whether a preset number of bits of the operands in the XMM register should be translated. When the translation of the preset number of bits is a redundant operation, the cancellation flag indicates no. The translation identifier further includes: The first synchronization instruction indicates whether the operands of the XMM register in the current X86 vector instruction should be synchronized from floating point to vector. It indicates whether the data of the floating point register under the RISC-V architecture corresponding to the XMM register should be copied to the vector register under the same RISC-V architecture corresponding to the XMM register. The first synchronization instruction is set to yes when the following first preset condition is met, and set to no otherwise: In the current x86 vector instruction, the operand of the XMM register is written to the lower 64 bits, and subsequent x86 vector instructions read the lower 64 bits of the operand of the same XMM register. And current x86 vector instructions are translated into floating-point instructions of the RISC-V instruction set, and subsequent x86 vector instructions are translated into vector instructions of the RISC-V instruction set; S3. Based on the translation instruction information of each X86 vector instruction in the assembly instruction set of each translation block, translate each X86 vector instruction to obtain the RISC-V instruction set program.

2. The method according to claim 1, characterized in that, In S23, the translation identifier also includes: The second synchronization instruction indicates whether the operand of the XMM register in the current X86 vector instruction should be synchronized from vector to floating point. It indicates whether the data of the vector register under the RISC-V architecture corresponding to the XMM register should be copied to the floating point register under the RISC-V architecture corresponding to the same XMM register. The second synchronization instruction is set to yes when the following second preset conditions are met, and set to no otherwise: In the current x86 vector instruction, the operand of the XMM register is written to the lower 64 bits, and subsequent x86 vector instructions read the lower 64 bits of the operand of the same XMM register. And current x86 vector instructions are translated into RISC-V instruction set vector instructions, and subsequent x86 vector instructions are translated into RISC-V instruction set floating-point instructions.

3. The method according to claim 1, characterized in that, In step S23, the preset bit length is the high 64 bits, and the elimination flag is set for the current x86 vector instruction in the following manner: When the operand of the XMM register is written to the high 64 bits in the current X86 vector instruction and the subsequent X86 vector instruction reads the high 64 bits of the operand of the same XMM register, the cancellation flag is set to yes, which indicates that the high 64 bits of the operand of the same XMM register are translated. When the high 64 bits of the operand in the same XMM register are not read in the subsequent x86 vector instruction, the high 64 bits of the operand in the same XMM register are translated as a redundant operation. The cancellation flag indicates no, which means that the high 64 bits of the operand in the same XMM register are not translated.

4. The method according to claim 1, characterized in that, In step S22, the usage of operands in the X86 vector instruction relative to the XMM register is obtained based on the read / write status of the operand in the XMM register by the X86 vector instruction, the read / write status of the operand in the XMM register by subsequent X86 vector instructions, and the translation type indication of subsequent X86 vector instructions. The usage is represented by a preset usage array, which includes: The first value used indicates whether the high 64 bits of the XMM register in the x86 vector instruction should be used by the subsequent x86 vector instruction translated into a RISC-V instruction set vector instruction. The second value indicates whether the lower 64 bits of the XMM register in the x86 vector instruction should be translated into the subsequent x86 vector instruction of the RISC-V instruction set. The third value indicates whether the lower 64 bits of the XMM register in the x86 vector instruction should be translated into the subsequent x86 vector instruction of the RISC-V instruction set for use as a floating-point instruction. Read and write states are represented by a preset read and write array, which includes: Indicates whether the first write value has been written to the high 64 bits of the XMM register and whether the first read value has been read from the XMM register; The second write value indicates whether the lower 64 bits of the XMM register have been written and the second read value has been read.

5. The method according to claim 4, characterized in that, S22 includes constructing the initial usage of all XMM registers under the X86 architecture for each translation block; The initial usage scenario construction method includes: Perform data flow analysis on all subsequent translation blocks of the current translation block to obtain the initial usage of each XMM register corresponding to each subsequent translation block; The initial usage of all XMM registers corresponding to the current translation block is obtained by taking the union of the initial usage of all XMM registers corresponding to all subsequent translation blocks.

6. The method according to claim 5, characterized in that, In S2, the preset analysis method includes: for each translation block, sequentially analyzing each X86 vector instruction backward from the last X86 vector instruction of the translation block to obtain the translation instruction information for each X86 vector instruction. Specifically, when analyzing each X86 vector instruction, the operands of each XMM register under that instruction are analyzed in the following manner, and their current usage is updated to obtain the updated usage: Based on the read / write status of the current x86 vector instruction, the read / write status of the subsequent x86 vector instruction, and the translation type indicators of the current and subsequent x86 vector instructions, when it is the destination operand, the analysis method includes: If the high 64 bits of the operand are redundant, set the elimination flag to yes and update the first used value indicator to no; otherwise, set the elimination flag to no. Determine whether the first preset condition is met, and update the second usage value indicator to no. If it is met, set the first synchronization instruction indicator to yes; otherwise, set the first synchronization instruction indicator to no. Determine whether the second preset condition is met, and update the third use value indicator to no. If it is met, set the second synchronization instruction indicator to yes; otherwise, set the second synchronization instruction indicator to no. When it is a source operand, the analysis methods include: If the high 64 bits of the operand of the XMM register are read in a subsequent x86 vector instruction, update the first used value indicator to yes. If the subsequent x86 vector instruction is translated into a RISC-V instruction set vector instruction, and the lower 64 bits of the operand of the XMM register are read, update the second use value indicator to yes; If the subsequent x86 vector instruction is translated into a floating-point instruction of the RISC-V instruction set, and the lower 64 bits of the operand of the XMM register are read, update the third use value indicator to yes; In each translation block, when the operands of the XMM register are analyzed for the first time, the current usage is the initial usage of the XMM register corresponding to that translation block. In subsequent analyses of the operands of the XMM register, the current usage of the operands is the usage after the previous update.

7. The method according to claim 1, characterized in that, S21 includes: Obtain a pre-built record table, including multiple x86 vector instructions and a label for each instruction to be classified as either a Class I or Class II instruction. If the execution speed of an x86 vector instruction translated into RISC-V floating-point instructions is better than that of an instruction translated into RISC-V vector instructions, it is marked as a Class I instruction; otherwise, it is marked as a Class II instruction. Based on the record table, the markers of X86 vector instructions in the translation block are determined. The translation type indicator of X86 vector instructions marked as Class 1 instructions is set to floating point class, and the translation type indicator of X86 vector instructions marked as Class 2 instructions is set to vector class.

8. The method according to claim 7, characterized in that, The X86 vector instructions in the record table, which are categorized into one class, include any one of the following instructions or a combination of the following instructions: MULSD, SQRTSD, SUBSD, UNPCKLPD, ROUNDSD, CVTSS2SD, CVTSI2SD, CVTSD2SI, CVITSD2SI, VCVITSD2SI, ADDSD, DIVSD, UCOMISD, COMISD, VUCOMISD, VCOMISD, MAXSD, MINSD, CMPSD, VCVTSI2SD, VCVTSS2SI, VMOVSD, VMOVQ, VMULSD, VADDSD, VDIVSD, VSUBSD, VSORTSD, VMAXSD, VMINSD, MOVLPS, MOVLPD, MOVQ, and MOVSD instructions.

9. The method according to claim 1, characterized in that, The method also includes constructing a mapping relationship between each XMM register under the x86 architecture and each floating-point register under the RISC-V architecture; Specifically, when an X86 vector instruction is translated into a floating-point instruction of the RISC-V instruction set, based on the mapping relationship, operands that are XMM registers in the X86 vector instruction are translated into operands that are floating-point registers in the RISC-V instruction set floating-point instruction.

10. A binary translation system for implementing the method of any one of claims 1-9, characterized in that, The system includes: The disassembler module is used to divide the binary form of an x86 program into multiple translation blocks and disassemble each translation block to obtain the assembly instruction set of each translation block; The backward data flow analysis module is used to obtain the translation indication information of each X86 vector instruction in the assembly instruction set of each translation block according to the preset analysis method, including translation type indication and translation identifier; The translation module is used to translate each x86 vector instruction according to the translation instruction information of each x86 vector instruction in the assembly instruction set of each translation block, so as to obtain the RISC-V instruction set program.

11. A computer-readable storage medium, characterized in that, It stores a computer program that can be executed by a processor to implement the steps of the method according to any one of claims 1-9.

12. An electronic device, characterized in that, include: One or more processors; as well as Memory, wherein the memory is used to store executable instructions; The one or more processors are configured to implement the steps of the method according to any one of claims 1-9 by executing the executable instructions.

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