Battery system based on double processors, firmware upgrading method, equipment and medium

Abstract

The invention is suitable for the technical field of battery management systems, and provides a battery system based on double processors, a firmware upgrading method and device and a medium, and the system comprises an inverter which is used for sending a firmware package; the main BMS comprises a first ARM processor and a first DSP processor which have different functions, the first ARM processor is connected with the inverter, and the first DSP processor is connected with the first ARM processor; the slave BMS comprises a second ARM processor and a second DSP processor which have different functions, the second ARM processor is connected with the first ARM processor, and the second DSP processor is connected with the second ARM processor; and the first ARM processor is used for storing a firmware package, sending the firmware package to the corresponding processor of the master BMS and distributing the firmware package to the corresponding processors of the plurality of slave BMSs for firmware upgrading according to the target processor type. In the firmware upgrading process, system functions are not affected, resource occupation is effectively reduced, the situation that all storage space is occupied is avoided, upgrading time is short, and efficiency is high.

Description

Technical Field

[0001] The present invention belongs to the technical field of battery management systems, and in particular relates to a dual-processor-based battery system, a firmware upgrade method, a device, and a medium. Background Art

[0002] Currently, the battery management system (BMS) firmware upgrade technologies mainly include: (1) centralized upgrade, which mainly involves connecting devices one by one through a host computer to perform upgrade operations. This method relies on physical interfaces (such as UART and USB) to implement upgrades. Since the firmware upgrade operation needs to be performed on each device, it cannot support parallel upgrade operations on multiple devices, making the firmware upgrade time-consuming and inefficient. (2) single processor architecture, which uses only one of the ARM or MCU processors. The communication and real-time control functions are not separated in the architecture. Therefore, during the firmware upgrade, the system functions are affected and the real-time monitoring of the battery pack is affected.

[0003] Therefore, there are problems in the art such as low firmware upgrade efficiency and impact on system functions during the firmware upgrade process. Summary of the Invention

[0004] An embodiment of the present invention provides a dual-processor based battery system, aiming to solve the problem of low firmware upgrade efficiency and impact on system functions.

[0005] The embodiment of the present invention is implemented as follows: a dual-processor-based battery system, comprising: Inverter, used to send firmware packages; A master BMS, the master BMS including a first ARM processor and a first DSP processor having different functions, the first ARM processor being connected to the inverter, and the first DSP processor being connected to the first ARM processor; a plurality of slave BMSs, each of which includes a second ARM processor and a second DSP processor having different functions, the second ARM processor being connected to the first ARM processor, and the second DSP processor being connected to the second ARM processor; The first ARM processor is used to store the firmware package, and, according to the target processor type of the firmware package, send the firmware package to the corresponding processor of the master BMS and distribute it to the corresponding processors of the multiple slave BMSs to perform firmware upgrade.

[0006] Furthermore, the first ARM processor is connected to the inverter via a first CAN bus, the first DSP processor is connected to the first ARM processor via a 485 bus, the first ARM processor is connected to the second ARM processor via a second CAN bus, and the second DSP processor is connected to the second ARM processor via a 485 bus.

[0007] Furthermore, the first ARM processor is further configured to dynamically allocate addresses to the plurality of second ARM processors.

[0008] An embodiment of the present invention further provides a firmware upgrade method, which is implemented based on the battery system. The firmware upgrade method includes: Receive and store the firmware package sent by the inverter; Identify the target processor type of the firmware package, the target processor type including ARM processor and DSP processor; According to the target processor type, the firmware package is sent to a corresponding processor of the master BMS and corresponding processors of the plurality of slave BMSs to perform firmware upgrade.

[0009] Furthermore, according to the target processor type, the firmware package is sent to a corresponding processor of the master BMS and corresponding processors of the plurality of slave BMSs to perform a firmware upgrade, including: In a case where the target processor type includes an ARM processor, writing the firmware package into a first storage area in a memory of the first ARM processor; Distributing the firmware package to the second ARM processor of each slave BMS, so that each second ARM processor performs a firmware upgrade according to the firmware package and then restarts; When each of the second ARM processors completes the firmware upgrade, the first ARM processor is restarted to complete the firmware upgrade.

[0010] Furthermore, according to the target processor type, the firmware package is sent to a corresponding processor of the master BMS and corresponding processors of the plurality of slave BMSs to perform a firmware upgrade, including: In a case where the target processor type includes a DSP processor, writing the firmware package into a second storage area in the memory of the first ARM processor; Sending the firmware package to the first DSP processor and writing it into the memory of the first DSP processor, so that the first DSP processor performs a firmware upgrade according to the firmware package and then restarts; The firmware package is distributed to the second ARM processor of each of the slave BMSs, so that the firmware package is sent to the corresponding second DSP processor through each of the second ARM processors.

[0011] Furthermore, before identifying the target processor type of the firmware package, the method further includes: Performing integrity check on the firmware package; If the integrity check passes, verify the serial number and / or check code of the firmware package; If the serial number and / or the check code of the firmware package pass the verification, the target processor type of the firmware package is identified.

[0012] Furthermore, the firmware upgrade method further includes: verifying the write operation of the firmware package.

[0013] An embodiment of the present invention further provides an electronic device, including: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the firmware upgrade method.

[0014] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program implements the firmware upgrade method when executed by a processor.

[0015] Since the present invention integrates ARM and DSP dual processors with different functions, it fully utilizes the division of labor and cooperation between the ARM processor and the DSP processor. There is no need to disassemble each device one by one to perform firmware upgrade operations. The ARM and DSP firmware can be upgraded independently and multiple devices can be upgraded in parallel. System functions are not affected during the firmware upgrade process, and resource usage is effectively reduced to avoid occupying all storage space. The upgrade takes a short time and is highly efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of a dual-processor-based battery system provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of address allocation provided by an embodiment of the present invention; Figure 3 Schematic diagram of a multi-level verification mechanism provided by an embodiment of the present invention; Figure 4 This is a flowchart of a firmware upgrade method provided by an embodiment of the present invention; Figure 5This is an example of the firmware upgrade process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0018] At present, the battery management system (BMS) firmware upgrade technology mainly includes: (1) centralized upgrade, which is mainly performed by connecting the upper computer to each device one by one. This method relies on physical interfaces (such as UART and USB) to achieve the upgrade. Since the firmware upgrade operation needs to be carried out by disassembling each device one by one, it cannot support the parallel upgrade operation of multiple devices, making the firmware upgrade time-consuming and inefficient. (2) single processor architecture, which only uses one of the ARM or MCU processors. The communication and real-time control functions are not separated in the architecture, and the division of labor and cooperation between ARM and DSP is not fully utilized. Therefore, during the firmware upgrade, the system function is affected, the system function is easily interrupted, and may even stop completely, which will affect the real-time monitoring of the battery pack.

[0019] In addition to the above problems, the prior art also has the following defects: Poor protocol compatibility: Static address allocation is used, and device addresses are assigned through hardware dial switches or fixed codes. Dynamic expansion is not supported. Static address allocation limits the number of devices (usually ≤8), device scalability is limited, and hot plugging is not supported.

[0020] Insufficient security: The lack of a multi-level verification mechanism makes it easy for the system to crash due to data errors.

[0021] High resource usage: Firmware upgrades require all storage space, and module updates cannot be performed separately.

[0022] Based on the above problems, an embodiment of the present invention provides a dual-processor based battery system, which at least solves the problems of low firmware upgrade efficiency and impact on system functions, and at least can bring about parallel upgrades of multiple devices to improve upgrade efficiency and not affect system functions during firmware upgrades.

[0023] Example 1 This embodiment provides a dual-processor based battery system, such as Figure 1 Shown, including: Inverter 11, used for sending a firmware package; The main BMS 12 includes a first ARM processor 121 and a first DSP processor 122 with different functions. The first ARM processor 121 is connected to the inverter 11, and the first DSP processor 122 is connected to the first ARM processor 121; Multiple slave BMSs 13 , each slave BMS 13 including a second ARM processor 131 and a second DSP processor 132 with different functions, the second ARM processor 131 being connected to the first ARM processor 121 , and the second DSP processor 132 being connected to the second ARM processor 131 ; The first ARM processor 121 is used to store the firmware package, and, according to the target processor type of the firmware package, send the firmware package to the corresponding processor of the master BMS 12 and distribute it to the corresponding processors of the plurality of slave BMSs 13 for firmware upgrade.

[0024] Specifically, inverter 11, acting as a central coordination node, obtains and stores the BMS firmware package from the host computer. In the master BMS 12 and slave BMS 13, the ARM processor and DSP processor each have distinct functions: the ARM processor is responsible for data processing and communication, while the DSP processor is responsible for real-time battery status monitoring and control. Depending on whether the firmware package is for an ARM processor or a DSP processor, the firmware package is distributed to the corresponding processors in the master and slave BMSs. For example, if the current target upgrade package is for an ARM processor, the DSP processor's real-time battery status monitoring and control functions are unaffected.

[0025] In this embodiment, ARM and DSP dual processors with different functions are integrated, making full use of the division of labor and cooperation between the ARM processor and the DSP processor. There is no need to disassemble each device one by one to perform firmware upgrade operations. The ARM and DSP firmware can be upgraded independently and multiple devices can be upgraded in parallel. System functions are not affected during the firmware upgrade process, and resource usage is effectively reduced to avoid occupying all storage space. The upgrade takes a short time and is highly efficient.

[0026] Example 2 This embodiment provides a dual-processor battery system. Based on the first embodiment, a first ARM processor 121 is connected to the inverter 11 via a first CAN bus, a first DSP processor 122 is connected to the first ARM processor 121 via a 485 bus, the first ARM processor 121 is connected to the second ARM processor 131 via a second CAN bus, and the second DSP processor 132 is connected to the second ARM processor 131 via a 485 bus. The first ARM processor 121 is also used to dynamically assign addresses to multiple second ARM processors 131.

[0027] In this embodiment, since the communication between the host and the inverter is realized through the first CAN bus (CAN1), the communication between the host and the slave is realized through the second CAN bus (CAN2), and the communication between the ARM and the DSP is realized through 485, the CAN and 485 dual-channel collaborative upgrade is realized.

[0028] Specifically, in the master BMS, the ARM processor is responsible for CAN communication (connecting to the inverter via CAN1 and to the slave devices via CAN2), firmware package distribution, and dynamic address allocation. The DSP processor interacts with the ARM processor via the 485 bus to perform real-time battery status monitoring and control. The slave BMS's hardware architecture is consistent with the master BMS, supporting dynamic addresses and hot swapping. Inverter 11 can send firmware packages (for example, frame ID: 0x5000) via the first CAN bus (CAN1). The first ARM processor 12 implements dynamic address allocation using the CAN ID extension field (0x5000 + Addressr). Firmware packages are transmitted incrementally, with a single packet length of 128 bytes, transmitted in 16 frames (ID: 0x5040), effectively reducing bandwidth usage. The master BMS 12 writes the firmware package to its first storage area based on the target processor type (ARM / DSP).

[0029] At the software level: On the one hand, partitioned storage of firmware packages is implemented, namely: in the memory (Flash) of the ARM processor, the first storage area FW_ARM_SCT is divided for storing firmware packages whose target processor type is an ARM processor. After the upgrade, only the ARM processor needs to be restarted to take effect; the second storage area FW_DSP_SCT is used to store firmware packages whose target processor type is a DSP processor, which needs to be transmitted to the DSP processor via 485.

[0030] On the other hand, a dynamic address allocation protocol is implemented: the first BMS connected to the inverter automatically becomes the master BMS (host). The host allocates the address Addr according to the serial number of the slave, and allocates it incrementally in case of conflict. For example, in the dynamic address, Address = 1~15, which means that 15 slave BMSs can be upgraded in parallel. After arranging the 15 slave BMSs in ascending or descending order of the serial number, the addresses are allocated in sequence, such as Figure 2 In addition, the Modbus protocol (ID: 60300~60420) is integrated to dynamically bind the processor ID and Modbus ID.

[0031] In a specific implementation, the battery system further includes: a CAN bus drive circuit and a 485 isolation circuit.

[0032] In one example, the CAN bus driver circuit uses the SN65HVD230 chip, which supports high-speed CAN communication (1 Mbps). The 485 isolation circuit uses the ADM2483 chip to implement isolated communication between the ARM and DSP.

[0033] In some embodiments, the ARM processor's memory (Flash) is further divided into a third storage area and a fourth storage area. The third storage area is used to store the current version of the ARM processor firmware package. After the ARM processor firmware is upgraded, the firmware package in the first storage area is updated to the third storage area to update the current version of the ARM processor firmware package. The fourth storage area is used to store the current version of the DSP processor firmware package. After the DSP processor firmware is upgraded, the firmware package in the second storage area is updated to the fourth storage area to update the current version of the DSP processor firmware package. The third and fourth storage areas serve as backup areas. In the event that the ARM processor or DSP processor firmware upgrade fails, the current version of the firmware package is retrieved from the backup area to restore the original program.

[0034] It should be noted that in a specific implementation, the memory (Flash) of the first ARM processor of the master BMS and the memory (Flash) of the second ARM processor of the slave BMS can both be divided into storage areas as described above. When a firmware package is received, the firmware package is stored in the corresponding storage area based on the target processor type. Regardless of whether the current target processor type is an ARM processor or a DSP processor, the master BMS must be finally restarted after all corresponding processors of the slave BMS are upgraded.

[0035] The following describes how to upgrade the master BMS and slave BMS firmware based on the system of this embodiment: Main BMS upgrade process: (1) Firmware reception: The inverter sends the firmware package (ID: 0x5000+Addr) through CAN1, and the ARM processor of the main BMS writes the firmware package to the corresponding storage area according to the target processor type (ARM or DSP).

[0036] (2) ARM processor upgrade: directly restart the ARM processor to take effect.

[0037] (3) DSP processor upgrade: The ARM processor transmits the firmware package to the DSP processor via 485.

[0038] After verification, the DSP processor writes the data into the Flash and restarts.

[0039] Upgrade process from BMS: (1) Host polling: The ARM processor of the master BMS queries the slave status (ID: 0x5060) through CAN2.

[0040] (2) Firmware distribution: The ARM processor of the master BMS sends the firmware package to the first storage area FW_ARM_SCT of the ARM processor of the master BMS of the slave BMS.

[0041] (3) Processing from BMS: ARM processor upgrade: To take effect, directly restart the ARM processor from the BMS.

[0042] DSP processor upgrade: The firmware package is transferred from the BMS ARM processor to the DSP processor via 485, and the DSP restart takes effect.

[0043] (4) Cycle detection: After the ARM processor of the master BMS confirms that the upgrade of all the ARM processors of the slave BMS is completed, it performs a final restart.

[0044] In order to avoid system crashes due to data packet errors, this embodiment also designs the following safety mechanisms in the upgrade process group: (1) Multi-level verification mechanism, such as Figure 3 Shown, including: Firmware level: CRC check (ID: 0x5000) verifies integrity.

[0045] Packet level: packet sequence number verification (ID: 0x5020) and single packet CRC check (ID: 0x5040).

[0046] Write level: Flash write verification (ID: 0x5050).

[0047] Specifically, before the ARM processor of the main BMS identifies the target processor type of the firmware package (or the ARM processor of the slave BMS identifies the target processor type of the firmware package), it also includes: performing an integrity check on the firmware package; if the integrity check fails, triggering a firmware package retransmission operation; if the integrity check passes, verifying the serial number and / or check code of the firmware package; if the serial number and / or check code of the firmware package are abnormal, discarding the current firmware package; if the serial number and / or check code of the firmware package pass the verification, identifying the target processor type of the firmware package, and then performing subsequent upgrade operations. In addition, each time the firmware package is written to at each stage of the upgrade process, the write operation of the firmware package is verified, thereby realizing a three-level verification mechanism at the firmware level, package level, and write level.

[0048] In one example, the integrity check of the firmware package can be performed using CRC check, the package level can be checked by serial number and / or CRC check, and the write level can use Flash check combined with firmware level, package level and write level triple check to ensure the security of firmware upgrade.

[0049] (2) Abnormal recovery mechanism, including: When the firmware upgrade fails, the original program is restored from the backup area (FW_BACKUP_SCT).

[0050] Hardware watchdog forced reset to avoid deadlock.

[0051] When an abnormality occurs during the upgrade process, at least one of the two abnormality recovery mechanisms can be executed.

[0052] Example 3 This embodiment provides a firmware upgrade method, which is implemented based on the battery system provided in the first or second embodiment. Figure 4 As shown, the firmware upgrade method can be executed by the first ARM processor in the aforementioned embodiment, including: Step 101: Receive and store a firmware package sent by an inverter.

[0053] Step 102: Identify the target processor type of the firmware package. The target processor types include ARM processors and DSP processors.

[0054] Step 103 : Send the firmware package to the corresponding processor of the master BMS and the corresponding processors of the multiple slave BMSs according to the target processor type to perform firmware upgrade.

[0055] According to the target processor type of the firmware package, the firmware package is sent to the corresponding processor of the master BMS and the corresponding processors of the multiple slave BMSs to perform firmware upgrade.

[0056] In this embodiment, since the ARM and DSP dual processors can independently perform firmware upgrades and realize parallel upgrades of multiple slave BMSs, the division of labor and cooperation between the ARM processor and the DSP processor is fully utilized. There is no need to disassemble each machine one by one to perform firmware upgrade operations. The system functions are not affected during the ARM and DSP firmware upgrade process, and resource usage is effectively reduced, avoiding occupying all storage space. The upgrade takes a short time and is highly efficient.

[0057] The following describes the firmware upgrade process for ARM and DSP processors: (1) Target processor types include ARM processors According to the target processor type, the firmware package is sent to the corresponding processor of the master BMS and the corresponding processors of multiple slave BMSs for firmware upgrade, including: Writing the firmware package into a first storage area in the memory of the first ARM processor; Distribute the firmware package to the second ARM processor of each slave BMS, so that each second ARM processor performs firmware upgrade according to the firmware package and then restarts; When each second ARM processor completes the firmware upgrade, the first ARM processor is restarted to complete the firmware upgrade.

[0058] (2) Target processor types include DSP processors According to the target processor type, the firmware package is sent to the corresponding processor of the master BMS and the corresponding processors of multiple slave BMSs for firmware upgrade, including: Writing the firmware package into a second storage area in the memory of the first ARM processor; Sending the firmware package to the first DSP processor and writing it into the memory of the first DSP processor, so that the first DSP processor performs firmware upgrade according to the firmware package and then restarts; The firmware package is distributed to the second ARM processor of each slave BMS, so that the firmware package is sent to the corresponding second DSP processor through each second ARM processor.

[0059] The above firmware upgrade process can be as follows Figure 5 shown.

[0060] In a specific implementation, before the first ARM processor or the second ARM processor identifies the target processor type of the firmware package, the method further includes: Perform integrity check on the firmware package; If the integrity check passes, verify the serial number and check code of the firmware package; When the serial number and the check code of the firmware package pass the verification, the target processor type of the firmware package is identified.

[0061] Furthermore, each time a firmware package is written during each step of the upgrade process, the write operation is verified.

[0062] Specifically, before the ARM processor of the main BMS identifies the target processor type of the firmware package (or the ARM processor of the slave BMS identifies the target processor type of the firmware package), it also includes: performing integrity verification on the firmware package; if the integrity verification fails, triggering the firmware package retransmission operation, and if the integrity verification passes, verifying the serial number and / or check code of the firmware package; if the serial number and / or check code of the firmware package are abnormal, discarding the current firmware package, and if the serial number and / or check code of the firmware package pass the verification, identifying the target processor type of the firmware package, and then performing subsequent upgrade operations. In addition, each time the firmware package is written to at each stage of the upgrade process, the write operation of the firmware package is verified, thereby realizing a three-level verification mechanism at the firmware level, package level, and write level to ensure the security of the firmware upgrade.

[0063] Example 4 This embodiment provides two examples of using the system or method in the above embodiment to perform firmware upgrade: (1) Main BMS DSP processor firmware upgrade The inverter sends a DSP-type firmware package (ID: 0x5000+Addr, with the target processor type code identifying it as DSP). The main BMS's ARM receives it, writes it to the FW_DSP_SCT storage area, and transmits it to the DSP processor via 485. The DSP verifies the firmware and writes it to Flash, which takes effect after a reboot.

[0064] (2) Batch upgrade from BMS ARM processor The master BMS's ARM processor queries the slave status (ID: 0x5060) via CAN2, detects the address of the unupgraded slave BMS (Addr = 3), and sends an ARM-type firmware package (ID: 0x5040+Addr). The slave BMS's ARM processor receives it, writes it to FW_ARM_SCT, and restarts. The master BMS's ARM processor confirms that all slave BMS ARM processors have completed the upgrade and restarts.

[0065] Example 5 This embodiment provides an electronic device, including: at least one processor; and, a memory communicatively connected to at least one processor; wherein, The memory stores instructions that can be executed by at least one processor. The instructions are executed by the at least one processor so that the at least one processor can execute the energy regulation method of the above embodiment.

[0066] The memory and processor are connected using a bus, which can include any number of interconnected buses and bridges. The bus connects various circuits of one or more processors and memories. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits. These are all well known in the art and are therefore not described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over a wireless medium via an antenna. Furthermore, the antenna receives data and transmits it to the processor.

[0067] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0068] Example 6 This embodiment provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the firmware upgrade method of the above embodiment is implemented.

[0069] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented by instructing related hardware through a program. The program, stored in a storage medium, includes instructions for causing a device (such as a microcontroller or chip) or a processor to execute all or part of the steps in the various method embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0070] The embodiment of the present invention integrates an ARM and DSP dual processor with different functions, making full use of the division of labor and cooperation between the ARM processor and the DSP processor. There is no need to disassemble each machine one by one to perform firmware upgrade operations. The ARM and DSP firmware can be upgraded independently and multiple devices can be upgraded in parallel. The system functions are not affected during the firmware upgrade process, and the resource usage is effectively reduced, avoiding occupying all storage space. The upgrade is time-saving and efficient. The division of labor and cooperation between ARM and DSP is fully utilized, so that the system functions are not easily interrupted during the firmware upgrade. Dynamic address allocation improves scalability and supports hot plugging. The multi-level verification mechanism improves system security and is less likely to cause system crashes due to data errors. Firmware upgrades are updated in modules, without occupying all storage space, effectively reducing resource usage.

[0071] It is understandable that those skilled in the art can, under the guidance of the above embodiments, combine various implementation methods in the above embodiments to obtain technical solutions of multiple implementation methods.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A dual-processor based battery system, characterized in that: include: Inverter, used to send firmware packages; A master BMS, the master BMS including a first ARM processor and a first DSP processor having different functions, the first ARM processor being connected to the inverter, and the first DSP processor being connected to the first ARM processor; a plurality of slave BMSs, each of which includes a second ARM processor and a second DSP processor having different functions, the second ARM processor being connected to the first ARM processor, and the second DSP processor being connected to the second ARM processor; The first ARM processor is used to store the firmware package, and, according to the target processor type of the firmware package, send the firmware package to the corresponding processor of the master BMS and distribute it to the corresponding processors of the multiple slave BMSs to perform firmware upgrade.

2. The dual-processor battery system according to claim 1, wherein: The first ARM processor is connected to the inverter via a first CAN bus, the first DSP processor is connected to the first ARM processor via a 485 bus, the first ARM processor is connected to the second ARM processor via a second CAN bus, and the second DSP processor is connected to the second ARM processor via a 485 bus.

3. The dual-processor battery system according to claim 1, wherein: The first ARM processor is further configured to dynamically allocate addresses to the plurality of second ARM processors.

4. A firmware upgrade method, characterized in that: Based on the battery system implementation according to any one of claims 1 to 3, the firmware upgrade method includes: Receive and store the firmware package sent by the inverter; Identify the target processor type of the firmware package, the target processor type including ARM processor and DSP processor; According to the target processor type, the firmware package is sent to a corresponding processor of the master BMS and corresponding processors of the plurality of slave BMSs to perform firmware upgrade.

5. The firmware upgrade method according to claim 4, wherein: According to the target processor type, the firmware package is sent to a corresponding processor of the master BMS and corresponding processors of the plurality of slave BMSs to perform a firmware upgrade, including: In a case where the target processor type includes an ARM processor, writing the firmware package into a first storage area in a memory of the first ARM processor; Distributing the firmware package to the second ARM processor of each slave BMS, so that each second ARM processor performs a firmware upgrade according to the firmware package and then restarts; When each of the second ARM processors completes the firmware upgrade, the first ARM processor is restarted to complete the firmware upgrade.

6. The firmware upgrade method according to claim 4, wherein: According to the target processor type, the firmware package is sent to a corresponding processor of the master BMS and corresponding processors of the plurality of slave BMSs to perform a firmware upgrade, including: In a case where the target processor type includes a DSP processor, writing the firmware package into a second storage area in the memory of the first ARM processor; Sending the firmware package to the first DSP processor and writing it into the memory of the first DSP processor, so that the first DSP processor performs a firmware upgrade according to the firmware package and then restarts; The firmware package is distributed to the second ARM processor of each of the slave BMSs, so that the firmware package is sent to the corresponding second DSP processor through each of the second ARM processors.

7. The firmware upgrade method according to claim 4, wherein: Before identifying the target processor type of the firmware package, the method further includes: Performing integrity check on the firmware package; If the integrity check passes, verify the serial number and / or check code of the firmware package; If the serial number and / or the check code of the firmware package pass the verification, the target processor type of the firmware package is identified.

8. The firmware upgrade method according to claim 7, wherein: Also includes: A write operation of the firmware package is verified.

9. An electronic device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the firmware upgrade method according to any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the firmware upgrade method according to any one of claims 1 to 8 is implemented.

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