Application migration method and device, electronic equipment and storage medium

Abstract

The invention provides an application migration method and device, electronic equipment and a storage medium, and the method comprises the steps: analyzing the architectural features of a target hardware platform to generate architectural feature data, analyzing a ray tracing application to generate resource demand information, building a mapping relation between the architectural feature data and the resource demand data, and transmitting the mapping relation between the architectural feature data and the resource demand data. Generating migration priorities and code adjustment information of the algorithm modules; performing adaptive conversion on an execution framework of the ray tracing application according to the migration priority and the code adjustment information, and generating a target adaptive application supporting a target hardware platform; distributing the target adaptive application to a target hardware platform to execute test verification, and collecting resource occupation data when the target adaptive application is executed; and performing optimization processing on the target adaptive application based on the resource occupation data to generate a ray tracing migration application. Compared with the prior art, the ray tracing application is migrated to the target hardware platform, and through iterative optimization, the comprehensive performance of the final ray tracing migration application is remarkably improved compared with that of the initial version.

Description

Technical Field

[0001] The present disclosure relates to the field of chip technology, and in particular to a method and device for application migration, an electronic device, and a storage medium. Background Art

[0002] In the field of computer graphics, ray tracing technology is the core method for achieving highly realistic image rendering, but its high computational complexity places strict demands on hardware performance, and there are significant bottlenecks in architecture migration and performance optimization. Although traditional image processor architectures have improved performance through dedicated hardware and instruction sets, they rely on closed-source architectures, have poor portability, and there is still room for optimization in hardware design for the special needs of ray tracing. CPU solutions are highly flexible but lack floating-point operations and memory bandwidth, making it difficult to meet real-time requirements. The open source RISC-V architecture lacks a dedicated design for ray tracing, and existing research has only stayed at the stage of simple scene porting, failing to fully utilize its parallel computing potential. In addition, the lack of hardware acceleration units and cross-architecture programming models has led to insufficient migration efficiency and rendering performance. Therefore, building an efficient ray tracing migration and optimization solution for the RISC-V architecture is a key issue that needs to be addressed. Summary of the Invention

[0003] The present disclosure provides a method and apparatus for application migration, an electronic device, and a storage medium, the main purpose of which is to solve the problem that ray tracing applications cannot be migrated across hardware platforms.

[0004] According to a first aspect of the present disclosure, a method for application migration is provided, comprising:

[0005] Analyze the architecture characteristics of the target hardware platform to generate architecture characteristic data, analyze the ray tracing application to generate resource requirement information, establish a mapping relationship between the architecture characteristic data and resource requirement data, and based on the mapping relationship, generate migration priorities and code adjustment information for algorithm modules in the ray tracing application;

[0006] Based on instruction mapping rules, the execution architecture of the ray tracing application is adapted and converted according to migration priority and code adjustment information to generate a target-adapted application that supports the target hardware platform;

[0007] Assign the target adaptation application to the target hardware platform for test verification, and collect resource usage data when executing the target adaptation application; optimize the target adaptation application based on the resource usage data and generate a ray tracing migration application.

[0008] Optionally, analyzing the architecture characteristics of the target hardware platform to generate architecture characteristic data, analyzing the ray tracing application to generate resource requirement information, and establishing a mapping relationship between the architecture characteristic data and the resource requirement data, including:

[0009] Analyze the target hardware platform's instruction set, register configuration, storage system, and parallel computing architecture to generate architectural feature data;

[0010] Determine the computing resource data required to execute the ray tracing application, match the computing resource data with the architecture feature data, and generate resource requirement information;

[0011] Map the architecture feature data and resource requirement data to establish a mapping relationship.

[0012] Optionally, based on instruction mapping rules, the execution architecture of the ray tracing application is adapted and converted according to migration priorities and code adjustment information, including:

[0013] According to the instruction mapping rules and code adjustment information, adjust and adapt the source code of the algorithm module that needs to be adjusted;

[0014] Convert the adjusted source code into target code supported by the target hardware platform;

[0015] Converts metadata for ray tracing applications into a format compatible with the target hardware platform.

[0016] Optionally, distribute the target adaptation application to the target hardware platform for testing and verification, including:

[0017] When testing and verifying the target adaptation application, a dynamic block scheduling mechanism is used to balance the computing load and a hierarchical spatial partitioning structure is constructed to optimize the geometric intersection path.

[0018] Call the hardware acceleration module of the target hardware platform to perform accelerated computing processing on the target adaptation application.

[0019] Optionally, a dynamic block scheduling mechanism is used to balance the computing load and construct a hierarchical spatial partitioning structure to optimize the geometric intersection path, including:

[0020] The target ray is divided into parallel processing computing units through a dynamic block scheduling mechanism, and the target ray generation process is reconstructed in parallel using a vectorized instruction set.

[0021] The hierarchical space partitioning structure is used to optimize the intersection path between the target light and the target object.

[0022] Optionally, call the hardware acceleration module of the target hardware platform to perform accelerated computing processing on the target adaptation application, including:

[0023] Based on the computational complexity and data dependency of the target adaptation application, the subtasks of the target adaptation application are assigned to the hardware acceleration module or processor core for computational processing.

[0024] Optionally, optimize the target application based on resource usage data to generate a ray tracing migration application, including:

[0025] Analyze resource usage data and locate target algorithm modules with high resource usage in target adaptation applications;

[0026] Generate migration optimization strategies based on target algorithm modules and resource usage data;

[0027] In response to a code optimization instruction, the target code of the target adaptation application is optimized to generate a ray tracing migration application, wherein the code optimization instruction is generated based on a migration optimization strategy.

[0028] According to a second aspect of the present disclosure, there is provided an apparatus for application migration, comprising:

[0029] an analysis unit, configured to analyze the architecture characteristics of the target hardware platform to generate architecture characteristic data, analyze the ray tracing application to generate resource requirement information, establish a mapping relationship between the architecture characteristic data and the resource requirement data, and generate migration priorities and code adjustment information for algorithm modules in the ray tracing application based on the mapping relationship;

[0030] A first generating unit is configured to adapt and convert the execution architecture of the ray tracing application based on the instruction mapping rule, the migration priority, and the code adjustment information, and generate a target-adapted application that supports the target hardware platform;

[0031] The second generation unit is used to allocate the target adaptation application to the target hardware platform for test verification, collect resource usage data when executing the target adaptation application; optimize the target adaptation application based on the resource usage data, and generate a ray tracing migration application.

[0032] Optionally, the analysis unit includes:

[0033] The parsing module is used to analyze the instruction system, register configuration, storage system and parallel computing architecture of the target hardware platform and generate architectural feature data;

[0034] A first generation module is configured to determine computing resource data required to execute the ray tracing application, and to match and compare the computing resource data with the architecture feature data to generate resource requirement information;

[0035] A module is established to map the architecture feature data and resource requirement data and establish a mapping relationship.

[0036] Optionally, the first generating unit includes:

[0037] The adaptation module is used to adjust and adapt the source code of the algorithm module that needs to be adjusted according to the instruction mapping rules and code adjustment information;

[0038] A first conversion module, configured to convert the adjusted source code into a target code supported by the target hardware platform;

[0039] The second conversion module is used to convert the metadata of the ray tracing application into a format compatible with the target hardware platform.

[0040] Optionally, the second generation unit includes:

[0041] A construction module is used to balance the computing load by using a dynamic block scheduling mechanism and to build a hierarchical spatial partitioning structure to optimize the geometric intersection path when performing test verification on the target adaptation application;

[0042] The calling module is used to call the hardware acceleration module of the target hardware platform to perform accelerated computing processing on the target adaptation application.

[0043] Optionally, the building block is also used to:

[0044] The target ray is divided into parallel processing computing units through a dynamic block scheduling mechanism, and the target ray generation process is reconstructed in parallel using a vectorized instruction set.

[0045] The hierarchical space partitioning structure is used to optimize the intersection path between the target light and the target object.

[0046] Optionally, the calling module is also used to:

[0047] Based on the computational complexity and data dependency of the target adaptation application, the subtasks of the target adaptation application are assigned to the hardware acceleration module or processor core for computational processing.

[0048] Optionally, the second generating unit further includes:

[0049] Analysis module, used to analyze resource usage data and locate the target algorithm modules with high resource usage in the target adaptation application;

[0050] The second generation module is used to generate a migration optimization strategy based on the target algorithm module and resource usage data;

[0051] The optimization module is used to optimize the target code of the target adaptation application in response to the code optimization instruction and generate a ray tracing migration application, wherein the code optimization instruction is generated based on the migration optimization strategy.

[0052] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0053] at least one processor; and

[0054] a memory communicatively connected to the at least one processor; wherein,

[0055] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the application migration method described in the first aspect.

[0056] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable the computer to execute the application migration method described in the first aspect.

[0057] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the method for application migration as described in the first aspect above.

[0058] The present disclosure provides a method and apparatus, electronic device, and storage medium for application migration, relating to the field of chip technology. Compared to related technologies, the present disclosure generates architectural feature data by analyzing the instruction set characteristics of the target hardware platform, simultaneously parsing the algorithm code of the ray tracing application to generate resource requirement information, and establishing a mapping relationship between the two. This process accurately identifies the hardware support boundaries of the target hardware platform for ray tracing applications, avoiding performance losses caused by blind migration, making migration priorities and code adjustments more targeted, and improving operational efficiency compared to traditional "one-size-fits-all" migration methods. The migration priority of the algorithm module is determined based on the mapping relationship to avoid resource waste. The code is then converted to architectural adaptation based on instruction mapping rules. When generating the target-adapted application, task allocation is dynamically adjusted to reduce data transmission overhead between the processor and hardware units, thereby improving overall resource utilization. By performing test verification on the target hardware platform, resource usage data such as memory usage, processor utilization, and rendering time are collected to accurately locate performance bottlenecks. Through multiple rounds of data feedback and iterative optimization, the overall performance of the final ray tracing migration application is significantly improved compared to the initial version.

[0059] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0061] Figure 1 A flowchart of a method for application migration provided by an embodiment of the present disclosure;

[0062] Figure 2 A flowchart of another application migration method provided by an embodiment of the present disclosure;

[0063] Figure 3 A schematic diagram of the structure of an application migration device provided in an embodiment of the present disclosure;

[0064] Figure 4 A schematic structural diagram of another device for application migration provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0066] The following describes the application migration method and apparatus, electronic device, and storage medium according to embodiments of the present disclosure with reference to the accompanying drawings.

[0067] Figure 1 A flowchart of an application migration method provided by an embodiment of the present disclosure.

[0068] like Figure 1 As shown, the method comprises the following steps:

[0069] Step 101: Analyze the architecture characteristics of the target hardware platform to generate architecture characteristic data, analyze the ray tracing application to generate resource requirement information, establish a mapping relationship between the architecture characteristic data and the resource requirement data, and based on the mapping relationship, generate the migration priority and code adjustment information of the algorithm module in the ray tracing application.

[0070] In an embodiment of the present disclosure, by abstractly modeling the underlying hardware characteristics of a target hardware platform (e.g., the RISC-V architecture), including its instruction set architecture, register configuration, storage hierarchy (e.g., L1 / L2 cache structure, memory alignment rules), and parallel computing units (e.g., SIMD instruction set support, multi-threaded scheduling mechanism), architectural feature data is generated, encompassing dimensions such as instruction set compatibility, computing unit performance parameters, and storage access latency. This data describes the hardware platform's computing capability boundaries in a structured form. For example, by analyzing parameters such as the vector operation width and floating-point unit throughput of the RISC-V instruction set, a quantitative representation of the hardware's parallel computing capabilities is formed. The algorithm components of a ray tracing application are functionally decomposed to identify the computational resource consumption characteristics of each module. Technical indicators characterizing resource consumption characteristics include, but are not limited to, computational intensity, such as the frequency of floating-point operations required by the ray-object intersection module; data parallelism, such as the potential for pixel shading modules to adapt to SIMD vectorization operations; storage access patterns, such as the cache locality characteristics of scene geometry data; and control complexity, such as the branch prediction difficulty of the ray traversal acceleration structure (BVH) construction.

[0071] Through static code analysis and dynamic performance profiling, resource requirement information is generated, including the resource consumption priority of each algorithm module. For example, core modules that require high-frequency floating-point operations and auxiliary modules that can be processed lazily are identified. A bidirectional mapping model is established between hardware architecture characteristics and application resource requirements, and the adaptation strategy is determined through correlation analysis. Based on the above mapping relationship, migration priorities are generated according to the module adaptation cost and performance-benefit ratio (such as prioritizing the migration of core rendering path modules), and code adjustment instructions (such as vectorization transformation tags and memory alignment declarations) are output.

[0072] Step 102 : Based on the instruction mapping rules, the execution architecture of the ray tracing application is adapted and converted according to the migration priority and the code adjustment information to generate a target adapted application supporting the target hardware platform.

[0073] In an embodiment of the present disclosure, a cross-architecture instruction mapping knowledge base is constructed, which contains the semantic correspondence between the instruction sets of the target hardware platform (such as RISC-V) and the source architecture (such as x86), covering basic instructions such as arithmetic operations, logical operations, memory access, and extended instructions such as vector operations (SIMD) and floating-point processing. For example, the operand width and operation type mapping rules of the SSE instructions and RISC-V vector instructions in the source architecture are defined to form standardized instruction mapping rules. The instruction sequence of the ray tracing application is traversed by a static code parsing tool, and a cross-architecture instruction conversion candidate set is generated based on the rule base. According to the migration priority generated in step 101, the algorithm modules of the ray tracing application are converted in stages: the core computing modules are adapted first: for modules with high computing density (such as ray intersection and shading calculation), vectorization conversion is implemented based on instruction mapping rules (such as reconstructing scalar operations into SIMD instruction sequences), and the dedicated acceleration units of the target hardware (such as RISC-V's floating-point operation unit or hardware acceleration module RTU) are adapted; the control logic module is adaptively adjusted: for process control modules (such as acceleration structure traversal logic), the conditional judgment path is optimized according to the branch prediction mechanism of the target architecture to reduce pipeline bubbles; the alignment of storage-related modules is optimized: for data access modules (such as scene data loading), the data structure layout is adjusted according to the memory alignment rules of the target architecture (such as 16-byte boundary alignment) to generate storage access code that conforms to the hardware access characteristics. Combined with the code adjustment information output in step 101, the application code is structurally modified: Instruction-level conversion: Through the abstract syntax tree (AST) traversal technology, the instruction patterns unique to the source architecture (such as AVX instructions of x86) are replaced with equivalent instructions of the target architecture (such as RVV instructions of RISC-V), and hardware-specific inline assembly or intrinsic functions are inserted; Parallelism reconstruction: For parallelizable modules (such as pixel-level rendering tasks), the multi-threaded programming model of the target architecture (such as POSIX threads or OpenMP) is introduced, and computing resources are allocated in combination with migration priorities; Interface adaptation: For graphics API calls (such as OpenGL / Vulkan), they are mapped to the graphics processing library of the target architecture through an intermediate layer abstract interface to shield the underlying hardware differences.

[0074] Step 103 : Allocate the target adaptation application to the target hardware platform for test verification, collect resource usage data when executing the target adaptation application, optimize the target adaptation application based on the resource usage data, and generate a ray tracing migration application.

[0075] In an embodiment of the present disclosure, the target adaptation application generated by step 102 is loaded onto the target hardware platform (such as a RISC-V architecture processor) and instantiated and deployed based on the platform resource configuration (such as the number of cores, cache capacity, and hardware acceleration unit RTU). By constructing standardized test cases (such as benchmark scene rendering and pressure load simulation), the actual execution of each module of the application is triggered to form a functional verification and performance evaluation scenario in a real runtime environment. The performance monitoring interface (such as performance counters, cache analysis tools) and software probe technology of the target hardware platform are used to collect the following key data in real time: computing resource data, storage resource data, task scheduling data, time performance data, etc. The above information is normalized by the data acquisition system to form a structured resource occupancy data set, which provides a quantitative basis for subsequent optimization. An association analysis model between resource occupancy data and application modules is established to identify performance bottlenecks and implement targeted optimization. Through multiple rounds of "acquisition-analysis-optimization" iterations, the final ray tracing migration application is generated to ensure that its resource utilization efficiency on the target hardware platform is maximized.

[0076] The present disclosure provides a method for application migration. Compared with related technologies, the present disclosure generates architectural feature data by analyzing the instruction set characteristics of the target hardware platform, and at the same time parses the algorithm code of the ray tracing application to form resource demand information, and establishes a mapping relationship between the two. This process can accurately identify the hardware support boundary of the target hardware platform for the ray tracing application, avoid performance loss caused by blind migration, make migration priority and code adjustment more targeted, and improve operating efficiency compared to the traditional "one-size-fits-all" migration method. Determine the migration priority of the algorithm module based on the mapping relationship to avoid resource waste. According to the instruction mapping rules, perform architecture adaptation conversion on the code. When generating the target adaptation application, the data transmission overhead between the processor and the hardware unit is reduced by dynamically adjusting the task allocation, and the overall resource utilization is improved. By performing test verification on the target hardware platform, resource usage data such as memory usage, processor utilization, and rendering time are collected to accurately locate performance bottlenecks. Through multiple rounds of data feedback iterative optimization, the comprehensive performance of the final ray tracing migration application is significantly improved compared to the initial version.

[0077] In order to clearly illustrate the embodiment of the present disclosure, this embodiment provides a flowchart of another application migration method.

[0078] like Figure 2 As shown, the method comprises the following steps:

[0079] Step 201 , analyze the instruction system, register configuration, storage system and parallel computing architecture of the target hardware platform to generate architecture feature data.

[0080] Specifically, in step 201, the instruction system of the target hardware platform (such as the RISC-V architecture) is parsed, and the encoding format and operation characteristics of arithmetic / logical instructions, vector instructions (such as SIMD), and floating-point instructions are extracted to form instruction set compatibility data; the register configuration is analyzed to clarify the number, bit width, and access rules of general registers and floating-point registers (such as RVV vector registers), and generate register resource description data; the storage system is disassembled to obtain the capacity, line size, replacement strategy, and memory alignment rules (such as 16-byte boundary alignment) of the cache hierarchy (L1 / L2 cache) to form storage access feature data; the parallel computing architecture is evaluated, and the number of processor cores, hardware thread scheduling mechanism, and SIMD instruction parallel width are counted to generate parallel computing capability parameters.

[0081] Through the above analysis, structured architecture feature data including instruction set characteristics, register resources, storage performance, and parallel capabilities is generated, providing a quantitative basis at the hardware level for resource requirement mapping of subsequent ray tracing applications, ensuring that the migration adaptation strategy is deeply coupled with hardware characteristics, and improving adaptation efficiency and execution performance.

[0082] Step 202 : Determine the computing resource data required to execute the ray tracing application, match and compare the computing resource data with the architecture feature data, and generate resource requirement information.

[0083] Specifically, in step 202, the computing resource data of the ray tracing application is determined, including the vector operation amount of the ray generation module, the floating-point operation frequency of the ray-object intersection module, the parallel pixel processing scale of the shading module, etc. The above data is compared with the architectural feature data generated in step 201 (such as the SIMD instruction width, floating-point unit throughput, and cache line size of RISC-V) to identify the hardware's support capabilities for the application's computing needs (such as determining whether the vector instruction set can accelerate the parallel calculation of ray generation). Through adaptation analysis, resource requirement information including instruction set matching, register usage efficiency, cache utilization, and parallel task granularity is generated, and key modules that require hardware acceleration (such as ray generation that requires SIMD vectorization) and storage access paths that need to be optimized (such as adjusting the BVH node layout based on cache characteristics) are identified, providing data support for subsequent migration priority formulation and ensuring efficient collaboration between application algorithms and hardware architecture.

[0084] Step 203 : Mapping the architecture feature data and the resource requirement data to establish a mapping relationship; based on the mapping relationship, generating migration priorities and code adjustment information of the algorithm modules in the ray tracing application.

[0085] Specifically, in step 203, the architecture feature data generated in step 201 (e.g., RISC-V SIMD instruction support and cache line size) is mapped to the resource requirement information in step 202 (e.g., the vector operation requirements of the ray generation module and the floating-point operation requirements of the intersection module) to establish a mapping table between hardware capabilities and application requirements. For example, vectorizable ray generation tasks in an application are mapped to the RISC-V SIMD instruction set, and frequently accessed BVH node data is mapped to the hardware cache capacity.

[0086] Based on this mapping, migration priorities are generated based on module adaptation benefits. Modules that are computationally intensive and well-matched to hardware acceleration (such as ray-object intersection) are prioritized for migration, and code adjustments requiring vectorization or hardware unit calls (such as memory alignment declarations and SIMD intrinsic insertion) are noted. This process ensures that migration resources are allocated to performance-sensitive modules, reducing adaptation costs and improving overall migration efficiency and hardware utilization.

[0087] Step 204 : According to the instruction mapping rules and the code adjustment information, the source code of the algorithm module that needs to be adjusted is adjusted and adapted; and the adjusted source code is converted into a target code supported by the target hardware platform.

[0088] Specifically, in step 204, based on the instruction mapping rules (such as the SIMD instruction mapping table between RISC-V and the source architecture) and the code adjustment information generated in step 203 (such as vectorization tags and memory alignment requirements), the algorithm module of the ray tracing application is structurally modified. For example, the RISC-V vector instruction Intrinsic is inserted into the loop structure of the ray generation module, a 16-byte alignment declaration is added to the scene data storage module, and the instruction mode specific to the source architecture is automatically replaced by the abstract syntax tree (AST) traversal tool (such as converting x86 AVX instructions to RISC-V RVV instructions). After the source code adjustment is completed, the target hardware platform's compilation tool chain (such as the RISC-V GCC compiler) is used to compile the adapted source code into target code executable by the target architecture, and during this process, compilation optimization options (such as -O3 level optimization) are enabled to improve instruction execution efficiency. This process realizes the instruction-level adaptation of the algorithm module from the source architecture to the target architecture, ensuring the efficient operation of the core computing logic on the RISC-V platform and reducing performance loss caused by architectural differences.

[0089] Step 205 : Convert the metadata of the ray tracing application into a format compatible with the target hardware platform.

[0090] Specifically, in step 205, the metadata of the ray tracing application is parsed, including scene geometry data (such as triangle mesh vertex coordinates), material parameters (such as reflectivity, refractive index), light source information (such as position, intensity), etc., to identify its data format characteristics (such as byte order, data type precision). Based on the storage format requirements of the target hardware platform (such as the RISC-V architecture), the following conversions are performed: Byte order adaptation: converting the big-endian data of the source architecture to a RISC-V-compatible little-endian format; data type alignment: adjusting the data field length (such as mapping a 64-bit floating-point type to the floating-point register bit width of the target platform) to ensure that memory access complies with hardware alignment rules (such as 16-byte boundary alignment); format standardization: converting custom data structures (such as the acceleration structure index table unique to ray tracing) to a common format supported by the target platform (such as a binary serialization format) to avoid parsing errors caused by format differences.

[0091] Through metadata format conversion, we ensure that scene data is correctly loaded and parsed on the target hardware platform, maintain the rendering logic consistency of ray tracing applications, reduce functional failures caused by data format incompatibility, and improve the integrity and reliability of cross-architecture migration.

[0092] Step 206 : When performing test verification on the target adaptation application, the dynamic block scheduling mechanism is used to balance the computing load and to construct a hierarchical space partitioning structure to optimize the geometric intersection path.

[0093] As a more specific implementation method, "using a dynamic block scheduling mechanism to balance computing loads and constructing a hierarchical space division structure to optimize geometric intersection paths" includes but is not limited to: dividing the target light into parallelizable computing units through a dynamic block scheduling mechanism, and using a vectorized instruction set to parallelize and reconstruct the target light generation process; and using a hierarchical space division structure to optimize the intersection path between the target light and the target object.

[0094] Specifically, in step 206, when performing test verification on the target adaptation application, the target light set is divided into subtask blocks of granularity-adaptive target hardware parallel computing units (such as RISC-V processor cores or SIMD channels) through a dynamic block scheduling mechanism. For example, the light is divided into independently processable tiles according to the rendering target resolution, each tile is assigned to a processor core, and the load of each core is dynamically adjusted through the task queue to avoid pipeline idling caused by load imbalance. At the same time, the vector instruction set supported by the target hardware (such as RISC-V's RVV) is used to vectorize and reconstruct the light generation process, converting the scalar loop generation logic into single instruction multiple data (SIMD) operations, processing the initial parameter calculations of multiple rays at a time, and improving the parallel efficiency of the light generation stage.

[0095] In the geometric intersection stage, a hierarchical space partitioning structure (such as a hierarchical bounding box BVH) is constructed to organize scene objects in a hierarchical manner. By recursively partitioning the space or object set, a tree structure from the root node to the leaf node is formed, and each node contains a bounding box and a child node index. During the ray traversal process, the bounding box of the parent node is quickly intersected first. If the intersection occurs, the child nodes are recursively processed to avoid invalid intersection calculations for invisible objects. Combined with the cache characteristics of the target hardware (such as the L1 cache line size), the data layout of the space partitioning structure is optimized, and the data of nodes at the same level are continuously stored to improve the cache hit rate and reduce memory access latency, thereby shortening the time taken to intersect the path between the ray and the target object.

[0096] Step 207: Call the hardware acceleration module of the target hardware platform to perform accelerated computing processing on the target adaptation application.

[0097] As a more specific implementation method, "calling the hardware acceleration module of the target hardware platform to perform accelerated computing processing on the target adaptation application" includes but is not limited to: based on the computational complexity and data dependency of the target adaptation application, allocating the subtasks of the target adaptation application to the hardware acceleration module or processor core for computing processing.

[0098] Specifically, in step 207, when performing test verification on the target adaptive application, the computing task characteristics of the target adaptive application are analyzed, and a matching model between subtasks and hardware resources is established based on the computational complexity (such as the number of floating-point operations) and data dependencies (such as synchronization requirements between tasks). For computationally intensive and data-independent tasks (such as ray-object intersection and shading calculations), the hardware acceleration module of the target hardware platform (such as the dedicated ray tracing acceleration unit RTU of the RISC-V architecture) is called to implement batch processing by utilizing its parallel computing capabilities (such as the multi-channel intersection processor); for tasks with complex control logic or high data dependency (such as acceleration structure construction), they are assigned to the processor core for execution to ensure that task scheduling conforms to the characteristics of hardware heterogeneous computing.

[0099] Through task allocation strategies, ray tracing application subtasks are dynamically distributed to heterogeneous computing units. For example, high-frequency intersection tasks are offloaded to the RTU hardware pipeline, while the processor core is responsible for task scheduling and data preprocessing. This mechanism fully leverages the computing advantages of the hardware acceleration module, reduces the processor core load, and improves overall computing efficiency. This significantly improves the critical path performance of the target application compared to pure software implementation, forming a highly efficient acceleration solution in heterogeneous computing environments.

[0100] Step 208 , collecting resource occupancy data when executing the target adaptation application, analyzing the resource occupancy data, locating the target algorithm module with high resource occupancy in the target adaptation application; and generating a migration optimization strategy based on the target algorithm module and the resource occupancy data.

[0101] Specifically, in step 208, the target hardware platform's performance monitoring interface (such as RISC-V's PMU performance counters) and software probes are used to collect real-time resource usage data during the execution of the target application. This data includes, but is not limited to, the number of floating-point unit (FPU) cycles of the processor core, the SIMD instruction execution rate, the L1 cache hit rate, and memory bandwidth utilization. The collected data is statistically analyzed, and a threshold determination method is used to identify target algorithm modules with high resource usage. For example, if the FPU usage of the ray-object intersection module exceeds 70% and the cache hit rate is less than 40%, it is determined to be a performance bottleneck module.

[0102] Based on the target hardware architecture features (such as RISC-V's RVV vector instruction set and RTU acceleration unit) and module resource usage characteristics, a migration optimization strategy is generated. For modules with high vectorization potential (such as ray generation), a SIMD instruction reconstruction plan is developed; for cache-unfriendly modules (such as BVH traversal), a data layout adjustment strategy is planned; and for modules that can be hardware-accelerated (such as intersection calculations), an RTU call instruction set is generated. This process uses data to identify optimization directions, ensuring deep coupling between strategies and hardware capabilities, and improving subsequent optimization efficiency.

[0103] Step 209 : In response to the code optimization instruction, optimize the target code of the target adaptation application to generate a ray tracing migration application, wherein the code optimization instruction is generated based on the migration optimization strategy.

[0104] Specifically, in step 209, the code optimization instructions generated by the migration optimization strategy in step 208 are parsed, such as vectorization optimization instructions or cache alignment adjustment instructions for the ray-object intersection module. Instruction-level optimization is then applied to the target code using the target hardware platform's compilation toolchain (e.g., RISC-V GCC). Advanced optimization options are used during the compilation phase, enabling optimization techniques such as loop unrolling, instruction reordering, and dead code elimination, and performing multiple rounds of compilation optimization on the target code. Specific call interface code is generated for hardware acceleration units (e.g., RTUs), enabling task distribution and data exchange between the processor core and the RTU through function pointers or inline assembly.

[0105] The final ray tracing migration application achieved a deep integration of computing logic and target hardware architecture through this process, significantly improving the instruction execution efficiency, cache utilization, and hardware acceleration unit call efficiency of key algorithm modules. Compared with the initial adaptation version, resource usage was reduced, forming a final product that can run efficiently on the RISC-V platform.

[0106] It should be noted that the embodiments of the present disclosure may include multiple steps. For the convenience of description, these steps are numbered, but these numbers do not limit the execution time slots or execution order between the steps; these steps can be implemented in any order, and the embodiments of the present disclosure do not limit this.

[0107] Corresponding to the above-mentioned method for application migration, the present disclosure also proposes an apparatus for application migration. Since the apparatus embodiment of the present disclosure corresponds to the above-mentioned method embodiment, details not disclosed in the apparatus embodiment can be referred to the above-mentioned method embodiment and will not be repeated in this disclosure.

[0108] Figure 3 A schematic diagram of a structure of an application migration device provided by an embodiment of the present disclosure is shown as follows: Figure 3 As shown, including:

[0109] An analysis unit 31 is configured to analyze the architecture characteristics of the target hardware platform to generate architecture characteristic data, analyze the ray tracing application to generate resource requirement information, establish a mapping relationship between the architecture characteristic data and the resource requirement data, and generate migration priorities and code adjustment information for algorithm modules in the ray tracing application based on the mapping relationship;

[0110] A first generating unit 32 is configured to adapt the execution architecture of the ray tracing application based on the instruction mapping rule, the migration priority, and the code adjustment information to generate a target-adapted application that supports the target hardware platform;

[0111] The second generation unit 33 is used to allocate the target adaptation application to the target hardware platform for test verification, collect resource usage data when executing the target adaptation application; optimize the target adaptation application based on the resource usage data, and generate a ray tracing migration application.

[0112] The present disclosure provides a device for application migration. Compared with related technologies, the present disclosure generates architectural feature data by analyzing the instruction set characteristics of the target hardware platform, and at the same time parses the algorithm code of the ray tracing application to form resource demand information, and establishes a mapping relationship between the two. This process can accurately identify the hardware support boundary of the target hardware platform for the ray tracing application, avoid performance loss caused by blind migration, make migration priority and code adjustment more targeted, and improve operating efficiency compared to the traditional "one-size-fits-all" migration method. The migration priority of the algorithm module is determined based on the mapping relationship to avoid resource waste. According to the instruction mapping rules, the code is converted for architectural adaptation. When generating the target adaptation application, the data transmission overhead between the processor and the hardware unit is reduced by dynamically adjusting the task allocation, and the overall resource utilization is improved. By performing test verification on the target hardware platform, resource usage data such as memory usage, processor utilization, and rendering time are collected to accurately locate performance bottlenecks. Through multiple rounds of data feedback iterative optimization, the comprehensive performance of the final ray tracing migration application is significantly improved compared to the initial version.

[0113] Furthermore, in a possible implementation of this embodiment, as Figure 4 As shown, the analysis unit 31 includes:

[0114] The parsing module 311 is used to parse the instruction system, register configuration, storage system and parallel computing architecture of the target hardware platform to generate architecture feature data;

[0115] A first generating module 312 is configured to determine computing resource data required to execute the ray tracing application, and to match and compare the computing resource data with the architecture feature data to generate resource requirement information;

[0116] The establishing module 313 is used to perform data mapping between the architecture feature data and the resource requirement data to establish a mapping relationship.

[0117] Furthermore, in a possible implementation of this embodiment, as Figure 4 As shown, the first generating unit 32 includes:

[0118] Adaptation module 321, used to adjust and adapt the source code of the algorithm module that needs to be adjusted according to the instruction mapping rules and code adjustment information;

[0119] A first conversion module 322 is configured to convert the adjusted source code into a target code supported by the target hardware platform;

[0120] The second conversion module 323 is used to convert the metadata of the ray tracing application into a format compatible with the target hardware platform.

[0121] Furthermore, in a possible implementation of this embodiment, as Figure 4As shown, the second generating unit 33 includes:

[0122] A construction module 331 is used to balance the computing load by using a dynamic block scheduling mechanism and to construct a hierarchical space partitioning structure to optimize the geometric intersection path when performing test verification on the target adaptation application;

[0123] The calling module 332 is used to call the hardware acceleration module of the target hardware platform to perform accelerated computing processing on the target adaptation application.

[0124] Furthermore, in a possible implementation of this embodiment, the construction module 331 is further configured to:

[0125] The target ray is divided into parallel processing computing units through a dynamic block scheduling mechanism, and the target ray generation process is reconstructed in parallel using a vectorized instruction set.

[0126] The hierarchical space partitioning structure is used to optimize the intersection path between the target light and the target object.

[0127] Furthermore, in a possible implementation of this embodiment, the calling module 332 is further configured to:

[0128] Based on the computational complexity and data dependency of the target adaptation application, the subtasks of the target adaptation application are assigned to the hardware acceleration module or processor core for computational processing.

[0129] Furthermore, in a possible implementation of this embodiment, as Figure 4 As shown, the second generating unit 33 further includes:

[0130] An analysis module 333 is used to analyze resource occupancy data and locate target algorithm modules with high resource occupancy in target adaptation applications;

[0131] A second generating module 334 is configured to generate a migration optimization strategy based on the target algorithm module and resource usage data;

[0132] The optimization module 335 is configured to optimize the target code of the target adaptation application in response to a code optimization instruction, and generate a ray tracing migration application, wherein the code optimization instruction is generated based on a migration optimization strategy.

[0133] It should be noted that the above explanation of the method embodiment is also applicable to the device of this embodiment, and the principles are the same, which is not limited in this embodiment.

[0134] For the description of the features in the embodiment corresponding to the device for application migration, please refer to the relevant description of the embodiment corresponding to the method for application migration, which will not be repeated here.

[0135] An embodiment of the present application further provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned application migration method embodiments.

[0136] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned application migration method embodiments when running.

[0137] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0138] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned application migration method embodiments are implemented.

[0139] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned application migration method embodiments are implemented.

[0140] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0141] The above is a detailed introduction to the method and device, electronic device and storage medium for application migration provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for application migration, characterized in that: include: Analyzing architectural features of a target hardware platform to generate architectural feature data, analyzing a ray tracing application to generate resource requirement information, establishing a mapping relationship between the architectural feature data and the resource requirement data, and generating migration priorities and code adjustment information for algorithm modules in the ray tracing application based on the mapping relationship; Adapting and converting the execution architecture of the ray tracing application according to the migration priority based on the instruction mapping rule and the code adjustment information to generate a target-adapted application that supports the target hardware platform; Allocating the target adaptation application to the target hardware platform for testing and verification, and collecting resource usage data when executing the target adaptation application; The target adaptation application is optimized based on the resource occupancy data to generate a ray tracing migration application.

2. The method for application migration according to claim 1, wherein: The analyzing the architecture characteristics of the target hardware platform to generate architecture characteristic data, analyzing the ray tracing application to generate resource requirement information, and establishing a mapping relationship between the architecture characteristic data and the resource requirement data includes: Analyzing the instruction system, register configuration, storage system, and parallel computing architecture of the target hardware platform to generate the architecture feature data; determining computing resource data required to execute the ray tracing application, and performing adaptation and comparison between the computing resource data and the architecture feature data to generate the resource requirement information; The architecture feature data and the resource requirement data are data mapped to establish the mapping relationship.

3. The application migration method according to claim 1, characterized in that: Adapting and converting the execution architecture of the ray tracing application according to the migration priority based on the instruction mapping rule and the code adjustment information includes: According to the instruction mapping rules and the code adjustment information, source code adjustment and adaptation are performed on the algorithm module that needs to be adjusted; Converting the adjusted source code into target code supported by the target hardware platform; The metadata of the ray tracing application is converted into a format compatible with the target hardware platform.

4. The method for application migration according to claim 1, wherein: The step of allocating the target adaptation application to the target hardware platform for testing and verification includes: When performing test verification on the target adaptation application, a dynamic block scheduling mechanism is used to balance the computing load and a hierarchical space partitioning structure is constructed to optimize the geometric intersection path; The hardware acceleration module of the target hardware platform is called to perform accelerated computing processing on the target adaptation application.

5. The method for application migration according to claim 4, characterized in that: The method utilizes a dynamic block scheduling mechanism to balance the computational load and constructs a hierarchical spatial partitioning structure to optimize the geometric intersection path, including: Dividing the target light into parallelizable computing units through the dynamic block scheduling mechanism, and reconstructing the target light generation process in parallel using a vectorized instruction set; The hierarchical space division structure is used to optimize the intersection path between the target light and the target object.

6. The method for application migration according to claim 4, characterized in that: The calling of the hardware acceleration module of the target hardware platform to perform accelerated computing processing on the target adaptation application includes: Based on the computational complexity and data dependency of the target adaptation application, the subtasks of the target adaptation application are allocated to the hardware acceleration module or the processor core for computational processing.

7. The method for application migration according to claim 1, wherein: The optimizing the target adaptation application based on the resource occupancy data to generate a ray tracing migration application includes: Analyze the resource occupancy data and locate the target algorithm module with high resource occupancy in the target adaptation application; Generate a migration optimization strategy based on the target algorithm module and the resource occupancy data; In response to a code optimization instruction, the target code of the target adaptation application is optimized to generate the ray tracing migration application, wherein the code optimization instruction is generated based on the migration optimization strategy.

8. An application migration device, characterized in that: include: an analysis unit, configured to analyze architectural features of a target hardware platform to generate architectural feature data, analyze a ray tracing application to generate resource requirement information, establish a mapping relationship between the architectural feature data and the resource requirement data, and generate migration priorities and code adjustment information for algorithm modules in the ray tracing application based on the mapping relationship; A first generating unit is configured to adapt and convert the execution architecture of the ray tracing application based on an instruction mapping rule, according to the migration priority and the code adjustment information, to generate a target-adapted application supporting the target hardware platform; A second generating unit is configured to allocate the target adaptation application to the target hardware platform for testing and verification, and collect resource usage data when executing the target adaptation application; The target adaptation application is optimized based on the resource occupancy data to generate a ray tracing migration application.

9. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the application migration method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to enable the computer to execute the application migration method according to any one of claims 1 to 7.

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