Equipment information display method and device, equipment and storage medium

Abstract

The invention discloses an equipment information display method and device, equipment and a storage medium, and relates to the technical field of data processing.The method includes the steps that in the initialization process of a basic input and output system, a depth-first search algorithm is adopted to sequentially read hardware equipment and obtain hardware equipment information, and the hardware equipment is equipment connected to a high-speed serial expansion bus; acquiring reference hardware information; the reference hardware information is identification information of a multi-core device connected to the high-speed serial expansion bus; identifying whether a multi-core device is connected to the high-speed serial expansion bus according to the hardware device information and the reference hardware information; if the multi-core device is connected, the device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information, and the device information is sent to the client device through the substrate management controller to be displayed, so that the accuracy of device information display is ensured.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a method, apparatus, device, and storage medium for displaying device information. Background Art

[0002] In modern computing systems, PCIe (Peripheral Component Interconnect Express) is a high-speed expansion bus standard widely used to connect peripherals such as graphics processing units, storage controllers, and network interfaces. Currently, PCIe devices are becoming increasingly complex, with many physical devices integrating multiple functional units to achieve multi-core or multi-tasking capabilities.

[0003] Currently, when a server is powered on, the basic input / output system enumerates and reads the hardware devices connected to the high-speed expansion bus, and sends the read hardware device information to the front end for display. This may cause a physical device integrating multiple functional units to be identified as multiple independent devices, leading to abnormal device information display. Summary of the Invention

[0004] The present application provides a device information display method, apparatus, device and storage medium to at least solve the problem of abnormal device information display in the related art.

[0005] In a first aspect, the present application provides a method for displaying device information, the method comprising:

[0006] During the initialization process, the basic input and output system uses a depth-first search algorithm to sequentially read hardware devices and obtain hardware device information. The hardware devices are devices connected to the high-speed serial expansion bus.

[0007] Obtain reference hardware information; the reference hardware information is identification information of a multi-core device connected to a high-speed serial expansion bus;

[0008] Identify whether a multi-core device is connected to the high-speed serial expansion bus based on hardware device information and reference hardware information;

[0009] If a multi-core device is connected, device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information, and is sent to the client device for display via the baseboard management controller.

[0010] In a second aspect, the present application provides a device information display method, the method comprising:

[0011] Receiving a query request sent by a basic input and output system; the query request includes a preset query command;

[0012] Obtaining identification information of a multi-core device connected to the high-speed serial expansion bus from an electrically erasable programmable read-only memory according to a query request, and determining the identification information of the multi-core device connected to the high-speed serial expansion bus as reference hardware information;

[0013] Sending reference hardware information to a basic input and output system; the reference hardware information is used to indicate a multi-core device connected to a high-speed serial expansion bus;

[0014] The device information corresponding to the multi-core device sent by the basic input and output system is received and sent to the client device for display; the device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information.

[0015] In a third aspect, the present application provides a method for displaying device information, the method comprising:

[0016] The basic input and output system sends a query request to the baseboard management controller; the query request includes a preset query command; the preset query command includes command identification information;

[0017] The baseboard management controller obtains identification information of the multi-core device connected to the high-speed serial expansion bus from the electrically erasable programmable read-only memory, and determines the identification information of the multi-core device connected to the high-speed serial expansion bus as reference hardware information;

[0018] The baseboard management controller sends the reference hardware information to the basic input and output system;

[0019] The basic input and output system identifies whether a multi-core device is connected to the high-speed serial expansion bus based on the hardware device information and the reference hardware information. If a multi-core device is connected, the basic input and output system generates device information corresponding to the multi-core device based on the hardware device information and the reference hardware information, and sends it to the client device for display through the baseboard management controller.

[0020] In a fourth aspect, the present application further provides a device information display apparatus, comprising:

[0021] The acquisition module is used to read the hardware devices in sequence using a depth-first search algorithm to obtain hardware device information during the initialization process of the basic input and output system. The hardware devices are devices connected to the high-speed serial expansion bus;

[0022] The acquisition module is further used to obtain reference hardware information; the reference hardware information is identification information of a multi-core device connected to the high-speed serial expansion bus;

[0023] an identification module, configured to identify whether a multi-core device is connected to the high-speed serial expansion bus based on hardware device information and reference hardware information;

[0024] A generation module, configured to generate device information corresponding to the multi-core device based on the hardware device information and reference hardware information if a multi-core device is connected;

[0025] The sending module is used to send the data to the client device for display via the baseboard management controller.

[0026] In a fifth aspect, the present application further provides a device information display apparatus, comprising:

[0027] A receiving module, configured to receive a query request sent by a basic input / output system; the query request includes a preset query command;

[0028] a determination module, configured to obtain identification information of a multi-core device connected to the high-speed serial expansion bus from the electrically erasable programmable read-only memory according to a query request, and determine the identification information of the multi-core device connected to the high-speed serial expansion bus as reference hardware information;

[0029] The sending module is used to send reference hardware information to the basic input and output system; the reference hardware information is used to indicate the multi-core device connected to the high-speed serial expansion bus;

[0030] The sending module is used to receive the device information corresponding to the multi-core device sent by the basic input and output system and send it to the client device for display; the device information corresponding to the multi-core device is generated based on the hardware device information and reference hardware information.

[0031] In a sixth aspect, the present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of the device information display method provided in the first aspect, the second aspect, or the third aspect when executing the computer program.

[0032] In the seventh aspect, the present application also provides a computer-readable storage medium, which stores a computer program, wherein when the computer program is executed by a processor, the steps of the device information display method provided in the first aspect, the second aspect, or the third aspect are implemented.

[0033] In an eighth aspect, the present application also provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of the device information display method provided in the first aspect, the second aspect, or the third aspect.

[0034] Through the device information display method, apparatus, equipment and storage medium provided by the present application, since a multi-core device can be composed of multiple independent hardware devices, in order to ensure that the device information of the multi-core device is displayed correctly and prevent it from being identified as multiple independent devices for device information display, during the initialization process of the basic input and output system, a depth-first search algorithm is first used to read the hardware devices in sequence to obtain the hardware device information of the hardware devices connected to the high-speed serial expansion bus, and obtain reference hardware information containing the identification information of the multi-core devices connected to the high-speed serial expansion bus. Therefore, the basic input and output system can identify whether a multi-core device is connected to the high-speed serial expansion bus based on the hardware device information and the reference hardware information. If a multi-core device is identified as being connected to the high-speed serial expansion bus, the device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information, and sent to the client device for display through the baseboard management controller, thereby avoiding the basic input and output system from identifying the multi-core device as multiple independent devices and ensuring the accuracy of the multi-core device information displayed on the client device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0036] Figure 1 This is an application scenario diagram of the device information display method provided in an embodiment of the present application;

[0037] Figure 2 A flowchart of a device information display method provided in one embodiment of the present application;

[0038] Figure 3 A flowchart of a device information display method provided in another embodiment of the present application;

[0039] Figure 4 A flowchart of a device information display method provided in another embodiment of the present application;

[0040] Figure 5 A schematic diagram of the structure of a device information display apparatus provided in one embodiment of the present application;

[0041] Figure 6 A schematic diagram of the structure of a device information display apparatus provided in another embodiment of the present application;

[0042] Figure 7 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0044] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0045] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0046] In modern server hardware architectures, when a device is powered on, the Basic Input / Output System (BIOS) initializes the system's hardware components. This process typically involves detecting devices connected to the motherboard's high-speed serial expansion bus. The BIOS scans the system bus and identifies all devices connected to it. After identification, it communicates with the baseboard management controller (BMC) through the hardware management interface. The BMC then displays information about the identified devices connected to the motherboard's high-speed serial expansion bus on the client device. Currently, for multi-core devices that include multiple independently functioning physical devices, the BIOS identifies these devices as separate devices. This results in the multi-core device not being displayed on the client device, resulting in device information display anomalies.

[0047] Therefore, when facing the above technical problems, during the initialization process of the basic input and output system, the correct device information corresponding to the multi-core device is generated by identifying the multi-core device. Specifically, the basic input and output system uses a depth-first search algorithm to read the hardware devices in sequence, so that the hardware device information of the device connected to the high-speed serial expansion bus can be obtained, and the reference hardware information containing the identification information of the multi-core device connected to the high-speed serial expansion bus can be obtained. Then, whether a multi-core device is connected to the high-speed serial expansion bus is identified through the hardware device information and the reference hardware information. If a multi-core device is identified as being connected to the high-speed serial expansion bus, the device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information, and is sent to the client device for display through the baseboard management controller, thereby achieving the correct identification of the multi-core device and the accurate generation of the multi-core device information, thereby ensuring the correct display of the device information.

[0048] Figure 1 This is an application scenario diagram of the device information display method provided in the embodiment of the present application. Figure 1 As shown, the application scenario provided by this embodiment includes: a server device 10, a basic input / output system 11, a baseboard management controller 12, and a client device 20. The device information display method is applied to the basic input / output system 11. The server device 10 includes the basic input / output system 11 and the baseboard management controller 12. When the server device 10 is turned on, the basic input / output system 11 uses a depth-first search algorithm to read hardware devices in sequence during initialization to obtain hardware device information. The hardware device is a device connected to a high-speed serial expansion bus. In addition, the basic input / output system 11 obtains reference hardware information, wherein the reference hardware information is identification information of a multi-core device connected to the high-speed serial expansion bus. The basic input / output system 11 identifies whether a multi-core device is connected to the high-speed serial expansion bus based on the hardware device information of the device connected to the high-speed serial expansion bus and the reference hardware information. If a multi-core device is identified as being connected to the high-speed serial expansion bus, the basic input / output system 11 generates device information corresponding to the multi-core device based on the hardware device information and the reference hardware information, and sends the information to the client device 20 for display via the baseboard management controller 12.

[0049] Figure 2 A flow chart of a device information display method provided in an embodiment of the present application is shown as follows: Figure 2 The device information display method provided in this embodiment is applied to a basic input and output system. The device information display method provided in this embodiment specifically includes the following steps:

[0050] S201: During the initialization process, the basic input and output system uses a depth-first search algorithm to read hardware devices in sequence to obtain hardware device information.

[0051] Hardware devices are devices connected to a high-speed serial expansion bus. Hardware device information is used to identify the device, allocate resources, configure the driver, and ensure the normal operation of the device.

[0052] Among them, the depth-first search algorithm is an algorithm for traversing a tree structure.

[0053] It is understandable that when a computer starts, the basic input and output system identifies and initializes all hardware devices connected to the motherboard, including the processor, memory, storage devices, PCIe devices, etc. These hardware devices usually exist in a hierarchical structure, such as a device tree or topology.

[0054] Specifically, in this embodiment, during the initialization process, the basic input and output system will use a depth-first search algorithm to enumerate from the root node and traverse the device tree layer by layer until all hardware devices are traversed, thereby obtaining hardware device information.

[0055] S202: Acquire reference hardware information.

[0056] The reference hardware information is identification information of a multi-core device connected to the high-speed serial expansion bus. The identification information of the multi-core device is used to uniquely identify the multi-core device.

[0057] Optionally, the identification information of the multi-core device may include source identification information of the multi-core device, sub-source identification information of the multi-core device, multi-core device identification information, etc., which is not limited in this embodiment.

[0058] Specifically, in this embodiment, the basic input and output system obtains reference hardware information from a preset database.

[0059] Optionally, the preset database may be an electrically erasable programmable read-only memory, etc., which is not limited in this embodiment.

[0060] S203: Identify whether a multi-core device is connected to the high-speed serial expansion bus according to the hardware device information and the reference hardware information.

[0061] Among them, a multi-core device can be a hardware device that physically integrates multiple independent computing cores or functional units.

[0062] It is understandable that the functional unit may be a physical device connected to a high-speed serial expansion bus, and multiple functional units may be combined into a logical multi-core device.

[0063] For example, multiple independent graphics processing units can be connected to the same server via a high-speed serial expansion bus and regarded as a logical multi-core device.

[0064] Specifically, in this embodiment, the basic input / output system reads the hardware device's head type register based on the hardware device information. If the type field of the hardware device's head type register is 0x00, the basic input / output system determines that the hardware device is a terminal device. The basic input / output system compares the hardware device information determined to be a terminal device with the identification information of the multi-core device. If the hardware device information of a device that matches the identification information of the multi-core device matches the identification information of the multi-core device, it indicates that the multi-core device is connected to the high-speed serial expansion bus. If the hardware device information of a device that matches the identification information of the multi-core device does not match the identification information of the multi-core device, it indicates that the multi-core device is not connected to the high-speed serial expansion bus.

[0065] Among them, the header type register is used to define the type and function of the PCIe device, and the lower 3 bits are used to distinguish the device role.

[0066] Optionally, the hardware device information may include identification information of the hardware device, source identification information of the hardware device, sub-source identification information of the hardware device, etc., which is not limited in this embodiment.

[0067] S204: If a multi-core device is connected, device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information, and is sent to the client device via the baseboard management controller for display.

[0068] The reference hardware information includes the bus width and transmission rate supported by the multi-core device.

[0069] It is understood that the bus width supported by the multi-core device refers to the data transmission bit width between the multi-core device and the bus. The transmission rate supported by the multi-core device refers to the physical layer transmission rate between the multi-core device and the bus.

[0070] Specifically, in this embodiment, if the basic input and output system recognizes that a multi-core device is connected to the high-speed serial expansion bus, it obtains the device information corresponding to the multi-core device from the hardware device information and the reference hardware information, and sends the generated device information corresponding to the multi-core device to the baseboard management controller, and then sends the generated device information of the multi-core device to the client device through the baseboard management controller for display.

[0071] Exemplarily, the basic input and output system obtains the bus width and transmission rate supported by the multi-core device from the reference hardware information, and obtains the location string of the multi-core device from the hardware device information, and uses the bus width, transmission rate and location string of the multi-core device as the device information corresponding to the multi-core device.

[0072] Furthermore, the basic input and output system updates the device information corresponding to the generated multi-core device in the system slot information table.

[0073] It is understandable that the system slot information table is used to describe the type, location, status and configuration information of the physical expansion slots (such as PCIe, etc.) on the computer motherboard, helping the system to identify available slots and their hardware connection status.

[0074] Among them, PCIe's full English name is Peripheral Component Interconnect express, and its full Chinese name is high-speed serial computer expansion bus standard.

[0075] Specifically, since a multi-core device may be composed of multiple independent hardware devices, in order to ensure that the device information of the multi-core device is displayed correctly and prevent it from being identified as multiple independent devices for device information display, during the initialization process of the basic input and output system, a depth-first search algorithm is first used to read the hardware devices in sequence, obtain the hardware device information of the hardware devices connected to the high-speed serial expansion bus, and obtain the reference hardware information containing the identification information of the multi-core devices connected to the high-speed serial expansion bus. In this way, the basic input and output system can identify whether a multi-core device is connected to the high-speed serial expansion bus based on the hardware device information and the reference hardware information. If a multi-core device is identified as being connected to the high-speed serial expansion bus, the device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information, and sent to the client device for display through the baseboard management controller, thereby avoiding the basic input and output system from identifying the multi-core device as multiple independent devices and ensuring the accuracy of the multi-core device information displayed on the client device.

[0076] As an optional implementation manner, based on any of the above embodiments, obtaining reference hardware information includes:

[0077] Create the first target structure;

[0078] Send a query request to the baseboard management controller using a preset query command;

[0079] In response to receiving identification information of a multi-core device connected to a high-speed serial expansion bus sent by a baseboard management controller, the identification information of the multi-core device connected to the high-speed serial expansion bus is stored in a first target structure, and the identification information of the multi-core device stored in the first target structure is determined as reference hardware information.

[0080] The first target structure is used to store identification information of the multi-core device.

[0081] The preset query command is a pre-defined command used to query the identification information of a multi-core device. The preset query command is independently created by the baseboard management controller. The preset query command is an OEM IPMI command. The OEM IPMI command is an OEM (Original Equipment Manufacturer) extension of the IPMI (Intelligent Platform Management Interface).

[0082] Specifically, in this embodiment, the basic input / output system constructs a first target structure, communicates with the baseboard management controller via a preset interface, and sends a preset query command to query the identification information of the multi-core device. In response to receiving the identification information of the multi-core device connected to the high-speed serial expansion bus from the baseboard management controller, the basic input / output system stores the obtained identification information of the multi-core device in the first target structure and uses the identification information of the multi-core device stored in the first target structure as reference hardware information. Optionally, the preset interface can be a representational state transfer application programming interface or an IPMI interface, etc., which is not limited in this embodiment.

[0083] The Representational State Transfer (RST) API is a software interface running on the baseboard management controller. It is based on the REST (Representational State Transfer) architectural style and interacts with external systems via the HTTP protocol. The IPMI interface, short for Intelligent Platform Management Interface, is a hardware-level remote management standard.

[0084] The preset query command includes specific command unique identification information for identifying the command as a query command, and also includes command identification information for identifying the command category.

[0085] It can be understood that the command identification information may be used to identify that the command is a command for a multi-core device, and the command unique identification information is used to identify that the command is a query command.

[0086] Specifically, by using a predefined query command to query the identification information of the multi-core device, the protocol compatibility with the baseboard management controller is ensured, communication errors are reduced, and the obtained identification information of the multi-core device is stored in the created first target structure, which can avoid data confusion and facilitate subsequent calls.

[0087] As an optional implementation manner, based on any of the above embodiments, the identification information of the multi-core device includes source identification information of the multi-core device, sub-source identification information of the multi-core device, multi-core device identification information and model identification information of the multi-core device;

[0088] Identify whether a multi-core device is connected to the high-speed serial expansion bus based on the hardware device information and reference hardware information, including:

[0089] Determining whether each hardware device is a terminal device based on the hardware device information;

[0090] If it is determined that the hardware device is a terminal device, then sequentially read the source identification information of the hardware device, the sub-source identification information of the hardware device, and the model identification information of the hardware device in the hardware device information;

[0091] Comparing the source identification information of the hardware device with the source identification information of the multi-core device, the sub-source identification information of the hardware device with the sub-source identification information of the multi-core device, the hardware device identification information with the multi-core device identification information, and the model identification information of the hardware device with the model identification information of the multi-core device;

[0092] If there is simultaneously the source identification information of a multi-core device that is the same as the source identification information of the hardware device, the sub-source identification information of a multi-core device that is the same as the sub-source identification information of the hardware device, the multi-core device identification information that is the same as the hardware device identification information, and the model identification information of a multi-core device that is the same as the model identification information of the hardware device, it is determined that a multi-core device is connected to the high-speed serial expansion bus.

[0093] The source identification information is used to identify the manufacturer of the device. The sub-source identification information is used to identify the manufacturer of the device's subsystem. The device identification information is used to identify the specific model of the device. The model identification information is used to identify the subsystem model of the device.

[0094] The hardware device information includes the source identification information of the device, the sub-source identification information of the device, the device identification information of the device, and the model identification information of the device.

[0095] The source identification information of the device may be the device manufacturer identification code. The sub-source identification information of the device may be the subsystem manufacturer identification code. The identification information of the device may be the hardware device identification code. The model identification information of the device may be the subsystem identification code.

[0096] Specifically, in this embodiment, the basic input and output system reads the bus information, device information and function information in the hardware device information in sequence, obtains the configuration space address of each device through the bus information, device information and function information and the preset offset address, and accesses the configuration space, thereby reading the head type register of the hardware device. If the type field of the head type register of the hardware device is 0x00, it is determined that the hardware device is a terminal device. If the device is a terminal device, the basic input and output system reads the source identification information, sub-source identification information, hardware device identification information and model identification information of the hardware device in sequence, and compares the source identification information of each hardware device with the source identification information of the multi-core device, as well as the sub-source identification information of the hardware device with the sub-source identification information of the multi-core device, and the hardware device identification information with the multi-core device identification information, and the model identification information of the hardware device with the model identification information of the multi-core device. When there is source identification information of a multi-core device that is identical to the source identification information of the hardware device, and there is sub-source identification information of a multi-core device that is identical to the sub-source identification information of the hardware device, and there is multi-core device identification information that is identical to the hardware device identification information, and there is model identification information of a multi-core device that is identical to the model identification information of the hardware device, it means that a multi-core device is connected to the high-speed serial expansion bus.

[0097] The bus information identifies the bus on which the device is located. The device information identifies the location of the device on the bus. The function information specifies the specific function of the device.

[0098] It is understood that a terminal device is a leaf node device on a high-speed serial expansion bus, and is generally used to implement specific functions. A multi-core device is connected to the bus as a terminal device.

[0099] It can be understood that it is necessary to simultaneously meet the following conditions: the source identification information of the hardware device is the same as the source identification information of the multi-core device, the sub-source identification information of the hardware device is the same as the sub-source identification information of the multi-core device, the hardware device identification information is the same as the multi-core device identification information, and the model identification information of the hardware device is the same as the model identification information of the multi-core device, in order to indicate that a multi-core device is connected to the high-speed serial expansion bus.

[0100] Specifically, since the multi-core device is connected to the bus as a terminal device, it is first determined whether the device is a terminal device based on the hardware device information, thereby avoiding identification errors. The source identification information of the hardware device, the sub-source identification information of the device, the device identification information and the model identification information of the device can uniquely identify the device. Therefore, by sequentially reading the source identification information, the sub-source identification information and the model identification information of the hardware device determined as a terminal device in the hardware device information, and comparing them one by one with the source identification information of the multi-core device, the sub-source identification information of the multi-core device, the multi-core device identification information and the model identification information of the multi-core device in the reference hardware information, only when the source identification information of the device, the sub-source identification information of the device, the device identification information and the model identification information of the device are all the same, will it be determined that the multi-core device is connected to the high-speed serial expansion bus, thereby achieving accurate identification of the multi-core device.

[0101] As an optional implementation manner, based on any of the above embodiments, the identification information of the multi-core device includes source identification information of the multi-core device, sub-source identification information of the multi-core device, multi-core device identification information, and model identification information of the multi-core device; the multi-core device includes at least two sub-devices; the sub-devices have the same source identification information, the same sub-source identification information, the same device identification information, and the same model identification information; the hardware device information includes first location information, a first device supported bus width, and a first device supported communication speed; the device information corresponding to the multi-core device includes second location information, a second device bus width, and a second device supported communication speed;

[0102] Generate device information corresponding to the multi-core device based on the hardware device information and reference hardware information, including:

[0103] Sequentially read the first device bus width and the first device supported communication speed from the hardware device information of each sub-device and the first location information of the upper-level device commonly connected to each sub-device;

[0104] Determine the maximum first device bus width and the first device supported communication speed corresponding to each sub-device as the second device bus width and the second device supported communication speed of the multi-core device;

[0105] Determine the first location information of the upper-level device to which each sub-device is commonly connected as the second location information of the multi-core device;

[0106] The second location information, the second device bandwidth, and the second device supported communication speed are determined as device information corresponding to the multi-core device.

[0107] It is understandable that a multi-core device is composed of multiple sub-devices, and the sub-devices are also connected to a high-speed serial expansion bus.

[0108] The first device supports a bus width corresponding to the data transmission bit width between each device connected to the high-speed serial expansion bus and the bus. The first device supports a communication speed corresponding to the physical layer transmission rate between each device connected to the high-speed serial expansion bus and the bus. The first location information is location information of a higher-level device commonly connected to the sub-devices of the multi-core device.

[0109] The second location information is the location information of the upper-level device to which the sub-devices of the multi-core device are commonly connected. The upper-level device may be a bridge device. The second device bus width is the corresponding data transmission bit width between the multi-core device as a whole and the bus. The second device supported communication speed is the corresponding physical layer transmission rate between the multi-core device as a whole and the bus.

[0110] The upper-level device is a device that is commonly connected to the sub-devices that make up the multi-core device.

[0111] Optionally, the upper-level device may be a bridge device, which is not limited in this embodiment.

[0112] Specifically, in this embodiment, the basic input / output system sequentially reads the first device supported bus width and first device supported communication speed of each hardware device in the hardware device information, as well as the first location information of the upper-level device to which each sub-device is commonly connected. The basic input / output system compares the first device supported bus widths of each sub-device and selects the largest first device supported bus width as the second device bus width. The basic input / output system also compares the first device supported communication speeds of each sub-device and selects the largest first device supported communication speed as the second device supported communication speed. The basic input / output system uses the first location information of the upper-level device to which each sub-device is commonly connected as the second location information of the multi-core device. The second location information, the second device bandwidth, and the second device supported communication speed are determined as the device information corresponding to the multi-core device.

[0113] Specifically, since a multi-core device is composed of multiple sub-devices, each sub-device has a corresponding first device-supported bus width and first device-supported communication speed. Therefore, by obtaining the first device-supported bus width and first device-supported communication speed corresponding to each sub-device in the multi-core device, the maximum first device bus width and first device-supported communication speed corresponding to each sub-device are determined as the second device bus width and second device-supported communication speed of the multi-core device, thereby fully utilizing the maximum capabilities of the sub-devices. Since each sub-device is connected through an upper-level device, the first position information of the upper-level device to which each sub-device is commonly connected is used as the second position information of the multi-core device, thereby ensuring that the position identification of the multi-core device in the system is consistent with its physical connection. In addition, by aggregating the hardware characteristics of the sub-devices into the unified characteristics of the multi-core device, the multi-core device is represented as a whole in the system, rather than a simple collection of multiple independent sub-devices.

[0114] Figure 3 A flow chart of a device information display method provided in another embodiment of the present application is shown as follows: Figure 3 The device information display method provided in this embodiment is applied to a baseboard management controller. The device information display method provided in this embodiment specifically includes the following steps:

[0115] S301: Receive a query request sent by a basic input and output system.

[0116] The query request includes a preset query command.

[0117] The query request is used to query the identification information of the multi-core device.

[0118] Specifically, in this embodiment, the baseboard management controller receives a query request sent by the basic input and output system, which includes a preset query command.

[0119] S302: Obtain identification information of a multi-core device connected to the high-speed serial expansion bus from the EEPROM according to the query request, and determine the identification information of the multi-core device connected to the high-speed serial expansion bus as reference hardware information.

[0120] Specifically, in this embodiment, the baseboard management controller obtains the identification information of the multi-core device connected to the high-speed serial expansion bus pre-stored from the electrically erasable programmable read-only memory, and determines the identification information of the multi-core device connected to the high-speed serial expansion bus as the reference hardware information.

[0121] S303: Send reference hardware information to the basic input and output system.

[0122] The reference hardware information is used to indicate a multi-core device connected to the high-speed serial expansion bus.

[0123] Specifically, in this embodiment, the baseboard management controller communicates with the basic input and output system through a preset interface and sends the reference hardware information to the basic input and output system.

[0124] Optionally, the preset interface may be an application programming interface designed in accordance with REST architecture principles, which is not limited in this embodiment.

[0125] S304: Receive device information corresponding to the multi-core device sent by the basic input and output system, and send it to the client device for display.

[0126] The device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information.

[0127] Specifically, in this embodiment, the baseboard management controller receives device information corresponding to the multi-core device sent by the basic input and output system, communicates with the client device, and sends the device information corresponding to the multi-core device to the client device for display.

[0128] Optionally, the baseboard management controller may also receive a query request sent by a client device, and after receiving the query request, obtain the identification information of the multi-core device connected to the high-speed serial expansion bus from the electrically erasable programmable read-only memory and store it in a pre-created structure. Since the identification information of the multi-core device connected to the high-speed serial expansion bus exists in machine language, the identification information of the multi-core device connected to the high-speed serial expansion bus stored in the structure is escaped according to preset rules, and the escaped identification information of the multi-core device connected to the high-speed serial expansion bus is sent to the client device.

[0129] Optionally, the preset rules can be set independently, which is not limited in this embodiment.

[0130] Specifically, the electrically erasable programmable read-only memory is non-volatile, and data will not be lost even after a power outage, so that the identification information of the multi-core devices connected to the high-speed serial expansion bus stored therein can be preserved for a long time and is not affected by the system power state. After receiving a query request, the identification information of the multi-core devices connected to the high-speed serial expansion bus can be quickly and accurately obtained from the electrically erasable programmable read-only memory, and the electrically erasable programmable read-only memory can allow the data to be updated, thereby ensuring that the identification information of the multi-core devices connected to the high-speed serial expansion bus obtained is the latest. Furthermore, by receiving the device information corresponding to the multi-core devices sent by the basic input and output system and sending it to the client device for display, the normal display of the device information of the multi-core devices is achieved.

[0131] As an optional implementation manner, based on the above embodiment, it also includes:

[0132] Receive a storage request; the storage request includes a storage command; the storage command includes command identification information and identification information of the multi-core device to be stored; the command identification information is used to identify the type of the command;

[0133] Comparing the command identification information in the preset stored command with the preset verification information;

[0134] If the command identification information is different from the preset verification information, the preset warning information is returned;

[0135] If the command identification information is the same as the preset verification information, a second target structure is created;

[0136] Reading identification information of the multi-core device to be stored, and storing the identification information of the multi-core device to be stored in a second target structure;

[0137] Obtaining identification information of the stored multi-core device from the electrically erasable programmable read-only memory, and comparing the identification information with the identification information of the multi-core device to be stored in the second target structure;

[0138] If there is identification information of a multi-core device to be stored that is different from the identification information of the stored multi-core device, the identification information of the multi-core device to be stored that is different from the identification information of the stored multi-core device is stored in the EEPROM.

[0139] The storage request is used to guide the storage of identification information of the multi-core device.

[0140] The storage command is a pre-defined command for storing identification information of a multi-core device. The storage command is independently created by the baseboard management controller. The storage command is an OEM IPMI command. The preset verification information is used to verify whether the command identification information is correct. The preset warning information is used to indicate that the command identification information is incorrect and is information identifying the command as a multi-core device command. The second target structure is a structure for storing the identification information of the multi-core device to be stored.

[0141] There is also command identification information in the preset query command, and the command identification information of the preset query command is the same as the command identification information of the storage command, indicating that both the preset query command and the storage command are commands for multi-core devices.

[0142] Optionally, the command identification information can be set independently, which is not limited in this embodiment.

[0143] Optionally, the preset warning information can be set independently, which is not limited in this embodiment.

[0144] Specifically, in this embodiment, the baseboard management controller receives a storage request sent by the user through a storage command on the client device, and the storage command includes command identification information and identification information of the multi-core device to be stored. After receiving the storage command, the baseboard management controller reads the command identification information in the storage command and compares it with the preset verification information. If the command identification information is different from the preset verification information, it means that the storage command is invalid, and returns a preset warning information to the client device. If the command identification information is the same as the preset verification information, a second target structure is created, the identification information of the multi-core device to be stored in the storage command is parsed and read, and the identification information of the multi-core device to be stored is stored in the second target structure. Further, the identification information of the stored multi-core device is read from the electrically erasable programmable read-only memory, and the identification information of the stored multi-core device is compared with the identification information of the multi-core device to be stored in the second target structure. If the identification information of the multi-core device to be stored already exists in the identification information of the stored multi-core device, it does not need to be stored again, and the identification information of the multi-core device to be stored that is different from the identification information of the stored multi-core device is stored in the electrically erasable programmable read-only memory.

[0145] Specifically, after receiving a storage request, the storage command is verified by using preset verification information to ensure the legality and validity of the storage command, and when the command identification information is different from the preset verification information, the preset warning information is promptly returned to help the requester discover and correct the error in a timely manner. When the command identification information is the same as the preset verification information, the identification information of the multi-core device to be stored is stored by creating a second target structure, and the identification information of the multi-core device to be stored is compared with the identification information of the stored multi-core device to avoid repeated storage of the identification information of the multi-core device, thereby saving storage space and improving the efficiency of data query.

[0146] Optionally, if the multi-core device is adjusted and the identification information of the multi-core device stored in the electrically erasable programmable read-only memory needs to be deleted, this can be achieved through a delete command.

[0147] Specifically, the baseboard management controller receives a deletion request sent by the user through a deletion command on a client device, and the deletion command includes command identification information and identification information of the multi-core device to be deleted. After receiving the deletion command, the baseboard management controller reads the command identification information in the deletion command and compares it with the preset verification information. If the command identification information is different from the preset verification information, it means that the storage command is invalid, and returns the preset warning information to the client device. If the command identification information is the same as the preset verification information, a third target structure is created, the identification information of the multi-core device to be deleted in the deletion command is parsed and read, and the identification information of the multi-core device to be deleted is stored in the third target structure. Furthermore, the identification information of the stored multi-core device is read from the electrically erasable programmable read-only memory, the identification information of the stored multi-core device read is stored in the preset variable, and the identification information of the multi-core device stored in the electrically erasable programmable read-only memory is deleted. The identification information of the multi-core device stored in the preset variable is compared with the identification information of the multi-core device to be deleted in the second target structure. If the identification information of the multi-core device to be deleted exists in the identification information of the stored multi-core device, the identification information of the multi-core device in the preset variable that is the same as the identification information of the multi-core device to be deleted is deleted to obtain the updated identification information of the multi-core device, and the updated identification information of the multi-core device is re-stored in the electrically erasable programmable read-only memory. After the storage is successful, a prompt message of successful deletion is returned to the client device.

[0148] The deletion request is used to instruct deletion of identification information of the multi-core device.

[0149] The delete command is a pre-set command for deleting identification information of a multi-core device. The delete command is autonomously created by the baseboard management controller. The delete command is an OEM IPMI command. Pre-set verification information is used to verify whether the command identification information is correct. Pre-set warning information is used to indicate that the command identification information is incorrect and is information identifying the command as a multi-core device command. The third target structure is a structure for storing the identification information of the multi-core device to be deleted.

[0150] The command identification information of the preset query command is the same as the command identification information of the storage command and the delete command, indicating that the preset query command, the storage command and the delete command are all commands for multi-core devices.

[0151] Optionally, the prompt message of successful deletion can be set independently, which is not limited in this embodiment.

[0152] Optionally, the preset variables can be set independently, which is not limited in this embodiment.

[0153] Specifically, after receiving a deletion request, the deletion command is verified by using preset verification information to ensure the legality and validity of the deletion command, and when the command identification information is different from the preset verification information, the preset warning information is returned in time, which helps the requester to find and correct the error in time. When the command identification information is the same as the preset verification information, the identification information of the multi-core device to be deleted is stored by creating a third target structure, and the identification information of the multi-core device stored in the electrically erasable programmable read-only memory and the identification information of the multi-core device stored in the electrically erasable programmable read-only memory are read, and the identification information of the multi-core device stored in the electrically erasable programmable read-only memory is stored in the preset variables and deleted. By comparing the identification information of the multi-core device to be deleted with the identification information of the stored multi-core device, the identification information of the multi-core device to be deleted can be accurately found and deleted in the identification information of the stored multi-core device, and the updated identification information of the multi-core device can be re-stored in the electrically erasable programmable read-only memory, thereby realizing the update of the identification information of the stored multi-core device and improving the flexibility of multi-core device recognition.

[0154] This embodiment also provides a device information display method, which includes:

[0155] The basic input and output system sends a query request to the baseboard management controller; the query request includes a preset query command; the preset query command includes command identification information.

[0156] The baseboard management controller obtains identification information of the multi-core device connected to the high-speed serial expansion bus from the electrically erasable programmable read-only memory, and determines the identification information of the multi-core device connected to the high-speed serial expansion bus as reference hardware information.

[0157] The baseboard management controller sends the reference hardware information to the basic input and output system.

[0158] The basic input and output system identifies whether a multi-core device is connected to the high-speed serial expansion bus based on the hardware device information and the reference hardware information. If a multi-core device is connected, the basic input and output system generates device information corresponding to the multi-core device based on the hardware device information and the reference hardware information, and sends it to the client device for display through the baseboard management controller.

[0159] Specifically, in this embodiment, the basic input / output system sends a query request to the baseboard management controller. After receiving the query request, the baseboard management controller reads the identification information of the multi-core device connected to the high-speed serial expansion bus stored in the electrically erasable programmable read-only memory, and sends the identification information of the multi-core device connected to the high-speed serial expansion bus as reference hardware information to the basic input / output system. The basic input / output system identifies whether a multi-core device is connected to the high-speed serial expansion bus based on the hardware device information and the reference hardware information. If it is determined that a multi-core device is connected, the basic input / output system generates device information corresponding to the multi-core device based on the hardware device information and the reference hardware information, and sends the generated device information corresponding to the multi-core device to the baseboard management controller, which then sends the generated device information corresponding to the multi-core device to the client device for display.

[0160] Specifically, the basic input / output system obtains the identification information of the multi-core device connected to the stored high-speed serial expansion bus from the baseboard management controller, so that the multi-core device connected to the high-speed serial expansion bus can be identified according to the hardware device information, and the device information corresponding to the multi-core device is generated, which is then sent to the client device for display through the baseboard management controller, thereby avoiding the basic input / output system from identifying the multi-core device as multiple independent devices, and realizing the correct display of the multi-core device information on the client device.

[0161] Figure 4 A flow chart of a device information display method provided in another embodiment of the present application is shown as follows: Figure 4 This embodiment also provides a device information display method, which includes:

[0162] S401: During the initialization process, the basic input and output system uses a depth-first search algorithm to enumerate hardware devices in sequence to obtain hardware device information.

[0163] S402: The basic input / output system sends a query request to the baseboard management controller using a preset query command.

[0164] S403: The baseboard management controller receives the query request and obtains identification information of the multi-core device connected to the high-speed serial expansion bus from the electrically erasable programmable read-only memory.

[0165] S404: The baseboard management controller sends identification information of the multi-core device connected to the high-speed serial expansion bus to the basic input and output system.

[0166] S405: The basic input and output system creates a first target structure to store identification information of the multi-core device connected to the high-speed serial expansion bus.

[0167] Among them, the identification information of the multi-core device connected to the high-speed serial expansion bus includes the source identification information of the multi-core device, the sub-source identification information of the multi-core device, the multi-core device identification information, the model identification information of the multi-core device and the number of sub-devices included in the multi-core device.

[0168] S406: Read the header type registers of the configuration space of the hardware devices in sequence according to the hardware device information to determine whether each hardware device is a terminal device.

[0169] S407: If it is determined that the hardware device is a terminal device, the source identification information, sub-source identification information and model identification information of the hardware device are compared with the identification information of the multi-core device connected to the high-speed serial expansion bus stored in the first target structure to determine whether there is a multi-core device source identification information, sub-source identification information, multi-core device identification information and model identification information that are the same as the source identification information, sub-source identification information and model identification information of the hardware device.

[0170] S408: If there is no source identification information of a multi-core device, sub-source identification information of a multi-core device, multi-core device identification information and model identification information of a multi-core device that are identical to the source identification information, sub-source identification information and model identification information of the hardware device, then the device information corresponding to the hardware device is directly sent to the baseboard management controller.

[0171] S409: If there is a multi-core device's source identification information, a multi-core device's sub-source identification information, a multi-core device's identification information, and a multi-core device's model identification information that are identical to the hardware device's source identification information, the hardware device's sub-source identification information, and the hardware device's model identification information, then generate device information corresponding to the multi-core device based on the hardware device information and the reference hardware information.

[0172] S410: Send the generated device information corresponding to the multi-core device to the baseboard management controller.

[0173] S411: The basic input and output system reads the number of sub-devices included in the multi-core device, skips reading the remaining sub-devices, and does not send device information corresponding to the sub-devices to the baseboard management controller.

[0174] The basic input / output system updates the device information sent to the baseboard management controller in the system slot information table.

[0175] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0176] Figure 5 This is a schematic diagram of the structure of the device information display device provided in one embodiment of the present application. Figure 5 As shown, the device information display method described above is implemented by a device information display device. This device information display device can be implemented via a computer program; it can also be implemented via a medium storing the relevant computer program, such as a USB flash drive and / or optical disk, or it can also be implemented via a physical device, such as an electronic device, that integrates or installs the relevant computer program. The electronic device can be a computer or a server. The device information display device provided in this embodiment is located in the electronic device. The device information display device 50 provided in this embodiment includes: an acquisition module 51, an identification module 52, a generation module 53, and a transmission module 54.

[0177] Specifically, the acquisition module 51 is used to read the hardware devices in sequence using a depth-first search algorithm during the initialization process of the basic input and output system to obtain hardware device information. The hardware device is a device connected to the high-speed serial expansion bus; the acquisition module 51 is also used to obtain reference hardware information; the reference hardware information is the identification information of the multi-core device connected to the high-speed serial expansion bus; the identification module 52 is used to identify whether a multi-core device is connected to the high-speed serial expansion bus based on the hardware device information and the reference hardware information; the generation module 53 is used to generate device information corresponding to the multi-core device based on the hardware device information and the reference hardware information if a multi-core device is connected; the sending module 54 is used to send it to the client device for display through the baseboard management controller.

[0178] Optionally, when acquiring reference hardware information, the acquisition module 51 is specifically used to: create a first target structure; send a query request to the baseboard management controller using a preset query command; in response to receiving identification information of a multi-core device connected to the high-speed serial expansion bus sent by the baseboard management controller, store the identification information of the multi-core device connected to the high-speed serial expansion bus in the first target structure, and determine the identification information of the multi-core device stored in the first target structure as the reference hardware information.

[0179] Optionally, the identification information of the multi-core device includes source identification information of the multi-core device, sub-source identification information of the multi-core device, multi-core device identification information, and model identification information of the multi-core device.

[0180] Accordingly, when identifying whether a multi-core device is connected to the high-speed serial expansion bus based on the hardware device information and the reference hardware information, the identification module 52 is used to: determine whether each hardware device is a terminal device based on the hardware device information; if it is determined that the hardware device is a terminal device, then read the source identification information of the hardware device, the sub-source identification information of the hardware device, the hardware device identification information and the model identification information of the hardware device in the hardware device information in sequence; compare the source identification information of the hardware device with the source identification information of the multi-core device, the sub-source identification information of the hardware device with the sub-source identification information of the multi-core device, the hardware device identification information with the multi-core device identification information and the model identification information of the hardware device with the model identification information of the multi-core device; if there is simultaneously the source identification information of the multi-core device that is identical to the source identification information of the hardware device, the sub-source identification information of the multi-core device that is identical to the sub-source identification information of the hardware device, the multi-core device identification information that is identical to the hardware device identification information and the model identification information of the multi-core device that is identical to the model identification information of the hardware device, then it is determined that a multi-core device is connected to the high-speed serial expansion bus.

[0181] Optionally, the identification information of the multi-core device includes the source identification information of the multi-core device, the sub-source identification information of the multi-core device, the multi-core device identification information and the model identification information of the multi-core device; the multi-core device includes at least two sub-devices; the sub-devices have the same source identification information, the same sub-source identification information, the same device identification information and the same model identification information; the hardware device information includes first location information, the first device supported bus width and the first device supported communication speed; the device information corresponding to the multi-core device includes second location information, the second device supported bus width and the second device supported communication speed.

[0182] Accordingly, when generating device information corresponding to a multi-core device based on hardware device information and reference hardware information, the generation module 53 is used to: sequentially read the first device supported bus width and the first device supported communication speed in the hardware device information of each sub-device and the first position information of the upper-level device to which each sub-device is commonly connected; determine the maximum first device supported bus width and first device supported communication speed corresponding to each sub-device as the second device supported bus width and the second device supported communication speed of the multi-core device; determine the first position information of the upper-level device to which each sub-device is commonly connected as the second position information of the multi-core device; and determine the second position information, the second device supported bus width and the second device supported communication speed as the device information corresponding to the multi-core device.

[0183] For the description of the features in the embodiment corresponding to the device information display apparatus, please refer to the relevant description of the embodiment corresponding to the device information display method, and will not be repeated here.

[0184] Figure 6This is a structural diagram of a device information display device provided by another embodiment of the present application. Figure 6 As shown, the device information display method described above is implemented by a device information display device. This device information display device can be implemented via a computer program; it can also be implemented via a medium storing the relevant computer program, such as a USB flash drive and / or optical disk, or it can also be implemented via a physical device, such as an electronic device, that integrates or installs the relevant computer program. The electronic device can be a computer or a server. The device information display device provided in this embodiment is located in the electronic device. The device information display device 60 provided in this embodiment includes: a receiving module 61, a determining module 62, and a sending module 63.

[0185] Specifically, the receiving module 61 is used to receive a query request sent by the basic input and output system; the query request includes a preset query command; the determining module 62 is used to obtain the identification information of the multi-core device connected to the high-speed serial expansion bus from the electrically erasable programmable read-only memory according to the query request, and determine the identification information of the multi-core device connected to the high-speed serial expansion bus as the reference hardware information; the sending module 63 is used to send the reference hardware information to the basic input and output system; the reference hardware information is used to indicate the multi-core device connected to the high-speed serial expansion bus; the sending module 63 is also used to receive the device information corresponding to the multi-core device sent by the basic input and output system, and send it to the client device for display; the device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information.

[0186] Optionally, the device information display apparatus 60 further includes: a comparison module, a return module, a creation module and a storage module.

[0187] Correspondingly, the receiving module 61 is used to receive a storage request; the storage request includes a storage command; the storage command includes command identification information and identification information of the multi-core device to be stored; the command identification information is used to identify the category of the command. The comparison module is used to compare the command identification information in the preset storage command with the preset verification information. The return module is used to return the preset warning information if the command identification information is different from the preset verification information. The creation module is used to create a second target structure if the command identification information is the same as the preset verification information. The storage module is used to read the identification information of the multi-core device to be stored and store the identification information of the multi-core device to be stored in the second target structure. The comparison module is also used to obtain the identification information of the stored multi-core device from the electrically erasable programmable read-only memory and compare it with the identification information of the multi-core device to be stored in the second target structure. The storage module is used to store the identification information of the multi-core device to be stored that is different from the identification information of the stored multi-core device in the electrically erasable programmable read-only memory if there is identification information of the multi-core device to be stored that is different from the identification information of the stored multi-core device. Figure 7 This is a schematic diagram of the structure of an electronic device provided in one embodiment of the present application. Figure 7 As shown, the electronic device 70 provided in an embodiment of the present application includes: a memory 71 and a processor 72.

[0188] The memory 71 stores a computer program, and the processor 72 is configured to run the computer program to execute the steps in any of the above-mentioned device information display method embodiments.

[0189] The specific implementation process of the processor 72 can be found in the above-mentioned method embodiment. Its implementation principle and technical effects are similar, and will not be repeated here in this embodiment.

[0190] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the application may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0191] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0192] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0193] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. The computer program is configured to execute the steps of any of the above-mentioned device information display method embodiments when running.

[0194] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0195] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned device information display method embodiments are implemented.

[0196] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned device information display method embodiments.

[0197] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0198] The above is a detailed introduction to a device information display method provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A device information display method, characterized in that: The method comprises: During the initialization process, the basic input and output system uses a depth-first search algorithm to sequentially read hardware devices to obtain hardware device information, wherein the hardware devices are devices connected to the high-speed serial expansion bus; Acquire reference hardware information; the reference hardware information is identification information of a multi-core device connected to a high-speed serial expansion bus; identifying whether the multi-core device is connected to the high-speed serial expansion bus according to the hardware device information and the reference hardware information; If the multi-core device is connected, device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information, and is sent to the client device for display via the baseboard management controller.

2. The device information display method according to claim 1, characterized in that: The obtaining of reference hardware information includes: Create the first target structure; Send a query request to the baseboard management controller using a preset query command; In response to receiving identification information of the multi-core device connected to the high-speed serial expansion bus sent by the baseboard management controller, the identification information of the multi-core device connected to the high-speed serial expansion bus is stored in the first target structure, and the identification information of the multi-core device stored in the first target structure is determined as the reference hardware information.

3. The device information display method according to claim 1, characterized in that: The identification information of the multi-core device includes source identification information of the multi-core device, sub-source identification information of the multi-core device, multi-core device identification information and model identification information of the multi-core device; The identifying whether the multi-core device is connected to the high-speed serial expansion bus according to the hardware device information and the reference hardware information includes: Determining whether each of the hardware devices is a terminal device based on the hardware device information; If it is determined that the hardware device is a terminal device, sequentially reading the source identification information of the hardware device, the sub-source identification information of the hardware device, the hardware device identification information, and the model identification information of the hardware device in the hardware device information; Comparing the source identification information of the hardware device with the source identification information of the multi-core device, the sub-source identification information of the hardware device with the sub-source identification information of the multi-core device, the hardware device identification information with the multi-core device identification information, and the model identification information of the hardware device with the model identification information of the multi-core device; If there is simultaneously the source identification information of a multi-core device that is identical to the source identification information of the hardware device, the sub-source identification information of the multi-core device that is identical to the sub-source identification information of the hardware device, the multi-core device identification information that is identical to the hardware device identification information, and the model identification information of the multi-core device that is identical to the model identification information of the hardware device, it is determined that the multi-core device is connected to the high-speed serial expansion bus.

4. The device information display method according to claim 1, characterized in that: The identification information of the multi-core device includes source identification information of the multi-core device, sub-source identification information of the multi-core device, multi-core device identification information and model identification information of the multi-core device; the multi-core device includes at least two sub-devices; the sub-devices have the same source identification information, the same sub-source identification information, the same device identification information and the same model identification information; the hardware device information includes first location information, a bus width supported by the first device and a communication speed supported by the first device; the device information corresponding to the multi-core device includes second location information, a bus width supported by the second device and a communication speed supported by the second device; The generating device information corresponding to the multi-core device based on the hardware device information and the reference hardware information includes: sequentially reading the first device supported bus width and the first device supported communication speed from the hardware device information of each of the sub-devices and the first location information of the upper-level device commonly connected to each of the sub-devices; Determine the maximum first device supported bus width and first device supported communication speed corresponding to each of the sub-devices as the second device supported bus width and second device supported communication speed of the multi-core device; Determining the first location information of the upper-level device to which each of the sub-devices is commonly connected as the second location information of the multi-core device; The second location information, the second device supported bus width, and the second device supported communication speed are determined as device information corresponding to the multi-core device.

5. A device information display method, characterized in that: include: Receiving a query request sent by a basic input and output system; The query request includes a preset query command; Obtaining identification information of a multi-core device connected to the high-speed serial expansion bus from an electrically erasable programmable read-only memory according to the query request, and determining the identification information of the multi-core device connected to the high-speed serial expansion bus as reference hardware information; Sending the reference hardware information to the basic input and output system; the reference hardware information is used to indicate a multi-core device connected to a high-speed serial expansion bus; The device information corresponding to the multi-core device sent by the basic input and output system is received and sent to the client device for display; the device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information.

6. The device information display method according to claim 5, characterized in that: Also includes: Receive a storage request; the storage request includes a storage command; the storage command includes command identification information and identification information of the multi-core device to be stored; The command identification information is used to identify the category of the command; Comparing the command identification information in the preset stored command with preset verification information; If the command identification information is different from the preset verification information, the preset warning information is returned; If the command identification information is the same as the preset verification information, creating a second target structure; Reading identification information of a multi-core device to be stored, and storing the identification information of the multi-core device to be stored in a second target structure; Obtaining identification information of the multi-core device stored in the electrically erasable programmable read-only memory, and comparing the identification information with the identification information of the multi-core device to be stored in the second target structure; If there is identification information of a multi-core device to be stored that is different from the identification information of the stored multi-core device, the identification information of the multi-core device to be stored that is different from the identification information of the stored multi-core device is stored in the EEPROM.

7. A device information display method, characterized in that: include: The basic input and output system sends a query request to the baseboard management controller; The query request includes a preset query command; the preset query command includes command identification information; The baseboard management controller obtains identification information of the multi-core device connected to the high-speed serial expansion bus from the electrically erasable programmable read-only memory, and determines the identification information of the multi-core device connected to the high-speed serial expansion bus as reference hardware information; The baseboard management controller sends the reference hardware information to the basic input and output system; The basic input / output system identifies whether the multi-core device is connected to the high-speed serial expansion bus based on the hardware device information and the reference hardware information. If the multi-core device is connected, the basic input / output system generates device information corresponding to the multi-core device based on the hardware device information and the reference hardware information, and sends it to the client device for display through the baseboard management controller.

8. A device information display device, characterized in that: include: An acquisition module is used to read hardware devices in sequence using a depth-first search algorithm to acquire hardware device information during the initialization process of the basic input and output system, wherein the hardware devices are devices connected to the high-speed serial expansion bus; The acquisition module is further used to acquire reference hardware information; the reference hardware information is identification information of a multi-core device connected to the high-speed serial expansion bus; an identification module, configured to identify whether the multi-core device is connected to the high-speed serial expansion bus based on the hardware device information and the reference hardware information; a generating module, configured to generate device information corresponding to the multi-core device based on the hardware device information and the reference hardware information if the multi-core device is connected; The sending module is used to send the data to the client device for display via the baseboard management controller.

9. A device information display device, characterized in that: include: A receiving module, used for receiving a query request sent by a basic input and output system; The query request includes a preset query command; a determination module, configured to obtain identification information of a multi-core device connected to the high-speed serial expansion bus from an electrically erasable programmable read-only memory according to the query request, and determine the identification information of the multi-core device connected to the high-speed serial expansion bus as reference hardware information; A sending module, configured to send the reference hardware information to the basic input / output system; the reference hardware information is used to indicate a multi-core device connected to a high-speed serial expansion bus; The sending module is further used to receive the device information corresponding to the multi-core device sent by the basic input and output system, and send it to the client device for display; the device information corresponding to the multi-core device is generated based on the hardware device information and the reference hardware information.

10. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is configured to implement the steps of the device information display method according to claims 1 to 7 when executing the computer program.

11. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the device information display method according to claims 1 to 7.

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