Dynamic cross-layer data multiplexing method for efficient deep convolution calculation

Abstract

The invention relates to the technical field of neural network optimization, in particular to an efficient deep convolution calculation-oriented dynamic cross-layer data multiplexing method, which comprises the following steps of: 1, designing a single-layer block optimization and cyclic sequence optimization model; step 2, performing independent block optimization and cyclic sequence optimization; step 3, performing multi-layer joint block optimization and cyclic sequence optimization; and step 4, carrying out single-layer and multi-layer dynamic composite block optimization and cyclic sequence optimization. According to the method, a multi-layer joint data partitioning strategy, a loop expansion control strategy and a data storage mapping updating strategy of minimum DRAM access can be finally realized, a data access and data flow scheme of fine granularity maximized data multiplexing can be realized, and automatic code generation and calculation mapping optimization for realizing calculation and memory access efficiency optimization can be effectively supported.

Description

Technical Field

[0001] The present invention relates to the field of neural network optimization technology, and in particular to a dynamic cross-layer data multiplexing method for efficient deep convolution calculation. Background Art

[0002] When various deep neural network models are deployed and applied in practice, a large number of input feature map coefficients and weight coefficients are stored in large-capacity DRAM memories. The computing core of a CNN accelerator has limited computing resources, and the on-chip SRAM cache capacity is also limited. When performing actual multi-layer convolution calculations, the input feature map coefficients and weight coefficients are loaded from off-chip DRAM into the on-chip SRAM cache near the computing core. The computing core's MAC array is typically only capable of performing a portion of the convolution calculation. The resulting output feature map coefficients need to be stored in DRAM, and the computing core then continues to perform convolution calculations on other input feature coefficients. The large amount and diversity of data in CNN network layers results in large and complex data transfers between the computing core, on-chip cache, and off-chip DRAM. DRAM-based off-chip memory access is the most energy-intensive operation in deep neural network (DNN) accelerators, representing the intelligent computing memory wall problem.

[0003] To optimize the storage access of network models on a specific CNN acceleration engine platform, it is necessary to solve the following issues: the CNN convolution weight coefficient and feature coefficient block partitioning method, the core computing unit calculation mapping, the external pipeline scheduling (i.e., loop order strategy), and the data storage mapping update strategy, so as to achieve code generation and implementation mapping for optimized computing and memory access efficiency. The solution space dimension of this optimization solution is very large, involving variables such as batch size concurrency intensity (Tz), the width and height of the feature map participating in the calculation of the computing core (Tn*Tm), the on-chip cache input feature dimension (Ti), the on-chip cache output feature dimension (Tj), the number of cross-layer optimization layers, and the loop priority strategy category. The loop priority strategy category is also manifested in the following data reuse mode: input coefficient reuse IRO\output coefficient reuse ORO\weight coefficient reuse WRO.

[0004] In addition, the coefficients of the output and input features of two adjacent layers may be reused. For example, the output feature map coefficients of the uth layer are the input feature map coefficients of the u+1th layer. If the adjacent layers are optimized separately, then after the feature map coefficients of the uth layer are calculated, a DRAM write operation will be initiated to store these output coefficients. Then, when the convolution calculation of the next layer is performed, a DRAM read operation will be initiated to read these feature map coefficients. This results in redundant feature map coefficient write and read access operations. If the uth layer is optimized separately in ORO mode, then when the output feature map coefficients are stored in the on-chip SRAM, the convolution calculation of the u+1th layer will continue to be initiated. Assuming that the u+1 layer is cyclically in IRO mode, the feature map coefficients cached in the on-chip SRAM of the previous layer can be maximized. This ORO+IRO combination of two adjacent layers can maximize the reuse of the output and input feature map coefficients. Theoretically, the input and output feature map coefficients can achieve data reuse between more layers, but it is necessary to consider that the weight coefficients also need to be reused, and there are also trade-offs such as batch concurrency. Generally speaking, the more layers involved in cross-layer optimization, the more efficient the reuse of feature coefficients between adjacent layers. However, it's important to consider the limited on-chip SRAM cache. Due to SRAM limitations, the more layers involved in cross-layer optimization, the smaller the block size. This reduces the number of weight coefficient blocks, and the redundant transfer of weight coefficient data is more severe than with fewer layers or single-layer partitioning. There's a trade-off between the increased bandwidth caused by redundant transfer of weight coefficient data and the reduced data access savings from data reuse between adjacent layers. This is a factor that needs to be considered when developing optimization plans.

[0005] Currently, existing work generally focuses only on single-layer bandwidth access optimization, without considering that the output feature data of the previous layer is already in the cache and can be reused by the input feature coefficients of subsequent layers. This cross-layer data reuse is very effective for the efficient deployment of network layers with a high proportion of feature coefficients. Some work does not consider input batch concurrency. Input batch concurrency can effectively reuse weight coefficients and is very effective for the WRO mode with weight coefficient priority. Some work also organizes data according to the data access paradigm required for core calculations when building bandwidth access function models. This process will cause some overlapping data in the input and output feature map coefficients. The repeated loading of this overlapping data reduces the accuracy of the model and the efficiency of coefficient optimization. In addition, some work considers the bandwidth consumption in an ideal logical sense when building bandwidth models, without considering the actual DRAM structure, resulting in inconsistencies between the actual DRAM access bandwidth consumption and the logical access bandwidth. This problem has not been considered by most existing work.

[0006] At the same time, the optimal data flow strategy that considers batch concurrency strength optimization, block strategy optimization, loop order strategy optimization, and cross-layer data reuse optimization, and achieving globally optimized on-chip DRAM access and on-chip data reuse under the constraints of on-chip cache and computing core computing resources, is a problem that needs further research and solution. It is of great significance for the efficient deployment and computational mapping of network models on specific convolutional accelerator hardware platforms. Summary of the Invention

[0007] In order to solve the above technical problems existing in the prior art, the present invention proposes a dynamic cross-layer data multiplexing method for efficient deep convolution calculation. The specific technical solution is as follows: A dynamic cross-layer data reuse method for efficient deep convolution computation, comprising: Step 1: Design a single-layer block optimization and loop sequence optimization model; Step 2: Perform separate block optimization and loop sequence optimization; Step 3: Perform multi-layer joint block optimization and loop sequence optimization; Step 4: Perform single-layer and multi-layer dynamic composite block optimization and loop sequence optimization.

[0008] Furthermore, the design of the model in step 1 specifically includes: According to the characteristics of deep convolution calculation data flow, three data access modes are set, including input feature map coefficient reuse IRO mode, output feature map coefficient reuse ORO mode and weight coefficient reuse WRO mode; According to the data flow characteristics of the three data access modes, the single access data volume and the number of cyclic accesses of the input feature map, output feature map and weight in each mode are set.

[0009] Furthermore, the single access data volume of the input feature map, output feature map and weight in each mode specifically includes: input feature map coefficients: Bif1, Bif2, Bif3, output feature map coefficients: Bof1, Bof2, Bof3, and weight coefficients: Bwgt1, Bwgt2, Bwgt3; the number of cyclic accesses of the input feature map, output feature map and weight in each mode specifically includes: input feature map coefficient access times: Cif1, Cif2, Cif3, output feature map coefficient access times: Cof1, Cof2, Cof3, and weight coefficient access times: Cwgt1, Cwgt2, Cwgt3.

[0010] Furthermore, the step 2 specifically includes: Step 2.1: Divide the feature data calculated by the single-layer convolution into blocks and obtain the block parameters; Step 2.2: Traverse all possible block combinations, calculate the memory bandwidth and storage occupancy under the three data access modes respectively, and compare the storage threshold and minimum memory bandwidth to determine the optimal block combination and data access mode.

[0011] Furthermore, the step 2.1 specifically includes: using the step sizes of 1, stepM, stepN, stepI, and stepJ to divide Z, M, N, I, and J into blocks respectively to obtain block parameters Tz, Th, Tw, Tm, Tn, Ti, and Tj; wherein Z is the maximum batch number, I is the number of input feature map channels, J*M*N is the feature map coefficient dimension, Th=S*(Tm-1)+P, Tw=S*(Tn-1)+Q, S is the convolution step size, I*J*P*Q is the convolution kernel size, and Tp=P and Tq=Q are taken; Tz is the batch cycle block size, Tm*Tn and Th*Tw are the horizontal and vertical block sizes of the data feature map coefficients, Ti is the input feature map channel block size, and Tj is the output feature map channel block size.

[0012] Furthermore, in step 2.2, the calculation of the memory bandwidth and storage occupancy is specifically as follows: Input feature map ifmaps bandwidth: BWif = Bif * Cif * size (ifmaps); The bandwidth of the output feature map ofmaps: BWof= Bof*Cof*size(ofmaps); The bandwidth of the convolution kernel weight weight: BWwgt= Bwgt*Cwgt*size(weight); Storage usage: SRAMtot=Bif*size(ifmaps)+Bwgt*size(weight)+Bof*size(ofmaps); Total bandwidth: BWtot = BWif + BWof + BWwgt; Among them, Bif, Bof, and Bwgt represent the data size of the input feature map, output feature map, and convolution kernel respectively, Cif, Cof, and Cwgt represent the number of cyclic visits to the input feature map, output feature map, and convolution kernel respectively, and size represents the size; The comparison of the storage threshold and the minimum bandwidth to determine the optimal block combination and data access mode is as follows: Assume the storage threshold SRAM_TH and the minimum bandwidth minBW. Under the conditions of SRAMtot<=SRAM_TH and BWtot2<=minBW, that is, if the storage occupancy of the current mode does not exceed the storage threshold SRAM_TH and the total bandwidth is smaller, then update the minimum bandwidth and data access mode, that is, finally obtain the optimal block combination and mode, so that the total bandwidth is minimized and the storage limit is met.

[0013] Furthermore, the step 3 specifically includes: Step 3.1: Traverse the block combination of the three adjacent convolution layers to calculate the data, specifically including: For the u-th layer, u+1-th layer, and u+2-th layer, that is, the three adjacent layers, first block the feature data calculated by the u-th layer convolution to obtain the u-th layer block combination, and then reuse the u-th layer block parameters to obtain the u+1-th layer block combination, where Tw(u+1)=Tn(u), Th(u+1)=Tm(u), that is: the width and height of the feature map calculated by the u-th layer convolution are directly reused as the width and height of the u+1-th layer convolution input feature map, and then reuse the u+1-th layer block parameters to obtain the u+2-th layer block combination, and at the same time adjust the lower layer block parameters based on the upper layer block results; Step 3.2: Loop through and calculate the bandwidth and storage occupancy of the current layer for different block combinations, set storage constraints, loop through and check whether the total storage occupancy of the three adjacent layers meets the storage constraints, and select the block combination with the smallest total bandwidth.

[0014] Furthermore, the step 4 specifically includes: Step 4.1: Select a three-layer adjacent layer group GOP and generate four candidate block modes, including: Mode 1: Each layer is optimized separately, the bandwidth of each layer is calculated and summed to obtain the total bandwidth BAND1, and the last two layers are merged into the next GOP; Mode 2: The first two layers are optimized in two layers, and the third layer is optimized in a separate block. The bandwidth of each layer is calculated and summed to obtain the total bandwidth BAND2. The third layer will be merged into the next GOP. Mode 3: The first layer is optimized in a separate block, and the next two layers are optimized in a dual-layer block. The bandwidth of each layer is calculated and summed to obtain the total bandwidth BAND3. The last two layers are then merged into the next GOP. Mode 4: Perform multi-layer joint block optimization on three layers, calculate the bandwidth of each layer and sum them to obtain the total bandwidth BAND4; Step 4.2: Compare the total bandwidths of the four modes and select the mode corresponding to the minimum value as the optimal blocking strategy for the selected adjacent layer group GOP.

[0015] Beneficial effects: The present invention can ultimately implement a multi-layer joint data partitioning strategy, a loop expansion control strategy, and a data storage mapping update strategy for minimum DRAM access, and realize a data access and data flow solution with fine-grained maximum data reuse, which can effectively support automatic code generation and calculation mapping optimization for optimizing computing and memory access efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the code design of the three data access modes IRO / ORO / WRO according to an embodiment of the present invention; Figure 2 Schematic diagram of the block relationship of an embodiment of the present invention; Figure 3 This is a code implementation flow chart of single-layer independent block optimization and loop sequence optimization according to an embodiment of the present invention; Figure 4 This is a code implementation flow chart of the two-layer joint block optimization and loop sequence optimization according to an embodiment of the present invention; Figure 5 This is a code implementation flow chart of layer joint block optimization and loop sequence optimization according to an embodiment of the present invention; Figure 6 This is a flow chart of the code implementation of the composite cross-layer multi-layer adaptive block scanning mode strategy of an embodiment of the present invention; Figure 7 This is a flow chart of a composite cross-layer multi-layer adaptive block scanning mode strategy according to an embodiment of the present invention; Figure 8 This is a diagram showing the cross-layer block optimization results of different layers of the VGG network according to an embodiment of the present invention; Figure 9 This is a comparison diagram of block optimization of different layer combination modes of the first three layers of the VGG network according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solution and technical effect of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0018] This embodiment provides a dynamic cross-layer data multiplexing method for efficient depthwise convolutional computing, which specifically includes the following contents: Step 1: Design single-layer block optimization and loop sequence optimization models.

[0019] According to the characteristics of deep convolution calculation data flow, three data access modes are determined: input feature coefficient reuse IRO, output feature coefficient reuse ORO and weight coefficient reuse WRO, such as Figure 1 shown.

[0020] According to the characteristics of IRO, ORO and WRO data streams, the single access data volume of the input feature map, output feature map and weight in the three data access modes is determined, specifically including the input feature map coefficients: Bif1, Bif2, Bif3, the output feature map coefficients: Bof1, Bof2, Bof3, and the weight coefficients: Bwgt1, Bwgt2, Bwgt3; the number of cyclic accesses of the input feature map, output feature map and weight in the three data access modes, specifically including the number of input feature map coefficient accesses: Cif1, Cif2, Cif3, the number of output feature map coefficient accesses: Cof1, Cof2, Cof3, and the number of weight coefficient accesses: Cwgt1, Cwgt2, Cwgt3. Among them, the batch cycle block size is set to Tz, the horizontal and vertical block sizes of the data feature map coefficients are Tm*Tn and Th*Tw, the input feature map channel block size is Ti, and the output feature map channel block size is Tj, as shown in Table 1 below.

[0021]

[0022] Table 1: Single access data volume and number of cyclic accesses in the three modes of IRO / ORO / WRO.

[0023] Step 2: Single-layer independent block optimization and loop sequence optimization.

[0024] The goal of optimizing the block and loop order of single-layer convolution calculation is to determine the block parameters Tz, Tm, Tn, Th, Tw, Ti, and Tj. Assume that the maximum batch size is Z, the number of input feature map channels is I, the input feature map coefficient dimension is J*M*N, and the convolution kernel size is I*J*P*Q. Because the current mainstream convolution kernel P*Q is relatively small, generally 3*3, then Tp=P and Tq=Q can be taken. The relationship between the block parameters Tz, Th, Tw, Tm, Tn, Ti, Tj and Z, M, N, I, J is as follows: Figure 2 As shown in the figure, Th=S*(Tm-1)+P, Tw=S*(Tn-1)+Q, and S is the convolution step size.

[0025] In the different modes listed in Table 1, Z, M, N, I, and J are divided into blocks using step sizes of 1, stepM, stepN, stepI, and stepJ to obtain the block parameters Tz, Th, Tw, Tm, Tn, Ti, and Tj. Under different values of Tz, Th, Tw, Tm, Tn, Ti, and Tj, the data size Bif / Bof / Bwgt stored in the computing core and on-chip cache, as well as the number of DRAM cycle reads Cif / Cof / Cwgt are obtained. Assuming that the total on-chip SRAM cache size is SRAM_TH, the required SRAM size and the amount of data read from the DRAM external memory are calculated based on the characteristics of each combined data flow. Then compare the bandwidth consumption of all Tz, Th, Tw, Tm, Tn, Ti, and Tj values that meet the requirement that the overall SRAM consumption does not exceed SRAM_TH, determine the minimum bandwidth case minBW as the optimal block combination, and input different cycle sequence modes mode. The above specific implementation process can be referred to as follows Figure 3 The algorithm function 1 is shown.

[0026] Step 3: Multi-layer joint block optimization and loop sequence optimization.

[0027] There is a possibility of reuse of coefficients between the output and input features of two adjacent layers. The ORO+IRO combination of two adjacent layers means that the weight coefficients of the two adjacent layers need to be cached. Different network models have different parameters. Not all ORO+IRO combinations of adjacent layers have better memory bandwidth consumption. When the overall SRAM consumption does not exceed the available on-chip SRAM budget, find the combination with the minimum total memory bandwidth under different block parameters of two adjacent layers. This optimization selection process can be referred to as follows Figure 4 The algorithm function 2 is shown.

[0028] There is a possibility of reuse of coefficients between the output and input features of three adjacent layers. The combination of ORO+IRO / ORI+IRO of three adjacent layers means that the weight coefficients of the three adjacent layers need to be cached. The parameters of different network models are different, and not all combinations of three adjacent layers have better memory bandwidth consumption. When the overall SRAM consumption does not exceed the available on-chip SRAM budget, find the combination with the minimum total memory bandwidth under different block parameters of the three adjacent layers. This optimization selection process can be referred to as follows: Figure 5 As shown in algorithm function 3.

[0029] Actual observations show that for some network layers with relatively large feature maps, three-layer joint optimization has better bandwidth access performance than single-layer or two-layer optimization. The performance of more than three layers is worse than that of less than three layers.

[0030] Step 4: Dynamic composite block optimization and loop sequence optimization of single layer and multi-layer.

[0031] For an L-layer network, it is divided into no more than 3 GOPs of different lengths, and the block division and loop order optimization within each block group are determined, including: independent optimization of three adjacent layers, optimization of the first single layer and the next two layers across layers, optimization of the first two layers across layers and the next single layer, and optimization of all three layers as single layers. This mainly depends on the characteristics of the three-layer network structure parameters. This optimization selection process can be referred to as Figure 6 The algorithm function 4 shown, and Figure 7 The algorithm flow is shown.

[0032] This embodiment takes the VGG network as an example to provide the simulation results of the adaptive block partitioning experiment of this method. Figure 8 As shown, the different layers of the VGG network are consistent with the cross-layer block optimization results. It can be seen that only the first three layers of GOP combination optimization performance is better than other division performance. Figure 9 As shown in the figure, the comparison results of block optimization of different layer combination modes of the first three layers are given. Compared with single-layer optimization, the three-layer cross-layer optimization can reduce the bandwidth by about 25% while meeting the SRAM constraint. Compared with the joint optimization of the first two layers and then the optimization of one layer, the bandwidth can be reduced by about 3.3%. Compared with the joint optimization of the first layer and then the joint optimization of the two layers, the bandwidth can be reduced by about 13.8%.

[0033] In summary, the content of the present invention is aimed at the structural differences of different neural network models, which are composed of different numbers of network layers. The convolution kernel size configuration of each layer may be different, and the number of input channels and output channels of each layer are also different. According to the different parameters of each layer, the mathematical model of cache consumption and external memory access bandwidth consumption under different combination modes is determined, and it is analyzed that bandwidth and memory consumption are important supports for the selection of optimal blocking and loop sequence strategies. It is also considered that there is a possibility of reuse of output and input feature coefficients between two adjacent layers. Is it better to optimize the ORO+IRO combination of two adjacent layers or to optimize the two layers using separate blocking and loop sequence to minimize the overall bandwidth consumption? Different network model parameters are different, and the results vary greatly. Under the condition that the overall SRAM consumption does not exceed the available SRAM budget on the chip, and at the same time, it is also necessary to meet the data reuse maximization constraint, a cross-layer combination optimization or a separate single-layer optimization strategy is determined to achieve the optimal selection of blocking and loop sequence between multiple layers.

[0034] The above description is only a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the implementation process of the present invention is described in detail above, it is still possible for those familiar with the art to modify the technical solutions described in the above examples or to replace some of the technical features therein with equivalents. Any modifications, equivalent replacements, etc. made within the spirit and principles of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A dynamic cross-layer data multiplexing method for efficient deep convolutional computing, characterized by: include: Step 1: Design a single-layer block optimization and loop sequence optimization model; Step 2: Perform separate block optimization and loop sequence optimization; Step 3: Perform multi-layer joint block optimization and loop sequence optimization; Step 4: Perform single-layer and multi-layer dynamic composite block optimization and loop sequence optimization.

2. The dynamic cross-layer data multiplexing method according to claim 1, wherein: The model design of step 1 specifically includes: According to the characteristics of deep convolution calculation data flow, three data access modes are set, including input feature map coefficient reuse IRO mode, output feature map coefficient reuse ORO mode and weight coefficient reuse WRO mode; According to the data flow characteristics of the three data access modes, the single access data volume and the number of cyclic accesses of the input feature map, output feature map and weight in each mode are set.

3. The dynamic cross-layer data multiplexing method according to claim 2, wherein: The single access data volume of the input feature map, output feature map and weight in each mode specifically includes: input feature map coefficients: Bif1, Bif2, Bif3, output feature map coefficients: Bof1, Bof2, Bof3, and weight coefficients: Bwgt1, Bwgt2, Bwgt3; the number of cyclic accesses of the input feature map, output feature map and weight in each mode specifically includes: input feature map coefficient access times: Cif1, Cif2, Cif3, output feature map coefficient access times: Cof1, Cof2, Cof3, and weight coefficient access times: Cwgt1, Cwgt2, Cwgt3.

4. The dynamic cross-layer data multiplexing method according to claim 2, wherein: The step 2 specifically includes: Step 2.1: Divide the feature data calculated by the single-layer convolution into blocks and obtain the block parameters; Step 2.2: Traverse all possible block combinations, calculate the memory bandwidth and storage occupancy under the three data access modes respectively, and compare the storage threshold and minimum memory bandwidth to determine the optimal block combination and data access mode.

5. The dynamic cross-layer data multiplexing method according to claim 4, wherein: The step 2.1 specifically includes: using the step sizes of 1, stepM, stepN, stepI, and stepJ to divide Z, M, N, I, and J into blocks respectively to obtain block parameters Tz, Th, Tw, Tm, Tn, Ti, and Tj; wherein Z is the maximum batch number, I is the number of input feature map channels, J*M*N is the feature map coefficient dimension, Th=S*(Tm-1)+P, Tw=S*(Tn-1)+Q, S is the convolution step size, I*J*P*Q is the convolution kernel size, and Tp=P and Tq=Q are taken; Tz is the batch cycle block size, Tm*Tn and Th*Tw are the horizontal and vertical block sizes of the data feature map coefficients, Ti is the input feature map channel block size, and Tj is the output feature map channel block size.

6. The dynamic cross-layer data multiplexing method according to claim 5, characterized in that: In step 2.2, the storage threshold and the minimum bandwidth are compared to determine the optimal block combination and data access mode, specifically: Assume the storage threshold SRAM_TH and the minimum bandwidth minBW. If the storage occupancy of the current mode does not exceed the storage threshold SRAM_TH and the total bandwidth is smaller, then update the minimum bandwidth and data access mode, that is, finally obtain the optimal block combination and mode, so that the total bandwidth is minimized and the storage limit is met.

7. The dynamic cross-layer data multiplexing method according to claim 6, characterized in that: The step 3 specifically includes: Step 3.1: Traverse the block combination of the three adjacent convolution layers to calculate the data, specifically including: For the u-th layer, u+1-th layer, and u+2-th layer, that is, the three adjacent layers, first block the feature data calculated by the u-th layer convolution to obtain the u-th layer block combination, and then reuse the u-th layer block parameters to obtain the u+1-th layer block combination, where Tw(u+1)=Tn(u), Th(u+1)=Tm(u), that is: the width and height of the feature map calculated by the u-th layer convolution are directly reused as the width and height of the u+1-th layer convolution input feature map, and then reuse the u+1-th layer block parameters to obtain the u+2-th layer block combination, and at the same time adjust the lower layer block parameters based on the upper layer block results; Step 3.2: Loop through and calculate the bandwidth and storage occupancy of the current layer for different block combinations, set storage constraints, loop through and check whether the total storage occupancy of the three adjacent layers meets the storage constraints, and select the block combination with the smallest total bandwidth.

8. The dynamic cross-layer data multiplexing method according to claim 7, wherein: The step 4 specifically includes: Step 4.1: Select a three-layer adjacent layer group GOP and generate four candidate block modes, including: Mode 1: Each layer is optimized separately, the bandwidth of each layer is calculated and summed to obtain the total bandwidth BAND1, and the last two layers are merged into the next GOP; Mode 2: The first two layers are optimized in two layers, and the third layer is optimized in a separate block. The bandwidth of each layer is calculated and summed to obtain the total bandwidth BAND2. The third layer will be merged into the next GOP. Mode 3: The first layer is optimized in a separate block, and the next two layers are optimized in a dual-layer block. The bandwidth of each layer is calculated and summed to obtain the total bandwidth BAND3. The last two layers are then merged into the next GOP. Mode 4: Perform multi-layer joint block optimization on three layers, calculate the bandwidth of each layer and sum them to obtain the total bandwidth BAND4; Step 4.2: Compare the total bandwidths of the four modes and select the mode corresponding to the minimum value as the optimal blocking strategy for the selected adjacent layer group GOP.

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