Multi-channel dc source asynchronous write synchronous refresh system and method

Abstract

The application discloses a kind of multi-channel direct current source asynchronous write synchronization refreshing system and method, it is related to quantum computer technical field, including the FPGA motherboard for outputting the output parameter of each channel of direct current source, and at least two DAC sub-boards for executing output parameter;FPGA motherboard is used to write output parameter to each DAC sub-board, and the receiving time of the DAC output channel of each DAC sub-board is controlled to receive output parameter before the start time of next refreshing cycle;FPGA motherboard is also used to send refreshing instruction to each DAC sub-board in parallel at start time;After each DAC sub-board receives refreshing instruction, the DAC output channel of the DAC sub-board is controlled to execute the received output parameter;All working time sequences of all DAC output channels have greatest common divisor, greatest common divisor is equal to X times of refreshing cycle, X is greater than or equal to 1 positive integer, to guarantee the synchronization of multi-channel output.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computers, and particularly relates to a multi-channel direct current source asynchronous writing and synchronous refreshing system and method. BACKGROUND

[0002] In an ion trap quantum computer, the quantum state of each ion needs to be independently regulated, a localized electric field is constructed by a combination of exclusive electrodes, and a single quantum bit gate is realized with high fidelity. When ion movement, splitting and combining operations are implemented, a gradual voltage gradient needs to be applied by adjacent electrode groups to ensure that the ion migration process maintains sub-micron positioning accuracy.

[0003] In addition, in order to break through the limitations of traditional linear ion chains, a honeycomb electrode array is constructed in the XY plane to support two-dimensional confinement of ions, and six adjacent electrodes are needed for each ion to form a three-dimensional confinement field. In order to suppress the micro-motion caused by the radio frequency electric field, a compensation electrode group is deployed at the bottom of the chip, and the ion displacement is controlled within λ / 20 (λ is the wavelength of the laser) through phase synchronization technology.

[0004] In addition, a microwave standing wave field is generated by a distributed electrode array, which can realize consistent coupling strength between different ions and support high-fidelity two-qubit gate operations. By configuring redundant electrodes to compensate for environmental magnetic field drift in real time, it is beneficial to reduce the frequency drift of ion hyperfine energy level transitions.

[0005] Based on the above reasons, the dense electrode architecture can simultaneously meet the multiple requirements of high-precision quantum manipulation, large-scale quantum bit expansion, dynamic reconstruction, and support the realization of quantum computing breakthroughs in large-scale ion matrices; for example, the current advanced 512-bit ion chip needs to integrate more than 1500 electrodes.

[0006] A multi-channel direct current source is used to control the direct current electrodes of an ion trap quantum computing chip. Different channels have different output voltages and different output timing. For the above hundreds or even thousands of direct current source channel numbers, it is obviously impossible to write output parameters simultaneously in parallel. In this case, how to ensure the synchronization of multi-channel output is a problem to be solved. SUMMARY

[0007] The present application aims to at least solve one of the technical problems in the related art. To this end, one object of the present application is to provide a multi-channel direct current source asynchronous writing and synchronous refreshing system and method to ensure the synchronization of multi-channel output.

[0008] According to a first aspect of an embodiment of the present application, a multi-channel direct current source asynchronous writing and synchronous refreshing system is provided, the system comprising an FPGA motherboard for outputting output parameters of each channel of a direct current source, and at least two DAC daughter boards for executing the output parameters; each DAC daughter board is provided with a plurality of DAC output channels;

[0009] The FPGA motherboard is configured to write the output parameters to each DAC daughter board, and control the receiving time of the DAC output channels of each DAC daughter board to receive the output parameters to be before the start time of a next refreshing period;

[0010] The FPGA motherboard is further configured to send a refreshing instruction to each DAC daughter board at the start time in parallel;

[0011] After each DAC daughter board receives the refreshing instruction, the DAC output channels of the DAC daughter board are controlled to execute the received output parameters;

[0012] All working time sequences of all DAC output channels have a greatest common divisor, and the greatest common divisor is equal to X times of the refreshing period, X being a positive integer greater than or equal to 1.

[0013] Optionally, the refreshing period satisfies the following setting condition: the FPGA motherboard writes the output parameters to each DAC daughter board in parallel.

[0014] Optionally, the refreshing period satisfies the following setting condition:

[0015]

[0016] wherein the maximum number of DAC output channels on each DAC daughter board is N, the time for the FPGA motherboard to write the output parameters into each DAC output channel is t, and the refreshing period is T.

[0017] Optionally, the writing of the output parameters to each DAC daughter board in parallel comprises:

[0018] For each DAC daughter board, it is determined whether the historical output parameters received by each DAC output channel of the DAC daughter board are different from the output parameters;

[0019] If there is a first DAC output channel whose output parameters are different from the historical output parameters, the output parameters are written to the first DAC output channel.

[0020] Optionally, the refreshing period satisfies the following setting condition:

[0021]

[0022] Wherein, the maximum number of the first DAC output channels in each DAC sub-board is m, the time for the FPGA mother board to write output parameters into each DAC output channel is t, and the refresh period is T.

[0023] Optionally, the DC electrodes of the DC source are grouped according to voltage adjustment frequency, and each group includes DC electrodes that are evenly distributed to the DAC output channels of each DAC sub-board.

[0024] Optionally, the DC electrodes of the DC source are distributed to the DAC output channels of each DAC sub-board, including:

[0025] Determine the time when the number of voltage adjustment of the DC electrodes is the largest according to the working time sequence of the DC electrodes;

[0026] Evenly distribute the DC electrodes that need to adjust voltage at the time to each DAC sub-board to obtain the number M of the first DAC output channels of each DAC sub-board at the time;

[0027] Determine m according to the working time sequence of the DC electrodes;

[0028] Adjust the distribution of the DC electrodes in each DAC sub-board so that m-M is less than a set threshold.

[0029] Optionally, each DAC sub-board is also provided with a voltage reference chip.

[0030] Optionally, the FPGA mother board and the DAC modules of each DAC sub-board have equal length wiring, and each DAC output channel of each DAC sub-board and the DC electrode of the DC source corresponding to the DAC output channel have equal length wiring; wherein, the DAC output channel of each DAC sub-board is arranged in the DAC module of the DAC sub-board.

[0031] Optionally, the refresh period is set to be less than or equal to 100us.

[0032] Optionally, the system includes a system clock chip, and the refresh period is generated based on a local clock signal provided by the system clock chip;

[0033] The FPGA mother board controls the local clock signal and the external clock signal to be in phase.

[0034] According to the second aspect of the embodiment of the application, a multi-channel DC source asynchronous writing and synchronous refreshing method is provided, which is applied to the FPGA mother board of a multi-channel DC source asynchronous writing and synchronous refreshing system, and the method includes:

[0035] Write output parameters to each DAC sub-board, and control the receiving time of the DAC output channel of each DAC sub-board to receive the output parameters to be before the start time of the next refresh period.

[0036] sending refresh instructions to each DAC sub-board at the starting time, so that each DAC sub-board receives the refresh instructions and controls the DAC output channel of the DAC sub-board to execute the received output parameters;

[0037] All working time sequences of all DAC output channels have a greatest common divisor, and the greatest common divisor is equal to X times of the refresh period, X is a positive integer greater than or equal to 1.

[0038] According to a third aspect of the embodiments of the present application, an ion trap quantum computing DC electrode system is provided, comprising the multi-channel DC source asynchronous writing and synchronous refreshing system according to any one of the above.

[0039] According to a fourth aspect of the embodiments of the present application, an ion trap quantum computing system is provided, comprising the multi-channel DC source asynchronous writing and synchronous refreshing system according to any one of the above.

[0040] In the scheme provided by the embodiments of the present application, as can be seen from the above, in the scheme provided by the embodiments of the present application, the FPGA mother board can write output parameters to each DAC sub-board in parallel, so that the time when each DAC sub-board obtains the output parameters is close, and the refresh instructions are sent at a certain period to refresh the output parameters executed by the DAC output channel of each DAC sub-board, before the refresh starting time of each period arrives, the output parameters to be refreshed are written first, so that unified refreshing can be performed according to the refresh instructions at the beginning of the next period, which guarantees the synchronization of multi-channel output, reduces the output time sequence error of each channel of the DC source or even the time sequence misalignment, is suitable for the application scene of ion trap quantum computing which is sensitive to time sequence, and can meet the time sequence requirements of high-precision systems.

[0041] Additional aspects and advantages of the present application will be made apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a structural schematic diagram of a multi-channel DC source asynchronous writing and synchronous refreshing system provided by the embodiments of the present application;

[0043] Figure 2 is a structural schematic diagram of a multi-channel DAC provided by the embodiments of the present application;

[0044] Figure 3 is a structural schematic diagram of an FPGA development board provided by the embodiments of the present application;

[0045] Figure 4is a flowchart of a multi-channel direct current source asynchronous writing and synchronous refreshing method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0046] Embodiments of the present application are described in detail below with reference to examples shown in the attached drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the attached drawings are exemplary and are intended to explain the present application, and cannot be understood as limiting the present application.

[0047] In one embodiment of the present application, referring to Figure 1 , a multi-channel direct current source asynchronous writing and synchronous refreshing system is provided, comprising an FPGA (Field Programmable Gate Array) motherboard for outputting parameters of each channel of a direct current source, and at least two DAC (Digital-to-Analog Converter) daughter boards for executing the output parameters; each DAC daughter board is provided with a plurality of DAC output channels;

[0048] The FPGA motherboard is configured to write the output parameters to each DAC daughter board, and control the receiving time of the DAC output channels of each DAC daughter board to receive the output parameters to be before the start time of the next refreshing cycle;

[0049] The FPGA motherboard is further configured to send refreshing instructions to each DAC daughter board in parallel at the start time;

[0050] After each DAC daughter board receives the refreshing instructions, the DAC output channels of the DAC daughter board are controlled to execute the received output parameters;

[0051] All working time sequences of all DAC output channels have a greatest common divisor, and the greatest common divisor is equal to X times of the refreshing cycle, X being a positive integer greater than or equal to 1.

[0052] In the above system, the FPGA motherboard refers to a circuit board developed based on FPGA, and the DAC daughter board refers to a circuit board connected to the motherboard and comprising a DAC module. Figure 1 As an example, only the connection mode of two DAC daughter boards and the motherboard is shown, and when there are more than two DAC daughter boards, each DAC daughter board is connected to the FPGA motherboard and the multi-channel direct current source in the mode shown in Figure 1 .

[0053] The output parameters include output voltages, which are transmitted in the form of voltage coding. Specifically, each DAC output channel receives an output parameter, and the output parameter is converted from a digital signal to an analog signal through the conversion function of the DAC module arranged on the DAC subboard, so as to control the voltage value of a direct current electrode.

[0054] In an embodiment, the DAC subboard can be a multi-channel DAC of AD5370, AD5371, AD5770R, etc. After the output parameters are transmitted through a high-speed serial interface such as an SPI (Serial Peripheral Interface), a Load signal is used as a refresh instruction to uniformly trigger the output parameters to take effect, which can reduce timing errors and is suitable for the application scenario of ion trap quantum computing which is sensitive to timing, and can meet the timing requirements of a high-precision system.

[0055] One DAC output channel can control one or more direct current electrodes according to the voltage specified by the output parameter.

[0056] After receiving the refresh instruction, all DAC output channels can be refreshed, or only part of the DAC output channels can be refreshed as shown in subsequent embodiments.

[0057] The working timing refers to the output duration or the output interval duration of any DAC output channel in one time, for example, the working timing of the first channel is (a1, a2, a3, … aa), where the odd elements such as a1, a3, etc. are output durations, and the even elements such as a2, a4, etc. are output interval durations, that is, in a non-output state, and vice versa, the odd elements such as a1, a3, etc. are output interval durations, and the even elements such as a2, a4, etc. are output durations; the working timing of the second channel is (b1, b2, b3, … bb), where the odd elements such as b1, b3, etc. are output durations, and the even elements such as b2, b4, etc. are output interval durations, and vice versa, the odd elements such as b1, b3, etc. are output interval durations, and the even elements such as b2, b4, etc. are output durations; the working timing of the third channel is (c1, c2, c3, … cc), where the odd elements such as c1, c3, etc. are output durations, and the even elements such as c2, c4, etc. are output interval durations, and vice versa, the odd elements such as c1, c3, etc. are output interval durations, and the even elements such as c2, c4, etc. are output durations. The greatest common divisor of all the working timings of all the DAC output channels is: the greatest common divisor of a1, a2, a3, … aa, b1, b2, b3, … bb, c1, c2, c3, … cc; only in this way can the refresh be aligned with the rising edge or the falling edge of the output of each DAC output channel.

[0058] It can be seen from the above that, in the scheme provided by the embodiment of the application, the FPGA mother board can write output parameters to each DAC daughter board in parallel, so that each DAC daughter board obtains the output parameters at close time, and the refresh instruction is sent to refresh the output parameters of the execution of the DAC output channel of each DAC daughter board at a certain period, the output parameters to be refreshed are written before the refresh start time of each period arrives, so that unified refreshing can be performed according to the refresh instruction at the start of the next period, the synchronization of multi-channel output is ensured, the output timing error of each channel of the direct current source is reduced, and even the situation of timing misalignment is avoided, the application scene of ion trap quantum computing which is sensitive to timing is suitable, and the timing requirement of a high-precision system can be met.

[0059] The structure of the DAC daughter board is shown in Figure 2 The multi-channel DAC refers to the DAC daughter board, the FPGA mother board and the DAC daughter board can be connected through a mother board connector, various communication mode interfaces are integrated in the mother board connector, for example, interfaces of digital power supply, analog power supply, SPI (Serial Peripheral Interface, serial peripheral interface) and the like.

[0060] In an embodiment of the application, each DAC daughter board is further provided with a voltage reference chip. Figure 2 In the embodiment, the voltage reference chip can provide a reference voltage signal to the multi-channel DAC, and the output form is an analog signal.

[0061] Through the D-Sub connector, ~ 39 represents 40 DAC output channels, which correspondingly control 40 output voltages of the multi-channel direct current source. Before refreshing the output parameters, the voltage reference chip outputs a voltage reference signal to control the output voltage of the DAC output channel.

[0062] In an embodiment of the application, the refresh period satisfies the following setting condition: the FPGA mother board writes output parameters to each DAC daughter board in parallel.

[0063] In an embodiment of the application, the refresh period is set to be less than or equal to 100us.

[0064] Specifically, the refresh period can be set to 1-20us. The FPGA motherboard can send output parameters to multiple-channel DACs on each daughter board simultaneously, but within the multi-channel DAC, multiple channels in the same DAC cannot be written with control parameters in parallel; the control refresh period is not less than 1us, so that there is more sufficient time for the DAC daughter board to write the output parameters to each DAC channel to be refreshed after receiving the output parameters. Avoiding setting the refresh period too large can better adapt to the high time resolution operation in the output voltage control timing.

[0065] In one embodiment, the above period is set to be less than the shortest change interval of the output parameters of the DAC output channels of all the DAC daughter boards.

[0066] For example, factors affecting the shortest change interval include the shortest operation period or the preset working period.

[0067] For output channels with high time resolution output voltage operations, the control period is less than the shortest operation period, where the operation period refers to the execution period of the output voltage operation, which adjusts the voltage value of the output current of the output channel once per output voltage operation.

[0068] In one embodiment of the present application, the refresh period satisfies the following setting conditions:

[0069]

[0070] Wherein, the maximum number of DAC output channels on each DAC daughter board is N, the time for the FPGA motherboard to write output parameters into each DAC output channel is t, and the refresh period is T.

[0071] Specifically, each DAC daughter board can have N DAC output channels to achieve average distribution.

[0072] In one embodiment of the present application, the output parameters can be written to the DAC daughter board in the following manner: for each DAC daughter board, determine whether the historical output parameters received by each DAC output channel of the DAC daughter board are different from the output parameters;

[0073] If there is a first DAC output channel with an output parameter different from the historical output parameter, the output parameter is written to the first DAC output channel.

[0074] The historical output parameter refers to the output parameter used at the last refresh relative to the current output parameter. In this way, when refreshing, only the DAC channels with changed output parameters are selected to write the output parameters, and the DAC output channels with unchanged output parameters are not operated, maintaining the original output parameters, which can further simplify the parameter refresh process.

[0075] In the case of refreshing only the DAC channel of the output parameter change, the refresh period satisfies the following setting condition:

[0076]

[0077] Wherein, the maximum number of first DAC output channels in each DAC sub-board is m, the time for the FPGA mother board to write output parameters into each DAC output channel is t, and the refresh period is T.

[0078] Specifically, all DAC output channels are provided with registers, and after completing an output parameter refresh, the mother board writes the output parameters required to be executed in the next period into the output channel registers of the multi-channel DAC on each sub-board through SPI in the time interval before the next output parameter refresh. The writing method can be serial or parallel.

[0079] The FPGA mother board and the DAC module of each DAC sub-board have equal length wiring, and each DAC output channel of each DAC sub-board and the DC electrode of the DC source corresponding to the DAC output channel have equal length wiring; wherein, the DAC output channel of each DAC sub-board is arranged in the DAC module of the DAC sub-board.

[0080] In this way, by controlling the length of the wiring, the transmission time of the output parameter in the transmission line is made as consistent as possible, thereby further improving the synchronization.

[0081] The DC electrode of the DC source corresponding to the DAC output channel refers to the voltage value of the output voltage of the DC electrode controlled by the output parameter, i.e. the voltage code, of the DAC output channel.

[0082] In one embodiment, the correspondence is set in the following manner: each DC electrode of the DC source is grouped according to the voltage regulation frequency, and each group of DC electrodes is evenly distributed to the DAC output channels of each DAC sub-board.

[0083] Specifically, the working timing of each DC electrode of each ion trap can be obtained, and according to the working characteristics of each DC electrode, the DC electrodes are divided into at least two groups according to the voltage regulation frequency.

[0084] For example, one part of the direct current electrode is refreshed every 100us, and another part of the direct current electrode is refreshed every 10us, and the two groups are executed uniformly refreshed, and the corresponding relationship between the groups and the DAC output channels is evenly distributed. For example, for a certain group of direct current electrodes, 40 DAC output channels are required to perform output parameters, and each sub-board has 8 DAC output channels. In the case of, the direct current electrode is evenly distributed to 5 DAC sub-boards for control, so that each DAC output channel controls one direct current electrode, instead of allowing one DAC sub-board to control 40 outputs.

[0085] The above optimization can reduce the total time of writing control parameters to the DAC output channels of each DAC sub-board, and can make the total time of writing output parameters to each DAC sub-board relatively average, so as to further reduce the refresh period, which is equivalent to T being less than Nt in the foregoing formula, thereby adapting to the improvement of quantum manipulation efficiency of ion trap quantum computing.

[0086] In one embodiment of the application, each direct current electrode of the direct current source is distributed to the DAC output channels of each DAC sub-board, comprising:

[0087] Determine the time when the number of voltage adjustments of the direct current electrode is the largest according to the working time sequence of each direct current electrode;

[0088] Distribute the direct current electrode whose voltage needs to be adjusted at this time to each DAC sub-board to obtain the number M of first DAC output channels of each DAC sub-board at this time;

[0089] Determine m according to the working time sequence of each direct current electrode;

[0090] Adjust the distribution of each direct current electrode in each DAC sub-board so that m-M is less than a set threshold.

[0091] According to the preset resolution, the number of direct current electrodes with voltage adjustment at each time sequence node is counted to determine the time when the number of voltage adjustments of the direct current electrode is the largest.

[0092] Determine the maximum number m according to the working time sequence of each direct current electrode, that is, count the number of first DAC output channels at each time sequence node, thereby obtaining the maximum number m of first DAC output channels of each sub-board.

[0093] The smaller the set threshold is, the better, and the most ideal case is to make m-M reach 0 or the minimum; if M is not an integer, rounding is required - that is, if M is 30.2, rounding to 31 is required.

[0094] When m or M exceeds the set threshold, the part of the direct current electrode already distributed on the corresponding DAC sub-board can be redistributed to other DAC sub-boards with smaller m or M values.

[0095] The above system includes a system clock chip, and the refresh cycle is generated based on a local clock signal provided by the system clock chip;

[0096] The FPGA motherboard controls the local clock signal and the external clock signal to be coherent.

[0097] The following embodiments describe how an FPGA motherboard controls the coherence of a local clock signal and an external clock signal.

[0098] In one embodiment of the present invention, a clock control system is provided. Figure 3 , FPGA motherboard, synchronous sampling source and system clock chip for quantum measurement and control. The FPGA motherboard includes a time interval measurement module and a PID control module;

[0099] System clock chip, used to provide local clock signal to the time interval measurement module;

[0100] A synchronous sampling source, used for providing a measurement clock signal to the time interval measurement module;

[0101] a time interval measurement module, configured to obtain frequency and / or phase information of an external clock signal and a local clock signal based on a measurement clock signal;

[0102] A PID control module, configured to output a clock adjustment signal based on frequency and / or phase information of an external clock signal and a local clock signal;

[0103] The system clock chip is further configured to adjust the frequency and / or phase of the local clock signal according to the clock adjustment signal.

[0104] The quantum measurement and control process includes multi-channel DC source control based on ion trap quantum computing. The FPGA motherboard is used to output the output parameters of each channel of the DC source. The system also includes a DAC daughterboard for executing the output parameters.

[0105] The local clock signal is used to control the timing of the output parameters of each channel of the DC source.

[0106] Figure 3 In the figure, FPGA refers to the FPGA motherboard, which is connected to the DAC daughterboard through the motherboard connector. The motherboard connector also connects to the power supply.

[0107] A clock signal is a periodically changing electrical signal that can be expressed as alternating high and low levels. In the above system, the local clock signal and the measurement clock signal are clock signals provided by the system clock chip and the synchronous sampling source, respectively.

[0108] The refresh period is set to be smaller than the shortest change interval of the output parameters in each channel of the DC source.

[0109] The external clock signal refers to a clock signal of an ion trap monitoring or signal detection related system.

[0110] In the case of obtaining the measurement clock signal and the local clock signal, the phase information can include a phase difference between the measurement clock signal and the local clock signal, and the phase difference reflects a timing deviation between the local clock signal and the measurement clock signal. The phase difference between the two clock signals can be measured by using a DDMTD (Digital Dual-Mixing Time-to-Digital Converter) technology. The DDMTD adopts a full-digital processing, can realize Kalman filtering and other algorithms through an FPGA motherboard, and suppresses burst noise. The DDMTD supports real-time phase adjustment at a nanosecond level, such as temperature drift compensation. The DDMTD can simultaneously measure the phase differences of multiple clock signals, and realizes cluster device synchronization. Therefore, the above architecture is particularly suitable for a board of a quantum control system.

[0111] The phase difference can be obtained by calculating a delay time of an edge of the local clock signal relative to the measurement clock signal. In the case of obtaining the phase difference, the frequency of the local clock signal can be obtained based on the phase difference and the frequency of the measurement clock signal. In this embodiment, the synchronous sampling source can be configured to output a clock signal with a fixed frequency, so as to calculate the frequency of the local clock signal and / or the phase information, and the frequency of the external clock signal and / or the phase information in a unified standard.

[0112] The calculation manner of the frequency and the phase information of the external clock signal is similar to the calculation manner of the frequency and the phase information of the local clock signal, and the difference is only in the replacement of the names and concepts of the external clock signal and the local clock signal.

[0113] Figure 3 The overall structure schematic diagram of the FPGA motherboard in the scheme provided by the embodiment of the application is shown. The synchronous sampling source directly outputs the measurement clock signal to the time interval measurement module.

[0114] The system further includes a frequency synthesizer for outputting the external clock signal to the time interval measurement module. The frequency synthesizer is configured to receive and adjust the clock signal from the outside to be the same frequency as the local clock signal. Thus, the external clock signal with the same frequency as the local clock signal is output.

[0115] The frequency synthesizer can generate a clock signal with a target frequency by using PLL (Phase-Locked Loop) feedback adjustment or DDS (Direct Digital Synthesizer) phase accumulation. The target frequency is set to the frequency of the local clock signal, so as to output the external clock signal with the same frequency as the local clock signal.

[0116] The core of DDMTD is to measure the phase difference of two clock signals through a double mixer structure, but this technology requires that the frequencies of the two input signals are strictly consistent. If the frequencies of the external clock signal and the local clock signal are different, a difference frequency signal will be generated after mixing, and the phase difference cannot be directly quantified. The external clock is converted to the local clock frequency domain by a frequency synthesizer, i.e., the same frequency, so that the two signals meet the conditions for phase difference detection.

[0117] Figure 3 The PID in the PID control module represents a PID control module. According to the requirements of quantum measurement and control, if it is necessary to adjust the local clock signal and the external clock signal to be in phase, the phase information of the external clock signal and the local clock signal is used.

[0118] Specifically, the phase difference between the local clock signal and the external clock signal can be calculated through the phase information of the external clock signal and the phase information of the local clock signal, the clock adjustment signal is a PID control signal output according to the phase difference, the relationship between the output and the phase difference is controlled by constructing a PID formula of the phase difference and the output and parameter setting, and the PID control signal is obtained. After that, the PID control signal is converted into a reference clock signal.

[0119] Or, if it is necessary to adjust the local clock signal and the external clock signal to be in the same frequency and phase, the phase information of the external clock signal and the local clock signal, and the frequency of the external clock signal and the local clock signal are used as the input of the PID control, so as to output the PID control signal.

[0120] In this way, the two clock signals can be in the same frequency and have a constant phase difference, or the two clock signals can have different frequencies, and the change of the phase difference conforms to the relationship of a trigonometric function or other functions, so as to realize the phase correlation between the local clock signal and the external clock signal.

[0121] The system clock chip can select a high-performance clock generator chip such as LMK04828 and HMC7044. By setting an additional system clock chip, the development of a module for providing a local clock signal on an FPGA motherboard is avoided, thereby reducing the development cost.

[0122] In the above embodiment, the specific implementation of the PID control module for controlling the system clock chip is that the PID control module outputs a PID control signal as a clock adjustment signal to control a voltage-controlled crystal oscillator. Please refer to Figure 3 , the clock control system further comprises a second DAC and a voltage-controlled crystal oscillator.

[0123] The voltage-controlled crystal oscillator is used to provide a reference clock signal for the system clock chip to control the system clock chip to adjust the frequency and / or phase of the local clock signal.

[0124] The second DAC is used for converting the clock adjustment signal into an analog signal to control the voltage-controlled crystal oscillator to output a reference clock signal.

[0125] The second described in the second DAC is only used to distinguish from the DAC sub-boards in the foregoing embodiments, to represent different DAC devices.

[0126] The frequency and / or phase information of the local clock signal output by the system clock chip is controlled by the voltage-controlled crystal oscillator, and the voltage-controlled crystal oscillator is controlled by the clock adjustment signal, since the voltage-controlled crystal oscillator is controlled by an analog signal, and the PID control module is part of the FPGA, and the output is a digital signal, therefore, the digital signal needs to be converted into an analog signal by the DAC.

[0127] In one embodiment of the application, the clock control system further comprises a first crystal oscillator;

[0128] The first crystal oscillator is used to provide a system configuration clock signal to the FPGA motherboard, so that the FPGA motherboard starts running and establishes an SPI connection with the system clock chip to obtain the local clock signal.

[0129] The FPGA circuit board refers to the FPGA motherboard in the foregoing embodiments. The system configuration clock signal is a clock signal with a preset frequency. The system configuration clock signal is provided to the FPGA circuit board, and the same system configuration clock signal is provided to the system clock chip, so that the FPGA circuit board and the system clock chip can communicate according to consistent timing.

[0130] The clock control system is provided with a synchronous sampling source, and the first crystal oscillator is also provided. The reason for repeatedly providing an independent clock signal source is that DDMTD realizes high-precision alignment by measuring the phase difference of two clock signals. If the first crystal oscillator is directly used as a sampling clock, the internal logic noise of the first crystal oscillator, such as power supply jitter and cross-clock domain interference, will pollute the measurement results, leading to phase noise deterioration. The independent synchronous sampling source can avoid mixing of FPGA digital noise into the measurement link. Moreover, the first crystal oscillator serving as the system configuration clock has a large clock path delay and is easily affected by temperature / voltage drift, and cannot meet the stringent requirements of DDMTD on the phase consistency of the sampling clock.

[0131] In one embodiment of the application, the clock control system further comprises a DDR (Double Data Rate Synchronous Dynamic Random Access Memory) used for storing the quantum measurement and control issued instructions received by the communication module.

[0132] The system clock chip is also configured to provide a local clock signal to the DDR, so that the DDR performs a data processing operation based on the local clock signal.

[0133] In one embodiment, the clock control system further comprises:

[0134] a FLASH for storing system firmware, the system firmware being loaded from the FLASH to the FPGA motherboard after the system is powered on;

[0135] The clock control system further comprises an EEPROM for storing version numbers and factory numbers of the software and hardware.

[0136] As shown in Figure 3 The FPGA motherboard is connected with a FLASH, a DDR and an EEPROM (Electrically Erasable Programmable read only memory), the FLASH can be a NAND FLASH (Not AND Flash), which is used as a large-capacity storage device. The DDR can be any RAM (Random Access Memory) device, which is used as a system running cache. The EEPROM can be any ROM device or NOR FLASH, which is used as a system firmware device. Specifically, the FLASH can store system firmware, the firmware being loaded from the FLASH to the FPGA motherboard after the system is powered on, and the DDR can store timing information of output voltages of a multi-channel DC source.

[0137] The DDR stores the issued instructions directly for quantum computing tasks, and the DDR controller controls using a local clock signal provided by the system clock chip, so as to ensure that the data read-write operation of the DDR is synchronized with the quantum measurement and control core, and the same clock domain is used to ensure the low-delay synchronization of the instruction reading and the quantum measurement and control, to avoid data errors or performance bottlenecks caused by clock switching, and to reduce the timing risk caused by cross-clock domain; and the data path design in the FPGA is simplified, such as the depth control of the FIFO buffer, to improve the overall efficiency of the system.

[0138] In one embodiment, the local clock signal provided by the system clock chip comprises parallel phase measurement signals, system global signals and DDR control signals respectively;

[0139] The phase measurement signals are provided to a time interval measurement module;

[0140] The system global signals are used to control quantum measurement and control operations;

[0141] The DDR control signals are used to provide to the DDR.

[0142] Figure 3 In the embodiment, the system clock chip provides four lines of connection, wherein the SPI connection is used for connection with the FPGA, the phase measurement signal is used for measuring whether the local clock signal and the external clock signal are in phase, if not, the PID control module is used to adjust the local clock signal until the phase is achieved, and the Global connection represents the system global signal.

[0143] The phase measurement signal is parallel and isolated from other signal lines, so that the measurement process can be as little as possible to be interfered by other signal clutter.

[0144] The DDR represents a DDR control signal, and the purpose is to:

[0145] The output processing operation performed by the DDR interface includes clock and data alignment, and the global clock signal is difficult to directly meet the setup / hold time requirement of the DDR interface due to path delay difference, and the duty cycle of the DDR clock needs to be close to 50%, and the global clock may be distorted due to load changes in long-distance transmission, and relatively, a local clock signal is provided separately, and the local clock buffer (such as BUFR) can reduce such distortion; in addition, the independent DDR clock path can reduce the crosstalk of the high-speed switching signal to the global clock network, and improve the system stability.

[0146] In one embodiment of the application, the clock control system further comprises a communication module;

[0147] The first crystal oscillator is also used to provide a system configuration clock signal to the communication module.

[0148] The communication module comprises an Ethernet port and a serial transceiver connected to the Ethernet port based on a communication protocol, and the system configuration clock signal is provided to the serial transceiver.

[0149] The communication module can be Figure 3 In the embodiment, the serial transceiver and the Ethernet port communicate based on the SGMII (Serial Gigabit Media Independent Interface) communication protocol.

[0150] The system configuration clock is used for SPI connection and Ethernet serial transceiver to physical layer operation, which belongs to lower priority or asynchronous communication task. Because the data communication is usually associated with the output timing sequence of the direct current source, the clock signal provided by the crystal oscillator does not exist phase adjustment, and the frequency and phase are relatively stable, so that the stability of the data communication can be ensured.

[0151] As Figure 3 The first crystal oscillator divides the system configuration clock signal into two paths by the clock distribution module, one path is provided to the FPGA motherboard, and the other path is provided to the serial transceiver.

[0152] Corresponding to the above system embodiment, one embodiment of the present application further provides a multi-channel DC source asynchronous write synchronous refresh method, see Figure 4 The method is applied to the FPGA motherboard of the multi-channel DC source asynchronous write synchronous refresh system, and comprises steps S401-S402.

[0153] S401: write output parameters to each DAC sub-board, and control the receiving time of the DAC output channel of each DAC sub-board receiving the output parameters to be before the start time of the next refresh period;

[0154] S402: send refresh instructions to each DAC sub-board at the start time in parallel, so that each DAC sub-board receives the refresh instructions, and controls the DAC output channel of the DAC sub-board to execute the received output parameters.

[0155] Wherein, all working time sequences of all DAC output channels have a greatest common divisor, and the greatest common divisor is equal to X times of the refresh period, and X is a positive integer greater than or equal to 1.

[0156] One embodiment of the present application further provides an ion trap quantum computing DC electrode system, comprising the multi-channel DC source asynchronous write synchronous refresh system of any one of the above embodiments.

[0157] One embodiment of the present application further provides an ion trap quantum computing system, comprising the multi-channel DC source asynchronous write synchronous refresh system of any one of the above embodiments.

[0158] It is to be appreciated that the above description and the examples that follow are intended to be illustrative only and that changes can be made to the description, either functionally or chronologically, as well as changes being made concerning the order of implementation. The logic and / or steps represented in the flow diagrams and / or described herein can be considered as a sequence of executable instructions, and can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For purposes of this specification, a "computer-readable medium" can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be, for example, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus) or a propagation medium. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber (optical), and a portable compact disc read-only memory (CDROM). Note that the computer-readable medium can even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, for example via the optical scanner of a device or device or via an intermediary, such as a facility bureau, then compiled, interpreted, or processed in a suitable manner if necessary, and then stored in a computer storage medium.

[0159] It should be understood that aspects of the application can be implemented in hardware, software, firmware or combinations thereof. In the above embodiments, various steps or methods can be implemented in software or firmware that is stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any of the following technologies, known in the art, or combinations thereof, can be used: a discrete logic circuit having logic gates for implementing logic functions upon data signals, an application specific integrated circuit having appropriate combinational logic gates, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0160] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Also, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in an appropriate manner.

[0161] In the description of the application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application.

[0162] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise explicitly specified and limited.

[0163] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0164] In the present application, unless otherwise explicitly specified and limited, the first feature "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature "above", "above" and "above" the second feature can be that the first feature is directly above or obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature can be that the first feature is directly below or obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0165] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as a limitation on the present application, and those skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present application.

Claims

1. A multi-channel DC source asynchronous writing and synchronous refreshing system, characterized in that: The system includes an FPGA motherboard for outputting output parameters of each channel of a DC source, and at least two DAC daughterboards for executing the output parameters; each DAC daughterboard is provided with a plurality of DAC output channels; The FPGA motherboard is used to write output parameters to each DAC daughter board and control the DAC output channel of each DAC daughter board to receive the output parameters before the start time of the next refresh cycle; The FPGA motherboard is further configured to send a refresh instruction to each DAC daughter board in parallel at the start time; After receiving the refresh instruction, each DAC sub-board controls the DAC output channel of the DAC sub-board to execute the received output parameter; All operating timings of all DAC output channels have a greatest common divisor, where the greatest common divisor is equal to X times the refresh period, where X is a positive integer greater than or equal to 1; The refresh cycle satisfies the following setting conditions: the FPGA motherboard writes output parameters to each DAC daughterboard in parallel; Writing output parameters to each DAC sub-board in parallel includes: For each DAC daughter board, determining whether a historical output parameter received by each DAC output channel of the DAC daughter board is different from the output parameter; If there is a first DAC output channel whose output parameter is different from the historical output parameter, the output parameter is written to the first DAC output channel.

2. The system according to claim 1, wherein: The refresh cycle meets the following setting conditions: The maximum number of DAC output channels on each DAC daughter board is N, the time for the FPGA mother board to write output parameters to each DAC output channel is t, and the refresh period is T.

3. The system according to claim 1, wherein: The refresh cycle meets the following setting conditions: The maximum number of the first DAC output channels in each DAC daughter board is m, the time for the FPGA motherboard to write output parameters to each DAC output channel is t, and the refresh period is T.

4. The system according to claim 3, characterized in that The DC electrodes of the DC source are grouped according to the voltage regulation frequency, and the DC electrodes included in each group are evenly distributed to the DAC output channels of each DAC sub-board.

5. The system according to claim 3, wherein: Each DC electrode of the DC source is distributed to a DAC output channel of each DAC sub-board, including: Determine the moment when the DC electrode voltage adjustment is the largest according to the working sequence of each DC electrode; Evenly distribute the DC electrodes that need voltage adjustment at the moment to each DAC sub-board, and obtain the number M of the first DAC output channels of each DAC sub-board at the moment; m is determined according to the working sequence of each DC electrode; Adjust the distribution of each DC electrode in each DAC sub-board so that mM is less than the set threshold.

6. The system according to claim 1, wherein: Each DAC daughter board is also equipped with a voltage reference chip.

7. The system according to claim 1, wherein: There is wiring of equal length between the FPGA motherboard and the DAC modules of each DAC daughter board, and there is wiring of equal length between each DAC output channel of each DAC daughter board and the DC electrode of the DC source corresponding to the DAC output channel; wherein, the DAC output channel of each DAC daughter board is arranged in the DAC module of the DAC daughter board.

8. The system according to claim 1, wherein: The refresh period is set to be less than or equal to 100 μs.

9. The system according to any one of claims 1 to 8, characterized in that The system includes a system clock chip, and the refresh cycle is generated based on a local clock signal provided by the system clock chip; The FPGA motherboard controls the local clock signal and the external clock signal to be coherent.

10. A multi-channel DC source asynchronous writing and synchronous refreshing method, characterized in that: An FPGA motherboard applied to a multi-channel DC source asynchronous writing and synchronous refreshing system, the method comprising: Writing output parameters to each DAC sub-board, and controlling the DAC output channel of each DAC sub-board to receive the output parameters before the start time of the next refresh cycle; Sending a refresh instruction to each DAC sub-board in parallel at the start time, so that after each DAC sub-board receives the refresh instruction, it controls the DAC output channel of the DAC sub-board to execute the received output parameter; All operating timings of all DAC output channels have a greatest common divisor, where the greatest common divisor is equal to X times the refresh period, where X is a positive integer greater than or equal to 1; The refresh cycle satisfies the following setting conditions: the FPGA motherboard writes output parameters to each DAC daughterboard in parallel; Writing output parameters to each DAC sub-board in parallel includes: For each DAC daughter board, determining whether a historical output parameter received by each DAC output channel of the DAC daughter board is different from the output parameter; If there is a first DAC output channel whose output parameter is different from the historical output parameter, the output parameter is written to the first DAC output channel.

11. An ion trap quantum computing DC electrode system, characterized in that: A multi-channel DC source asynchronous writing and synchronous refreshing system comprising any one of claims 1-9.

12. An ion trap quantum computing system, characterized in that: A multi-channel DC source asynchronous writing and synchronous refreshing system comprising any one of claims 1-9.

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