Joint simulation method, system and equipment for power supply integrity and signal integrity

Abstract

The invention provides a joint simulation method, system and equipment for power supply integrity and signal integrity. The joint simulation method comprises the following steps: acquiring a first excitation signal; the first excitation signal is obtained by a first simulation result obtained by performing power supply integrity simulation on the to-be-tested system according to the second excitation signal; and performing signal integrity simulation on the to-be-tested system according to the first excitation signal and the second excitation signal to generate a second simulation result. According to the invention, by using the result of the power supply integrity simulation as the input of the signal integrity simulation, the power supply dynamic state of the circuit in the actual working environment can be simulated more accurately, and the influence of the power supply noise on the signal quality can be revealed, so that the potential problem can be avoided in the design stage. In addition, the problem of excessive design caused by separate simulation of SI simulation and PI simulation can be avoided, so that a better solution is provided for PPA and cost of a high-speed interface system.

Description

Technical Field

[0001] The present disclosure relates to the field of signal simulation, and in particular to a method, system, and device for joint simulation of power integrity and signal integrity. Background Art

[0002] When simulating a system under test (SUT), simulation analysis methods for power integrity (PI) and signal integrity (SI) are generally included. Although mature simulation analysis methods exist for PI and SI simulations, existing simulation analysis generally generates simulation results based on SI and PI simulations independently. Finally, jitter evaluation is performed based on these two simulation results to evaluate the performance of the SUT.

[0003] However, this simulation method often fails to accurately evaluate jitter. The main reasons are as follows: PI jitter and SI jitter lack a clear mathematical relationship, such as simple linear addition or power addition. Furthermore, in certain scenarios (e.g., multi-channel), PI power supply ripple can affect SI crosstalk simulation results. Furthermore, the worst-case corner cases for PI and SI jitter differ, requiring precise matching of PI and SI jitter. Ultimately, PI and SI simulations cannot be used to accurately evaluate the performance of the system under test. Summary of the Invention

[0004] The technical problem to be solved by the present disclosure is to overcome the defect in the prior art that PI simulation and SI simulation cannot be used to accurately evaluate the performance of the system to be tested, and to provide a joint simulation method, system and device for power integrity and signal integrity.

[0005] The present disclosure solves the above technical problems through the following technical solutions:

[0006] The present disclosure provides a joint simulation method for power integrity and signal integrity, the joint simulation method comprising:

[0007] Acquire a first excitation signal; the first excitation signal is obtained by a first simulation result of a power integrity simulation of the system to be tested according to the second excitation signal;

[0008] A second simulation result is generated after performing signal integrity simulation on the system to be tested according to the first excitation signal and the second excitation signal.

[0009] Optionally, before the step of obtaining the first excitation signal, the step includes:

[0010] Inputting the second excitation signal into the power integrity simulation workbench of the system to be tested to perform power integrity simulation and generate the first simulation result;

[0011] The first simulation result includes at least one of the following: impedance characteristics of the power integrity simulation workbench, power supply ripple, and power supply noise.

[0012] Optionally, the power integrity simulation workbench includes at least one of the following: a first design module, a voltage regulation module, a first printed circuit board, a first package, and a first redistribution layer;

[0013] and / or,

[0014] The power integrity simulation workbench uses S-parameter models.

[0015] Optionally, the first design module is a netlist, a partial netlist affecting power integrity simulation, or a chip power model.

[0016] Optionally, generating a second simulation result after performing signal integrity simulation on the system to be tested according to the first excitation signal and the second excitation signal includes:

[0017] The first excitation signal and the second excitation signal are input into a signal integrity simulation workbench of the system to be tested to perform signal integrity simulation and generate the second simulation result.

[0018] Optionally, the signal integrity simulation workbench includes at least one of the following: a second design module, a second printed circuit board, a second package, and a second redistribution layer.

[0019] Optionally, the second design module is a netlist or a portion of the netlist that affects signal integrity simulation.

[0020] Optionally, the second simulation result is used to generate a jitter budget, and the jitter budget is used to perform performance evaluation on the system under test;

[0021] and / or,

[0022] The system to be tested is a high-speed interface system.

[0023] The present disclosure further provides a joint simulation system for power integrity and signal integrity, the joint simulation system comprising:

[0024] An acquisition module, configured to acquire a first excitation signal; the first excitation signal is obtained by performing a first simulation result of a power integrity simulation on the system to be tested according to the second excitation signal;

[0025] The joint simulation module is used to generate a second simulation result after performing signal integrity simulation on the system to be tested according to the first excitation signal and the second excitation signal.

[0026] Optionally, the joint simulation system further includes:

[0027] a power supply simulation module, configured to input the second excitation signal into a power integrity simulation workbench of the system to be tested to perform power integrity simulation and generate the first simulation result;

[0028] The first simulation result includes at least one of the following: impedance characteristics of the power integrity simulation workbench, power supply ripple, and power supply noise.

[0029] Optionally, the power integrity simulation workbench includes at least one of the following: a first design module, a voltage regulation module, a first printed circuit board, a first package, and a first redistribution layer;

[0030] and / or,

[0031] The power integrity simulation workbench uses S-parameter models.

[0032] Optionally, the first design module is a netlist, a partial netlist affecting power integrity simulation, or a chip power model.

[0033] Optionally, the joint simulation module is further specifically configured to:

[0034] The first excitation signal and the second excitation signal are input into a signal integrity simulation workbench of the system to be tested to perform signal integrity simulation and generate the second simulation result.

[0035] Optionally, the signal integrity simulation workbench includes at least one of the following: a second design module, a second printed circuit board, a second package, and a second redistribution layer.

[0036] Optionally, the second design module is a netlist or a portion of the netlist that affects signal integrity simulation.

[0037] Optionally, the second simulation result is used to generate a jitter budget, and the jitter budget is used to perform performance evaluation on the system under test;

[0038] and / or,

[0039] The system to be tested is a high-speed interface system.

[0040] The present disclosure also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and used to run on the processor, wherein when the processor executes the computer program, the combined simulation method of power integrity and signal integrity described in any one of the above items is implemented.

[0041] The present disclosure also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the method for jointly simulating power integrity and signal integrity described in any one of the above items is implemented.

[0042] The present disclosure also provides a computer program product, including a computer program, which, when executed by a processor, implements any of the above-mentioned methods for jointly simulating power integrity and signal integrity.

[0043] The present disclosure also provides a chip having a computer program stored thereon. When the computer program is executed by the chip, the combined simulation method of power integrity and signal integrity described in any one of the above items is implemented.

[0044] The present disclosure also provides a chip module, which is applied to electronic equipment, including a transceiver component and a chip, wherein the chip is used to implement the joint simulation method of power integrity and signal integrity as described in any one of the above items.

[0045] On the basis of conforming to the common sense in this field, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0046] The positive impact of this disclosure is that by using the results of power integrity simulation as input for signal integrity simulation, the power dynamics of the circuit in the actual working environment can be more accurately simulated, revealing the impact of power noise on signal quality, thereby avoiding potential problems in the design phase. In addition, it can also avoid the over-design problem caused by separate SI simulation and PI simulation, thereby providing a more optimized solution for PPA (Power, Performance, Area) and cost of high-speed interface systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 A flowchart of a method for co-simulating power integrity and signal integrity provided by an exemplary embodiment of the present disclosure;

[0048] Figure 2 A flowchart of another method for co-simulating power integrity and signal integrity provided by an exemplary embodiment of the present disclosure;

[0049] Figure 3 A flowchart of another method for co-simulating power integrity and signal integrity provided by an exemplary embodiment of the present disclosure;

[0050] Figure 4 A schematic diagram of an eye diagram and an eye diagram evaluation standard Eye Mask provided by an exemplary embodiment of the present disclosure;

[0051] Figure 5 This is a schematic diagram of an existing 1UI jitter budget;

[0052] Figure 6 A schematic diagram of a 1UI jitter budget provided by an exemplary embodiment of the present disclosure;

[0053] Figure 7 A schematic diagram of a module of a power integrity and signal integrity co-simulation system provided by an exemplary embodiment of the present disclosure;

[0054] Figure 8 A schematic diagram of a module of another power integrity and signal integrity co-simulation system provided by an exemplary embodiment of the present disclosure;

[0055] Figure 9 The present invention provides a structural diagram of an electronic device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0056] The present disclosure is further illustrated below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0057] In the embodiments of the present disclosure, prefixes such as "first" and "second" are used only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. In the embodiments of the present disclosure, the use of prefixes such as ordinal numbers to distinguish description objects does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitations should be constituted due to the use of such prefixes. In addition, in the description of this embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0058] Figure 1 This is a flow chart of a method for co-simulating power integrity and signal integrity according to an exemplary embodiment of the present disclosure. As can be seen from the figure, the co-simulation method includes:

[0059] Step 101: Obtain a first excitation signal. The first excitation signal is obtained from a first simulation result of a power integrity simulation of a system under test according to a second excitation signal.

[0060] The purpose of this step is to obtain a first excitation signal, which is based on the result of power integrity simulation of the system under test. In this way, the electrical characteristics of the power distribution network (PDN, Power Distribution Network) (such as impedance, ripple and noise) can be incorporated into the subsequent signal integrity analysis. Specifically, in the power integrity simulation, a second excitation signal is used as input. This signal represents the power demand or interference that the system may encounter in actual work. The first simulation results are obtained through the power integrity simulation. These results describe in detail the response of the power distribution network under different frequency and load conditions. The electrical parameters related to the signal transmission characteristics are extracted from the first simulation results to generate the first excitation signal. This signal contains information about the possible impact of the power distribution network on signal transmission.

[0061] This step is crucial for ensuring that the electrical characteristics of the power distribution network are accurately factored into the signal integrity analysis. By using the first stimulus signal, we can more realistically simulate the signal's behavior when subjected to power supply noise and ripple, thereby improving the accuracy and reliability of the simulation.

[0062] As a specific example, consider a digital circuit board containing multiple high-speed digital devices, such as processors and memory, powered by a complex power distribution network. A power integrity simulation is performed on the circuit board's power distribution network using a representative operating current waveform as the second stimulus signal. Power ripple and noise data are extracted from the simulation results, reflecting the actual performance of the power network under different loads and frequencies. Based on the extracted data, a first stimulus signal is generated that incorporates the potential impact of power ripple and noise on signal transmission. This first stimulus signal is then applied to a signal integrity simulation tool (such as a signal integrity simulation workbench) to perform signal integrity simulation and analyze the data transmission path between the processor and memory. By accounting for the impact of power noise, performance indicators such as the signal's eye diagram, jitter, and bit error rate can be more accurately predicted.

[0063] Step 102: Perform signal integrity simulation on the system to be tested according to the first excitation signal and the second excitation signal to generate a second simulation result.

[0064] Optionally, step 102 specifically includes: inputting the first excitation signal and the second excitation signal into a signal integrity simulation workbench of the system to be tested to perform signal integrity simulation and generate a second simulation result.

[0065] Optionally, the signal integrity simulation workbench includes at least one of the following: a second design module, a second printed circuit board, a second package, and a second redistribution layer.

[0066] Optionally, the second design module is a netlist or a portion of the netlist that affects signal integrity simulation.

[0067] Optionally, the second simulation result is used to generate a jitter budget, and the jitter budget is used to perform performance evaluation on the system to be tested; and / or the system to be tested is a high-speed interface system.

[0068] The purpose of this step is to evaluate the performance of the system under test through signal integrity simulation, especially after considering the influence of the power distribution network. This is to ensure the quality and integrity of the signal during transmission, especially in high-speed interface systems. Specifically, based on the first excitation signal (reflecting the electrical characteristics of the power distribution network) and the second excitation signal (representing the input signal or power demand when the system is working normally), the signal integrity simulation of the system under test is performed. These two excitation signals are input into the signal integrity simulation workbench, which may include components such as a second design module (such as a netlist or a part of the netlist that affects the signal integrity simulation), a second printed circuit board, a second package, and a second redistribution layer. After the signal integrity simulation is performed, a second simulation result is generated, which includes various performance indicators during signal transmission, such as jitter, noise margin, signal loss and reflection.

[0069] This step is crucial for evaluating the performance of high-speed interface systems because it reveals the combined impact of power supply noise and signal effects on signal transmission quality. Furthermore, by analyzing the second simulation results, system design can be optimized to reduce signal degradation and improve signal transmission reliability and performance.

[0070] To give a specific example, consider a digital circuit board containing multiple high-speed digital devices, such as processors and memory, which are powered by a complex power distribution network. Ensuring the signal integrity of the processor-memory interface at high data rates is essential. Signal integrity simulation of the processor-memory interface is performed using a first stimulus signal (containing power supply ripple and noise information) and a second stimulus signal (representing the clock and data signals during normal operation). These two stimulus signals are input into a signal integrity simulation tool to simulate the actual behavior of the processor-memory interface. The simulation results are analyzed for metrics such as jitter, signal attenuation, and crosstalk to evaluate the interface's performance. Furthermore, if jitter is found to be outside acceptable limits, the circuit board layout can be adjusted or termination resistors can be added to improve signal quality. This approach allows the performance of the processor-memory interface to be predicted and optimized during the design phase, reducing the need for field testing.

[0071] Optionally, Figure 2 This is a flowchart of another method for co-simulating power integrity and signal integrity provided by an exemplary embodiment of the present disclosure. As can be seen from the figure, before step 101, the following steps are included:

[0072] Step 103: Input the second excitation signal to a power integrity simulation workbench of the system under test to perform power integrity simulation and generate a first simulation result, wherein the first simulation result includes at least one of the following: impedance characteristics of the power integrity simulation workbench, power supply ripple, and power supply noise.

[0073] Optionally, the power integrity simulation workbench includes at least one of the following: a first design module, a voltage regulation module, a first printed circuit board, a first package, and a first redistribution layer; and / or, the power integrity simulation workbench uses an S-parameter model.

[0074] Optionally, the first design module is a netlist, a portion of the netlist that affects power integrity simulation, or a chip power model.

[0075] The purpose of this step is to evaluate the power distribution network performance of the system under test through power integrity simulation, which is closely related to the first excitation signal in step 101. This helps to ensure that the system can provide a stable and low-noise power supply voltage under various working conditions, thereby meeting the working requirements of the device. Specifically, the second excitation signal (representing the power demand or interference when the system is working normally) is input into the power integrity simulation workbench of the system under test. Power integrity simulation is performed to generate a first simulation result, including indicators such as the impedance characteristics of the power integrity simulation workbench, the ripple of the power supply, and the noise of the power supply. The power integrity simulation workbench may include components such as a first design module (such as a netlist, a partial netlist that affects the power integrity simulation, or a chip power supply model), a voltage regulation module, a first printed circuit board, a first package, and a first redistribution layer.

[0076] This step is crucial for evaluating the performance of the system's power distribution network, as it reveals the system's power stability and noise levels in real-world applications. By analyzing the first simulation results, we can optimize the power distribution network design, reduce power noise, and improve system reliability and performance.

[0077] As a specific example, consider a digital circuit board containing multiple high-speed digital devices, such as processors and memory, which have stringent requirements for power supply stability and noise levels. Ensuring signal integrity at the processor-memory interface is essential at high data rates. A power integrity simulation of the processor's power supply path is performed using a representative operating current waveform as a second stimulus signal. This second stimulus signal is input into a power integrity simulation workbench to simulate the processor's behavior under high load. The simulation results analyze metrics such as the processor's power plane impedance, power ripple, and noise to assess the processor's power supply quality. If the power ripple is found to be outside the allowable range, the board layout can be adjusted or decoupling capacitors can be added to improve power quality. This approach allows the processor's power supply performance to be predicted and optimized during the design phase, ensuring stable operation at high data rates.

[0078] Based on the above content, a specific example is given here to illustrate the complete process of the joint simulation method of power integrity and signal integrity. Figure 3 As can be seen from the figure, the whole process is roughly divided into two stages:

[0079] The first is the power integrity simulation stage. The dotted box is the power integrity simulation workbench 501. The input stimulus (Stimulus) 502 is input into the design module (Design Module) 503 that needs to be verified. In most cases, the design module 503 will have a shared power supply: (1) different circuit function modules share power supply, (2) different submodules of the same circuit function module share power supply, such as a digital module that is not sensitive to power supply and an analog module that is sensitive to power supply share power supply. If a single module has exclusive power supply, the design module 503 can only retain a single module. The design module 503 can also be a complete netlist (netlist), or a CPM (chip power model) can be used to speed up the simulation rate. In addition to the design module 503, the power integrity simulation workbench 501 contains all the complete PDN networks that affect the power integrity simulation performance, mainly: voltage regulator module (VRM), printed circuit board (PCB), package (PKG), and redistribution layer (RDL). The PDN network may use an S-parameter model, or a corresponding complete or simplified resistance-inductance-capacitance (RLC) model. The power integrity simulation result 504 may be a network impedance in the frequency domain or a waveform in the time domain.

[0080] Next comes the co-simulation phase of power integrity simulation and signal integrity simulation. Specifically, the power integrity simulation result 504 is used as input to the signal integrity simulation workbench 505. The input stimulus 506 of the signal integrity simulation needs to be consistent with the input of the design module 503 in the power integrity simulation input stimulus 502. The design module 507 can be a complete netlist. To speed up the simulation, it can be simplified to a partial netlist that only affects the signal integrity simulation, such as a key netlist that only affects performance. In addition to the design module 507, the signal integrity simulation workbench 505 contains all channel networks that affect the signal integrity simulation performance, including the printed circuit board (PCB), package (PKG), redistribution layer (RDL) on the design module side, and the package and redistribution layer on the cooperating object (Cooperator) side. The channel network can use an S-parameter model or a corresponding complete or simplified resistor, inductor, and capacitor (RLC) model. The co-simulation of power integrity simulation and signal integrity simulation produces simulation results 508.

[0081] Compared with the traditional method, the simulation result 508 obtained by the joint simulation method proposed in the present disclosure can simultaneously reflect the influence of the PDN network and the channel network.

[0082] High-speed interface systems are generally used for data transmission between chips or between chip modules. For high-speed interface systems such as PCIe6.0, 112G / 224G serdes, LPDDR5, GDDR6, etc., all components of the entire link, including circuits, RDL, PKG, PCB, etc., will affect the performance of the system. High-speed interface performance is usually characterized by eye diagrams, such as Figure 4 As shown in Figure 1, Eye Mask is the minimum eye diagram standard that meets the requirements. In high-speed interface systems, performance is generally evaluated using a 1UI jitter budget, such as Figure 5 As shown, UI is the unit interval. In traditional system performance evaluation, 1UI = circuit jitter 201 + PI jitter 202 + SI jitter 203 + EyeMask 205 + margin (Margin) 204, that is, the jitter introduced by the circuit netlist itself, the jitter introduced by power integrity (PI), the jitter introduced by signal integrity (SI), the minimum eye diagram standard EyeMask that needs to be met, and the necessary design margin. However, the 1UI jitter budget of the joint simulation method proposed in this disclosure is as follows Figure 6 As shown: SIPI jitter 602 replaces Figure 5 The PI jitter 202 and SI jitter 203 in FIG. 200 can be reduced, and the following advantages can be achieved:

[0083] 1. Directly obtain accurate SIPI simulation results without converting the power integrity simulation results and signal integrity simulation results, thus avoiding the introduction of additional errors.

[0084] 2. Accurately evaluate the impact of PDN PI power supply jitter on SI, such as the crosstalk of multi-channel PI power supply ripple on SI.

[0085] 3. Accurately evaluate the performance of the interface system under a specific process corner (corner case), avoiding the over-design problem caused by inconsistent worst-case process corners for PI jitter and SI jitter, thereby improving the system margin or PPA performance.

[0086] In summary, this technical solution provides a more accurate and efficient simulation process by integrating the joint simulation method of PI and SI, which can better evaluate and optimize power supply and signal integrity issues in electronic systems.

[0087] This embodiment uses the results of power integrity simulation as input for signal integrity simulation, allowing for more accurate simulation of the circuit's power dynamics in an actual operating environment. This can reveal the impact of power noise on signal quality, thus avoiding potential problems during the design phase. Furthermore, it avoids overdesign issues caused by separate SI and PI simulations, thus providing a more optimized solution for PPA (Power, Performance, Area) and cost in high-speed interface systems.

[0088] Example 2

[0089] Corresponding to the aforementioned embodiment of the method for co-simulating power integrity and signal integrity, the present disclosure also provides an embodiment of a system for co-simulating power integrity and signal integrity.

[0090] Figure 7 This is a module diagram of a power integrity and signal integrity co-simulation system provided by an exemplary embodiment of the present disclosure. As can be seen from the figure, the co-simulation system includes:

[0091] An acquisition module 21 is configured to acquire a first excitation signal; the first excitation signal is obtained by performing a first simulation result of a power integrity simulation on the system under test according to the second excitation signal;

[0092] The joint simulation module 22 is configured to generate a second simulation result after performing a signal integrity simulation on the system to be tested according to the first excitation signal and the second excitation signal.

[0093] Optionally, Figure 8A schematic diagram of a module of another power integrity and signal integrity co-simulation system provided by an exemplary embodiment of the present disclosure. As can be seen from the figure, the co-simulation system also includes:

[0094] A power simulation module 23 is configured to input the second excitation signal into a power integrity simulation workbench of the system to be tested to perform power integrity simulation and generate a first simulation result;

[0095] The first simulation result includes at least one of the following: impedance characteristics of a power integrity simulation workbench, ripple of a power supply, and noise of a power supply.

[0096] Optionally, the power integrity simulation workbench includes at least one of the following: a first design module, a voltage regulation module, a first printed circuit board, a first package, and a first redistribution layer;

[0097] and / or,

[0098] The Power Integrity Simulation Workbench uses S-parameter models.

[0099] Optionally, the first design module is a netlist, a portion of the netlist that affects power integrity simulation, or a chip power model.

[0100] Optionally, the joint simulation module 22 is further specifically configured to:

[0101] The first excitation signal and the second excitation signal are input into a signal integrity simulation workbench of the system to be tested to perform signal integrity simulation and generate a second simulation result.

[0102] Optionally, the signal integrity simulation workbench includes at least one of the following: a second design module, a second printed circuit board, a second package, and a second redistribution layer.

[0103] Optionally, the second design module is a netlist or a portion of the netlist that affects signal integrity simulation.

[0104] Optionally, the second simulation result is used to generate a jitter budget, and the jitter budget is used to perform performance evaluation on the system under test;

[0105] and / or,

[0106] The system under test is a high-speed interface system.

[0107] Since the system embodiments generally correspond to the method embodiments, reference will be made to the description of the method embodiments for relevant details. The system embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components of the units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the disclosed solution.

[0108] This embodiment uses the results of power integrity simulation as input for signal integrity simulation, allowing for more accurate simulation of the circuit's power dynamics in an actual operating environment. This can reveal the impact of power noise on signal quality, thus avoiding potential problems during the design phase. Furthermore, it avoids overdesign issues caused by separate SI and PI simulations, thus providing a more optimized solution for PPA (Power, Performance, Area) and cost in high-speed interface systems.

[0109] Example 3

[0110] Figure 9 This is a structural schematic diagram of an electronic device showing an example embodiment of the present disclosure. The electronic device includes a memory, a processor, and a computer program stored in the memory and configured to run on the processor. When the processor executes the computer program, the method for jointly simulating power integrity and signal integrity as described in any of the above embodiments is implemented. Figure 9 The electronic device 90 shown is only an example and should not limit the functionality and scope of use of the embodiments of the present disclosure.

[0111] like Figure 9 As shown, the electronic device 90 may be a general-purpose computing device, such as a server device. Components of the electronic device 90 may include, but are not limited to, the at least one processor 91, the at least one memory 92, and a bus 93 connecting different system components (including the memory 92 and the processor 91).

[0112] The bus 93 includes a data bus, an address bus, and a control bus.

[0113] The memory 92 may include a volatile memory, such as a random access memory (RAM) 921 and / or a cache memory 922 , and may further include a read-only memory (ROM) 923 .

[0114] The memory 92 may also include a program tool 925 (or utility) having a set (at least one) of program modules 924, such program modules 924 including but not limited to: an operating system, one or more application programs, other program modules and program data, each of which or some combination may include an implementation of a network environment.

[0115] The processor 91 executes various functional applications and data processing by running the computer program stored in the memory 92, such as the joint simulation method of power integrity and signal integrity provided in any of the above embodiments.

[0116] The electronic device 90 can also communicate with one or more external devices 94 (e.g., a keyboard, pointing device, etc.). Such communication can occur via an input / output (I / O) interface 95. Furthermore, the electronic device 90 can communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 96. As shown, the network adapter 96 communicates with other modules of the electronic device 90 via a bus 93. It should be understood that, although not shown, other hardware and / or software modules can be used in conjunction with the electronic device 90, including but not limited to microcode, device drivers, redundant processors, external disk drive arrays, RAID (RAID) systems, tape drives, and data backup storage systems.

[0117] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided and embodied by multiple units / modules.

[0118] Example 4

[0119] An embodiment of the present disclosure further provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the method for jointly simulating power integrity and signal integrity provided in any of the above embodiments is implemented.

[0120] The readable storage medium may include, but is not limited to, a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0121] Example 5

[0122] An embodiment of the present disclosure further provides a computer program product, including a computer program, which, when executed by a processor, implements any of the above-mentioned methods for jointly simulating power integrity and signal integrity.

[0123] The program code for executing the computer program product of the present disclosure may be written in any combination of one or more programming languages, and the program code may be executed entirely on the user device, partially on the user device, as a standalone software package, partially on the user device and partially on a remote device, or entirely on the remote device.

[0124] Example 6

[0125] An embodiment of the present disclosure further provides a chip having a computer program stored thereon, and when the computer program is executed by the chip, any one of the above-mentioned joint simulation methods is implemented.

[0126] Example 7

[0127] An embodiment of the present disclosure further provides a chip module, which is applied to an electronic device and includes a transceiver component and a chip, wherein the chip is used to implement any of the above-mentioned joint simulation methods.

[0128] While specific embodiments of the present disclosure have been described above, those skilled in the art will appreciate that these are merely illustrative and that the scope of protection of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, and such changes and modifications are intended to fall within the scope of protection of the present disclosure.

Claims

1. A joint simulation method for power integrity and signal integrity, characterized in that: The joint simulation method comprises: Acquire a first excitation signal; the first excitation signal is obtained by a first simulation result of a power integrity simulation of the system to be tested according to the second excitation signal; A second simulation result is generated after performing signal integrity simulation on the system to be tested according to the first excitation signal and the second excitation signal.

2. The joint simulation method according to claim 1, characterized in that: The step of obtaining the first excitation signal includes: Inputting the second excitation signal into the power integrity simulation workbench of the system to be tested to perform power integrity simulation and generate the first simulation result; The first simulation result includes at least one of the following: impedance characteristics of the power integrity simulation workbench, power supply ripple, and power supply noise.

3. The joint simulation method according to claim 2, characterized in that: The power integrity simulation workbench includes at least one of the following: a first design module, a voltage regulation module, a first printed circuit board, a first package, and a first redistribution layer; and / or, The power integrity simulation workbench uses S-parameter models.

4. The joint simulation method according to claim 3, characterized in that: The first design module is a netlist, a portion of the netlist that affects power integrity simulation, or a chip power model.

5. The joint simulation method according to claim 1, characterized in that: Generating a second simulation result after performing signal integrity simulation on the system to be tested according to the first excitation signal and the second excitation signal includes: The first excitation signal and the second excitation signal are input into a signal integrity simulation workbench of the system to be tested to perform signal integrity simulation and generate the second simulation result.

6. The joint simulation method according to claim 5, characterized in that: The signal integrity simulation workbench includes at least one of the following: a second design module, a second printed circuit board, a second package, and a second redistribution layer.

7. The joint simulation method according to claim 6, characterized in that: The second design module is a netlist or a portion of the netlist that affects signal integrity simulation.

8. The joint simulation method according to any one of claims 1 to 6, characterized in that: The second simulation result is used to generate a jitter budget, and the jitter budget is used to perform performance evaluation on the system under test; and / or, The system to be tested is a high-speed interface system.

9. A joint simulation system for power integrity and signal integrity, characterized in that: The joint simulation system includes: An acquisition module, configured to acquire a first excitation signal; the first excitation signal is obtained by performing a first simulation result of a power integrity simulation on the system to be tested according to the second excitation signal; The joint simulation module is used to generate a second simulation result after performing signal integrity simulation on the system to be tested according to the first excitation signal and the second excitation signal.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and configured to run on the processor, wherein: When the processor executes the computer program, the power integrity and signal integrity joint simulation method according to any one of claims 1 to 8 is implemented.

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