High fault-tolerant memristor online learning method and system based on cutting strategy
By adopting a cropping strategy in memristor online learning, the performance degradation caused by memristor inconsistency is solved, the learning ability and robustness of neural networks are improved, and the consumption of hardware resources is simplified.
Patent Information
- Application Number
- CN202510578614.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-07
- Publication Date
- 2025-08-15
AI Technical Summary
The performance of memristors in pulsed neural networks is degraded due to the inconsistency between C2C and D2D, which affects the network learning ability and system robustness. The existing fault-tolerant methods consume high resources and are not suitable for online learning.
A high fault-tolerant memristor online learning method adopts a cropping strategy. By building a neural network architecture that supports Trace-STDP learning rules, the memristor conductance characteristics are used to simulate the writing and attenuation of Trace variables, the conductance state is read line by line and compared with the crop threshold, the Trace variables below the threshold are cropped, and the neural network connection weight is adjusted to enhance robustness.
It significantly improves the learning ability and system robustness of the network, reduces the consumption of hardware resources, and improves the accuracy and stability of online learning.
Smart Images
Figure CN120494005A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of artificial intelligence and neuromorphic computing technology, and in particular to a high-fault-tolerant memristor online learning method and system based on a clipping strategy. Background Art
[0002] Memristors, due to their non-volatility, high integration density, and low power consumption, hold broad application prospects in brain-inspired computing, particularly in spiking neural networks (SNNs). However, in actual operation, memristors often exhibit significant non-ideal properties, such as C2C and D2D inconsistencies. These inconsistencies significantly reduce the stability and accuracy of neural network systems, hindering their large-scale deployment. Memristor C2C and device D2D inconsistencies are primarily caused by inherent random physical mechanisms during operation and process variations during manufacturing. C2C inconsistency refers to the time-varying variations in the response of a memristor to the same pulse signal under the same initial state; D2D inconsistency stems primarily from process variations between different devices during manufacturing. These variations include factors such as line edge roughness, oxide layer thickness fluctuations, and the discrete nature of random doping materials. These inconsistencies are inherent to memristors, making them extremely challenging to completely eliminate. However, through precise model development and circuit design optimization, their impact can be managed and mitigated to a certain extent.
[0003] Existing fault-tolerant methods, such as inconsistency-aware retraining and mapping reoptimization, have problems such as high training resource consumption and complex hardware implementation, and are not applicable in online learning scenarios.
[0004] Therefore, there is an urgent need for a method that can effectively enhance the robustness of the system while being hardware resource-friendly. Summary of the Invention
[0005] The purpose of the present invention is to overcome the problems of the above-mentioned prior art and provide a high-fault-tolerant memristor online learning method and system based on a clipping strategy to solve the performance degradation problem caused by the inherent cycle-to-cycle (C2C) and device-to-device (D2D) inconsistency of memristors in spiking neural networks (SNN) online learning applications; and the technical problem that the conductance state of the memristor has obvious randomness in the pulse response, especially in the near-zero interval of the Trace variable, this inconsistency will be amplified, causing serious interference to the weight update, thereby affecting the learning ability of the network and the overall robustness of the system.
[0006] The above objectives are achieved through the following technical solutions:
[0007] A high-fault-tolerant memristor online learning method and system based on a pruning strategy is applied to a spiking neural network based on the Trace-STDP rule, comprising the following steps:
[0008] Step (1) constructing a neural network architecture that supports the Trace-STDP learning rule, including an input layer, an excitation layer, an inhibition layer, and a memristor array for storing trace variables;
[0009] Step (2) performs the physical writing and decay process of the Trace variable based on the adjustable conductivity characteristic of the memristor, including:
[0010] When a neuron pulse occurs, a positive voltage pulse is applied to the target memristor to increase the conductance value, simulating a sudden increase in Trace;
[0011] When the neuron is at rest, negative voltage pulses are applied periodically to slowly decrease the conductance, simulating the exponential decay of Trace;
[0012] Step (3) obtains the conductance state of the memristor array through a row-by-row reading mechanism, converts the conductance value into a Trace variable, and compares it with the clipping threshold; if the Trace value is lower than the clipping threshold, it is clipped to 0, otherwise the original value is retained;
[0013] Step (4) inputs the pruned Trace variable into the weight update module and adjusts the neural network connection weights according to the Trace-STDP learning rule to enhance the system's robustness to the inconsistency between the C2C and D2D of the memristor.
[0014] Furthermore, the clipping threshold is an adjustable parameter with a value range of 0.01 to 1.0. The clipping threshold is dynamically optimized and set according to the classification accuracy performance of the current network under specific variation conditions.
[0015] Furthermore, the optimization of the clipping threshold is achieved by any of the following algorithms:
[0016] Fibonacci search method;
[0017] Quadratic interpolation search method;
[0018] Gaussian process Bayesian optimization algorithm.
[0019] Furthermore, the clipping operation is performed according to the following mathematical expression:
[0020]
[0021] Where x is the Trace value mapped by the memristor read, x th is the preset threshold, x clip It is the trimmed Trace variable.
[0022] Furthermore, the Trace variable is read using row-by-row scanning and ADC digital-to-analog conversion, and non-target rows are grounded to avoid current interference.
[0023] Furthermore, before processing each set of data, a negative voltage pulse is uniformly applied to the memristor array to restore the initial state and clear the residual of the previous round of learning.
[0024] A high-fault-tolerant memristor online learning system based on a trimming strategy, comprising:
[0025] Trace writing module, used to apply positive and negative pulses to the memristor array under neuron pulse events to simulate trace behavior;
[0026] The trace reading module uses line-by-line scanning and ADC digital-to-analog conversion to obtain the current trace value;
[0027] The trace clipping module is equipped with a comparator and a multiplexer to determine and clip traces below a threshold;
[0028] The weight update module performs weight increase and decrease according to the Trace-STDP rule;
[0029] A reset module, used for applying a reset pulse to the memristor array to restore the initial state;
[0030] The threshold optimization module executes the threshold search algorithm according to different inconsistency environments and network status to achieve adaptive parameter adjustment.
[0031] Furthermore, the hardware implementation of the trimming module in the FPGA includes comparators and multiplexer logic, with resource occupancy of 62LUTs and 98FFs, and the total system delay is dominated by the weight update module, and the trimming module does not add additional delay.
[0032] The present invention provides a highly fault-tolerant memristor online learning method and system based on a clipping strategy. By clipping memristor trace values close to zero to zero, this method effectively reduces the impact of inconsistencies on system accuracy in the low-conductance range. This method offers the advantages of simple implementation, significant accuracy improvements, and minimal impact on hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 This is a schematic diagram of the network structure of a high-fault-tolerant memristor online learning method based on a clipping strategy described in the present invention;
[0034] Figure 2 This is a schematic diagram of using positive and negative pulses to simulate the conductance state of a memristor during the write phase in a high-fault-tolerant memristor online learning method based on a clipping strategy according to the present invention;
[0035] Figure 3 This is a schematic diagram of a row-by-row reading strategy in a high-fault-tolerant memristor online learning method based on a clipping strategy according to the present invention;
[0036] Figure 4 A schematic diagram of resetting trace variables in a high-fault-tolerant memristor online learning method based on a clipping strategy according to the present invention;
[0037] Figure 5 The present invention provides a high fault-tolerant memristor online learning method based on a clipping strategy in different σ ab and σ gon Schematic diagram of the relationship between the clipping threshold and network accuracy under certain conditions;
[0038] Figure 6 Schematic diagram of three search algorithms for finding the optimal threshold in a high-fault-tolerant memristor online learning method based on a clipping strategy described in the present invention;
[0039] Figure 7 This is a schematic diagram of the optimal threshold under different network scales in the high fault-tolerant memristor online learning method based on the clipping strategy described in the present invention;
[0040] Figure 8 This is an architectural diagram of a high-fault-tolerant memristor online learning system based on a clipping strategy according to the present invention;
[0041] Figure 9 This is a schematic diagram of a trimming module in a high-fault-tolerant memristor online learning system based on a trimming strategy according to the present invention;
[0042] Figure 10 This is a schematic diagram of the power consumption decomposition of each functional module of the U50 FPGA in the high fault-tolerant memristor online learning system based on the trimming strategy described in the present invention;
[0043] Figure 11 This is a hardware resource occupancy table of the high-fault-tolerant memristor online learning system based on the clipping strategy described in the present invention. DETAILED DESCRIPTION
[0044] The present invention will be further described in detail below with reference to the accompanying drawings and examples. The described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort shall fall within the scope of protection of the present invention.
[0045] This solution provides a highly fault-tolerant memristor online learning method based on a pruning strategy. It is suitable for the application of memristors in spiking neural networks with C2C and D2D inconsistencies. It includes the following steps:
[0046] Step (1) Construct an SNN architecture that supports Trace-STDP learning rules. Use the SIMBRAIN framework to build a network that supports Trace-STDP. The network structure is as follows: Figure 1 As shown, it includes an input layer, an excitation layer, an inhibition layer, and two sets of memristor arrays for storing Trace variables;
[0047] Step (2) performs the physical writing and decay process of the Trace variable based on the adjustable conductivity characteristic of the memristor, including:
[0048] When a neuron pulse occurs, a positive voltage pulse is applied to the target memristor to increase the conductance value, simulating a sudden increase in Trace;
[0049] When the neuron is at rest, periodic application of negative voltage pulses causes the conductance to decrease slowly, simulating the exponential decay of Trace.
[0050] Specifically, the write phase uses positive and negative pulses to simulate the conductance state of the memristor. The positive pulse is used to simulate the sudden increase of Trace, and the negative pulse is used to simulate the exponential decay of the trace variable Trace, such as Figure 2 shown.
[0051] The memristor's write phase uses a "row-by-row write" control strategy. By applying voltage pulses of a specific polarity, a physical mapping of the Trace variable's sudden increase and exponential decay process is achieved:
[0052] Positive pulse: When a neuronal pulse is detected, a positive voltage pulse is applied to the target memristor unit, causing its conductance to increase rapidly, thereby simulating the sudden increase in the trace value when a pulse occurs.
[0053] Negative pulse: During the period when no pulse event is detected, negative voltage pulses are periodically applied to slowly decrease the conductance of the memristor, simulating the exponential decay behavior of the Trace value.
[0054] To ensure that only the rows corresponding to the target neurons are written, a row-by-row gating mode is used to keep the voltage of non-target rows at a safe value below the memristor conduction threshold to avoid erroneous writing.
[0055] To simplify the reading process, SIMBRAIN designed a row-by-row reading strategy (such as Figure 3 (As shown in Figure 2). During each read operation, only the target row receives the read pulse, while all other rows are grounded to prevent current interference and crosstalk. The conductance state of the read memristor is then converted into a digital signal via an analog-to-digital converter (ADC), eliminating the need for additional peripheral circuitry.
[0056] The advantages of this design are: it can significantly reduce the complexity of peripheral circuits; and improve the accuracy and reliability of reading operations.
[0057] In order to maintain the independence between each round of inputs during the continuous learning process, the Trace dynamic mechanism needs to perform a reset operation before processing each set of data. The reset phase restores the state of all memristors to their initial values (such as Figure 4 shown).
[0058] This reset process can effectively clear the residual state left by the previous learning, ensuring that the next round of learning is not interfered with by the previous round, thereby ensuring the stability and accuracy of the online learning process.
[0059] Step (3) obtains the conductance state of the memristor array through a row-by-row reading mechanism, converts the conductance value into a Trace variable, and compares it with the clipping threshold; if the Trace value is lower than the clipping threshold, it is clipped to 0, otherwise the original value is retained;
[0060] Specifically, to perform the Trace trimming operation, the steps are as follows:
[0061] Process each stored Trace value to determine whether it is below the clipping threshold:
[0062] If the Trace value is less than the threshold, it is set to 0;
[0063] Otherwise, keep the original value.
[0064] This cropping operation has low computational complexity and is suitable for online learning scenarios.
[0065] Step (4) inputs the pruned Trace variable into the weight update module and adjusts the neural network connection weights according to the Trace-STDP learning rule to enhance the system's robustness to the inconsistency between the C2C and D2D of the memristor.
[0066] Specifically, to verify the effectiveness of the pruning strategy under different memristor inconsistency conditions, this paper constructs a standard Trace-STDP spiking neural network on the MNIST dataset. The experimental settings are as follows:
[0067] The number of neurons in the processing layer is 400;
[0068] Number of test samples N cnt =50;
[0069] σ ab (characterizing the impact of C2C inconsistency) range: 0.04 to 0.24, σ gon(characterizes the impact of D2D inconsistency) Range: 1 to 25;
[0070] The impact of the optimal pruning threshold on network accuracy under different inconsistency conditions is analyzed separately.
[0071] The experimental results are as follows Figure 5 As shown, it shows the ab and σ gon The relationship between the pruning threshold and network accuracy under the following conditions. The analysis found that:
[0072] At the same level of absolute inconsistency, as the clipping threshold increases, the accuracy shows a trend of first increasing and then decreasing. This phenomenon indicates that a smaller threshold is difficult to effectively suppress inconsistency, while a larger threshold may lead to information loss in the trace variable.
[0073] Regarding the relationship between the magnitude of C2C inconsistency and the optimal pruning threshold, greater inconsistency generally requires stronger pruning. Even with pruning enabled, network accuracy may still decline when C2C inconsistency is large. However, in such high-inconsistency scenarios, the pruning strategy's enhanced robustness to inconsistency is further amplified.
[0074] Specifically, when σ ab = 0.08 and the optimal clipping threshold is 0.1, the clipping strategy can achieve a 1.15% improvement in accuracy; and when σ ab =0.24 and the threshold is 0.5, the accuracy is improved to 11.39%, showing a significant improvement.
[0075] For D2D inconsistency, the enhancement effect of the clipping strategy is similar to the above. However, its optimal clipping threshold is usually concentrated between 0.3 and 0.5, and at a larger σ gon Under these conditions, the robustness improvement brought by the pruning strategy is relatively limited.
[0076] As an optimization of the clipping threshold selection strategy in this embodiment, Figure 6 As shown, in order to obtain the best clipping effect, the threshold needs to be selected and optimized. The present invention provides three search algorithms:
[0077] Fibonacci Search Strategy: suitable for quickly converging to the global optimal solution;
[0078] Quadratic Interpolation Strategy: Applicable to scenarios where the threshold-accuracy curve has a smooth single peak.
[0079] Gaussian Process Strategy: Applicable to multimodal optimization problems and has good generalization performance.
[0080] By adopting the optimal clipping threshold search technique, we designed and performed a series of experiments to compare the effectiveness of three different search strategies. In the experiment, the number of neurons in the excitation layer was set to 400, and the number of test samples N was cnt Set to 50, the search precision dx is set to 0.01. Based on the ideal memristor array, D2D inconsistency is injected, and the inconsistency degree is set to σ gon =10.
[0081] The number of search rounds, the highest accuracy and the corresponding optimal thresholds under the three search strategies are as follows: Figure 6 The optimal thresholds found by the three strategies all fall within the range of 0.3 to 0.4, achieving classification accuracies exceeding 91.5%. This represents an accuracy improvement of over 2.15% compared to the case without the pruning strategy.
[0082] From the comparison results:
[0083] The Fibonacci search method has the fewest optimal and total search rounds during the search process, exhibiting low time complexity and fast convergence. However, this method is best suited for convex functions in a one-dimensional interval and may have difficulty finding the global optimal solution in scenarios with high randomness or unclear patterns.
[0084] The total number of search rounds of the quadratic interpolation search method is similar to that of the FS strategy, but its search performance is significantly affected by the initial threshold setting.
[0085] The Gaussian process search algorithm strikes a balance between known optimal regions and unexplored areas in the search space, reducing the risk of falling into local optima. However, this strategy also significantly slows convergence, making it more suitable for optimizing hyperparameters in high-dimensional networks. This strategy significantly outperforms the previous two methods in total search times, yet still achieves the highest network accuracy.
[0086] The optimal clipping threshold for neural networks of different sizes
[0087] In the experiment, we define the C2C inconsistency σ of the memristor ab Set to 0.1, D2D inconsistency σ gon The effect of different threshold conditions on improving network accuracy was explored in depth, and tests were conducted under different numbers of neurons in the excitation layer.
[0088] like Figure 7As shown in Figure 5, under different network sizes, the optimal pruning threshold is always stably distributed between 0.3 and 0.5, which indicates that the correlation between the optimal threshold and the network size is weak.
[0089] However, in small-scale networks, pruning strategies play a more significant role due to their poor robustness to device inconsistencies:
[0090] When the number of neurons in the excitation layer is 100, the maximum improvement in network accuracy can reach 16.97% after enabling the pruning strategy;
[0091] When the number of neurons increased to 900, the maximum accuracy increased to 4.07%.
[0092] In summary, in memristor-based STDP online learning tasks, whether for inconsistencies of different types and strengths or networks of different sizes, the reasonable introduction of pruning strategies and the selection of appropriate thresholds can significantly enhance the system's inconsistency robustness to varying degrees and effectively improve the overall learning performance.
[0093] In addition, this solution also provides a high-fault-tolerant memristor online learning system based on a trimming strategy, including:
[0094] Trace writing module, used to apply positive and negative pulses to the memristor array under neuron pulse events to simulate trace behavior;
[0095] The trace reading module uses line-by-line scanning and ADC digital-to-analog conversion to obtain the current trace value;
[0096] The trace clipping module is equipped with a comparator and a multiplexer to determine and clip traces below a threshold;
[0097] The weight update module performs weight increase and decrease according to the Trace-STDP rule;
[0098] A reset module, used for applying a reset pulse to the memristor array to restore the initial state;
[0099] The threshold optimization module executes the threshold search algorithm according to different inconsistency environments and network status to achieve adaptive parameter adjustment.
[0100] For the hardware implementation of the trimming module, in order to evaluate the impact of the trimming strategy on the hardware, this solution further deploys it into a neuromorphic accelerator based on FPGA. The system architecture used is as follows: Figure 8 shown.
[0101] In the clipping module, a simple comparator and MUX (multiplexer) logic are introduced to determine whether the Trace value is less than the clipping threshold and select the output. Figure 9 shown.
[0102] To evaluate the hardware performance of weight updates, this design was implemented on an FPGA platform based on a Xilinx Alveo U50 accelerator card. The clock cycle was set to 10 nanoseconds (corresponding to a 100MHz clock frequency), and system hardware resource utilization was categorized by lookup tables (LUTs), flip-flops (FFs), digital signal processors (DSPs), block random access memory (BRAM), and input / output (IO) units. The design architecture was divided into several key functional modules, including an IO control module, a finite state machine (FSM), a clipping module, a weight update module, and a memory control module.
[0103] like Figure 10 As shown in the figure, the power consumption decomposition of each functional module of U50 FPGA is shown. It can be seen that the power consumption of the trimmed module is only 0%.
[0104] like Figure 11 As shown in the figure, the hardware resource usage is displayed. It can be seen that the cropping module occupies nearly 62LUTs and 98FFs.
[0105] In the FPGA system, the trimming module and the weight update module operate in parallel. Because weight update calculations themselves are time-consuming, adding the trimming module does not increase overall system latency. Therefore, the total FPGA-side latency remains the same as the weight update module latency—3.15×10⁻² seconds. This means that the trimming module does not increase hardware latency.
[0106] Hardware simulation shows that the trimming module occupies very little resources in the FPGA and has almost no impact on resource usage, system latency and energy consumption.
[0107] Therefore, the method described in this paper was used to train an SNN model using the Trace-STDP learning rule on the MNIST dataset. During the experiment, varying degrees of C2C and D2D inconsistency were introduced, and the performance of the unpruned and pruned models was compared. The results showed that at the optimal pruned threshold, model accuracy improved by up to 16.7%. The pruned module had virtually no impact on power consumption, resource usage, or system latency, validating the effectiveness and practicality of this method.
[0108] The above description is only for explaining the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.
Claims
1. A high-fault-tolerant memristor online learning method based on a clipping strategy, characterized in that: The application of the spike neural network based on the Trace-STDP rule includes the following steps: Step (1) constructing a neural network architecture that supports the Trace-STDP learning rule, including an input layer, an excitation layer, an inhibition layer, and a memristor array for storing trace variables; Step (2) performs the physical writing and decay process of the Trace variable based on the adjustable conductivity characteristic of the memristor, including: When a neuron pulse occurs, a positive voltage pulse is applied to the target memristor to increase the conductance value, simulating a sudden increase in Trace; When the neuron is at rest, negative voltage pulses are applied periodically to slowly decrease the conductance, simulating the exponential decay of Trace; Step (3) obtains the conductance state of the memristor array through a row-by-row reading mechanism, converts the conductance value into a Trace variable, and compares it with the clipping threshold; if the Trace value is lower than the clipping threshold, it is clipped to 0, otherwise the original value is retained; Step (4) inputs the pruned Trace variable into the weight update module and adjusts the neural network connection weights according to the Trace-STDP learning rule to enhance the system's robustness to the inconsistency between the C2C and D2D of the memristor.
2. The high fault-tolerant memristor online learning method based on a clipping strategy according to claim 1, characterized in that: The clipping threshold is an adjustable parameter with a value range of 0.01 to 1.
0. The clipping threshold is dynamically optimized according to the classification accuracy performance of the current network under specific variation conditions.
3. The high fault-tolerant memristor online learning method based on a clipping strategy according to claim 2, characterized in that: The optimization of the clipping threshold is accomplished by any of the following algorithms: Fibonacci search method; Quadratic interpolation search method; Gaussian process Bayesian optimization algorithm.
4. The high fault-tolerant memristor online learning method based on a clipping strategy according to claim 1, characterized in that: The clipping operation is performed according to the following mathematical expression: Where x is the Trace value mapped by the memristor read, x th is the preset threshold, x clip It is the trimmed Trace variable.
5. The high fault-tolerant memristor online learning method based on a clipping strategy according to claim 1, characterized in that: The Trace variable is read using a row-by-row scanning and ADC digital-to-analog conversion method, and non-target rows are grounded to avoid current interference.
6. The high fault-tolerant memristor online learning method and system based on a trimming strategy according to claim 1, characterized in that: Before processing each set of data, a negative voltage pulse is uniformly applied to the memristor array to restore the initial state and clear the residual of the previous round of learning.
7. The high fault-tolerant memristor online learning system based on a trimming strategy according to claim 1, characterized in that: include: Trace writing module, used to apply positive and negative pulses to the memristor array under neuron pulse events to simulate trace behavior; The trace reading module uses line-by-line scanning and ADC digital-to-analog conversion to obtain the current trace value; The trace clipping module is equipped with a comparator and a multiplexer to determine and clip traces below a threshold; The weight update module performs weight increase and decrease according to the Trace-STDP rule; A reset module, used for applying a reset pulse to the memristor array to restore the initial state; The threshold optimization module executes the threshold search algorithm according to different inconsistency environments and network status to achieve adaptive parameter adjustment.
8. The high fault-tolerant memristor online learning method and system based on a trimming strategy according to claim 1, characterized in that: The hardware implementation of the trimming module in FPGA includes comparators and multiplexer logic, with resource usage of 62LUTs and 98FFs. The total system delay is dominated by the weight update module, and the trimming module does not add additional delay.