Defect detection method, device and system based on ZYNQ and Jetson hierarchical collaboration

Abstract

The invention discloses a defect detection method, device and system based on ZYNQ and Jetson hierarchical collaboration, and the method comprises the steps: a ZYNQ processor receives a surface image of a to-be-detected object sent by a linear array camera, carries out the preprocessing of the surface image to extract a Blob region image, and transmits the Blob region image to a Jetson processor; the Jetson processor performs defect marking on the Blob area image to obtain defect marking information, and returns the defect marking information to the ZYNQ processor; the ZYNQ processor screens the Blob area images according to the defect marking information to obtain the Blob area images with the defects, and the Blob area images with the defects are sent to the upper computer; and the upper computer performs target detection on the Blob area image with the defect to obtain the defect type and position. The ZYNQ processor and the Jetson processor are integrated in the same defect detection module to realize hierarchical collaboration, a traditional PCIe scheme is replaced, the development complexity and the system cost are remarkably reduced, and the system is efficient and reliable.

Description

Technical Field

[0001] The present invention relates to the field of defect detection technology, and in particular to a defect detection method, device and system based on ZYNQ and Jetson layered collaboration. Background Art

[0002] Machine vision uses cameras to capture images and combines them with image processing algorithms to detect targets and identify defects. It is widely used for surface defect detection on large-format materials. Machine vision systems utilize machine vision products to convert captured large-format material surfaces into image signals and transmit them to dedicated image processing systems. The image processing systems perform correlation operations on the image data based on pixel grayscale values and their distribution, extracting target features and generating corresponding defect detection results to monitor the surface condition of large-format materials in real time.

[0003] However, for surface inspection and defect identification of large-format materials, current defect detection equipment typically utilizes a "line scan camera + data acquisition card + industrial computer + GPU (Central Processing Unit)" architecture. This complex architecture requires each line scan camera to be equipped with a separate data acquisition card and industrial computer, and each industrial computer requires a GPU for data processing, resulting in high hardware costs. The number of industrial computers and data acquisition cards that can be installed is limited, and multiple line scan cameras require multiple industrial computers, increasing system complexity. Furthermore, maintaining too many data acquisition cards can be challenging, leading to poor reliability.

[0004] In recent years, some embedded solutions have attempted to simplify the system through the ARM+NPU architecture, but its camera interface support is limited, making it difficult to adapt to a variety of line scan cameras. In addition, the NPU requires a dedicated model format, which makes model deployment and updating complex, and its computing power cannot meet the real-time processing needs of multiple cameras. In addition, some solutions use the FPGA+Jetson architecture, parsing images through the FPGA and transmitting them to the Jetson for inspection, but there are still shortcomings: on the one hand, the FPGA requires complex protocol development to transmit data through the PCIe interface, and the Jetson needs to take on the entire inspection task (including preprocessing and inference). The heavy computational load makes it difficult to meet the real-time requirements of high-speed cameras (such as 8K resolution and 100KHz line frequency); on the other hand, Jetson usually has only one Gigabit network port, and network communication relies on CPU processing. When Jetson performs deep learning inference, CPU resources are tight, data transmission efficiency is limited, and data backlogs are easily caused.

[0005] Therefore, there is an urgent need for an efficient, cost-effective and easy-to-deploy defect detection solution to address the shortcomings of existing technologies in real-time, system complexity and multi-camera collaboration. Summary of the Invention

[0006] The main purpose of the present invention is to propose a defect detection method, device and system based on ZYNQ and Jetson layered collaboration to solve the problems of high cost and poor reliability of existing defect detection equipment when detecting surface defects of objects.

[0007] To achieve the above objectives, the present invention proposes a defect detection method based on ZYNQ and Jetson layered collaboration, the defect detection method based on ZYNQ and Jetson layered collaboration comprising:

[0008] The ZYNQ processor receives the surface image of the object to be measured sent by the linear array camera, pre-processes the surface image to extract the blob area image, and transmits the image to the Jetson processor;

[0009] The Jetson processor performs defect marking on the Blob area image to obtain defect marking information, and returns the defect marking information to the ZYNQ processor;

[0010] The ZYNQ processor filters the Blob area image according to the defect marking information to obtain a Blob area image with defects, and sends the Blob area image with defects to the host computer;

[0011] The host computer performs target detection on the Blob area image with defects to obtain the defect type and location;

[0012] The ZYNQ processor and the Jetson processor are integrated into the same defect detection module through a layered collaborative architecture.

[0013] In some embodiments, pre-processing the surface image to extract a blob area image includes:

[0014] Performing equal-area segmentation on the surface image to obtain multiple blob region images with the same area; or,

[0015] Extracting suspected defects from the surface image to obtain a suspected defect region image, and determining whether an image area of the suspected defect region image is larger than a preset image area;

[0016] If the image area of the suspected defect region image is larger than the preset image area, the suspected defect region image is divided into equal preset image areas to obtain multiple Blob region images with the same area as the preset image;

[0017] If the image area of the suspected defect region image is smaller than or equal to the preset image area, the image area is expanded with the suspected defect region image as the center to obtain a Blob region image with the same area as the preset image.

[0018] In some embodiments, the ZYNQ processor transmits the blob area image to the Jetson processor via a high-speed serial interface, wherein the high-speed serial interface is a MIPI CSI-2 interface.

[0019] In some embodiments, the layered collaborative architecture adopts a dual-channel communication mechanism, and the dual-channel communication mechanism includes:

[0020] The image data channel uses the MIPI CSI-2 interface to achieve high-speed image transmission from the ZYNQ processor to the Jetson processor through the GTX high-speed transceiver, and encapsulates the Blob image data at the protocol layer;

[0021] Control the data channel, using a gigabit network interface and UDP protocol to transmit defect marking information between the ZYNQ processor and the Jetson processor;

[0022] The sequence number synchronization mechanism uses the ZYNQ processor to periodically send the starting sequence number and the Jetson processor to automatically increment the Blob sequence number based on the MIPI frame synchronization signal.

[0023] In some embodiments, the Jetson processor uses a network port switching mechanism to time-share multiplex a single network interface to communicate with the ZYNQ processor and the host computer respectively.

[0024] In some embodiments, the defect marking information includes:

[0025] The classification result of whether the defect exists, the defect confidence level, and the blob number.

[0026] In some embodiments, before transmitting the Blob area image to the Jetson processor, the ZYNQ processor first stores the Blob area image in the DDR cache, and after receiving the defect marking information, extracts the corresponding Blob area image with defects from the DDR cache according to the Blob sequence number in the defect marking information and sends it to the host computer; or,

[0027] The ZYNQ processor sends the surface image to a host computer.

[0028] In some embodiments, the host computer performs target detection on the defective Blob area image to obtain the defect type and location, including:

[0029] The host computer processes the defective Blob area image to identify the defect, and identifies the defect area and category through image segmentation and target detection based on deep learning.

[0030] The present invention also proposes a defect detection device based on ZYNQ and Jetson layered collaboration, comprising:

[0031] A ZYNQ processor is configured to receive a surface image of the object to be measured sent by the line array camera, pre-process the surface image to extract a blob area image, and transmit the image to the Jetson processor; and

[0032] The Jetson processor is configured to perform defect marking on the Blob area image to obtain defect marking information, and return the defect marking information to the ZYNQ processor;

[0033] A communication interface configured to send the defective Blob area image screened by the ZYNQ processor to a host computer;

[0034] a memory in communication with the ZYNQ processor and a memory in communication with the Jetson processor;

[0035] The memory stores instructions executed by the ZYNQ processor, and the instructions are executed by the ZYNQ processor to enable the ZYNQ processor to perform any one of the above-mentioned defect detection methods based on ZYNQ and Jetson layered collaboration;

[0036] The ZYNQ processor and the Jetson processor are integrated into the same defect detection module through a layered collaborative architecture.

[0037] The present invention also proposes a defect detection system based on ZYNQ and Jetson layered collaboration, comprising:

[0038] Multiple line scan cameras, multiple defect detection modules, and a host computer, wherein the defect detection modules include a ZYNQ processor and a Jetson processor;

[0039] The plurality of line array cameras respectively capture corresponding areas of the surface image of the large-format object and transmit the images to the corresponding ZYNQ processors;

[0040] The multiple ZYNQ processors are the ZYNQ processors described above, configured to process surface images sent by multiple line array cameras in parallel, pre-process the surface images to extract blob area images, and transmit the images to corresponding Jetson processors;

[0041] The multiple Jetson processors are configured to collaboratively perform defect marking on the Blob area image to obtain defect marking information, and return the defect marking information to the corresponding ZYNQ processor;

[0042] The multiple ZYNQ processors are further configured to screen the Blob area images to obtain Blob area images with defects, and send the Blob area images with defects to a host computer;

[0043] The host computer is configured to perform target detection on the defective Blob area image to obtain the defect type and location;

[0044] The ZYNQ processor and Jetson processor in each defect detection module realize defect detection through layered collaboration;

[0045] The multiple defect detection modules are aggregated and connected to a host computer via Ethernet and a switch.

[0046] In some embodiments, an Ethernet switching unit is further included, wherein the Ethernet switching unit includes a first gigabit network port, a second gigabit network port, and a third gigabit network port;

[0047] The first gigabit network port is used to communicate with the host computer, the second gigabit network port is used to connect to the ZYNQ processor, and the third gigabit network port is used to connect to the Jetson processor;

[0048] The ZYNQ processor enables the Jetson processor to communicate with the ZYNQ processor or communicate with the host computer in a time-division multiplexing manner through an Ethernet switching unit;

[0049] The Ethernet switching unit is implemented by an analog switch to implement the above-mentioned network port switching mechanism.

[0050] In some embodiments, the network port switching mechanism includes:

[0051] In the detection mode, the PHY chip of the Jetson processor is connected to the PHY chip of the ZYNQ processor via the analog switch to transmit defect marking information;

[0052] Configuration mode: the Jetson processor is connected to the RJ45 network port and communicates with the host computer through the analog switch to update the model and parameters;

[0053] Switching control: the ZYNQ processor controls the analog switch to shut down data transmission before switching.

[0054] The present invention uses the ZYNQ processor to preprocess the image, and the Jetson processor to mark the defects of the preprocessed image. The ZYNQ processor only sends the images with defect marks to the host computer, so that the host computer only needs to process the images with defect marks, which reduces the workload of the host computer. Only one host computer is needed to complete the detection, thereby reducing the cost. In addition, the ZYNQ processor and the Jetson processor are used to process the image in a layered collaborative manner, avoiding the use of an acquisition card and improving the reliability of the equipment. The ZYNQ processor and the Jetson processor are integrated into the defect detection module, and the performance is further improved by optimizing the task allocation through layered collaboration and combining the following key technical features: MIPI The CSI-2 interface enables high-speed image transmission between ZYNQ and Jetson, replacing complex PCIe development solutions and reducing system costs. The dual-channel communication mechanism separates image data and control information, and improves transmission efficiency and reliability through the gigabit network interface and UDP protocol. The sequence number synchronization mechanism ensures data consistency based on the MIPI frame synchronization signal, solving the problem of data misalignment in high-speed scenarios. The network port switching mechanism uses a single network port for time-sharing multiplexing, combined with an Ethernet switching unit (preferably an analog switch) to reduce hardware costs and support multi-mode communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Schematic diagram of the process of a defect detection method based on ZYNQ and Jetson layered collaboration in an embodiment of the present invention;

[0056] Figure 2 This is a data flow diagram of a defect detection method based on ZYNQ and Jetson layered collaboration in an embodiment of the present invention;

[0057] Figure 3 2 is another flow chart of a defect detection method based on ZYNQ and Jetson layered collaboration in an embodiment of the present invention;

[0058] Figure 4 2 is another flow chart of a defect detection method based on ZYNQ and Jetson layered collaboration in an embodiment of the present invention;

[0059] Figure 5 This is a data flow graph for extracting the Blob area of a ZYNQ processor according to an embodiment of the present invention;

[0060] Figure 6 Schematic diagram of the structure of a defect detection device based on ZYNQ and Jetson layered collaboration in an embodiment of the present invention;

[0061] Figure 7 2 is another structural diagram of a defect detection device based on ZYNQ and Jetson layered collaboration in an embodiment of the present invention;

[0062] Figure 8 Schematic diagram of the structure of a defect detection system based on ZYNQ and Jetson layered collaboration in an embodiment of the present invention;

[0063] Figure 9 Schematic diagram of the network port switching mechanism in an embodiment of the present invention.

[0064] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0065] The following will be combined with the accompanying drawings to clearly and completely describe the solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0066] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0067] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element.

[0068] In addition, the descriptions of "first", "second", etc. in the present invention are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0069] To achieve the above objectives, the present invention proposes a defect detection method based on ZYNQ and Jetson layered collaboration, including:

[0070] Step S110: The ZYNQ processor receives the surface image of the object to be measured sent by the linear array camera, pre-processes the surface image to extract the blob area image, and transmits it to the Jetson processor;

[0071] Step S120: The Jetson processor performs defect marking on the Blob area image to obtain defect marking information, and returns the defect marking information to the ZYNQ processor;

[0072] Step S130: the ZYNQ processor filters the Blob region image according to the defect marking information to obtain the Blob region image with defects, and sends the Blob region image with defects to the host computer;

[0073] Step S140: The host computer performs target detection on the Blob area image with defects to obtain the defect type and location;

[0074] Among them, the ZYNQ processor and Jetson processor are integrated into the same defect detection module through a layered collaborative architecture.

[0075] In this embodiment, referring to Figure 1 and Figure 2 The defect detection method based on ZYNQ and Jetson layered collaboration is applied to a defect detection system based on ZYNQ and Jetson layered collaboration; the defect detection system based on ZYNQ and Jetson layered collaboration is used to detect the surface of the object to be tested to detect whether there are defects on the surface of the object to be tested.

[0076] The defect detection system based on the layered collaboration of ZYNQ and Jetson includes a line scan camera, a ZYNQ processor, a Jetson processor and a host computer. Multiple line scan cameras, ZYNQ processors and Jetson processors are configured. Among them, a ZYNQ processor and a Jetson processor are integrated into a defect detection module. Each detection module is connected to an 8K line scan camera or two 4K line scan cameras. Multiple groups of line scan cameras and detection modules work in parallel to cover the detection area of the object to be tested.

[0077] It is understood that the object to be measured is a large-format object, such as photovoltaic glass, lithium battery separators, cloth, coiled materials, and other objects with large surface areas. Due to the large surface area of the object to be measured, a single line scan camera cannot fully capture the entire width of the surface. In this case, multiple line scan cameras are required to capture the entire width of the surface. The object to be measured can be placed on a conveyor belt, and the line scan camera is fixed above the conveyor belt to capture the entire width of the surface. The line scan camera captures the entire length of the surface of the object to be measured every time the object moves a certain distance.

[0078] ZYNQ and Jetson work together in layers to pre-process and mark defects in surface images taken by line array cameras to filter out images with defect marks. Only images with defect marks are then sent to the host computer, allowing the host computer to directly process the images with defect marks, thereby reducing the workload of the host computer, lowering costs, and improving real-time performance and detection efficiency.

[0079] When the surface of an object to be tested needs to be inspected, a detection instruction can be sent to the ZYNQ processor via the host computer. When the ZYNQ processor receives the detection instruction, it can control the line scan camera to start capturing the surface image of the object to be tested according to the detection instruction. After the line scan camera captures the surface image, it can send the surface image to the ZYNQ processor. The line scan camera can be connected to the ZYNQ processor via the CXP-6 (CoaXPress-6) interface or the 10G GigE (10Gigabit Ethernet) interface to achieve high-speed image data transmission.

[0080] After the line scan camera sends the surface image to the ZYNQ processor, the ZYNQ processor can receive the surface image of the object to be measured sent by the line scan camera. The ZYNQ processor receives the surface image input by the line scan camera at 8K resolution and 100KHz line frequency.

[0081] After receiving the surface image, the ZYNQ processor preprocesses it to generate preprocessed image data. This preprocessing can include image enhancement, image noise reduction filtering, morphological processing, and blob (connected region) extraction. Preprocessing aims to reduce the data volume and highlight the characteristics of areas with potential defects, providing a foundation for subsequent analysis.

[0082] After the ZYNQ processor completes preprocessing, it performs blob extraction on the image. Blob extraction identifies connected regions with similar features (such as color, grayscale, and texture) within the image. Blob extraction is performed on the image based on a preset extraction strategy, resulting in multiple fixed-size blob region images. This extraction can use equal-area segmentation or adaptive segmentation based on suspected defect regions to ensure that the extracted regions contain complete potential defect information.

[0083] The Zynq processor transmits the extracted blob area images to the Jetson processor via a high-speed serial interface. The Jetson processor uses a lightweight deep learning model to quickly classify these areas to determine whether there are defects. If defects are present, they are marked, generating defect marking information and returning it to the Zynq processor.

[0084] Based on the received defect marking information, the ZYNQ processor can filter out defective blob area images and send only this data to the host computer, avoiding the transmission and processing of large numbers of defect-free blob area images, significantly reducing network bandwidth usage and the host computer's computing load. After receiving the defective blob area images, the host computer executes a more complex target detection algorithm to accurately identify the defect type and location and generate a complete inspection and analysis report.

[0085] The ZYNQ processor and the Jetson processor work together in layers to pre-process and mark defects on the surface image, and then only send the image of the blob area with defects to the host computer, so that the host computer can directly identify the image of the blob area with defects.

[0086] Reference Figure 2 The line scan camera and ZYNQ processor will first perform image acquisition and preprocessing: the line scan camera first acquires the image to obtain an image, and then sends the image to the ZYNQ processor; the ZYNQ processor performs image preprocessing and blob extraction on the image to obtain a blob image. The ZYNQ processor and Jetson processor then perform intelligent classification and recognition: the ZYNQ processor first sends the blob image to the Jetson processor; the Jetson processor processes the blob image based on deep learning and fast classification to obtain defect labeling information (defect serial number and confidence level), and then sends the defect serial number and confidence level back to the ZYNQ processor. Finally, the ZYNQ processor and the host computer will perform a precise analysis and processing phase: the ZYNQ processor extracts the blob image based on the defect serial number and confidence level to obtain multiple defect images, and generates defect image data from these multiple defect images. This defect image data is then sent to the host computer; the host computer performs target detection analysis on the defect image data and generates an inspection report showing the defect category and location.

[0087] In this embodiment, the ZYNQ processor preprocesses the image, and the Jetson processor marks defects on the preprocessed image. The ZYNQ processor only sends the images with defect marks to the host computer, so that the host computer only needs to process the images with defect marks, which reduces the workload of the host computer. Only one host computer is needed to complete the inspection, thereby reducing costs. In addition, the ZYNQ processor and the Jetson processor are used to process the image in a layered collaborative manner, which avoids the use of an acquisition card and improves the reliability of the equipment.

[0088] In some embodiments, the aforementioned pre-processing of the surface image to extract the blob area image includes:

[0089] The surface image is segmented into equal areas to obtain multiple blob region images with the same area.

[0090] In this embodiment, when the ZYNQ processor preprocesses the surface image to extract blob region images, it performs equal-area segmentation on the surface image. The area size in the equal-area segmentation can be customized; in an image, the area size can be represented by pixels, for example, setting the area size to 256×256 pixels. The surface image is segmented into fixed-size 256×256 pixels, thereby generating multiple blob region images.

[0091] During the segmentation process, a certain overlap area can be retained between adjacent blob region images to effectively avoid the problem of missed detection caused by defect segmentation. For example, adjacent blob region images can retain a 25% overlap area.

[0092] In some embodiments, the aforementioned pre-processing of the surface image to extract the blob area image includes:

[0093] Step S210, extracting suspected defects from the surface image to obtain a suspected defect region image, and determining whether the image area of the suspected defect region image is larger than a preset image area;

[0094] Step S220 , if the image area of the suspected defect region image is larger than the preset image area, the suspected defect region image is divided into equal parts with the preset image area to obtain a plurality of blob region images with the same area as the preset image area;

[0095] Step S230 : If the image area of the suspected defect region image is smaller than or equal to the preset image area, the image area is expanded with the suspected defect region image as the center to obtain a Blob region image with the same area as the preset image.

[0096] In this embodiment, referring to Figure 3 When the ZYNQ processor performs pre-processing on the surface image to extract the Blob area image, it first identifies the suspected defect area image and then segments it. The ZYNQ processor first extracts the suspected defects from the surface image to obtain the suspected defect area image. There may be multiple suspected defect area images, or there may be none; but when the ZYNQ processor works for a long time and processes a large number of surface images, there will be multiple suspected defect area images. After the suspected defect area image is identified, the image area of the suspected defect area image is determined, and then the image area is compared with the preset image area to select different processing methods. The image area can be represented by pixels. For example, the preset image area can be set to 256×256 pixels.

[0097] If the image area of the suspected defect region image is larger than 256×256 pixels, the suspected defect region image can be segmented into 256×256 pixel segments, and the suspected defect region image can be segmented into multiple 256×256 pixel Blob region images, thereby obtaining multiple Blob region images.

[0098] If the image area of the suspected defect region image is less than or equal to 256×256 pixels, the region will be expanded with the suspected defect region image as the center, and then a 256×256 pixel Blob region image will be segmented.

[0099] In another embodiment, extracting suspected defects from the surface image to obtain a suspected defect area image includes:

[0100] Step S310, performing image enhancement processing on the surface image to obtain enhanced image data;

[0101] Step S320, filtering the enhanced image data to obtain filtered image data;

[0102] Step S330, performing edge detection on the filtered image data according to a preset operator to obtain binary edge image data;

[0103] Step S340 , performing morphological processing on the binary edge image data to obtain a plurality of suspected defect area images.

[0104] In this embodiment, referring to Figure 4 When the ZYNQ processor extracts suspected defects from a surface image to obtain an image of the suspected defect area, it first processes the surface image and then extracts it. The ZYNQ processor first performs image enhancement on the surface image to improve image quality and edge feature visibility. Image enhancement can be performed using spatial domain methods (such as grayscale transformation and histogram equalization) or frequency domain methods (such as high-pass filtering, low-pass filtering, and wavelet transform). After the ZYNQ processor performs image enhancement on the surface image, it can obtain enhanced image data.

[0105] The ZYNQ processor will perform filtering on the enhanced image data. The filtering process may include Gaussian filtering or median filtering. The ZYNQ processor first uses a 3×3 operator to perform Gaussian filtering (σ=0.8) or median filtering on the enhanced image data to obtain filtered image data.

[0106] The ZYNQ processor first applies a Sobel filter to the image to obtain binary edge image data, then performs morphological dilation and erosion. This allows the processor to identify suspected defect regions within the binary edge image data. There may or may not be multiple suspected defect region images; however, when the ZYNQ processor processes a large number of surface images over a long period of time, multiple suspected defect region images will be generated.

[0107] In some embodiments, the ZYNQ processor transmits the blob area image to the Jetson processor via a high-speed serial interface, wherein the high-speed serial interface is a MIPI CSI-2 interface.

[0108] In this embodiment, the ZYNQ processor transmits the blob area image to the Jetson processor through a high-speed serial interface. The high-speed serial interface adopts the MIPI CSI-2 interface. The ZYNQ processor uses the GTX high-speed transceiver to send image data, and the Jetson processor receives the image data through the standard MIPI CSI-2 interface, supporting the bandwidth requirements of 8K resolution and 100KHz line frequency.

[0109] The ZYNQ processor converts the linear data stream of the aforementioned blob area image into a standard MIPI video frame format. Specifically, a dual-port RAM is configured to implement row data caching, maintaining a circular buffer of at least 2048 rows, and employing a ping-pong cache mechanism to prevent data conflicts. For example, using the ping-pong cache mechanism, the ZYNQ processor writes the linear data of the blob area image row by row into one buffer of the dual-port RAM, while simultaneously reading data from the other buffer and organizing it into a video frame format. When one buffer is full, it switches to writing to the other buffer while simultaneously reading data from the filled buffer, ensuring data flow continuity and real-time performance. The 8K×1024 pixels are organized into a standard frame format, generating frame synchronization signals compliant with the MIPI CSI-2 protocol, including VSYNC (frame synchronization signal), HSYNC (line synchronization signal), and PCLK (pixel clock signal). The VSYNC signal marks the start and end of a frame, the HSYNC signal marks the start and end of each row, and the PCLK signal provides clock synchronization for each pixel. Data transmission uses 4-channel MIPID-PHY with a rate of 5Gbps per channel, which is implemented through the GTX transceiver of the ZYNQ processor to ensure the stability and reliability of high-speed data transmission.

[0110] The Jetson processor receives blob region images via a standard MIPI CSI-2 driver. The driver parses the MIPI CSI-2 protocol packets, automatically unpacks the image data, and efficiently transfers the data to a memory buffer using DMA (Direct Memory Access), reducing CPU resource usage. The Jetson processor's application layer accesses image data via a standard V4L2 (Video for Linux 2) interface, supporting zero-copy operations to avoid duplicate data and improve processing efficiency.

[0111] Because the Zynq processor converts the blob area image into a standard MIPI video frame format before transmission, the Jetson processor can directly parse it into video frames upon receiving it, without the need for additional data format conversion. The Jetson processor's operating system reconstructs the 8K×1024 image via VSYNC (frame synchronization signal) and manages it through a frame buffer queue to ensure the integrity and sequentiality of the image data. In addition, the V4L2 interface allows the application layer to flexibly control the frame rate based on actual needs, such as by setting a frame interval or frame skipping to achieve frame rate adjustment, enhancing the system's adaptability in high-speed industrial visual inspection scenarios.

[0112] The MIPI CSI-2 interface used to transmit blob area images between the Zynq processor and the Jetson processor in this embodiment offers advantages over the PCIe interface transmission solutions of other similar modules, including simple hardware and software implementation, high reliability, superior performance, and easy maintenance. This eliminates the need for complex driver development and fully utilizes the mature MIPI interface, significantly reducing system development difficulty and maintenance costs. This is particularly suitable for high-speed industrial visual inspection scenarios, providing an efficient and reliable data transmission solution for the system.

[0113] In some embodiments, the layered collaborative architecture employs a dual-channel communication mechanism, which includes:

[0114] The image data channel uses the MIPI CSI-2 interface to achieve high-speed image transmission from the ZYNQ processor to the Jetson processor through the GTX high-speed transceiver, and encapsulates the Blob image data at the protocol layer;

[0115] Control the data channel, using a gigabit network interface and UDP protocol to transmit defect marking information between the ZYNQ processor and the Jetson processor;

[0116] The sequence number synchronization mechanism uses the ZYNQ processor to periodically send the starting sequence number and the Jetson processor to automatically increment the Blob sequence number based on the MIPI frame synchronization signal.

[0117] In this embodiment, referring to Figure 5,The layered collaborative architecture adopts a dual-channel communication mechanism, which includes an image data channel and a control data channel. Figure 5 As shown in the figure, the ZYNQ processor transmits the blob area image to the Jetson processor through the MIPI CSI-2 interface, and the Jetson processor returns the defect marking information to the ZYNQ processor through the network interface, realizing efficient and reliable communication between heterogeneous processors.

[0118] Specifically, the image data channel uses the MIPI CSI-2 standard interface, implemented based on the Zynq processor's GTX high-speed transceiver, for high-bandwidth image data transmission;

[0119] The control data channel uses a gigabit network interface and is implemented based on the UDP protocol to transmit defect marking information. After the Zynq processor parses this information, it extracts the corresponding image data from the DDR buffer only when the classification result is 1 and the confidence level is above a set threshold. The dual-channel design effectively prevents interference between image and control data.

[0120] The defect marking information, as shown in Table 1, includes a 4-byte Blob number, a 1-byte classification result (0 indicates no defect, 1 indicates a defect), and a 4-byte confidence level (expressed as a floating point number).

[0121] Table 1: Defect Marking Information Field Description

[0122]

[0123] The workflow of the dual-channel communication mechanism includes the following three stages:

[0124] Initialization synchronization phase: The ZYNQ processor sends a network data packet containing a 4-byte blob start sequence number and an 8-byte timestamp. After the Jetson processor receives and confirms the sequence number, it starts image data transmission.

[0125] During normal operation, the ZYNQ processor sends image data through the MIPI interface. The Jetson processor detects the VSYNC (frame synchronization signal) of the MIPI data stream to identify image boundaries. The received VSYNC signal triggers the incrementing of the Blob number count, performs fast defect classification processing, and returns defect marking information containing the Blob number, defect detection results, and confidence level. After receiving the information, the ZYNQ processor verifies whether the received Blob number matches the sent Blob number. This method can effectively solve the problem of Blob image data misalignment.

[0126] Serial number reset phase: When the Jetson processor serial number count reaches 8191, it sends a notification to the ZYNQ processor to wait for a new serial number. The ZYNQ processor sends a new starting serial number, and the Jetson processor confirms it and continues to work normally.

[0127] The present invention adopts the MIPI CSI-2 interface to transmit image data and transmits sequence numbers and detection results through the network interface, thus realizing efficient and reliable communication between heterogeneous processors.

[0128] To ensure communication reliability, the dual-channel communication mechanism implements multiple protection measures. UDP data packets, as shown in Table 2, contain a 2-byte header, a data segment with defect marking information or timestamp, and a 2-byte CRC checksum. The system sets a 10ms response timeout, with a maximum of three retransmissions. After exceeding this time, the abnormality recovery process is initiated. In terms of sequence number synchronization, a 32-bit unsigned integer is used as the sequence number, ranging from 0 to 8191 and used cyclically. Synchronization is performed during system initialization, after every 8192 blobs, and when an abnormality is detected. In the case of communication anomalies, the system triggers data retransmission by detecting response timeouts and reinitializes when necessary; in the case of sequence number anomalies, resynchronization is triggered by detecting sequence number discontinuity.

[0129] Table 2: UDP packet structure

[0130] Field Name Byte length Data Type Field Description Baotou 2 Unsigned short integer Packet Identifier Data segment variable Mixed Type Defect marking information, or timestamp Checksum 2 Unsigned short integer CRC check

[0131] The dual-channel communication mechanism of this embodiment ensures the efficiency and reliability of communication between heterogeneous processors by separating image data and control data transmission, using standard interfaces and lightweight protocols, and implementing a custom retransmission mechanism, providing technical support for the stable operation of the system.

[0132] In this embodiment, a lightweight deep learning classification model optimized for edge computing is configured on the Jetson processor. The image is fed into the deep learning classification model to obtain classification results and generate defect labeling information. The deep learning classification model uses a lightweight network structure suitable for edge computing, such as MobileNetV2. The input layer is configured as 256×256×1, matching the blob extraction size. The output layer provides a binary classification result of whether the defect exists and the confidence level.

[0133] The deep learning classification model is trained using sample blob area images as input and the corresponding defect annotations as sample labels. To increase inference speed, the system uses the optimized inference engine TensorRT for acceleration, achieving model quantization to improve processing efficiency. By optimizing the network structure and inference parameter configuration, the system achieves inference latency that meets the real-time requirements of online detection.

[0134] After the Jetson processor completes defect detection, it returns the defect marking information to the ZYNQ processor through the network interface. The ZYNQ processor filters out the image data with defects based on the Blob sequence number and classification results in the defect marking information, and further processes it or sends it to the host computer.

[0135] In some embodiments, the Jetson processor uses a network port switching mechanism to time-share a single network interface to communicate with the ZYNQ processor and the host computer respectively.

[0136] In this embodiment, the network port switching mechanism implements time-sharing multiplexing of the Jetson processor network port, solving the problem that the Jetson processor needs to communicate with the Zynq processor and the host computer at the same time but has only one network interface. The network port switching mechanism includes the following two working modes:

[0137] Detection mode: The analog switch directly connects the Jetson processor's PHY chip to the Zynq processor's PHY chip, forming a point-to-point communication channel. The Jetson processor receives blob image data sent by the Zynq processor and returns defect marking information.

[0138] Configuration mode: The analog switch connects the Jetson processor's PHY chip to the RJ45 network port, establishing communication with the host computer through the 10G switch for updating deep learning models and system parameter configurations.

[0139] The Zynq processor controls the mode switching process. Before the switch, the Zynq processor sends a switch notification to the Jetson processor via a control channel. Both parties suspend data transmission and disable the retransmission mechanism. After the switch is complete, the PHY chip re-negotiates and re-establishes the network connection, then resumes data transmission.

[0140] In some embodiments, before transmitting the Blob area image to the Jetson processor, the ZYNQ processor first stores the Blob area image in the DDR cache, and after receiving the defect marking information, extracts the corresponding Blob area image with defects from the DDR cache according to the Blob sequence number in the defect marking information and sends it to the host computer; or,

[0141] The ZYNQ processor sends the surface image to the host computer.

[0142] In this embodiment, the ZYNQ processor stores the blob image data in the DDR cache before transmitting it to the Jetson processor. Each blob is assigned a unique serial number. Upon receiving the defect marking information returned by the Jetson processor, the ZYNQ processor identifies the defective image area based on the blob serial number in the defect marking information, extracts the blob image data corresponding to the blob serial number from the DDR cache, and sends this defect image data to the host computer.

[0143] Specifically, the Zynq processor can operate in two modes depending on the system configuration: Screening mode sends only image data marked with defects to the host computer, significantly reducing data transmission; and Full mode sends all acquired image data directly to the host computer without filtering, making it suitable for scenarios requiring comprehensive recording or debugging analysis. The system can switch between these two modes based on actual application needs.

[0144] In some embodiments, the defect marking information includes:

[0145] The classification result of whether the defect exists, the defect confidence level, and the blob number.

[0146] In this embodiment, defect marking information includes the blob sequence number, defect classification result, and confidence level. In screening mode, the Zynq processor receives the defect confidence threshold transmitted by the host computer and selects blob sequence numbers marked as "defective" that meet the confidence level requirement. Based on these sequence numbers, the processor then accurately extracts the corresponding blob image data from the DDR cache. This cache- and sequence number-based screening mechanism avoids the transmission of large numbers of defect-free images to the host computer, significantly reducing network bandwidth usage.

[0147] In some embodiments, the host computer performs target detection on the defective blob area image to obtain the defect type and location, including:

[0148] The host computer processes the defective blob area image to identify the defects, and identifies the defect area and category through image segmentation and target detection based on deep learning.

[0149] In this embodiment, the host computer only needs to process defective images, avoiding the processing of a large number of non-defective images, significantly improving detection efficiency. Furthermore, the host computer can execute more complex target detection algorithms to accurately locate and classify defects in the images, ultimately generating a complete detection analysis report.

[0150] The present invention uses a ZYNQ processor to preprocess images, and a Jetson processor to mark defects on the preprocessed images. The ZYNQ processor only sends images with defect marks to a host computer, so that the host computer only needs to process images with defect marks, reducing the workload of the host computer. Only one host computer is needed to complete the detection, thereby reducing costs. In addition, the ZYNQ processor and the Jetson processor are used to process images in a layered and collaborative manner, avoiding the use of an acquisition card and improving the reliability of the equipment.

[0151] The present invention also proposes a defect detection device based on ZYNQ and Jetson layered collaboration, the hardware structure diagram of which is as follows: Figure 6 As shown, the device primarily consists of a carrier board 1001, a ZYNQ processor 1002, and a Jetson processor 1003. The two processors are integrated via the carrier board to form an integrated design. The ZYNQ chip model on the ZYNQ processor is not limited to Xilinx's XC7Z035, XC7Z045, and XC7Z100, and the Jetson processor model is not limited to Nvidia's Jetson Xavier NX module. These are complete computing units with built-in processors, memory, and interfaces.

[0152] The ZYNQ processor is equipped with memory for image caching and system operation, while the Jetson processor is equipped with memory for the system and deep learning models. Both are connected via the GTX interface and the MIPI interface for high-speed data transmission. The ZYNQ processor communicates with external devices via Ethernet ports 1 and 2, while the Jetson processor communicates with external devices via Ethernet port 4. The ZYNQ processor can also communicate with the Jetson processor via Ethernet port 3. Line scan cameras connect to the ZYNQ processor via the camera interface for image acquisition.

[0153] The present invention also proposes a defect detection device based on ZYNQ and Jetson layered collaboration, whose functional architecture is as follows: Figure 7 shown.

[0154] The defect detection device based on ZYNQ and Jetson layered collaboration in the embodiment of the present invention may be a ZYNQ processor capable of running a defect detection method based on ZYNQ and Jetson layered collaboration; the ZYNQ processor has at least one. Figure 7As shown, the defect detection device based on ZYNQ and Jetson layered collaboration may include: a defect detection module 2001, a network interface 2004, a user interface 2003, a memory 2005 and a communication bus 2002. Among them, the communication bus 2002 is used to realize the connection and communication between these components. The user interface 2003 may include a display screen (Display), an input unit, such as a keyboard (Keyboard), and the user interface 2003 may also include a standard wired interface and a wireless interface. The network interface 2004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 2005 may be a high-speed RAM memory or a stable memory (non-volatile memory), such as a disk memory. The memory 2005 may also be a storage device independent of the aforementioned defect detection module 2001.

[0155] Those skilled in the art will understand that Figure 6 and Figure 7 The structure of the defect detection device based on the layered collaboration of ZYNQ and Jetson shown in the figure does not constitute a limitation of the defect detection device based on the layered collaboration of ZYNQ and Jetson, and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0156] like Figure 7 As shown, the memory 2005 as a computer storage medium may include an operating system, a network communication module, a user interface module and a computer program.

[0157] exist Figure 7 In the defect detection device based on ZYNQ and Jetson layered collaboration shown, the network interface 2004 is mainly used to connect to the background server and communicate data with the background server; the user interface 2003 is mainly used to connect to the client (user end) and communicate data with the client; and the processor 2001 can be used to call the computer program stored in the memory 2005. When the computer program is called and executed by the processor 2001, the steps of the above-mentioned defect detection method based on ZYNQ and Jetson layered collaboration are implemented.

[0158] The present invention also proposes a defect detection system based on ZYNQ and Jetson layered collaboration, such as Figure 8 As shown in the figure, the defect detection system based on ZYNQ and Jetson layered collaboration includes: multiple line scan cameras, a defect detection module composed of multiple ZYNQ processors and Jetson processors, and a host computer;

[0159] The plurality of line array cameras respectively capture corresponding areas of the surface image of the large-format object and transmit the images to the corresponding ZYNQ processors;

[0160] The multiple ZYNQ processors are the aforementioned ZYNQ processors, configured to process surface images sent by multiple line array cameras in parallel, perform pre-processing to extract blob area images, and transmit them to corresponding Jetson processors;

[0161] The multiple Jetson processors are configured to collaboratively perform rapid classification of the blob area image, determine whether there is a defect, and return defect marking information to the corresponding ZYNQ processor;

[0162] The plurality of ZYNQ processors are further configured to filter image data having defects according to the defect marking information and send the image data to the host computer;

[0163] The host computer is configured to identify defect areas and categories;

[0164] The ZYNQ processor and Jetson processor in each defect detection module achieve efficient defect detection through layered collaboration;

[0165] The multiple defect detection modules are aggregated and connected to a host computer via Ethernet and a switch.

[0166] In one embodiment of the present invention, the system includes an Ethernet switching unit, which implements time-sharing multiplexing of the Jetson processor network port, solving the problem that the Jetson processor needs to communicate with the ZYNQ processor and the host computer at the same time but has only one network interface.

[0167] like Figure 9 As shown, the Ethernet switching unit includes a first Gigabit Ethernet port, a second Gigabit Ethernet port, and a third Gigabit Ethernet port; the first Gigabit Ethernet port is connected to the host computer via a 10 Gigabit switch, the second Gigabit Ethernet port is connected to the ZYNQ processor, and the third Gigabit Ethernet port is connected to the Jetson processor. The Ethernet switching unit is preferably implemented using an analog switch, with its operating mode switching controlled by the ZYNQ processor.

[0168] The network port switching mechanism includes the following two working modes:

[0169] Detection mode: The analog switch directly connects the PHY chip of the Jetson processor to the PHY chip of the ZYNQ processor, forming a point-to-point communication channel for the Jetson processor to receive the blob image data sent by the ZYNQ processor and return defect marking information;

[0170] Configuration mode: The analog switch connects the Jetson processor's PHY chip to the RJ45 network port and establishes communication with the host computer through the 10G switch to update the deep learning model and system parameter configuration.

[0171] The Zynq processor is responsible for controlling the mode switching process. Before the switch, the Zynq processor sends a switch notification to the Jetson processor through the control channel, causing both parties to suspend data transmission and disable the retransmission mechanism. After the switch is completed, the PHY chip re-negotiates and establishes a network connection, then resumes data transmission.

[0172] Compared with other Jetson module network expansion solutions that use PCIe expansion network cards, USB network cards or Ethernet switching chips, the Ethernet switching unit of this embodiment has the following advantages: it avoids the PCIe driver development required for complex PCIe network cards; it avoids the use of Ethernet switching chips and does not need to configure various interface settings of the switching chips; it realizes time-sharing multiplexing of network interfaces through simple analog switches, which reduces the cost of software and hardware development while meeting the system application scenarios; it has low hardware cost, simple circuit design and easy wiring; the switching mechanism is reliable and supports hot plugging and fault recovery.

[0173] This network port switching mechanism effectively addresses the limited network port resources of the Jetson processor, enabling efficient communication with the Zynq processor during defect detection. It also connects to the host computer when needed to update models and parameters, facilitating flexible system deployment and maintenance. This interface reuse mechanism effectively simplifies hardware design, reduces system costs and software development, and ensures system reliability.

[0174] Based on the computer program proposed in the aforementioned embodiment, the present invention further proposes a storage medium, which stores the computer program. When the computer program is executed by a controller, the defect detection method based on ZYNQ and Jetson layered collaboration described in the aforementioned embodiment is implemented.

[0175] The present invention also proposes a storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the defect detection method based on ZYNQ and Jetson layered collaboration as described in any one of the above technical solutions are implemented.

[0176] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural transformations made by using the contents of the present invention description and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.

Claims

1. A defect detection method based on ZYNQ and Jetson layered collaboration, characterized in that: The defect detection method based on ZYNQ and Jetson layered collaboration includes: The ZYNQ processor receives the surface image of the object to be measured sent by the linear array camera, pre-processes the surface image to extract the blob area image, and transmits the image to the Jetson processor; The Jetson processor performs defect marking on the Blob area image to obtain defect marking information, and returns the defect marking information to the ZYNQ processor; The ZYNQ processor filters the Blob area image according to the defect marking information to obtain a Blob area image with defects, and sends the Blob area image with defects to the host computer; The host computer performs target detection on the Blob area image with defects to obtain the defect type and location; The ZYNQ processor and the Jetson processor are integrated into the same defect detection module through a layered collaborative architecture.

2. The defect detection method based on ZYNQ and Jetson layered collaboration according to claim 1 is characterized in that: The preprocessing of the surface image to extract the Blob area image includes: Performing equal-area segmentation on the surface image to obtain multiple blob region images with the same area; or, Extracting suspected defects from the surface image to obtain a suspected defect region image, and determining whether an image area of the suspected defect region image is larger than a preset image area; If the image area of the suspected defect region image is larger than the preset image area, the suspected defect region image is divided into equal preset image areas to obtain multiple Blob region images with the same area as the preset image; If the image area of the suspected defect region image is smaller than or equal to the preset image area, the image area is expanded with the suspected defect region image as the center to obtain a Blob region image with the same area as the preset image.

3. The defect detection method based on ZYNQ and Jetson layered collaboration according to claim 1 is characterized in that: The ZYNQ processor transmits the Blob area image to the Jetson processor through a high-speed serial interface, wherein the high-speed serial interface is a MIPICS I-2 interface.

4. The defect detection method based on ZYNQ and Jetson layered collaboration according to claim 1, characterized in that: The layered collaborative architecture adopts a dual-channel communication mechanism, which includes: The image data channel uses the MIPI CSI-2 interface to achieve high-speed image transmission from the ZYNQ processor to the Jetson processor through the GTX high-speed transceiver, and encapsulates the Blob image data at the protocol layer; Control the data channel, using a gigabit network interface and UDP protocol to transmit defect marking information between the ZYNQ processor and the Jetson processor; The sequence number synchronization mechanism uses the ZYNQ processor to periodically send the starting sequence number and the Jetson processor to automatically increment the Blob sequence number based on the MIPI frame synchronization signal.

5. The defect detection method based on ZYNQ and Jetson layered collaboration according to claim 1, characterized in that: The Jetson processor uses a network port switching mechanism to time-share a single network interface to communicate with the ZYNQ processor and the host computer respectively.

6. The defect detection method based on ZYNQ and Jetson layered collaboration according to claim 1, characterized in that: The defect marking information includes: The classification result of whether the defect exists, the defect confidence level, and the blob number.

7. The defect detection method based on ZYNQ and Jetson layered collaboration according to claim 6, characterized in that: Before transmitting the Blob area image to the Jetson processor, the ZYNQ processor first stores the Blob area image in the DDR cache, and after receiving the defect marking information, extracts the corresponding Blob area image with defects from the DDR cache according to the Blob sequence number in the defect marking information and sends it to the host computer; or, The ZYNQ processor sends the surface image to a host computer.

8. The defect detection method based on ZYNQ and Jetson layered collaboration according to claim 1, characterized in that: The host computer performs target detection on the defective Blob area image to obtain the defect type and location, including: The host computer processes the defective Blob area image to identify the defect, and identifies the defect area and category through image segmentation and target detection based on deep learning.

9. A defect detection device based on ZYNQ and Jetson layered collaboration, characterized in that: include: The ZYNQ processor is configured to receive a surface image of the object to be measured sent by the line array camera, pre-process the surface image to extract a blob area image, and transmit the image to the Jetson processor; as well as, The Jetson processor is configured to perform defect marking on the Blob area image to obtain defect marking information, and return the defect marking information to the ZYNQ processor; A communication interface configured to send the defective Blob area image screened by the ZYNQ processor to a host computer; a memory in communication with the ZYNQ processor and a memory in communication with the Jetson processor; The memory stores instructions executed by the ZYNQ processor, and the instructions are executed by the ZYNQ processor so that the ZYNQ processor can execute the defect detection method based on ZYNQ and Jetson layered collaboration according to any one of claims 1 to 8; The ZYNQ processor and the Jetson processor are integrated into the same defect detection module through a layered collaborative architecture.

10. A defect detection system based on ZYNQ and Jetson layered collaboration, characterized in that: include: Multiple line scan cameras, multiple defect detection modules, and a host computer, wherein the defect detection modules include a ZYNQ processor and a Jetson processor; The plurality of line array cameras respectively capture corresponding areas of the surface image of the large-format object and transmit the images to the corresponding ZYNQ processors; The multiple ZYNQ processors are the ZYNQ processors according to claim 9, configured to process surface images sent by multiple line array cameras in parallel, pre-process the surface images to extract blob area images, and transmit them to corresponding Jetson processors; The multiple Jetson processors are configured to collaboratively perform defect marking on the Blob area image to obtain defect marking information, and return the defect marking information to the corresponding ZYNQ processor; The multiple ZYNQ processors are further configured to screen the Blob area images to obtain Blob area images with defects, and send the Blob area images with defects to a host computer; The host computer is configured to perform target detection on the defective Blob area image to obtain the defect type and location; The ZYNQ processor and Jetson processor in each defect detection module realize defect detection through layered collaboration; The multiple defect detection modules are aggregated and connected to a host computer via Ethernet and a switch.

11. The defect detection system based on ZYNQ and Jetson layered collaboration according to claim 10, characterized in that: It also includes an Ethernet switching unit, the Ethernet switching unit including a first gigabit network port, a second gigabit network port and a third gigabit network port; The first gigabit network port is used to communicate with the host computer, the second gigabit network port is used to connect to the ZYNQ processor, and the third gigabit network port is used to connect to the Jetson processor; The ZYNQ processor enables the Jetson processor to communicate with the ZYNQ processor or communicate with the host computer in a time-division multiplexing manner through an Ethernet switching unit; Wherein, the Ethernet switching unit is implemented by an analog switch, and is used to implement the network port switching mechanism described in claim 5.

12. The defect detection system based on ZYNQ and Jetson layered collaboration according to claim 11, characterized in that: The network port switching mechanism includes: In the detection mode, the PHY chip of the Jetson processor is connected to the PHY chip of the ZYNQ processor via the analog switch to transmit defect marking information; In configuration mode, the Jetson processor is connected to the RJ45 network port and communicates with the host computer through the analog switch to update the model and parameters; Switching control: the ZYNQ processor controls the analog switch to shut down data transmission before switching.

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