Method and system for detecting surface defects of display chip

Abstract

The invention discloses a surface defect detection method and system for a display chip, and relates to the technical field of display chips, a plurality of functional areas are determined according to matching of a surface image and an internal structure image of the display chip, and a first surface defect area of the surface image is marked; the plurality of abnormal functional areas are determined based on the plurality of functional areas, the first surface defect area and the fault signal of the display chip, so that the accuracy of the plurality of abnormal functional areas is ensured. Therefore, a plurality of surface defect events are determined according to the plurality of abnormal function areas, a database of the display chip and the model of the display chip, and a second surface defect area is determined according to the plurality of surface defect events and the surface image of the display chip; the surface defect type of the display chip is determined according to the second surface defect area and the first surface defect area, the second surface defect area and the first surface defect area are fully considered, and the accuracy of the surface defect type of the display chip is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of display chips, and in particular to a method and system for detecting surface defects of display chips. Background Art

[0002] With the development of technology, display chips have gradually been applied to people's lives and as part of electronic devices, display chips are often called display processing units (DPUs) or graphics processing units (GPUs). They are microprocessors specially designed to process image data and perform graphics rendering tasks.

[0003] In the prior art, the display chip is located inside the electronic device and may experience some failure events during long-term use, resulting in some directly observable surface defect areas on the surface of the display chip. The surface defect types of the display chip are determined only by the directly observed surface defect areas, while some surface defect areas that cannot be directly observed are ignored, resulting in low accuracy in the surface defect types of the display chip. Summary of the Invention

[0004] The purpose of the present invention is to overcome the deficiencies of the prior art. The present invention provides a method and system for detecting surface defects of a display chip.

[0005] An embodiment of the present invention provides a surface defect detection method for a display chip, comprising: when the display chip is in a fault state, collecting a surface image and an internal structure image of the display chip; determining multiple functional areas based on the matching of the surface image and the internal structure image of the display chip, and marking a first surface defect area of the surface image; determining multiple abnormal functional areas based on the multiple functional areas, the first surface defect area and a fault signal of the display chip; determining multiple surface defect events based on the multiple abnormal functional areas, a database of the display chip and a model of the display chip, and determining a second surface defect area based on the multiple surface defect events and the surface image of the display chip; the second surface defect area is a surface defect area that cannot be directly observed by the surface image of the display chip; and determining the type of surface defect of the display chip based on the second surface defect area and the first surface defect area.

[0006] An embodiment of the present invention provides a surface defect detection system for a display chip. The surface defect detection system for a display chip is applied to the above-mentioned surface defect detection method for a display chip. The surface defect detection system for a display chip includes:

[0007] An image module, used to capture surface images and internal structure images of the display chip when the display chip is in a fault state;

[0008] a first surface defect area module, configured to determine a plurality of functional areas based on a match between a surface image and an internal structure image of the display chip, and mark a first surface defect area of the surface image;

[0009] an abnormal functional area module, configured to determine a plurality of abnormal functional areas based on the plurality of functional areas, the first surface defect area, and a fault signal of the display chip;

[0010] a second surface defect region module, configured to determine a plurality of surface defect events based on the plurality of abnormal functional regions, a database of the display chip, and a model of the display chip, and to determine a second surface defect region based on the plurality of surface defect events and a surface image of the display chip; the second surface defect region being a surface defect region that cannot be directly observed in the surface image of the display chip;

[0011] The surface defect type module is used to determine the surface defect type of the display chip according to the second surface defect area and the first surface defect area.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] In an embodiment of the present invention, through the method in the embodiment of the present invention, multiple functional areas are determined based on the matching of the surface image and the internal structure image of the display chip, and the first surface defect area of the surface image is marked; multiple abnormal functional areas are determined based on the multiple functional areas, the first surface defect area and the fault signal of the display chip, which is compatible with the overall consideration of the multiple functional areas, the first surface defect area and the fault signal of the display chip, and ensures the accuracy of the multiple abnormal functional areas.

[0014] Therefore, multiple surface defect events are determined based on the multiple abnormal functional areas, the database of the display chip and the model of the display chip, and the second surface defect area is determined based on the multiple surface defect events and the surface image of the display chip; the second surface defect area is a surface defect area that cannot be directly observed by the surface image of the display chip; the surface defect type of the display chip is determined based on the second surface defect area and the first surface defect area, and the second surface defect area and the first surface defect area are fully considered to ensure the accuracy of the surface defect type of the display chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 1 is a flow chart of a method for detecting surface defects of a display chip according to an embodiment of the present invention;

[0016] Figure 2 1 is a flow chart of step S11 in the method for detecting surface defects of a display chip according to an embodiment of the present invention;

[0017] Figure 31 is a flow chart of step S12 in the method for detecting surface defects of a display chip according to an embodiment of the present invention;

[0018] Figure 4 1 is a flow chart of step S13 in the method for detecting surface defects of a display chip according to an embodiment of the present invention;

[0019] Figure 5 1 is a flow chart of step S14 in the method for detecting surface defects of a display chip according to an embodiment of the present invention;

[0020] Figure 6 1 is a flow chart of step S15 in the method for detecting surface defects of a display chip according to an embodiment of the present invention;

[0021] Figure 7 It is a schematic diagram of the structure of a surface defect detection system for a display chip in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0023] See also Figures 1 to 7 , a surface defect detection method for a display chip, comprising:

[0024] Step S11: when the display chip is in a fault state, collecting a surface image and an internal structure image of the display chip;

[0025] Step S12: determining a plurality of functional areas based on the matching of the surface image and the internal structure image of the display chip, and marking a first surface defect area of the surface image;

[0026] Step S13: determining a plurality of abnormal functional areas based on the plurality of functional areas, the first surface defect area, and the fault signal of the display chip;

[0027] Step S14: determining a plurality of surface defect events based on the plurality of abnormal functional areas, a database of the display chip, and a model of the display chip, and determining a second surface defect area based on the plurality of surface defect events and a surface image of the display chip; the second surface defect area is a surface defect area that cannot be directly observed in the surface image of the display chip;

[0028] Step S15: determining the type of surface defects of the display chip according to the second surface defect area and the first surface defect area;

[0029] refer to Figure 2 , in step S11, when the display chip is in a fault state, a surface image and an internal structure image of the display chip are collected;

[0030] In the specific implementation process of the present invention, the specific steps are:

[0031] S111: collecting multiple operating parameters of the display chip, determining multiple fault parameters of the display chip according to the multiple operating parameters of the display chip and the fault signal, and determining the fault state of the display chip based on the multiple fault parameters of the display chip, the model of the display chip, and the fault state mapping relationship;

[0032] S112: monitoring the fault status of the display chip in real time, determining detection parameters of the visual inspection part according to the fault status of the display chip, the size of the display chip, and previous detection data of the display chip, and the visual inspection part performing surface inspection on the display chip to output a surface image of the display chip;

[0033] S113: Determine detection parameters of the X-ray detection part according to the fault state of the display chip, the thickness of the display chip and the previous detection data of the display chip. The X-ray detection part performs internal detection on the display chip to output an internal structure image of the display chip.

[0034] In an embodiment of the present application, multiple operating parameters of the display chip are collected, and multiple fault parameters of the display chip are determined based on the multiple operating parameters of the display chip and the fault signal. The fault state of the display chip is determined based on the multiple fault parameters of the display chip, the model of the display chip, and the fault state mapping relationship. This is compatible with the overall consideration of the multiple fault parameters of the display chip, the model of the display chip, and the fault state mapping relationship, thereby ensuring the accuracy of the fault state of the display chip.

[0035] At this time, various sensors and test equipment are used to collect key parameters of the display chip when it is working. These parameters include but are not limited to current, voltage, power consumption, temperature, brightness, color uniformity, response time, etc. The collection of these parameters is usually completed through a test system connected to the display chip, which can record and analyze these data in real time; optionally, a display chip model XYZ123 is being tested; a special test equipment is connected to the chip, and it is set to record the current (I), voltage (V), power consumption (P) and temperature (T) during operation; for example, it is found that the current of the chip is 100mA, the voltage is 5V, the power consumption is 0.5W, and the temperature is 60℃ during normal operation.

[0036] The collected operating parameters are compared with the preset fault thresholds or standards; if a parameter exceeds the normal range or deviates significantly from the standard value, it is considered a fault parameter; in addition, if the system receives a fault signal from the display chip (such as an overheating warning, a short-circuit protection trigger, etc.), these should also be considered as the source of the fault parameter; optionally, it is found that the current of the XYZ123 display chip suddenly increases to 200mA during operation, far exceeding the normal 100mA; at the same time, the temperature also rises sharply to 85°C, which is beyond the safe range; in addition, the system also receives an overheating warning signal; therefore, the current (I) and temperature (T) are determined to be fault parameters.

[0037] The fault state of the display chip is determined using fault parameters, model information of the display chip, and a pre-established fault state mapping relationship; the fault state mapping relationship is a lookup table, decision tree, or machine learning model, which can map fault parameters to specific fault states or categories; optionally, based on the model information and fault parameters (current I and temperature T) of the XYZ123 display chip, a pre-established fault state mapping relationship is consulted, and it is learned from the fault state mapping relationship that when the current increases abnormally and the temperature exceeds the safe range, the fault state is "internal short circuit causing overheating"; therefore, it is determined that the XYZ123 display chip is currently in the fault state of "internal short circuit causing overheating".

[0038] Through the above steps, the operating parameters of the display chip were successfully collected, the fault parameters were determined, and the fault state of the display chip was determined using the fault state mapping relationship. In practical applications, this information will be used to guide subsequent defect detection processes, such as adjusting detection parameters, selecting appropriate detection technologies (such as visual inspection or X-ray inspection), and formulating targeted repair or replacement strategies.

[0039] Furthermore, the fault status of the display chip is monitored in real time, and the detection parameters of the visual detection part are determined according to the fault status of the display chip, the size of the display chip and the previous detection data of the display chip. The visual detection part performs surface detection on the display chip to output a surface image of the display chip, which is compatible with the overall consideration of the fault status of the display chip, the size of the display chip and the previous detection data of the display chip, thereby ensuring the accuracy of the detection parameters of the visual detection part.

[0040] At this time, the fault status of the display chip is tracked in real time based on a continuous monitoring system, which usually involves collecting and analyzing various sensor data from the display chip, such as temperature, current, voltage, etc., as well as any fault signals or warnings. These data are used to evaluate the health of the display chip in real time and trigger an immediate response when a fault occurs; optionally, this can be achieved through an automated testing system that integrates data acquisition, analysis and alarm functions; the system can read the operating parameters of the display chip in real time and determine whether there is a fault based on preset thresholds or rules.

[0041] Once the fault status of the display chip is determined, the inspection parameters of the visual inspection part need to be determined based on this status, the physical size of the display chip (which affects the field of view and resolution of image acquisition), and previous inspection data (which reveals the common location and type of defects). These parameters include camera focal length, exposure time, light source settings, image resolution, etc.; optionally, the inspection parameters can be dynamically adjusted based on the above factors to ensure optimal image quality and defect detection sensitivity.

[0042] Using the adjusted inspection parameters, a visual inspection system (such as a high-resolution camera) will capture images of the surface of the display chip; the captured images will be used in subsequent image processing and analysis steps to identify and locate any potential surface defects.

[0043] Specifically, assume that a display chip is being monitored in real time. The chip has a physical size of 50mm x 50mm, and there are records of previous test data for this model of chip. An automated test system is used to collect the chip's operating parameters, such as current, voltage, and temperature, in real time. The system detects a sudden increase in current and a significant rise in temperature, triggering an overheating warning.

[0044] Based on the overheating warning and chip size (50mm x 50mm), the camera's focus and exposure time were adjusted to ensure that subtle changes on the chip surface could be captured. Previous inspection data was also used to determine common defect types for this type of chip, including cracks, stains, and scratches, so the image processing algorithm was optimized accordingly. Using the adjusted inspection parameters, images of the chip surface were captured. The captured images showed a clear crack on the chip surface, which was consistent with previous expectations. This process successfully demonstrated the successful use of real-time monitoring, intelligent parameter adjustment, and advanced imaging technology to capture and analyze defects on the display chip surface. This information will be used in subsequent defect classification, location, and repair steps.

[0045] Therefore, the detection parameters of the X-ray detection part are determined according to the fault status of the display chip, the thickness of the display chip and the previous detection data of the display chip. The X-ray detection part performs internal detection on the display chip to output an internal structure image of the display chip, which is compatible with the overall consideration of the fault status of the display chip, the thickness of the display chip and the previous detection data of the display chip, thereby ensuring the accuracy of the detection parameters of the X-ray detection part.

[0046] At this time, the X-ray inspection parameters are determined by comprehensively considering the fault status, physical thickness and previous inspection data of the display chip; the fault status indicates the problem area or type inside the chip, while the thickness of the chip directly affects the penetration ability and image quality of the X-rays; previous inspection data provides valuable information about the defect type, location and frequency, which helps to optimize the inspection parameters; optionally, an intelligent parameter adjustment system is collected, which can dynamically adjust the X-ray source voltage, current, exposure time and detector sensitivity parameters according to the input information. The adjustment of these parameters is aimed at ensuring that the X-rays can penetrate the chip to a sufficient depth while producing high-quality internal structure images.

[0047] Using adjusted X-ray inspection parameters, the internal structure of the display chip will be non-destructively inspected; X-rays can penetrate the chip material and record the density and thickness differences of different materials inside the chip, thereby generating internal structure images. These images will be used in subsequent image processing and analysis steps to identify and locate any potential internal defects; optionally, X-ray diffraction imaging (DR) is introduced to provide high-resolution internal structure images while ensuring non-destructive inspection of the chip.

[0048] Specifically, assume that an X-ray inspection is being performed on a display chip; the physical thickness of the chip is 0.5 mm, and there are some records of previous inspection data for this model of chip; first, the fault status of the chip is analyzed, and it is found that the system reports an internal short circuit fault; considering that the thickness of the chip is 0.5 mm, the voltage and current of the X-ray source are adjusted to ensure that the X-rays can penetrate the chip and produce a clear image of the internal structure; also referring to previous inspection data, it is found that common internal defects of this model of chip include metal impurities, interlayer short circuits and cracks; therefore, the image processing algorithm is optimized to better identify these defect types.

[0049] Using adjusted X-ray inspection parameters, the chip's internal structure was inspected. The test results showed the presence of an obvious metal impurity in an internal layer of the chip, which was likely the cause of the internal short circuit. Through this process, fault status analysis, intelligent parameter adjustment, and advanced X-ray imaging technology were successfully used to capture and analyze the internal structural defects of the display chip. This information will be used in subsequent defect classification, location, and repair steps, helping to improve the quality and reliability of the display chip.

[0050] refer to Figure 3 , in step S12, a plurality of functional areas are determined based on the matching of the surface image and the internal structure image of the display chip, and a first surface defect area of the surface image is marked;

[0051] In the specific implementation process of the present invention, the specific steps are:

[0052] S121: Acquire a surface image and an internal structure image of the display chip, and determine a stacking structure model of the display chip based on the surface image and the internal structure image of the display chip. In this case, the stacking structure model contains multiple functional circuit paths;

[0053] S122: determining multiple functional areas of the display chip based on the multiple functional circuit paths of the stacked structure model and the surface image, wherein the multiple functional areas are presented on the surface of the display chip;

[0054] S123: determining a plurality of surface abnormal features based on the surface detection of the surface image of the display chip, and determining a first surface defect region of the surface image according to the positions of the plurality of surface abnormal features, the types of the plurality of surface abnormal features, and the influence ranges of the plurality of surface abnormal features, wherein the first surface defect region of the surface image is a surface defect region directly observed by the surface image of the display chip;

[0055] In an embodiment of the present application, the surface image and internal structure image of the display chip are collected, and the stacking structure model of the display chip is determined based on the surface image and internal structure image of the display chip. At this time, the stacking structure model contains multiple functional circuit paths, which is compatible with the overall consideration of the surface image and internal structure image of the display chip, thereby ensuring the accuracy of the stacking structure model of the display chip.

[0056] At this point, use high-precision imaging equipment (such as a high-resolution camera) to capture surface images of the display chip. These surface images should clearly show all details of the chip surface, including circuit layout, component positions, connection points, etc.; the quality of the acquired images is critical for subsequent analysis and modeling; optionally, use a high-resolution camera or microscope to photograph the display chip; adjust the focal length, exposure time, and light source intensity of the camera or microscope to ensure optimal image clarity and contrast; store the acquired image data for subsequent processing and analysis.

[0057] Use non-destructive imaging technology (such as X-ray imaging or ultrasonic imaging) to capture the internal structure images of the display chip. These internal structure images should be able to reveal the internal hierarchical structure, functional circuit paths and connection relationships between layers of the chip; optionally, use an X-ray imaging system or ultrasonic imaging equipment to scan the display chip; adjust the parameters of the imaging equipment (such as the voltage and current of the X-ray source, the frequency and intensity of the ultrasonic wave) according to the thickness and material properties of the chip to optimize the image quality; store the collected internal structure image data for subsequent processing and analysis.

[0058] Image processing and modeling techniques will be used to analyze the collected surface and internal structure images to construct a stacked structure model of the display chip. This stacked structure model will include the layout, thickness, and relative positional relationship of each functional layer inside the chip, especially detailed information on the functional circuit paths; optionally, image processing algorithms (such as edge detection, image segmentation, image registration, etc.) will be applied to extract key information from the image; 3D modeling software or computer-aided design (CAD) tools will be used to construct a stacked structure model based on the extracted information; and the model will be verified and optimized to ensure its accuracy and completeness.

[0059] Specifically, suppose a display chip is being analyzed; a high-resolution camera is used to capture an image of the chip's surface, clearly showing the circuit layout and component positions on its surface; an X-ray imaging system is used to scan the chip, obtaining an image of its internal structure, revealing the chip's internal hierarchical structure and functional circuit paths; an image processing algorithm is applied to extract key information from the image, such as the edges of the circuit, the outlines of the components, and the paths of the functional circuits; using this information, a layered structure model of the chip is constructed in 3D modeling software; in the layered structure model, the layout, thickness, and connection relationships of the functional layers inside the chip are clearly visible; the model is verified and optimized to ensure that it accurately reflects the actual structure of the chip.

[0060] Furthermore, multiple functional areas of the display chip are determined based on multiple functional circuit paths and surface images of the stacked structure model. The multiple functional areas are presented on the surface of the display chip, which is compatible with the overall consideration of multiple functional circuit paths and surface images of the stacked structure model, thereby ensuring the accuracy of multiple functional areas of the display chip.

[0061] At this point, carefully study the stacked structure model, especially the functional line paths therein. These functional line paths are the key channels for signal transmission inside the chip, and they connect different functional components and areas. By analyzing these paths, understand the functional layout and signal flow inside the chip. Optionally, use 3D modeling software or computer-aided design (CAD) tools to view and edit the stacked structure model. Trace the functional line paths and identify their starting points, end points, and connection points. Analyze the connection relationship and signal flow between the functional line paths to understand the functional layout of the chip.

[0062] The surface image of the display chip and the functional circuit paths in the stacked structure model are combined to identify functional areas on the chip. These functional areas correspond to the parts of the chip that perform specific functions or process specific signals. They have obvious layout features on the chip surface, such as specific geometric shapes, markings or color coding; optionally, image processing algorithms (such as edge detection, image segmentation, etc.) are used to extract key features in the surface image; the extracted features are matched and compared with the functional circuit paths in the stacked structure model; and based on the matching results, different functional areas are marked on the chip surface image.

[0063] It is necessary to verify and confirm whether the previously identified functional areas are accurate, which can be achieved by comparing with known chip design drawings, verifying with test signals, or referring to documents provided by the chip manufacturer; optionally, comparing with known chip design drawings or documents provided by the manufacturer to check whether the identified functional areas are consistent with expectations; testing the chip with test signals or test equipment to verify the correctness and functionality of the functional areas; and making necessary adjustments and optimizations to the identified functional areas based on the verification results.

[0064] Specifically, suppose a display chip is being analyzed; the functional circuit paths in the stacked structure model are carefully studied to understand the functional layout and signal flow inside the chip; combined with the surface image of the display chip, image processing algorithms are used to extract key features in the image, such as the edges of the circuit, the outlines of the components, etc.; the extracted features are matched and compared with the functional circuit paths in the stacked structure model, and different functional areas on the chip are identified, such as the display driver area, signal processing area, power management area, etc.; different colors or marks are used on the chip surface image to distinguish these functional areas in order to more intuitively display their position and layout; compared with known chip design drawings, and the chip is tested with test signals to verify the accuracy and functionality of the identified functional areas; through this process, multiple functional areas on the display chip are successfully identified, providing strong support for subsequent analysis and testing.

[0065] Therefore, based on the surface detection of the surface image of the display chip, multiple surface abnormality features are determined, and the first surface defect area of the surface image is determined according to the positions of the multiple surface abnormality features, the types of the multiple surface abnormality features and the influence range of the multiple surface abnormality features. The first surface defect area of the surface image is the surface defect area directly observed by the surface image of the display chip, which is compatible with the overall consideration of the positions of the multiple surface abnormality features, the types of the multiple surface abnormality features and the influence range of the multiple surface abnormality features, thereby ensuring the accuracy of the first surface defect area of the surface image.

[0066] At this point, a comprehensive inspection of the surface image of the display chip is performed to identify any abnormal features. This typically involves using advanced image processing algorithms and techniques, such as machine learning, deep learning, or traditional image processing methods, to automatically detect and analyze anomalies in the image. Optionally, the surface image of the display chip is processed using image processing software or algorithms. Image processing techniques such as edge detection, texture analysis, and color recognition are applied to identify abnormal features in the image. Thresholds or rules are set to determine which features are considered abnormal, typically based on comparison with a normal chip surface or based on features of known defects.

[0067] Each detected abnormal feature is analyzed in detail to determine its location, type and impact range; the location usually refers to the specific position of the abnormal feature in the chip surface image, and types include scratches, stains, cracks, missing components, etc., and the impact range refers to the potential impact of the abnormal feature on the chip function or performance; optionally, the measurement tools in the image processing software are used to determine the location and size of the abnormal feature; the abnormal features are classified into different types according to their morphology, color, texture and other characteristics; the impact range is evaluated by analyzing the comparison between the abnormal features and the surrounding normal areas, as well as their impact on the chip function.

[0068] The first surface defect area in the surface image will be delineated based on the location, type and impact range of the previously determined abnormal features. This first surface defect area is the defective part that can be directly observed on the chip surface image and is crucial for evaluating the quality and reliability of the chip. Optionally, in the image processing software, marking tools or drawing tools are used to delineate the defect area. According to the severity and impact range of the abnormal features, the defect area is graded or classified for subsequent analysis and processing. The information of the defect area is recorded and a detailed inspection report is generated, including the location, type, impact range and repair suggestions of the defect.

[0069] Specifically, suppose a display chip is being analyzed; a comprehensive inspection of the chip's surface image is performed, using advanced image processing algorithms and techniques to identify any abnormal features; during the inspection, a clear scratch and a stain are found; these two abnormal features are analyzed in detail; the scratch is located in the central area of the chip surface, with a length of approximately 2 mm and a width of approximately 0.1 mm; the stain is located at the edge of the chip, with an area of approximately 1 square millimeter; based on their morphology, color, and texture, the scratch is classified as physical damage and the stain is classified as contamination.

[0070] The potential impact of these two abnormal features on chip function or performance was evaluated; scratches can damage the conductive layer or insulating layer on the chip surface, resulting in poor signal transmission or short circuit; stains can cover key components or connection points on the chip surface, affecting signal reception and transmission; therefore, the impact range of these two abnormal features was rated as severe; the area where the two abnormal features were located was delineated as the first surface defect area in the image processing software and clearly marked using a marking tool; the information of the defect area was recorded, and a detailed inspection report was generated, including the location, type, impact range and repair suggestions of the defect. This report provides strong support for subsequent analysis and processing.

[0071] In one embodiment of the present application, an abnormal feature matching table is collected, and the abnormal feature matching table is shown in Table 1;

[0072] Table 1 Abnormal feature matching table

[0073]

[0074] Abnormal feature 1 (scratch): matches the scratch feature in the abnormal feature matching table, and the impact range is assessed as affecting the conductive layer or the insulating layer; Abnormal feature 2 (stain): matches the stain feature in the abnormal feature matching table, and the impact range is assessed as covering key components; Abnormal feature 3 (crack): matches the crack feature in the abnormal feature matching table, and the impact range is assessed as damaging the circuit structure.

[0075] To more accurately determine the first surface defect area, a weight is assigned to each abnormal feature and a score is given based on its impact range. The weight is determined based on factors such as the severity of the abnormal feature and its impact on chip function. The score is calculated based on factors such as the location, size, and number of the abnormal features. The first surface defect area of the surface image is determined based on the abnormal feature or combination of abnormal features with the highest total score. If the score of an abnormal feature is much higher than that of other features, the defect area is delineated with it as the center. If multiple abnormal features have similar scores, their relative positions and mutual influence are taken into consideration to delineate a defect area that includes all relevant features.

[0076] At this time, the first surface defect area: a circular area with a radius of R centered at (x2, y2) (the stain score is the highest and has the greatest impact on chip function); the first surface defect area contains a significant stain that covers key components, affecting signal reception and transmission; cleaning or replacing the chip is recommended.

[0077] refer to Figure 4 , in step S13, determining a plurality of abnormal functional areas based on the plurality of functional areas, the first surface defect area, and the fault signal of the display chip;

[0078] In the specific implementation process of the present invention, the specific steps are:

[0079] S131: collecting a fault signal of a display chip, determining the fault content of the display chip according to analysis of the fault signal of the display chip, and determining multiple fault items of the display chip based on the classification of the fault content of the display chip;

[0080] S132: Marking a surface area of multiple functional areas on the surface of the display chip, and determining a first sub-abnormal functional area based on a match between the surface areas of the multiple functional areas and multiple fault items of the display chip;

[0081] S133: Determine a second sub-abnormal functional area based on the surface area of multiple functional areas and the first surface defect area, and determine multiple abnormal functional areas based on the first sub-abnormal functional area, the second sub-abnormal functional area and the functional area mapping relationship, and the functional area mapping relationship is obtained based on the model of the display chip and the database matching of the display chip.

[0082] In an embodiment of the present application, a fault signal of a display chip is collected, the fault content of the display chip is determined based on the analysis of the fault signal of the display chip, and multiple fault items of the display chip are determined based on the classification of the fault content of the display chip;

[0083] At this time, the fault signals generated by the display chip during operation are collected. These fault signals manifest as voltage fluctuations, current anomalies, timing errors, signal loss, etc. The key to collecting fault signals is to ensure the accuracy and reliability of the test equipment so that the signal characteristics of the chip failure can be accurately captured; optionally, use oscilloscopes, logic analyzers, power supplies and other test equipment to connect the display chip; set test parameters, such as sampling rate, trigger conditions, etc., to ensure that the fault signal can be captured; start the test equipment and start collecting the signal of the display chip during operation.

[0084] After the fault signals are collected, they need to be analyzed. The purpose of the analysis is to identify the characteristics of the fault signals, such as the amplitude, frequency, phase, timing, etc. of the signal, as well as the differences between these characteristics and normal signals. By analyzing the fault signals, the type and cause of the chip fault can be preliminarily determined. Optionally, the collected signals can be preprocessed by filtering, amplifying, denoising, etc. The waveform, spectrum, timing and other characteristics of the signals are analyzed and compared with normal signals. Based on the differences in signal characteristics, the type and cause of the chip fault can be preliminarily determined.

[0085] Based on the analysis of the fault signal, it is necessary to further determine the fault content of the display chip; the fault content usually includes the specific type of fault, the location of occurrence and the scope of impact; determining the fault content requires comprehensive consideration of the chip's working principle, circuit design and the characteristics of the fault signal; optionally, combined with the working principle and circuit design of the display chip, analyze the relationship between the fault signal and the chip's internal components and circuits; based on the characteristics of the fault signal and the chip's working principle, determine the specific type of fault, such as power supply failure, signal processing failure, display driver failure, etc.; evaluate the scope of the fault's impact on the chip's functions to determine whether the fault affects the entire chip or only part of the function.

[0086] After determining the fault content, it is necessary to further divide the fault content into specific fault items. Fault items refer to specific, actionable repair or replacement parts in the fault content, or parameters or settings that need to be adjusted. Dividing fault items facilitates subsequent positioning, repair or replacement work. Optionally, the fault content can be divided into specific fault items based on the type and impact range of the fault content. Each fault item should be described and defined in detail, including the fault phenomenon, cause, repair or replacement parts, and adjusted parameters or settings. The fault items should be recorded for subsequent analysis and processing.

[0087] Specifically, suppose a display chip is being analyzed; when collecting the fault signal, an oscilloscope is used to connect to the signal output terminal of the display chip, and it is found that the signal waveform is obviously distorted; when analyzing the fault signal, it is found that the frequency and phase of the distorted signal are significantly different from the normal signal; after further analysis, it is determined that the fault content is a signal processing fault, which is specifically manifested as an abnormality in the signal amplification circuit; when dividing the fault items, the fault is divided into "signal amplification circuit fault item", and the fault phenomenon, cause and parts to be repaired or replaced (such as signal amplifiers, related resistors and capacitors, etc.) are described in detail.

[0088] Furthermore, a surface area of multiple functional areas is marked on the surface of the display chip, and the first sub-abnormal functional area is determined based on the matching of the surface areas of the multiple functional areas and the multiple fault items of the display chip, which is compatible with the overall consideration of the matching of the surface areas of the multiple functional areas and the multiple fault items of the display chip, thereby ensuring the accuracy of the first sub-abnormal functional area.

[0089] At this time, based on the design drawings or technical documents of the display chip, mark the surface areas of multiple functional areas on the surface image of the chip. These functional areas include the power management area, signal processing area, display driver area, interface connection area, etc. The purpose of marking is to be able to accurately match the faulty items with these functional areas later. Optionally, obtain the design drawings or technical documents of the display chip to understand the functional area division of the chip. Use image processing software or manually mark the boundaries of each functional area on the chip surface image. Ensure the accuracy and clarity of the marking for subsequent analysis and matching.

[0090] The first sub-abnormal functional area is determined based on the matching of the surface area of the functional area and the fault item. At this time, after marking the surface area of the functional area, these areas need to be matched with multiple fault items determined previously; the purpose of matching is to find out the functional areas directly related to the fault items, which are the core locations of the fault; through matching, the first sub-abnormal functional area is determined, that is, the functional area with the greatest possibility of fault; optionally, review the fault items determined previously to understand the specific content and impact range of each item; match each fault item with the marked functional area one by one, and analyze the correlation between the fault item and the functional area; based on the matching results, determine the functional area directly related to the fault item as the first sub-abnormal functional area; describe and record the first sub-abnormal functional area in detail, including its location, size, components or circuits involved, etc.

[0091] Specifically, assume that a display chip is being analyzed; in the previous steps, multiple fault items have been identified, including "power management fault item" and "display driver fault item"; the power management area and display driver area are marked on the surface image of the display chip; the "power management fault item" is matched with the power management area, and it is found that the fault item is directly associated with a component in the power management area (such as the power management IC); similarly, the "display driver fault item" is matched with the display driver area, and it is found that the fault item is directly associated with a circuit in the display driver area (such as the display driver circuit); through matching, two first sub-abnormal function areas are determined: one is the area where the power management IC is located in the power management area, and the other is the area where the display driver circuit is located in the display driver area. These two areas are the core locations where the fault occurs, so they need to be further inspected and tested.

[0092] Therefore, the second sub-abnormal functional area is determined based on the surface area of multiple functional areas and the first surface defect area, and multiple abnormal functional areas are determined based on the first sub-abnormal functional area, the second sub-abnormal functional area and the functional area mapping relationship. The functional area mapping relationship is obtained based on the model of the display chip and the database matching of the display chip, and is compatible with the overall consideration of the first sub-abnormal functional area, the second sub-abnormal functional area and the functional area mapping relationship. At the same time, it is compatible with the overall consideration of multiple functional areas, the first surface defect area and the fault signal of the display chip, thereby ensuring the accuracy of multiple abnormal functional areas.

[0093] At this time, the second sub-abnormal functional area is determined based on the surface areas of multiple functional areas and the first surface defect area. At this time, the second sub-abnormal functional area is determined by comprehensively considering the surface areas of the multiple functional areas determined previously and the first surface defect area (such as scratches, stains, cracks and other physical damage); the second sub-abnormal functional area refers to those functional areas that are not directly obtained through fault signal analysis but are affected by physical damage; optionally, the specific positions and ranges of the surface areas of the multiple functional areas determined previously and the first surface defect area are reviewed; the spatial relationship between the first surface defect area and each functional area is analyzed to determine whether the defect affects the normal operation of the functional area; based on the analysis results, the second sub-abnormal functional areas affected by the first surface defect area are determined, and these areas have performance degradation or complete failure due to physical damage.

[0094] Combine the first sub-abnormal functional area (obtained through fault signal analysis) and the second sub-abnormal functional area (obtained through physical damage analysis), and refer to the functional area mapping relationship to determine the final multiple abnormal functional areas; the functional area mapping relationship is obtained based on the model of the display chip and the database matching of the display chip, which describes the connection and dependency between the functional areas inside the chip; optionally, obtain the model information of the display chip, and retrieve the functional area mapping relationship related to the model from the database; analyze the functional area mapping relationship to understand the connection and dependency between the functional areas; match the first sub-abnormal functional area and the second sub-abnormal functional area with the functional area mapping relationship to determine the mutual influence and association between them; based on the matching results, determine the final multiple abnormal functional areas, which include direct fault points, potential fault points and other key functional areas related to the fault.

[0095] Specifically, assume that a display chip is being analyzed; in the previous steps, the first sub-abnormal functional area (such as the area where the power management IC is located and the area where the display driver circuit is located) and the first surface defect area (such as a scratch passing through the signal processing area) have been determined; now, it is necessary to determine the second sub-abnormal functional area based on this information; by analyzing the spatial relationship between the scratch and the signal processing area, it is found that the scratch has damaged a key component or circuit in the signal processing area, so this area is determined as the second sub-abnormal functional area.

[0096] Next, the final multiple abnormal functional areas are determined by referring to the display chip model and the functional area mapping relationship in the database; through the mapping relationship, it is found that there is a close dependency between the power management area and the display driver area, while the signal processing area has a direct connection with the display driver area; therefore, the area where the power management IC is located, the area where the display driver circuit is located, and the signal processing area (affected by scratches) are all determined to be abnormal functional areas. These abnormal functional areas are the direct cause or potential cause of the failure of the tablet computer display; through further inspection and testing, the specific fault point is determined, and corresponding repair measures are taken.

[0097] In one embodiment of the present application, it is assumed that the weights of the power management area, signal processing area, display driver area and interface connection area are 3, 4, 5 and 2 respectively (the larger the weight, the more important the area or the more relevant to the fault); the score of the first sub-abnormal functional area (such as the power management IC fault) is its weight value 3; the score of the second sub-abnormal functional area (such as the scratch of the signal processing area) is its weight value 4 plus the association score with the first sub-abnormal functional area (assuming it is 1, because although the power management area does not directly affect signal processing, the unstable power supply affects signal processing); the scores of other functional areas (such as the display driver area and the interface connection area) are calculated based on whether they are directly associated with the first or second sub-abnormal functional area; for example, the display driver area is directly related to the signal processing area, so its score is its weight value 5 plus the association score with the signal processing area (assuming it is 2).

[0098] Power management area: 3 points (first sub-abnormal function area); signal processing area: 5 points (second sub-abnormal function area + correlation score with the power management area); display driver area: 7 points (direct correlation score with the signal processing area); interface connection area: 2 points (only surface defects, no direct correlation); Based on the scores, the display driver area and signal processing area are determined to be the most important abnormal function areas, which need to be inspected and repaired first; although the power management area is the first sub-abnormal function area, its score is low, indicating that the fault impact range is limited or there are other factors that cause the fault to not be fully manifested; the interface connection area has the lowest score and only has surface defects, which is not the main cause of the fault.

[0099] refer to Figure 5 In step S14, a plurality of surface defect events are determined based on the plurality of abnormal functional areas, the database of the display chip, and the model of the display chip, and a second surface defect area is determined based on the plurality of surface defect events and the surface image of the display chip; the second surface defect area is a surface defect area that cannot be directly observed in the surface image of the display chip;

[0100] In the specific implementation process of the present invention, the specific steps are:

[0101] S141: collecting positions of multiple abnormal functional areas, determining transition areas between the multiple abnormal functional areas according to the positions of the multiple abnormal functional areas, and determining whether the transition areas are abnormal based on detection of the transition areas;

[0102] S142: If the transition region is abnormal, determining the overall abnormal region of the display chip based on the abnormal transition region and the multiple abnormal functional regions; determining a first defect event based on the overall abnormal region and a database of the display chip; and determining a second defect event based on the overall abnormal region and the model of the display chip;

[0103] S143: Determine a second surface defect area based on the first defect event, the second defect event, and the defect event mapping relationship, where the second surface defect area and the first surface defect area are distributed on the same surface of the display chip, and the second surface defect area is a surface defect area that cannot be directly observed in the surface image of the display chip.

[0104] In an embodiment of the present application, the positions of multiple abnormal functional areas are collected, and transition areas between the multiple abnormal functional areas are determined according to the positions of the multiple abnormal functional areas. Based on the detection of the transition area, it is determined whether the transition area is abnormal.

[0105] At this point, the position information of each abnormal functional area on the display chip is obtained, which usually involves using high-precision measurement tools or image recognition technology to locate the boundaries of the abnormal functional area; the position information includes coordinates, dimensions, and relative position relative to other parts of the chip; optionally, an image of the display chip is taken using a microscope or a high-resolution camera; image processing software is used to identify and mark the boundaries of the abnormal functional area; and the coordinates and size information of each abnormal functional area is recorded.

[0106] After obtaining the location information of the abnormal functional areas, it is necessary to identify and determine the transition zones between these areas; the transition areas are located at the edges of the abnormal functional areas, or on the paths connecting different abnormal functional areas. These areas function as bridges or buffers, so their abnormal states are crucial for understanding the functional disorders of the entire chip; optionally, based on the coordinates and size information of the abnormal functional areas, their boundaries are drawn on the chip image; the paths or edge areas connecting different abnormal functional areas are observed and marked as transition areas; the coordinates and boundaries of the transition areas are recorded.

[0107] After the transition areas are identified, they need to be inspected in detail to determine whether they have any abnormalities. Inspections include physical inspections (such as observing cracks, scratches, or contamination) and electrical tests (such as measuring resistance, capacitance, or signal integrity). These tests will help understand whether the transition areas maintain their proper functions or whether there are defects that cause dysfunction of the entire chip. Optionally, a microscope or electron scanning microscope is used to observe the physical state of the transition areas. Electrical tests are performed, such as using a multimeter to measure resistance or an oscilloscope to observe signal waveforms. Based on the results of the physical inspection and electrical tests, it is determined whether the transition areas have any abnormalities.

[0108] Specifically, assume that a display chip is being analyzed. In the previous step, it has been determined that the chip has multiple abnormal functional areas, including the power management area and the display driver area. A high-resolution camera is used to capture an image of the chip, and image processing software is used to mark the boundaries of the power management area and the display driver area. The coordinates and size information of these two areas are recorded.

[0109] On the chip image, a narrow path connecting the power management area and the display driver area was observed; this path was marked as a transition area, and its coordinates were recorded; the transition area was observed using a microscope, and tiny cracks were found in the area; electrical tests were performed, and the resistance value of the transition area was found to be abnormally high, indicating an open circuit or poor contact problem; based on the above steps and observations, it was determined that there was an abnormality in the transition area, which caused the signal transmission between the power management area and the display driver area to be blocked, thereby affecting the function of the entire chip. This discovery provides key information for subsequent repair or replacement work.

[0110] Furthermore, if there is an abnormality in the transition area, the overall abnormal area of the display chip is determined based on the abnormal transition area and multiple abnormal functional areas; the first defect event is determined based on the database of the overall abnormal area and the display chip, and the second defect event is determined based on the overall abnormal area and the model of the display chip, which is compatible with the overall consideration of the overall abnormal area and the model of the display chip and ensures the accuracy of the second defect event.

[0111] At this time, when the transition area is confirmed to be abnormal, it needs to be combined with multiple known abnormal functional areas to determine a larger overall abnormal area. This overall abnormal area covers all affected functional areas and the transition zones between them, which is the basis for further analysis of defect events and formulation of repair strategies; optionally, review the locations and boundaries of multiple known abnormal functional areas; add the confirmed abnormal transition area to these functional areas; use image processing or geographic information system (GIS) tools to merge these areas into an overall abnormal area; record the coordinates, size and shape of the overall abnormal area.

[0112] After determining the overall abnormal area, the display chip database is used to search for known defect events that match the area. The database contains historical defect event records, including the defect type, cause, impact range, and repair suggestions. The first defect event is determined by matching the overall abnormal area with the records in the database. Optionally, the display chip database is accessed, and the coordinates, size, and shape of the overall abnormal area are used as query conditions. The database is searched for defect event records similar to the overall abnormal area. The first defect event is determined based on the degree of match and correlation.

[0113] In addition to utilizing the database, the model information of the display chip also needs to be considered to determine the second defect event; different models of display chips have different design features, production processes, or known model-specific problems; therefore, it is necessary to combine the overall abnormal area and the chip model to analyze and determine the second defect event related to both factors; optionally, obtain the model information of the display chip; review the historical problems and known defects of the chip of this model; analyze the correlation between these defects and model-specific problems in combination with the position, size, and shape of the overall abnormal area; and determine the second defect event based on the analysis results.

[0114] Specifically, assume that a display chip is being analyzed; it is known that anomalies exist in the power management area and the display driver area, and the transition area connecting these two areas is also confirmed to be abnormal; using image processing tools, these three areas are merged into an overall abnormal area, which covers a part of the core functional area of the chip.

[0115] Determine the first defect event: Access the display chip database and input the coordinates and size information of the overall abnormal area; the database returns multiple defect event records similar to the overall abnormal area, one of which shows that the abnormality in this area is usually related to "signal transmission failure between the power management module and the display driver module"; therefore, the first defect event is determined to be "signal transmission failure between the power management module and the display driver module."

[0116] Determine the second defect event: The display chip model is obtained as XYZ123; review the historical problems and known defects of this model chip and find that this model chip has a specific process defect in the production process, which causes an unstable connection between the power management module and the display driver module; combined with the location and size of the overall abnormal area and the description of the model-specific problem, the second defect event is determined to be "unstable connection between the power management module and the display driver module caused by a process defect unique to the XYZ123 model chip"; through this series of steps, not only the overall abnormal area of the display chip is determined, but also two defect events related to the abnormal area are determined based on the database and chip model information. This information provides key basis for subsequent repair or replacement work.

[0117] Therefore, the second surface defect area is determined based on the first defect event, the second defect event and the mapping relationship between the defect events. The second surface defect area and the first surface defect area are distributed on the same surface of the display chip. The second surface defect area is a surface defect area that cannot be directly observed by the surface image of the display chip. It is compatible with the overall consideration of the first defect event, the second defect event and the mapping relationship between the defect events, and ensures the accuracy of the second surface defect area.

[0118] At this point, the defect event mapping relationship is a relational dataset that describes how different types of defect events produce visible and invisible defect areas on the display chip. This mapping relationship is established based on historical data, physical principles, chip design knowledge, and an in-depth understanding of the production process. It can help predict other unknown defect areas on the chip when certain defect events are known. Optionally, access a database or model of the defect event mapping relationship; become familiar with the working principle of the mapping relationship, including how it predicts unknown defect areas based on known defect events; and ensure that the mapping relationship matches the display chip model and defect event type currently being analyzed.

[0119] Integrate the previously identified first defect event and second defect event. These two events describe anomalies at different locations on the chip, but there is a certain correlation or causal relationship between them. Integrating this information helps to more comprehensively understand the defect situation on the chip. Optionally, review the description and location information of the first defect event and the second defect event. Analyze whether there is a correlation or causal relationship between the two events. Integrate the relevant information into a unified defect event report.

[0120] With the integrated defect event information and defect event mapping relationship, in this step, this information will be used to predict the second surface defect areas on the chip, which are hidden defects that cannot be directly observed through the surface image; optionally, the integrated defect event information is input into the defect event mapping relationship; the mapping relationship is used to make predictions to determine the position, size and properties of the second surface defect area; the prediction results, including the coordinates, size and relationship of the second surface defect area with the first surface defect area, are recorded.

[0121] Specifically, assume that a display chip model ABC456 is being analyzed, and the following two defect events have been identified: the first defect event: a signal transmission failure between the power management module and the display driver module; the second defect event: an unstable connection between the power management module and the display driver module caused by a process defect unique to the ABC456 model chip.

[0122] Now, we will use the defect event mapping relationship to determine the second surface defect area; we have accessed the defect event mapping relationship database for the ABC456 model chip; we have become familiar with the working principle of the mapping relationship, especially how it predicts other potential defect areas based on the defects of the power management module and display driver module; we have reviewed the descriptions of the two defect events and found that they both involve connection problems between the power management module and the display driver module; analysis has concluded that there is a causal relationship between the two events, that is, the process defect leads to the signal transmission failure.

[0123] The integrated defect event information is input into a mapping relationship; the mapping relationship predicts the presence of a hidden second surface defect area on the back side of the display chip (i.e., the other side opposite to the first surface defect area), near the connection between the power management module and the display driver module; the second surface defect area is a tiny crack or poor internal connection, which cannot be discovered by directly observing the surface image of the chip; through this series of steps, the second surface defect area on the display chip is successfully determined. This information is crucial for subsequent repair or replacement work because it points out other potential problems that need to be paid attention to and addressed in addition to the defects visible on the surface.

[0124] In one embodiment of the present application, a defect event matching table is constructed based on historical data, physical principles, and chip design knowledge. This defect event matching table lists the corresponding relationships between different types of defect events and the second surface defect areas caused by them; the defect event matching table is shown in Table 2; Table 2 Defect Event Matching Table

[0125]

[0126] Match the known first defect event and the second defect event with the entries in the matching table to find the second surface defect area; at this time, the first defect event is known: signal transmission failure between the power management module and the display driver module; the second defect event is known: unstable connection between the power management module and the display driver module caused by process defects unique to the ABC456 model chip; through the matching table, find the second surface defect area corresponding to these two defect events: tiny cracks or poor connection on the back near the connection between the power management module and the display driver module.

[0127] refer to Figure 6 , in step S15, determining the surface defect type of the display chip according to the second surface defect area and the first surface defect area;

[0128] In the specific implementation process of the present invention, the specific steps are:

[0129] S151: collecting the second surface defect area and the first surface defect area, determining the overall defect area of the display chip based on the second surface defect area and the first surface defect area, and determining multiple abnormal components of the display chip based on the overall defect area of the display chip and the surface distribution map of the display chip;

[0130] S152: determining a plurality of component combinations based on the positions of the plurality of abnormal components, the shapes of the plurality of abnormal components, and the component combination relationship, and determining a plurality of component defect events based on the identification of the plurality of component combinations;

[0131] S153: Collecting the use environment of the display chip and the service life of the display chip, and determining the type of surface defect of the display chip according to the multiple component defect events, the use environment of the display chip and the service life of the display chip.

[0132] In an embodiment of the present application, the second surface defect area and the first surface defect area are collected, the overall defect area of the display chip is determined based on the second surface defect area and the first surface defect area, and multiple abnormal elements of the display chip are determined based on the overall defect area of the display chip and the surface distribution map of the display chip. This is compatible with the overall consideration of the overall defect area of the display chip and the surface distribution map of the display chip, thereby ensuring the accuracy of the multiple abnormal elements of the display chip.

[0133] At this time, the second surface defect area and the first surface defect area are collected, and the first surface defect area and the second surface defect area are integrated into a unified coordinate system; the first surface defect area and the second surface defect area are analyzed to see whether they overlap, are adjacent or are related to each other; based on this information, an overall defect area covering all known defects is determined; optionally, GIS (geographic information system) or CAD (computer-aided design) software is used to integrate and analyze the data; and spatial analysis methods are applied to identify the relationship between the first surface defect area and the second surface defect area.

[0134] Obtain a surface distribution map of the display chip, which details the location, type, and interconnectedness of all components on the chip; compare the overall defect area with the surface distribution map and mark the components located within the defect area; analyze the function and importance of these components and their relationship to the defect area to determine which components are abnormal or affected by the defect; optionally, use image processing software or CAD software to overlay the defect area with the surface distribution map; apply an algorithm to automatically identify the components located within the defect area and generate a report.

[0135] Specifically, assume that a display chip model XYZ123 is being analyzed, which is used in high-end smartphones; collect the first surface defect area: use a high-resolution camera to photograph the first surface of the chip, and find a crack extending from the edge of the chip to the inside; collect the second surface defect area: through X-ray detection, a tiny cavity corresponding to the first surface crack is found on the back of the chip (second surface), which is caused by poor internal welding or material defects.

[0136] By integrating the defective areas of the first and second surfaces into a coordinate system, it was found that they almost completely overlapped, forming a continuous defective area extending from the edge of the chip to the interior; a surface distribution map of the XYZ123 model chip was obtained, and it was found that the defective area covered the power management module, several capacitors, and the signal transmission lines connected to them on the chip; after analyzing the functions and importance of these components, the power management module and the affected capacitors were determined to be abnormal components because they were directly located in the defective area and were critical to the normal operation of the chip; through this series of steps, multiple abnormal components on the display chip were successfully identified, providing key information for subsequent analysis and repair work.

[0137] Furthermore, multiple component combinations are determined based on the positions of multiple abnormal components, the shapes of multiple abnormal components, and the component combination relationships, and multiple component defect events are determined based on the identification of multiple component combinations, which is compatible with the overall consideration of the positions of multiple abnormal components, the shapes of multiple abnormal components, and the component combination relationships, ensuring the accuracy of multiple component combinations.

[0138] At this point, examine the physical location of each abnormal component on the display chip, paying particular attention to whether they are adjacent, located within the same functional module, or interconnected through circuits. Observe the morphological characteristics of the abnormal components, such as size changes, color changes, physical damage, etc. These characteristics indicate the failure mode or degree of damage of the component. Based on the analysis of position and morphology, group abnormal components with logical associations or physical connections together to form one or more component combinations. These combinations represent specific functional modules or circuit paths on the chip. Optionally, use CAD software or specialized electronic design automation (EDA) tools to visualize the location and morphology of abnormal components. Apply spatial clustering algorithms or graph theory methods to identify associations and combinations between components.

[0139] Each identified component combination is further reviewed to identify the key components within the combination, their connection relationships, and functional impacts. The defect events that occur in each component combination are analyzed with reference to known defect patterns, historical data, and component specifications. These events include component damage, poor connections, performance degradation, etc. Based on the above analysis, one or more specific defect events are determined for each component combination. These events will serve as the basis for subsequent troubleshooting, repair, or replacement work. Optionally, fault tree analysis (FTA) is used to identify and analyze defect events. A defect event learning model is applied to predict and classify defect events.

[0140] Specifically, assume that a display chip model ABC789 is being analyzed. In the previous step, it has been determined that the display chip has multiple abnormal components. It is found that the abnormal components are mainly concentrated in the power management area of the chip, including a damaged power management IC, two swollen capacitors, and multiple signal lines connected to them. Through position and morphology analysis, these components are combined together to form a component combination representing the power management function.

[0141] Further review of this component combination revealed that the power management IC was damaged due to overheating, resulting in unstable output voltage; the swollen capacitor was caused by electrolyte leakage due to prolonged exposure to excessively high voltage; and the affected signal lines were transmitting incorrect signals due to damage to the power management IC. Based on the above analysis, the following component defect events were identified: unstable output voltage due to damage to the power management IC, electrolyte leakage of the capacitor, and incorrect signal transmission of the signal line. Through this series of steps, not only were multiple component combinations on the display chip identified, but also specific defect events were determined for each combination, providing more detailed and accurate information for subsequent analysis and repair work.

[0142] Therefore, the use environment of the display chip and the service life of the display chip are collected, and the surface defect type of the display chip is determined based on multiple component defect events, the use environment of the display chip and the service life of the display chip. This takes into account the overall consideration of multiple component defect events, the use environment of the display chip and the service life of the display chip, ensuring the accuracy of the surface defect type of the display chip. At the same time, it fully considers the second surface defect area and the first surface defect area, further ensuring the accuracy of the surface defect type of the display chip.

[0143] At this point, collect information about the environmental conditions experienced by the display chip during its lifecycle, including but not limited to temperature, humidity, vibration, and electromagnetic interference. This data is obtained through sensor monitoring, user feedback, or historical records. Analyze the potential impact of these environmental conditions on the performance and lifespan of the display chip, paying particular attention to environmental factors that can cause component damage, performance degradation, or accelerated aging. Optionally, use an environmental monitoring system or data analysis platform to collect and analyze environmental data, and apply statistical analysis and machine learning techniques to evaluate the impact of environmental factors on chip performance.

[0144] Obtain information on the age of the display chip from production to the present time by querying production records, user purchase records, or maintenance logs; analyze the impact of age on aging and performance degradation of display chip components; pay special attention to defect modes that gradually emerge over time, such as material fatigue and loose connections; optionally, use a database management system or data warehouse to store and query age information; apply life prediction models or reliability analysis methods to evaluate the aging status of the chip.

[0145] Integrate multiple component defect events, display chip usage environment and service life information; analyze the correlation and causal relationship between this information to determine the root cause of the surface defects; based on the results of the comprehensive analysis, identify the types of surface defects on the display chip, which include physical damage (such as scratches, cracks), chemical corrosion (such as oxidation, corrosion), electrical faults (such as short circuits, open circuits), etc. Based on the determined defect types, formulate targeted repair strategies or suggestions, which include replacing damaged components, repairing connection problems, adjusting the working environment, etc.; optionally, use data fusion and decision support systems to integrate and analyze multiple data sources; apply preset defect type learning models to identify and classify surface defect types.

[0146] Specifically, let's assume we're analyzing a display chip, model XYZ456. In a previous step, this display chip was identified as having multiple component defect events, and information about its operating environment and age has been collected. It was discovered that the chip had been operating in extreme temperature conditions (up to 80°C) and frequently exposed to high humidity over the past few years. These conditions have caused accelerated aging of certain materials on the chip, such as corrosion of metal conductors and degradation of the insulation layer. The display chip has been in use for five years, exceeding its design life by three years. During this five-year period, the chip has experienced multiple performance degradations and required repairs.

[0147] Based on a combination of component defect events (such as overheating damage to the power management IC and electrolyte leakage from capacitors), operating environment (extreme temperature and high humidity), and service life (exceeding the design life), the following surface defect types were identified: metal wire corrosion and insulation degradation due to prolonged high-temperature operation; short circuits and performance degradation due to capacitor electrolyte leakage; and overall performance degradation due to extended use and extreme environmental conditions. It is recommended to replace damaged power management ICs and capacitors and thoroughly clean and test the chips. Additionally, it is recommended to improve the chip's operating environment, reducing temperature and humidity to extend its remaining life.

[0148] In one embodiment of the present application, a defect type matching table is collected, and the defect type matching table is shown in Table 3:

[0149] Table 3 Defect type matching table

[0150] Defect Type Typical component defect incidents Use environment characteristics Use period range physical damage scratches and cracks High temperature, mechanical stress any Chemical corrosion Oxidation and corrosion spots High humidity, corrosive gas >3 years Electrical failure Short circuit, open circuit, component overheating and damage Voltage fluctuations, electromagnetic interference any Material aging Degraded performance, poor connection Long-term high temperature operation >5 years

[0151] Assume that scratches and cracks exist on the display chip (component defect events), and the chip operates in a high-temperature environment for a long time (usage environment characteristics), with a service life of 4 years; according to the defect type matching table, the most suitable defect type is "physical damage".

[0152] See also Figure 7 , Figure 7 : is a schematic diagram of the structure of a surface defect detection system for a display chip in an embodiment of the present invention; the surface defect detection system for a display chip includes:

[0153] An image module 21 is used to capture a surface image and an internal structure image of the display chip when the display chip is in a fault state;

[0154] A first surface defect area module 22 is configured to determine a plurality of functional areas based on the matching of the surface image and the internal structure image of the display chip, and mark a first surface defect area of the surface image;

[0155] an abnormal functional area module 23, configured to determine a plurality of abnormal functional areas based on the plurality of functional areas, the first surface defect area, and a fault signal of the display chip;

[0156] a second surface defect region module 24 for determining a plurality of surface defect events based on the plurality of abnormal functional regions, a database of the display chip, and a model of the display chip, and determining a second surface defect region based on the plurality of surface defect events and a surface image of the display chip; the second surface defect region being a surface defect region that cannot be directly observed in the surface image of the display chip;

[0157] The surface defect type module 25 is configured to determine the surface defect type of the display chip according to the second surface defect area and the first surface defect area.

[0158] The technical features of the above embodiments are arbitrarily combined. In order to make the description more concise, not all combinations of the technical features in the above embodiments are described. However, as long as there is no technical contradiction in the combination of these technical features, they should be considered as the main scope recorded in this specification.

Claims

1. A method for detecting surface defects of a display chip, characterized in that: include: When the display chip is in a fault state, collecting the surface image and internal structure image of the display chip; determining a plurality of functional areas based on matching of a surface image and an internal structure image of the display chip, and marking a first surface defect area of the surface image; determining a plurality of abnormal functional areas based on the plurality of functional areas, the first surface defect area, and a fault signal of the display chip; Determining a plurality of surface defect events based on the plurality of abnormal functional areas, a database of the display chip, and a model of the display chip, and determining a second surface defect area based on the plurality of surface defect events and a surface image of the display chip; The second surface defect region is a surface defect region that cannot be directly observed by the surface image of the display chip; The type of the surface defect of the display chip is determined according to the second surface defect area and the first surface defect area.

2. The method for detecting surface defects of a display chip according to claim 1, wherein: When the display chip is in a fault state, collecting a surface image and an internal structure image of the display chip includes: Collecting multiple operating parameters of the display chip, determining multiple fault parameters of the display chip according to the multiple operating parameters of the display chip and the fault signal, and determining the fault state of the display chip based on a mapping relationship between the multiple fault parameters of the display chip, the model of the display chip, and the fault state; Monitor the fault status of the display chip in real time, determine the detection parameters of the visual detection part according to the fault status of the display chip, the size of the display chip and the previous detection data of the display chip, and the visual detection part performs surface detection on the display chip to output the surface image of the display chip; The detection parameters of the X-ray detection part are determined according to the fault status of the display chip, the thickness of the display chip and the previous detection data of the display chip. The X-ray detection part performs internal detection on the display chip to output an internal structure image of the display chip.

3. The surface defect detection method of a display chip according to claim 1, characterized in that: The method of determining a plurality of functional areas based on the matching of the surface image and the internal structure image of the display chip and marking the first surface defect area of the surface image includes: Acquiring a surface image and an internal structure image of the display chip, and determining a stacking structure model of the display chip based on the surface image and the internal structure image of the display chip, wherein the stacking structure model contains multiple functional circuit paths; Determining multiple functional areas of the display chip based on multiple functional circuit paths of the stacked structure model and the surface image, wherein the multiple functional areas are presented on the surface of the display chip; Based on surface detection of the surface image of the display chip, multiple surface abnormality features are determined, and a first surface defect area of the surface image is determined according to the positions of the multiple surface abnormality features, the types of the multiple surface abnormality features, and the influence ranges of the multiple surface abnormality features. The first surface defect area of the surface image is the surface defect area directly observed by the surface image of the display chip.

4. The surface defect detection method of a display chip according to claim 1, wherein: The determining of multiple abnormal functional areas based on the multiple functional areas, the first surface defect area, and the fault signal of the display chip includes: A fault signal of the display chip is collected, the fault content of the display chip is determined according to the analysis of the fault signal of the display chip, and multiple fault items of the display chip are determined based on the classification of the fault content of the display chip.

5. The method for detecting surface defects of a display chip according to claim 4, wherein: The determining of the plurality of abnormal functional areas based on the plurality of functional areas, the first surface defect area, and the fault signal of the display chip further includes: Marking a plurality of surface regions of functional areas on the surface of the display chip, and determining a first sub-abnormal functional area based on a match between the surface regions of the plurality of functional areas and a plurality of fault items of the display chip; The second sub-abnormal functional area is determined based on the surface area of multiple functional areas and the first surface defect area, and multiple abnormal functional areas are determined based on the first sub-abnormal functional area, the second sub-abnormal functional area and the functional area mapping relationship. The functional area mapping relationship is obtained based on the model of the display chip and the database matching of the display chip.

6. The method for detecting surface defects of a display chip according to claim 1, wherein: Determining a plurality of surface defect events based on the plurality of abnormal functional areas, a database of the display chip, and a model of the display chip, and determining a second surface defect area based on the plurality of surface defect events and a surface image of the display chip; The second surface defect area is a surface defect area that cannot be directly observed in the surface image of the display chip, including: collecting positions of a plurality of abnormal functional areas, determining transition areas between the plurality of abnormal functional areas according to the positions of the plurality of abnormal functional areas, and determining whether the transition areas are abnormal based on detection of the transition areas; If there is an abnormality in the transition area, the overall abnormal area of the display chip is determined based on the abnormal transition area and multiple abnormal functional areas; the first defect event is determined based on the overall abnormal area and the database of the display chip, and the second defect event is determined based on the overall abnormal area and the model of the display chip.

7. The method for detecting surface defects of a display chip according to claim 6, wherein: Determining a plurality of surface defect events based on the plurality of abnormal functional areas, a database of the display chip, and a model of the display chip, and determining a second surface defect area based on the plurality of surface defect events and a surface image of the display chip; The second surface defect region is a surface defect region that cannot be directly observed in the surface image of the display chip, and also includes: A second surface defect area is determined based on the first defect event, the second defect event and the defect event mapping relationship. The second surface defect area and the first surface defect area are distributed on the same surface of the display chip. The second surface defect area is a surface defect area that cannot be directly observed in the surface image of the display chip.

8. The method for detecting surface defects of a display chip according to claim 1, wherein: The determining the type of surface defects of the display chip according to the second surface defect area and the first surface defect area includes: The second surface defect area and the first surface defect area are collected, the overall defect area of the display chip is determined based on the second surface defect area and the first surface defect area, and multiple abnormal components of the display chip are determined based on the overall defect area of the display chip and the surface distribution map of the display chip.

9. The method for detecting surface defects of a display chip according to claim 8, wherein: The determining of the surface defect type of the display chip according to the second surface defect area and the first surface defect area further includes: Determining multiple component combinations based on the positions of the multiple abnormal components, the shapes of the multiple abnormal components, and the component combination relationship, and determining multiple component defect events based on the identification of the multiple component combinations; The use environment and service life of the display chip are collected, and the type of surface defects of the display chip is determined based on multiple component defect events, the use environment and service life of the display chip.

10. A surface defect detection system for a display chip, characterized in that: The surface defect detection system for a display chip is applied to the surface defect detection method for a display chip according to any one of claims 1 to 9, and the surface defect detection system for a display chip comprises: An image module, used to capture surface images and internal structure images of the display chip when the display chip is in a fault state; a first surface defect area module, configured to determine a plurality of functional areas based on a match between a surface image and an internal structure image of the display chip, and mark a first surface defect area of the surface image; an abnormal functional area module, configured to determine a plurality of abnormal functional areas based on the plurality of functional areas, the first surface defect area, and a fault signal of the display chip; a second surface defect region module, configured to determine a plurality of surface defect events based on the plurality of abnormal functional regions, a database of the display chip, and a model of the display chip, and to determine a second surface defect region based on the plurality of surface defect events and a surface image of the display chip; the second surface defect region being a surface defect region that cannot be directly observed in the surface image of the display chip; The surface defect type module is used to determine the surface defect type of the display chip according to the second surface defect area and the first surface defect area.

Images