Display panel and display device

Abstract

The invention provides a display panel and a display device, the display panel comprises a display area and a non-display area, and the non-display area at least partially surrounds the display area. The display panel further comprises a first circuit and a second circuit. The first circuit is located in the display area. In the light-emitting stage, the first circuit transmits light-emitting driving current to the light-emitting device, and the first circuit comprises a first type of transistors. The second circuit is located in the non-display area and comprises a second type of transistors. Wherein the first type of transistors and the second type of transistors are double-gate transistors; the two grids of the first type transistor receive the same electric signal; when the second-type transistor is turned on, the two grids of the second-type transistor receive different electric signals respectively. According to the arrangement mode, the conduction degree of the first type of transistors can be improved, and the requirement of the display panel for the high output current of the transistors is met; and the response speed of the second type of transistors is improved in a targeted manner, and the requirement of high time sequence precision of the display panel is met.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In current display panels, the transistor configuration of some circuits within the display area (e.g., pixel circuits) is identical or similar to the transistor structure of some circuits within the non-display area (e.g., shift register circuits). This results in similar transistor performance (e.g., output current intensity, switching response speed, etc.) in these two areas. However, during the display process, the performance requirements for transistors within the display area often differ from those for transistors within the non-display area. Therefore, the existing "unified" transistor configuration within and outside the display area is unable to meet display requirements. Summary of the Invention

[0003] In view of this, the present application provides a display panel and a display device to solve the problem that the unified arrangement of transistors mentioned above is difficult to meet display requirements.

[0004] In a first aspect, the present application provides a display panel, comprising a display area and a non-display area, wherein the non-display area at least partially surrounds the display area.

[0005] The display panel also includes a first circuit and a second circuit. The first circuit is located in the display area and transmits a light-emitting drive current to the light-emitting device during the light-emitting phase. The first circuit includes a first type of transistor. The second circuit is located in the non-display area and includes a second type of transistor.

[0006] Among them, the first type of transistor and the second type of transistor are both dual-gate transistors; the two gates included in the first type of transistor receive the same electrical signal; when the second type of transistor is turned on, the two gates included in the second type of transistor receive different electrical signals respectively.

[0007] In a second aspect, the present application provides a display device, comprising the display panel provided in the first aspect.

[0008] The embodiment of the present application, by setting the two gates of the first type of transistor to receive the same electrical signal, helps to improve the conductivity of the first type of transistor, so that the first type of transistor can meet the high output current requirements of the display panel. In addition, the setting method of each of the two gates of the second type of transistor receiving different electrical signals helps to improve the response speed of the second type of transistor in a targeted manner, improve its performance reliability, and meet the high timing accuracy requirements of the display panel. Therefore, the setting method of this embodiment meets the different performance requirements of the transistor during the operation of the display panel by adaptively adjusting the transistor settings in different areas. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0010] Figure 1 A schematic diagram of a partial structure of a display panel provided in this application; Figure 2 for Figure 1 A schematic structural diagram of a first type of transistor in a display panel shown; Figure 3 for Figure 1 A schematic structural diagram of the second type of transistor in the display panel shown; Figure 4 is an equivalent schematic diagram of a partial structure of the first circuit; Figure 5 is an equivalent schematic diagram of a partial structure of the second circuit; Figure 6 is a schematic top view of a partial structure of a first type of transistor; Figure 7 is a schematic top view of a partial structure of a second type of transistor; Figure 8 is another schematic top view of a partial structure of a second type of transistor; Figure 9 A schematic diagram of a display device provided in this application. DETAILED DESCRIPTION

[0011] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0012] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0013] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0014] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0015] In the prior art, a display panel can be divided into a display area and a non-display area. A pixel circuit is usually provided in the display area for outputting a light-emitting driving current to the light-emitting device; a shift register circuit is usually provided in the non-display area for transmitting a scanning signal to a part of the structure in the display area. During the display process, the display panel has requirements for the current output size of some transistors in the pixel circuit. For example, in order to meet a higher display brightness, it is necessary to enable the driving transistor in the pixel circuit to output a light-emitting driving current with a higher intensity. In addition, the display panel has requirements for the switching response speed of some transistors in the shift register circuit. For example, some transistors in the shift register circuit should have a higher on / off response speed to ensure that the scanning signal output by the shift register circuit has a good working timing with good accuracy.

[0016] However, existing display panels typically use a unified configuration for some transistors in the display area and some transistors in the non-display area. For example, some transistors in the display area and some transistors in the non-display area are configured as single-gate or dual-gate structures. In this configuration, the operating performance of these two transistors is similar, making it difficult to simultaneously meet the different requirements of the display panel for circuits in the display area and circuits in the non-display area.

[0017] Figure 1 A schematic diagram of a partial structure of a display panel provided in this application.

[0018] In order to solve the above problems, the present application provides a display panel 10, such as Figure 1 As shown, the display panel 10 includes a display area 01 and a non-display area 02, wherein the non-display area 02 at least partially surrounds the display area 01. A light-emitting device may be provided in the display area 01, so that during the display process, the display image can be located within the display area 01. The non-display area 02 may also include some off-plane circuits or wiring structures, which can be used to transmit scanning signals to some circuit structures in the display area 01.

[0019] The display panel 10 further includes a first circuit 11 and a second circuit 12. The first circuit 11 is located in the display area 01, and the second circuit 12 is located in the non-display area 02. During the light-emitting phase, the first circuit 11 transmits a light-emitting drive current to the light-emitting device. In this case, the first circuit 11 may be a pixel circuit. Alternatively, the second circuit 12 may be a shift register circuit, and the second circuit 12 may output a scan signal to the first circuit 11.

[0020] Figure 2 for Figure 1 The schematic diagram of the structure of the first type of transistor in the display panel shown in FIG. Figure 3 for Figure 1 A schematic structural diagram of the second type of transistor in the display panel is shown.

[0021] The first circuit 11 includes a first type of transistor T1 , and the second circuit includes a second type of transistor T2 .

[0022] Among them, combined Figure 2 and Figure 3 , the first type of transistor T1 and the second type of transistor T2 are both dual-gate transistors.

[0023] like Figure 3 As shown, the second-type transistor T2 may include a first gate T2a and a second gate T2b. The first gate T2a is located on a side of the active layer T20 of the second-type transistor T2 away from the second gate T2b, and the second gate T2b is located on a side of the active layer T20 closer to the substrate f1. When the gate of the second-type transistor T2 receives a turn-on signal, a channel may be formed in the channel region 201 in the active layer T20, thereby achieving electrical conduction between the two source-drain lap regions 202 of the second-type transistor T2. The source-drain lap regions 202 may be electrically connected to the source / drain 203.

[0024] like Figure 2 As shown, the first-type transistor T1 may include a third gate T1a and a fourth gate T1b. The third gate T1a is located on a side of the active layer T10 of the first-type transistor T1 away from the fourth gate T1b, and the fourth gate T1b is located on a side of the active layer T10 close to the substrate f1. When the gate of the first-type transistor T1 receives a turn-on signal, a channel may be formed in the channel region 101 in the active layer T10, thereby achieving electrical conduction between the two source-drain lap regions 102 of the first-type transistor T1. The source-drain lap regions 102 may be electrically connected to the source / drain 103.

[0025] Compared with a single-gate transistor, by controlling the electrical signals received by the two gates of the dual-gate transistor respectively, the output current intensity of the transistor can be increased, or the threshold voltage offset of the transistor under electrical test conditions can be reduced, which helps to meet various requirements of the display panel 10.

[0026] For example, when both gates of a dual-gate transistor receive a turn-on voltage signal, both gates of the dual-gate transistor can generate an electric field, and the electric field controls the formation of a channel on the active layer; at this time, compared with a single-gate transistor, the number of channels formed on the active layer of the dual-gate transistor is greater, and the degree of turn-on of the dual-gate transistor is greater, so the current intensity output by the dual-gate transistor can be greater than the current intensity output by the single-gate transistor.

[0027] For example, when the top gate of a dual-gate transistor receives a turn-on voltage signal and the bottom gate receives a positive voltage signal (the top gate may be located on the side of the active layer away from the substrate layer, such as the first gate T2a and the third gate T1a; the bottom gate may be located on the side of the active layer close to the substrate layer, such as the second gate T2b and the fourth gate T1b), the threshold voltage offset phenomenon of the dual-gate transistor can be alleviated compared to a single-gate transistor, thereby improving its response speed and enhancing the timing accuracy of the electrical signal it outputs.

[0028] The two gates of the first type transistor T1 receive the same electrical signal, so when the first type transistor T1 is turned on, the third gate T1a and the fourth gate T1b can both receive a turn-on voltage signal. When the second type transistor T2 is turned on, the two gates of the second type transistor T2 receive different electrical signals, so the first gate T2a and the second gate T2b can receive different electrical signals; for example, when the second type transistor T2 is turned on, the first gate T2a can receive a turn-on voltage signal, and the second gate T2b can receive a positive voltage signal.

[0029] In the embodiment of the present application, by configuring the two gates of the first-type transistor T1 to receive the same electrical signal, the conductivity of the first-type transistor T1 is improved, allowing the first-type transistor T1 to meet the high output current requirements of the display panel 10. Furthermore, the configuration in which the two gates of the second-type transistor T2 receive different electrical signals helps to specifically improve the response speed of the second-type transistor T2, enhance its performance reliability, and meet the high timing accuracy requirements of the display panel 10. Therefore, the configuration of this embodiment meets the different performance requirements of the transistors during operation of the display panel 10 by adaptively adjusting the transistor configurations in different regions.

[0030] Figure 4 Schematic diagram of an equivalent structure of part of the first circuit.

[0031] Combine Figure 1 and Figure 4 The first circuit 11 may include a driving transistor M0, a first transistor M1, a second transistor M2, a third transistor M3, a compensation transistor M4, a fourth transistor M5, a fifth transistor M6 and a first capacitor C1. The first circuit 11 may also be electrically connected to a first scan line S1, a second scan line S2, a third scan line S3, a data line L1, a power supply voltage signal line P1, a reset line V1, etc. The connection between the above transistors, capacitors, wiring and light-emitting devices is detailed in Figure 4 , I will not go into details here.

[0032] Figure 5 Schematic diagram of an equivalent structure of part of the second circuit.

[0033] Combine Figure 1 and Figure 5 The second circuit 12 may include a first output transistor M11, a first sub-transistor M12, a second sub-transistor M13, a second output transistor M21, a third sub-transistor M22, a fourth sub-transistor M23, a fifth sub-transistor M24, a sixth sub-transistor M25, a second capacitor C2, and a third capacitor C3. The second circuit 12 may also be electrically connected to a first signal line L2, a second signal line L3, a third signal line L4, a fourth signal line L5, a fifth signal line L6, etc. The connection between the above transistors, capacitors, and wiring is detailed in FIG. Figure 5 The second circuit 12 may be a shift register circuit, and may output a scan signal to the first circuit 11 through the output terminal OUT.

[0034] Figure 6 is a schematic top view of a partial structure of a first type of transistor, Figure 7 This is a top view of part of the structure of the second type of transistor. For ease of understanding, Figure 6 、 Figure 7 The figure shows an abstract diagram of the overlapping of some transistor structures from a top-down perspective, and does not mean that the actual structure of the transistor is as shown in the figure.

[0035] In one embodiment of the present application, Figure 2 and Figure 6 The two gates of the first type transistor T1 are electrically connected to each other. For example, the third gate T1a and the fourth gate T1b can be electrically connected across the membrane layer through the through-hole structure A, so that the third gate T1a and the fourth gate T1b can receive the same electrical signal, thereby helping to achieve the effect of improving the output current intensity of the first type transistor T1.

[0036] In contrast, combined Figure 3 and Figure 7 The first gate T2a and the fourth gate T2b of the second type transistor T2 may be electrically insulated so that the two gates receive different electrical signals respectively.

[0037] Figure 8 FIG. 1 is another top view schematic diagram of a partial structure of the second type transistor, for ease of understanding. Figure 8 The figure shows an abstract diagram of the overlapping of some transistor structures from a top-down perspective, and does not mean that the actual structure of the transistor is as shown in the figure.

[0038] In one possible implementation, Figure 8As shown, a fake hole structure B can be set on the first gate T2a of the second type transistor T2. The first gate T2a cannot be electrically connected to other film layer structures through the fake hole structure B. The significance of setting the fake hole structure B is: on the basis of setting the through-hole structure A, the distribution density of holes on the film layer where the gate is located is balanced, so that the metal density of each area of the film layer remains balanced, reducing the difficulty of preparation.

[0039] In one embodiment of the present application, Figure 4 As shown, the first circuit 11 includes a driving transistor M0. In the light-emitting stage, the driving transistor M0 generates a light-emitting driving current. The current intensity that the driving transistor M0 can output when turned on can affect the intensity of the light-emitting driving current, thereby affecting the brightness of the light-emitting device.

[0040] The driving transistor M0 is a first type transistor T1.

[0041] In the embodiment of the present application, by setting the driving transistor M0 as a dual-gate parallel transistor, it helps to improve the output current intensity of the driving transistor M0, enhance the intensity of the light-emitting driving current output by the first circuit 11, and thereby improve the display brightness of the display panel 10.

[0042] In one embodiment of the present application, Figure 4 As shown, the first circuit 11 further includes a second type transistor T2.

[0043] The first circuit 11 further includes a compensation transistor M4, the input terminal of which is electrically connected to the output terminal of the driving transistor M0, and the output terminal of which is electrically connected to the output terminal of the driving transistor M0. During the operation phase of the first circuit 11, when the compensation transistor M4 is turned on, it can transmit the data voltage signal received by the first circuit 11 to the gate of the driving transistor M0.

[0044] The compensation transistor M4 is a second type transistor T2.

[0045] In the embodiment of the present application, the main function of the compensation transistor M4 includes transmitting a data voltage signal, and the data voltage signal can control the on / off state of the driving transistor M0. Therefore, setting the compensation transistor M4 as the second type of transistor T2 can specifically improve the response speed of the compensation transistor M4, thereby improving the timing accuracy of the data voltage signal received by the driving transistor M0.

[0046] In one embodiment of the present application, all transistors in the first circuit 11 are first-type transistors T1 .

[0047] Given that the first circuit 11 can output a light-emitting drive current during the light-emitting phase, in display modes requiring higher brightness, the display panel 10 places high demands on the current intensity of the light-emitting drive current output by the first circuit 11. Furthermore, there are also high demands on the output current intensity of the transistors (including the drive transistor) within the first circuit 11. Therefore, this embodiment, by configuring all transistors in the first circuit 11 as first-type transistors T1, helps further increase the current intensity output by the first circuit 11 to meet display requirements. Furthermore, configuring all transistors in the first circuit 11 as the same type of transistor (here, this can mean configuring them as a dual-gate parallel structure) helps reduce the manufacturing complexity of the display panel 10.

[0048] In one embodiment of the present application, Figure 3 As shown, the second type transistor T2 includes a first gate T2a and a second gate T2b. The first gate T2a is located on a side of the active layer T20 away from the substrate f1, and the second gate T2b is located on a side of the active layer T20 away from the first gate T2a.

[0049] The second gate T2b receives a positive voltage.

[0050] In the embodiment of the present application, during the process of turning on the second type transistor T2, transmitting a positive voltage to the second gate T2b helps to reduce the threshold voltage value of the second type transistor T2, thereby achieving negative adjustment of the threshold voltage, and helping to improve the reliability of the second type transistor T2, thereby meeting the signal output requirements of the display panel 10 for the second circuit 12.

[0051] In one embodiment of the present application, Figure 2 As shown, the first type transistor T1 may include a third gate T1a and a fourth gate T1b, wherein the third gate T1a is located on a side of the active layer T10 away from the substrate f1, and the fourth gate T1b is located on a side of the active layer T10 away from the third gate T1a.

[0052] In the pre-turn-on stage, the second gate T2 b receives the first positive voltage V1 , and the fourth gate T1 b receives the second positive voltage V2 , where V1 > V2 .

[0053] In an embodiment of the present application, the transistor may first undergo a pre-conduction phase before the turn-on phase. During the pre-conduction phase, the gate of the transistor begins to receive a turn-on voltage signal, and a channel begins to appear in the channel region of the transistor (e.g., the channel region 101 of the first type transistor T1 and the channel region 201 of the second type transistor T2). However, the number of channels that appear at this time is relatively small and cannot yet support the transistor to be fully turned on. Therefore, during the pre-conduction phase, a positive voltage may be transmitted to the fourth gate T1b of the first type transistor T1 and the second gate T2b of the second type transistor T2. That is, during the pre-conduction phase, the threshold voltages of the first type transistor T1 and the second type transistor T2 are negatively adjusted, while the response speed of the first type transistor T1 and the second type transistor T2 is improved. It should be noted that when the threshold voltage is negatively adjusted by receiving a positive voltage at the bottom gate, the greater the voltage value of the positive voltage, the greater the degree of negative adjustment of the threshold voltage. Therefore, in this embodiment, by setting V1>V2, it is helpful to specifically improve the negative adjustment degree of the threshold voltage of the second type transistor T2, and further meet the reliability requirement of the display panel 10 for the second circuit 12.

[0054] In one embodiment of the present application, the second circuit 12 outputs a scan signal to the first circuit 11, and the second circuit 12 may be a shift register circuit. Figure 5 As shown, the second circuit 12 includes a first output transistor M11 and a second output transistor M21. The scan signal includes the electrical signals output by the first output transistor M11 and the second output transistor M21 when each is turned on. When the first output transistor M11 is turned on, the first output transistor M11 can output the electrical signal transmitted by the first signal line L2 to the output terminal OUT of the second circuit 12; when the second output transistor M21 is turned on, the second output transistor M21 can output the electrical signal transmitted by the second signal line L3 to the output terminal OUT of the second circuit 12.

[0055] At least one of the first output transistor M11 and the second output transistor M21 is a second type transistor T2.

[0056] In the embodiment of the present application, the electrical signals output by the first output transistor M11 and the second output transistor M21 are closely related to the scan signal. The timing accuracy of the electrical signals output by these two transistors affects the timing accuracy of the scan signal. Therefore, in the embodiment of the present application, by configuring at least one of these two transistors as the second-type transistor T2, this helps ensure that the scan signal has a high timing accuracy, thereby meeting the display requirements of the display panel 10.

[0057] In one embodiment of the present application, all transistors in the second circuit 12 are second-type transistors T2 .

[0058] This embodiment, by configuring all transistors in the second circuit 12 as second-type transistors T2, further improves the timing accuracy of the scan signals output by the second circuit 12 to meet display requirements. Furthermore, configuring all transistors in the second circuit 12 as the same type (here, a dual-gate non-parallel structure) helps reduce the manufacturing complexity of the display panel 10.

[0059] Figure 9 A schematic diagram of a display device provided in this application.

[0060] The present application provides a display device 20, such as Figure 9 As shown, the display device 20 includes the above-mentioned display panel 10. The display device 20 can be a mobile phone. In addition, the display device 20 can also be an electronic device such as a computer or a television.

[0061] The transistor design within the display panel 10 of the display device 20 provided in the embodiment of the present application greatly satisfies the operating performance requirements corresponding to the circuits within the display area and the circuits within the non-display area, respectively.

[0062] In this specification, reference can be made to the same or similar parts between the various embodiments. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A display panel, characterized in that: include: a display area and a non-display area, wherein the non-display area at least partially surrounds the display area; A first circuit is located in the display area; In the light-emitting stage, the first circuit transmits a light-emitting driving current to the light-emitting device; the first circuit includes a first type of transistor; A second circuit is located in the non-display area; the second circuit includes a second type of transistor; Among them, the first type of transistor and the second type of transistor are both dual-gate transistors; the two gates included in the first type of transistor receive the same electrical signal; when the second type of transistor is turned on, the two gates included in the second type of transistor receive different electrical signals respectively.

2. The display panel according to claim 1, wherein: The two gates of the first type transistors are electrically connected to each other.

3. The display panel according to claim 1, wherein: The first circuit includes a driving transistor, and in the light emitting stage, the driving transistor generates the light emitting driving current; Wherein, the driving transistor is the first type of transistor.

4. The display panel according to claim 3, wherein: The first circuit also includes the second type of transistor; The first circuit further includes a compensation transistor, wherein the input terminal of the compensation transistor is electrically connected to the output terminal of the driving transistor, and the output terminal of the compensation transistor is electrically connected to the output terminal of the driving transistor; Wherein, the compensation transistor is the second type of transistor.

5. The display panel according to claim 1, wherein: All of the transistors in the first circuit are transistors of the first type.

6. The display panel according to claim 1, wherein: The second type of transistor includes a first gate and a second gate, wherein the first gate is located on a side of the active layer away from the substrate, and the second gate is located on a side of the active layer away from the first gate; The second gate receives a positive voltage.

7. The display panel according to claim 6, wherein: The first type of transistor includes a third gate and a fourth gate, the third gate is located on a side of the active layer away from the substrate, and the fourth gate is located on a side of the active layer away from the third gate; In the pre-conduction stage, the second gate receives a first positive voltage V1 , and the fourth gate receives a second positive voltage V2 , where V1 > V2 .

8. The display panel according to claim 1, wherein: The second circuit outputs a scan signal to the first circuit; the second circuit includes a first output transistor and a second output transistor, and the scan signal includes electrical signals output by the first output transistor and the second output transistor respectively when they are turned on; At least one of the first output transistor and the second output transistor is a transistor of the second type.

9. The display panel according to claim 8, wherein: All of the transistors in the second circuit are transistors of the second type.

10. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 9.

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