Sub-pixel circuit, pixel structure, display device and display panel

Abstract

The invention discloses a sub-pixel circuit, a pixel structure, a display device and a display panel. The sub-pixel circuit comprises a light-emitting device, a first driving circuit and a second driving circuit, wherein the first driving circuit and the second driving circuit are connected with the light-emitting device; the first driving circuit is used for providing the duration of a driving current for the light emitting device under the voltage control of a first data signal, and the second driving circuit is used for providing the amplitude of the driving current for the light emitting device under the voltage control of a second data signal; the first driving circuit and the second driving circuit are connected with a constant voltage signal through a constant voltage signal line, and are connected with a data signal through a data signal wire harness. Wherein the first area of the first data signal wire harness connected to the first driving circuit and the constant voltage signal wire at the overlapping part is larger than the second area of the second data signal wire harness connected to the second driving circuit and the same constant voltage signal wire at the overlapping part.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a sub-pixel circuit, a pixel structure, a display device and a display panel. Background Art

[0002] Currently, a display device generally includes a display panel and a driving circuit. In the display panel, multiple pixel circuits are arranged in a matrix. The driving circuit includes a gate driving circuit for driving gate lines and a data driving circuit for driving data lines.

[0003] In practical applications, display panels often use a demultiplexer (Demux) to charge the pixel circuits, thereby providing energy for the light-emitting diodes. For display panels using a demultiplexer, line charging is often used to charge the pixel circuits.

[0004] However, there is a lot of voltage distortion when writing data signals, which ultimately affects the display effect. Summary of the Invention

[0005] The problem to be solved by the present invention is: how to improve the display effect.

[0006] To address the above-mentioned issues, an embodiment of the present invention provides a sub-pixel circuit, comprising: a light-emitting device, and a first drive circuit and a second drive circuit connected to the light-emitting device; the first drive circuit is configured to provide a driving current duration to the light-emitting device under the voltage control of a first data signal, and the second drive circuit is configured to provide a driving current amplitude to the light-emitting device under the voltage control of a second data signal; the first drive circuit and the second drive circuit are connected to a constant voltage signal via a constant voltage signal line and to a data signal via a data signal line harness;

[0007] The first area where the first data signal line bundle connected to the first driving circuit overlaps with the constant voltage signal line is larger than the second area where the second data signal line bundle connected to the second driving circuit overlaps with the same constant voltage signal line.

[0008] An embodiment of the present invention also provides a pixel structure, which includes: a red sub-pixel circuit, a green sub-pixel circuit, and a blue sub-pixel circuit distributed along a first direction, wherein any sub-pixel circuit among the red sub-pixel circuit, the green sub-pixel circuit, and the blue sub-pixel circuit is as described above.

[0009] An embodiment of the present invention further provides a display panel, which includes a pixel array. The pixel array is formed by arranging the pixel structures in the above embodiments in an array.

[0010] An embodiment of the present invention further provides a display device, which may include the display panel

[0011] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0012] By applying the solution of the present invention, since the first area at the intersection of the first data signal line bundle connected to the first driving circuit and the constant-voltage signal line is larger than the second area at the intersection of the second data signal line bundle connected to the second driving circuit and the same constant-voltage signal line, the inter-line capacitance between the first data signal line bundle and the constant-voltage signal line can be increased, and the parasitic capacitance of the first data signal line bundle can also be increased, thereby reducing the voltage drop amplitude of the first data signal line when the data signal is written, avoiding excessive voltage distortion, and ultimately improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a circuit structure diagram of a pixel circuit;

[0014] Figure 2 yes Figure 1 A schematic diagram of the timing of each signal during the operation of the pixel circuit;

[0015] Figure 3 1 is a schematic diagram of a circuit structure of another pixel circuit;

[0016] Figure 4 is a schematic diagram of fluctuation of the voltage of a first data signal line;

[0017] Figure 5 1 is a schematic diagram of a layout of a pixel structure in an embodiment of the present invention;

[0018] Figure 6 yes Figure 5 A schematic diagram of a partial cross-sectional structure of the pixel structure layout along the first direction X;

[0019] Figure 7 yes Figure 5 A partially enlarged schematic diagram of the first data signal harness 20;

[0020] Figure 8 yes Figure 5 A partially enlarged schematic diagram of the second data signal harness 30;

[0021] Figure 9 yes Figure 5 An enlarged schematic diagram of area A on the first data signal harness 20;

[0022] Figure 10 yes Figure 5 FIG. 1 is an enlarged schematic diagram of area B on the first data signal harness 30 . DETAILED DESCRIPTION

[0023] To reduce the cost of display devices, it's generally desirable to reduce the number of output channels in the data driver circuit while maintaining resolution. Therefore, display panels often employ a demultiplexer to charge the pixel circuits, thereby providing energy to the light-emitting diodes. The demultiplexer can connect two or more data signal lines to a single data signal input terminal, which in turn connects a single data signal input terminal to a single output channel of the data driver circuit. This significantly reduces the number of output channels in the data driver circuit.

[0024] For display panels that don't use a demultiplexer, direct charging is often used to charge the pixel circuits. This involves writing data directly to the pixel circuit's data signal lines. In this case, the data lines have high resistance and low parasitic capacitance. Direct charging simply requires ensuring that the data lines meet the load requirements.

[0025] For display panels using a demultiplexer, line charging is often used to charge the pixel circuits. When using a demultiplexer to charge the pixel circuits, the gate lines are turned on row by row, and clock pulse signals are applied to each clock control signal line in sequence. Data signals are then applied to each data signal line connected to the same demultiplexer in a time-sharing manner to charge a row of pixel circuits.

[0026] However, when the pixel circuit is charged using a conventional line charging method, a large amount of voltage distortion occurs, which ultimately affects the display effect.

[0027] The following is a detailed description of the pixel circuit structure:

[0028] Figure 1 A schematic diagram of a circuit structure of a pixel circuit provided by an embodiment of the present invention, referring to Figure 1 The pixel circuit may include: a first drive circuit 10 and a second drive circuit 20. The first drive circuit 10 is configured to provide a driving current duration to the light-emitting device PD under the voltage control of a first data signal PWM_DATA, and the second drive circuit 20 is configured to provide a driving current amplitude to the light-emitting device PD under the voltage control of a second data signal PAM_DATA. The connection point between the first drive circuit 10 and the second drive circuit 20 is node N1. In the first drive circuit 10 and the second drive circuit 20, the gate of each transistor is connected to the gate drive circuit via a gate line, and the gate drive circuit provides various signals connected to the transistor gate. Data signals are connected to the data drive circuit via data signal lines, and the data drive circuit provides data signals to the first drive circuit 10 and the second drive circuit 20.

[0029] The first driving circuit 10 may include: a first driving transistor M1, a first gate reset transistor M2, a second gate reset transistor M3, a first writing transistor M4, a first control transistor M5, a second control transistor M6, a first compensation transistor M7, a second compensation transistor M8 and a first capacitor C1.

[0030] The first control transistor M5, the first drive transistor M1, and the second control transistor M6 are connected in series. The other electrode of the first control transistor M5 is connected to the first power supply voltage signal PWM_VDD, and the gate is connected to the first light emission control signal PWM_EM. The other electrode of the second control transistor M6 is connected to the second drive circuit 20, and the gate is connected to the first light emission control signal PWM_EM. The gate of the first drive transistor M1 is connected to one electrode of the second gate reset transistor M3, the first capacitor C1, and the first compensation transistor M7. The second gate reset transistor M3 is connected in series with the first gate reset transistor M2. The other electrode of the first gate reset transistor M2 is connected to the first gate reset signal PWM_REF. The gates of the first gate reset transistor M2 and the first gate reset transistor M2 are connected to the first scan signal PWM_S1. The other electrode of the first capacitor C1 is connected to the sweep signal SWEEP. The first capacitor C1 serves as a storage capacitor in the first drive circuit 10. The first compensation transistor M7 is connected in series with the second compensation transistor M8. The other electrode of the second compensation transistor M8 is connected to the first drive transistor M1. The gates of the first compensation transistor M7 and the second compensation transistor M8 are connected to the second scan signal PWM_S2. One electrode of the first writing transistor M4 is connected to the first driving transistor M1 , a gate thereof is connected to the second scanning signal PWM_S2 , and the other electrode thereof is connected to the first data signal PWM_DATA.

[0031] The second driving circuit 20 may include: a second driving transistor M9, a third gate reset transistor M10, a fourth gate reset transistor M11, a second writing transistor M12, a third control transistor M13, a fourth control transistor M14, a third compensation transistor M15, a fourth compensation transistor M16, an anode reset transistor M17 and a second capacitor C2.

[0032] The third control transistor M13, the second drive transistor M9, and the fourth control transistor M14 are connected in series. The other electrode of the third control transistor M13 is connected to the second power supply voltage signal PAM_VDD, and the gate is connected to the second light-emission control signal PAM_EM. The other electrode of the fourth control transistor M14 is connected to the anode of the light-emitting device PD and one electrode of the anode reset transistor M17. The cathode of the light-emitting device PD is connected to the third power supply voltage signal PAM_VEE. The gate of the fourth control transistor M14 is connected to the second light-emission control signal PAM_EM. The other electrode of the anode reset transistor M17 is connected to the anode reset signal PAM_INIT, and the gate is connected to the third scan signal PAM_S1. The gate of the second drive transistor M9 is connected to the fourth gate reset transistor M11, the second capacitor C2, and the third compensation transistor M15. The fourth gate reset transistor M11 is connected in series with the third gate reset transistor M10. The other electrode of the third gate reset transistor M10 is connected to the second gate reset signal PAM_REF. The gates of the fourth gate reset transistor M11 and the third gate reset transistor M10 are connected to the third scan signal PAM_S1. The other electrode of the second capacitor C2 is connected to the second power supply voltage signal PAM_VDD, and the second capacitor C2 serves as the storage capacitor of the second drive circuit. A third compensation transistor M15 and a fourth compensation transistor M16 are connected in series. The other electrode of the fourth compensation transistor M16 is connected to the second drive transistor M9 and the fourth control transistor M14. The gates of the third compensation transistor M15 and the fourth compensation transistor M16 are connected to the fourth scan signal PAM_S2. One electrode of the second write transistor M12 is connected to the second drive transistor M9, with the gate connected to the fourth scan signal PAM_S2, and the other electrode connected to the second data signal PAM_DATA.

[0033] Figure 2 This is a timing diagram of each signal during the operation of the above pixel circuit. Figure 1 and Figure 2 In one frame of the display panel, the working process of the pixel circuit includes a writing phase P1 and a light emitting phase P2.

[0034] In the writing phase P1 , the second driving circuit 20 sequentially resets the gate and writes data to the second driving transistor M9 , and the first driving circuit 10 sequentially resets the gate and writes data to the first driving transistor M1 .

[0035] Specifically, the third gate reset transistor M10 and the fourth gate reset transistor M11 can be turned on by the third scan signal PAM_S1, and the second gate reset signal PAM_REF can be written into the gate of the second drive transistor M9 to reset the gate of the second drive transistor M9. During the process of the second drive circuit 20 resetting the gate of the second drive transistor M9, the first gate reset transistor M2 and the second gate reset transistor M3 can be turned on by the first scan signal PWM_S1, and the first gate reset signal PWM_REF can be written into the gate of the first drive transistor M1 to reset the gate of the first drive transistor M1.

[0036] After the gate is reset, in the first drive circuit 10, the second scan signal PWM_S2 can be used to control the first write transistor M4, the first compensation transistor M7, and the second compensation transistor M8 to turn on, thereby writing the first data signal PWM_DATA to the gate of the first drive transistor M1 and performing threshold compensation. In the second drive circuit 20, the fourth scan signal PAM_S2 can be used to control the second write transistor M12, the third compensation transistor M15, and the fourth compensation transistor M16 to turn on, thereby writing the second data signal PAM_DATA to the gate of the second drive transistor M9 and performing threshold compensation.

[0037] In the light emitting phase P2 , the second light emitting control signal PAM_EM controls the third control transistor M13 and the fourth control transistor M14 to be turned on, and the second driving transistor M9 generates a driving current under the control of its gate voltage and provides the driving current to the light emitting device PD.

[0038] The first light-emitting control signal PWM_EM controls the conduction of the first control transistor M5 and the second control transistor M6. Simultaneously, the voltage value of the sweep signal SWEEP gradually changes, and under the coupling effect of the first capacitor C1, the gate voltage of the first drive transistor M1 changes. When the gate voltage of the first drive transistor M1 is equal to or less than the difference between the absolute value of its source voltage and the threshold voltage, the first drive transistor M1 turns on, and the first drive circuit 10 gradually raises the voltage of the node N1. Ultimately, the second drive transistor M9 transmits the voltage of the first power supply voltage signal PWM_VDD to the node N1 via the second control transistor M6, thereby causing the gate voltage of the second drive transistor M9 to change, causing the second drive transistor M9 to turn off, thereby stopping the supply of drive current to the light-emitting device PD.

[0039] During the light-emitting stage, based on the voltage control of the first power supply voltage signal PWM_VDD and the sweep signal SWEEP in the first driving circuit 10, a control current is generated to control the duration of the driving current provided by the second driving circuit 20, thereby adjusting the light-emitting duration of the light-emitting device PD, and further controlling the brightness of the light-emitting device PD.

[0040] Figure 3 FIG. 1 is a schematic diagram of another circuit structure of a pixel circuit according to an embodiment of the present invention. Figure 3 ,and Figure 1 The difference between the pixel circuit shown in Figure 3 In the embodiment, the first drive circuit 10 further includes a sweep reset transistor M18. One electrode of the sweep reset transistor M18 is connected to the first capacitor C1, the gate of the sweep reset transistor M18 is connected to the first scanning signal PWM_S1, and the other electrode of the sweep reset transistor M18 is connected to the sweep reset signal SWEEP_GND. By adding the sweep reset transistor M18, the plate of the first capacitor C1 can be reset during the write phase of the pixel circuit.

[0041] In addition, Figure 3 In the embodiment, the second driving circuit 20 further includes: a third capacitor C3 connected to the second capacitor C2, a first charging transistor M19, a second charging transistor M20, and a third charging transistor M21. The other electrode of the third capacitor C3 is connected to the anode reset signal PAM_INIT. The gate of the first charging transistor M19 is connected to the first light-emitting control signal PWM_EM, and the other electrode is connected to the second power supply voltage signal PAM_VDD. The gate of the second charging transistor M20 is connected to the third scan signal PAM_S1, and the gate of the third charging transistor M21 is connected to the fourth scan signal PAM_S2. The other electrodes of the second charging transistor M20 and the third charging transistor M21 are connected to the second power supply voltage signal PAM_VDD.

[0042] The third capacitor C3 can be used to charge the second capacitor C2 during the anode reset process, thereby controlling the second drive transistor M9 to turn on and provide a driving current to the light-emitting device PD. The third charging transistor M21 can be used to charge the second capacitor C2 during the gate reset process of the pixel circuit, thereby controlling the second drive transistor M9 to turn on and provide a driving current to the light-emitting device PD. The second charging transistor M20 can be used to charge the second capacitor C2 during the data writing process of the pixel circuit, thereby controlling the second drive transistor M9 to turn on and provide a driving current to the light-emitting device PD. The first charging transistor M19 can be used to charge the second capacitor C2 during the light-emitting phase of the pixel circuit, thereby controlling the second drive transistor M9 to turn on and provide a driving current to the light-emitting device PD.

[0043] about Figure 3 The pixel circuit shown in FIG. 3 may be specifically referred to the above Figure 1 and Figure 2 The implementation is based on the description of , which will not be repeated here.

[0044] Reference Figure 1 and Figure 3 In a borderless tiled display panel using a demultiplexer, the first data signal PWM_DATA can be output by the data driver circuit through the demultiplexer. Specifically, the first data signal PWM_DATA output by the data driver circuit after the demultiplexer first charges the first data signal line where the first data signal PWM_DATA resides. The charge stored in the parasitic capacitance of the first data signal line then charges the node capacitance connecting the first driver circuit 10 and the second driver circuit 20 to the node N1, thereby inputting the control signal to the first driver circuit 10.

[0045] However, in actual applications, since the capacitance of the node N1 is very large, which can be as high as 500fF to 1000fF, and the parasitic capacitance of the first data signal line is generally 10pF to 15pF, when the node capacitance of the node N1 is charged by the parasitic capacitance of the first data signal line, the voltage of the first data signal line will drop sharply (e.g., Figure 4 As shown in FIG, the voltage of the first data signal line and the voltage actually charged into the node capacitor of the node N1 have a large deviation, which is as high as 0.3V~1V. As a result, the writing of the first data signal PWM_DATA has a large voltage distortion, which ultimately affects the display effect.

[0046] To address this problem, the present invention provides a sub-pixel circuit, in which a first area of a first data signal line bundle connected to a first driving circuit and a constant-voltage signal line at an overlapping point is made larger than a second area of a second data signal line bundle connected to a second driving circuit and the same constant-voltage signal line at an overlapping point, thereby increasing the inter-line capacitance between the first data signal line bundle and the constant-voltage signal line, and thus increasing the parasitic capacitance of the first data signal line bundle, thereby reducing the voltage drop amplitude of the first data signal line when the data signal is written, and ultimately improving the display effect.

[0047] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] Figure 5 A schematic diagram of a pixel structure is shown. Figure 5 An embodiment of the present invention provides a pixel structure, which may include: a red (R) sub-pixel circuit 11, a green (G) sub-pixel circuit 12, and a blue (B) sub-pixel circuit 13 distributed along a first direction X.

[0049] Each sub-pixel circuit is equipped with a light-emitting device, the light-emitting intensity of which can be independently controlled. Specifically, the light-emitting device in the red sub-pixel circuit 11 can emit red light, the light-emitting device in the green sub-pixel circuit 12 can emit green light, and the light-emitting device in the blue sub-pixel circuit 13 can emit blue light.

[0050] In a specific implementation, the structures of the sub-pixel circuits may be the same or different, and there is no limitation here.

[0051] In an embodiment of the present invention, any sub-pixel circuit may include: a light-emitting device, and a first driving circuit and a second driving circuit connected to the light-emitting device; the first driving circuit is used to provide the duration of the driving current to the light-emitting device under the voltage control of a first data signal, and the second driving circuit is used to provide the amplitude of the driving current to the light-emitting device under the voltage control of a second data signal.

[0052] In a specific implementation, the first driving circuit can be implemented using a variety of circuit structures.

[0053] For example, refer to Figure 1 The first driving circuit 10 may include: a first driving transistor M1, a first gate reset transistor M2, a second gate reset transistor M3, a first write transistor M4, a first control transistor M5, a second control transistor M6, a first compensation transistor M7, a second compensation transistor M8, and a first capacitor C1. The second driving circuit 20 may include: a second driving transistor M9, a third gate reset transistor M10, a fourth gate reset transistor M11, a second write transistor M12, a third control transistor M13, a fourth control transistor M14, a third compensation transistor M15, a fourth compensation transistor M16, an anode reset transistor M17, and a second capacitor C2.

[0054] For example, refer to Figure 3 The first driving circuit 10 may further include a frequency sweep reset transistor M18. The second driving circuit 20 may further include: a third capacitor C3 connected to the second capacitor C2, a first charging transistor M19, a second charging transistor M20, and a third charging transistor M21.

[0055] For details, please refer to the above Figure 1 and Figure 3 The description of the implementation is not repeated here.

[0056] Regardless of the circuit structure used to implement the first driving circuit and the second driving circuit, each pixel circuit can access the data signal through the data signal harness. Specifically, for the same pixel structure, the pixel structure along the first side of the first direction X (for example Figure 5A first data signal line bundle 20 may be provided on the left side of the pixel structure in the middle, and a first data signal line bundle 20 may be provided on the other side along the first direction X (eg Figure 5 A second data signal line bundle 30 may be provided on the right side of the pixel structure.

[0057] The first data signal line bundle 20 extends along a second direction Y, which is co-axial with and perpendicular to the first direction X. The first data signal line bundle 20 can provide a first data signal PWM_DATA to each sub-pixel circuit in the same column. The first data signal PWM_DATA can be output by a data driver circuit through a demultiplexer. The first data signal line bundle 20 can include multiple first data signal lines, each corresponding one-to-one to a sub-pixel circuit in the pixel structure.

[0058] For example, refer to Figure 5 The first data signal line bundle 20 may include a first data signal line 201, a first data signal line 202, and a first data signal line 203. The first data signal line 201 may provide a first data signal PWM_DATA for the sub-pixel circuit 11, the first data signal line 202 may provide a first data signal PWM_DATA for the sub-pixel circuit 12, and the first data signal line 203 may provide a first data signal PWM_DATA for the sub-pixel circuit 13.

[0059] The second data signal line bundle 30 can extend along a second direction Y. The second data signal line bundle 30 can provide a second data signal PAM_DATA to each sub-pixel circuit in the same column. The second data signal PAM_DATA can be output by the data driver circuit through a demultiplexer. The second data signal line bundle 30 can include multiple second data signal lines, each corresponding one-to-one to a sub-pixel circuit in the pixel structure.

[0060] For example, refer to Figure 5 The second data signal line bundle 30 may include a second data signal line 301, a second data signal line 302, and a second data signal line 303. The second data signal line 301 may provide a second data signal PAM_DATA for the sub-pixel circuit 11, the second data signal line 302 may provide a second data signal PAM_DATA for the sub-pixel circuit 12, and the second data signal line 303 may provide a second data signal PAM_DATA for the sub-pixel circuit 13.

[0061] In an embodiment of the present invention, any sub-pixel circuit can also be connected to a constant voltage signal via a constant voltage signal line. The constant voltage signal refers to a signal whose voltage remains constant, or a signal whose fluctuation amplitude varies within a specific small range (<0.02V). Each constant voltage signal line extends along a first direction X and is arranged along a second direction Y. Through this constant voltage signal line, a constant voltage signal can be provided to all sub-pixel circuits of each pixel structure in the same row of the pixel array.

[0062] In a specific implementation, the constant voltage signal line may include: a first power supply voltage signal PWM_VDD line and a first gate reset signal PWM_REF line connected to the first drive circuit; and a second power supply voltage signal PAM_VDD line, a second gate reset signal PAM_REF line, an anode reset signal PAM_INIT line and a swept frequency reset signal SWEEP_GND line connected to the second drive circuit.

[0063] Specifically, refer to Figure 1 The first power supply voltage signal PWM_VDD line can provide the first power supply voltage signal PWM_VDD for the first drive circuit 10. The first gate reset signal PWM_REF line can provide the first gate reset signal PWM_REF, and the first gate reset signal PWM_REF is used to sequentially reset the gate of the first drive transistor M1. The second power supply voltage signal PAM_VDD line can provide the second power supply voltage signal PAM_VDD, and the second power supply voltage signal PAM_VDD can provide the power supply voltage for the second drive circuit 20. The anode reset signal PAM_INIT line can provide the anode reset signal PAM_INIT, and the anode reset signal PAM_INIT is used to reset the anode of the second drive transistor M9 in the second drive circuit 20. The sweep frequency reset signal SWEEP_GND line can provide the sweep frequency reset signal SWEEP_GND, and the sweep frequency reset signal SWEEP_GND is used to reset the plate of the first capacitor C1 in the second drive circuit 20.

[0064] In an embodiment of the present invention, a first area at the intersection of a first data signal line bundle connected to the first driver circuit and the constant-voltage signal line can be set to be larger than a second area at the intersection of a second data signal line bundle connected to the second driver circuit and the same constant-voltage signal line. This increases the inter-line capacitance between the first data signal line bundle and the constant-voltage signal line, thereby increasing the parasitic capacitance of the first data signal line bundle. This reduces the voltage drop on the first data signal line when writing data signals, prevents excessive voltage distortion, and ultimately improves the display effect.

[0065] Figure 6 for Figure 5 Schematic diagram of the local cross-sectional structure of the pixel structure layout along the first direction X. Figure 6 Along the cross-sectional direction, the first driving circuit and the second driving circuit layout structure of the pixel structure may include, in sequence: a glass substrate Glass, a zeroth metal layer M0 located above the glass substrate Glass, an active layer poly located above the zeroth metal layer M0, a gate insulating layer G1 covering the active layer poly, a first metal layer M1 located above the gate insulating layer G1, a capacitor insulating layer IMD covering the first metal layer M1, a capacitor layer MC located above the capacitor insulating layer IMD, an interlayer insulating layer ILD covering the capacitor layer MC, a second metal layer M2 located above the interlayer insulating layer ILD, a first planar layer PV1 covering the second metal layer M2, a second planar layer PLN1 located above the first planar layer PV1, a third metal layer M3 located above the second planar layer PLN1, a third planar layer PLN2 covering the third metal layer M3, a fourth metal layer M4 located on the third planar layer PLN2, and a fourth planar layer PV2 covering the fourth metal layer M4. A light-emitting device is formed above the fourth planar layer PV2.

[0066] In a specific implementation, the first metal layer M1 can serve as a gate and partial signal routing layer. The capacitor layer MC can serve as a capacitor layer and partial signal routing layer. The second metal layer M2 can serve as a partial signal routing layer. The third metal layer M3 can also serve as a partial signal routing layer. The fourth metal layer M4 can serve as a corresponding electrode layer and a power signal line layer.

[0067] from Figure 6 It can be seen that along the cross-sectional direction perpendicular to the layout, the data signal line bundle and the constant voltage signal line overlap, and the area of the overlap will affect the parasitic capacitance of the first data signal line bundle.

[0068] The first area of the intersection of the first data signal line bundle and the constant-voltage signal line refers to the sum of the areas of the intersections of each first data signal line in the first data signal line bundle and the same constant-voltage signal line. Similarly, the second area of the intersection of the second data signal line bundle of the second driver circuit and the same constant-voltage signal line refers to the sum of the areas of the intersections of each second data signal line in the second data signal line bundle and the same constant-voltage signal line. Each constant-voltage signal line corresponds to a first area and a second area. The first area corresponding to the same constant-voltage signal line is greater than its corresponding second area.

[0069] It can be understood that, relative to the prior art, among all the constant voltage signal lines that provide constant voltage signals to the sub-pixel circuit, as long as the first area corresponding to one constant voltage signal line or two or more constant voltage signal lines is larger than the second area corresponding to the same, the purpose of increasing the inter-line capacitance between the first data signal line bundle and the constant voltage signal line can be achieved.

[0070] For example, refer to Figure 5 The first area may be the sum of the areas of the first data signal lines 201 to 203 in the first data signal line bundle 20 at their intersection with the first power supply voltage signal line PWM_VDD. Correspondingly, the second area may be the sum of the areas of the second data signal lines 301 to 303 in the second data signal line bundle 30 at their intersection with the first power supply voltage signal line PWM_VDD.

[0071] The first area may be the sum of the areas of the first data signal lines 201 to 203 in the first data signal line bundle 20 and the first gate reset signal PWM_REF line at their intersections. The corresponding second area may be the sum of the areas of the second data signal lines 301 to 303 in the second data signal line bundle 30 and the first gate reset signal PWM_REF line at their intersections.

[0072] In a specific implementation, various methods can be used to make the first area corresponding to the same constant voltage signal line larger than the second area corresponding to the same constant voltage signal line.

[0073] In one embodiment of the present invention, the line width of the first data signal line bundle and the constant voltage signal line at the intersection can be set to be greater than the line width of the second data signal line bundle and the same constant voltage signal line at the intersection. That is, by increasing the line width of the first data signal line bundle, the inter-line capacitance between the first data signal line bundle and the constant voltage signal line is increased. The line width of the first data signal line bundle and the constant voltage signal line at the intersection refers to the sum of the line widths of each first data signal line in the first data signal line bundle and the constant voltage signal line at the intersection. The line width of the second data signal line bundle and the same constant voltage signal line at the intersection refers to the sum of the line widths of each second data signal line in the second data signal line bundle and the same constant voltage signal line at the intersection.

[0074] Specifically, refer to Figure 5 The line width at the intersection of the first data signal line bundle 20 and the swept-frequency reset signal SWEEP_GND line refers to the sum of the line widths of the first data signal lines 201 to 203 in the first data signal line bundle 20 at the intersection with the swept-frequency reset signal SWEEP_GND line. For example, only the line width at the intersection of the first data signal line 201 and the swept-frequency reset signal SWEEP_GND line can be increased, while the line width at the intersection of the first data signal line 202 and the swept-frequency reset signal SWEEP_GND line remains unchanged. Alternatively, only the line widths at the intersection of the first data signal line 201 and the first data signal line 202 and the swept-frequency reset signal SWEEP_GND line can be increased, while the line width at the intersection of the first data signal line 203 and the swept-frequency reset signal SWEEP_GND line remains unchanged.

[0075] In one embodiment, the line width of each first data signal line in the first data signal line bundle at the intersection with the constant-voltage signal line can be set to be greater than the line width of each second data signal line in the second data signal line bundle at the intersection with the same constant-voltage signal line. That is, the line width of each first data signal line in the first data signal line bundle at the intersection with the constant-voltage signal line is greater than the maximum line width of each second data signal line in the second data signal line bundle at the intersection with the same constant-voltage signal line.

[0076] Specifically, refer to Figure 5 The line widths of the first data signal lines 201 to 203 at the intersections with the second power supply voltage signal line PAM_VDD can be set to be greater than the maximum value of the line widths of the second data signal line 301, the second data signal line 303 and the second power supply voltage signal line PAM_VDD at the intersections.

[0077] In a specific implementation, the line width of each first data signal line in the first data signal line bundle and the constant voltage signal line at the overlapped portion can be set to 6um to 8um. The line width of each first data signal line and the constant voltage signal line at the overlapped portion can be the same or different. For example, referring to Figure 5 , the line width of the first data signal line 201 and the second power supply voltage signal PAM_VDD line at the overlap can be set to 6um, the line width of the first data signal line 202 and the second power supply voltage signal PAM_VDD line at the overlap can be set to 7um, and the line width of the first data signal line 203 and the second power supply voltage signal PAM_VDD line at the overlap can be set to 8um.

[0078] In a specific implementation, the line width of each second data signal line in the second data signal line bundle at the intersection with the constant voltage signal line can be set to 3um to 5.6um. The line width of each second data signal line at the intersection with the same constant voltage signal line can be the same or different. For example, referring to Figure 5 , the line width of the second data signal line 301 and the second power supply voltage signal PAM_VDD line at the overlap can be set to 3um, the line width of the second data signal line 302 and the second power supply voltage signal PAM_VDD line at the overlap can be set to 4um, and the line width of the first data signal line 203 and the second power supply voltage signal PAM_VDD line at the overlap can be set to 5.2um.

[0079] In another embodiment of the present invention, the area of the constant voltage signal line at the intersection with the first data signal line bundle can be set to be larger than the area of the same constant voltage signal line at the intersection with the second data signal line bundle. That is, by increasing the area of the constant voltage signal line at the intersection with the first data signal line bundle, the inter-line capacitance between the first data signal line bundle and the constant voltage signal line is increased. The area of the constant voltage signal line at the intersection with the first data signal line bundle refers to the sum of the line widths of the constant voltage signal line and each first data signal line in the first data signal line bundle at the intersection. The area of the constant voltage signal line at the intersection with the second data signal line bundle refers to the sum of the line widths of the constant voltage signal line and each second data signal line in the second data signal line bundle at the intersection.

[0080] It can be understood that, relative to the prior art, among all the constant voltage signal lines that provide constant voltage signals to the sub-pixel circuit, as long as one constant voltage signal line or two or more constant voltage signal lines have a larger area at the intersection with the first data signal line bundle than the area at the intersection with the second data signal line bundle, the purpose of increasing the inter-line capacitance between the first data signal line bundle and the constant voltage signal line can be achieved.

[0081] For example, refer to Figure 5 The area of the intersection of the first power supply voltage signal PWM_VDD line and the first data signal line bundle 20 is the sum of the areas of the intersections of the first power supply voltage signal PWM_VDD line and the first data signal lines 201 to 203. Correspondingly, the area of the intersection of the first power supply voltage signal PWM_VDD line and the second data signal line bundle 30 is the sum of the areas of the intersections of the first power supply voltage signal PWM_VDD line and the second data signal lines 301 to 303.

[0082] In a specific implementation, various methods can be used to make the area of the same constant voltage signal line at the point where it overlaps with the first data signal line bundle larger than the area at the point where it overlaps with the second data signal line bundle.

[0083] In one embodiment of the present invention, the constant-voltage signal line may have the same line width at the intersection with the first data signal line bundle and the intersection with the second data signal line bundle, and may include a first slot at the intersection with the second data signal line bundle. The first slot may be a through-hole formed in the constant-voltage signal line, the first slot being surrounded by the remaining portion of the constant-voltage signal line. The second data signal line bundle covers the first slot and overlaps with the constant-voltage signal line outside the first slot.

[0084] Since the line width of the same constant-voltage signal line is the same at the intersection with the first data signal line bundle and the intersection with the second data signal line bundle, the provision of the first slot can reduce the area of the intersection of the constant-voltage signal line and the second data signal line bundle. Thus, without changing the line width of the constant-voltage signal line, the area of the same constant-voltage signal line at the intersection with the first data signal line bundle can be made larger than the area of the same constant-voltage signal line at the intersection with the second data signal line bundle.

[0085] In a specific implementation, the first slot of the constant voltage signal line at the intersection with the second data signal line bundle may only overlap with a portion of the second data signal lines in the second data signal line bundle, that is, the first slot exists only on the constant voltage signal line that overlaps with a portion of the second data signal lines, and the first slot does not exist on the constant voltage signal line that overlaps with another portion of the second data signal lines.

[0086] In one embodiment of the present invention, the first slot can be arranged to overlap with each second data signal line in the second data signal line bundle along the extension direction of the constant voltage signal line. That is, the first slot overlaps with each second data signal line in the second data signal line bundle, thereby minimizing the area where the constant voltage signal line and the second data signal line bundle overlap.

[0087] In a specific implementation, the first slot can be set only for constant-voltage signal lines whose line width exceeds a set line width threshold (for example, >5 μm). The shape of the first slot can be regular or irregular, depending on the line width of the constant-voltage signal line. For example, the first slot can be set to a square or rectangular shape, which is not limited here.

[0088] Specifically, Figure 7 for Figure 5 FIG. 1 is a partial enlarged schematic diagram of the first data signal harness 20 . Figure 8 for Figure 5 Schematic diagram of a partial enlargement of the second data signal harness 30. Figure 7 and Figure 8 No first slot is provided at the intersection of the first power supply voltage signal PWM_VDD line and the first data signal line bundle 20, but a first slot 61 is provided at the intersection with the second data signal line bundle 30, and the first slot 61 overlaps with the second data signal lines 301 to 303 in the second data signal line bundle 30 along the extension direction of the first power supply voltage signal PWM_VDD line.

[0089] No first slot is provided at the intersection of the anode reset signal PAM_INIT line and the first data signal line bundle 20, but a first slot 62 is provided at the intersection with the second data signal line bundle 30, and the first slot 62 overlaps with the second data signal lines 301 to 303 in the second data signal line bundle 30 along the extension direction of the anode reset signal PAM_INIT line.

[0090] In the specific implementation, refer to Figure 2 For any sub-pixel circuit, the first and second driver circuits also receive a fluctuation signal via a fluctuation signal line. The fluctuation signal refers to a signal with a large voltage fluctuation amplitude, typically greater than (>0.1V). Each fluctuation signal line extends along a first direction X and is arranged along a second direction Y. Through these fluctuation signal lines, a fluctuation signal can be provided to all sub-pixel circuits in each pixel structure within the same row of the pixel array.

[0091] In a specific implementation, the fluctuation signal line may include: a first scanning signal PWM_S1 line, a second scanning signal PWM_S2 line, and a first light-emitting control signal PWM_EM line connected to the first driving circuit; and a third scanning signal PAM_S1 line, a fourth scanning signal PAM_S2 line, a second light-emitting control signal PAM_EM line and a sweep signal SWEEP line connected to the second driving circuit.

[0092] The first scanning signal PWM_S1 line can provide the first scanning signal PWM_S1, and the first scanning signal PWM_S1 is used to control the first gate reset transistor M2 and the second gate reset transistor M3 (such as Figure 1 The second scanning signal PWM_S2 line can provide the second scanning signal PWM_S2, and the first writing transistor M4, the first compensation transistor M7 and the second compensation transistor M8 (as shown in FIG. Figure 1As shown). The first light-emitting control signal PWM_EM line can provide the first light-emitting control signal PWM_EM, which is used to control the first control transistor M5 and the second control transistor M6. The third scan signal PAM_S1 line can provide the third scan signal PAM_S1, which is used to control the third gate reset transistor M10 and the fourth gate reset transistor M11. The fourth scan signal PAM_S2 line can provide the fourth scan signal PAM_S2, which is used to control the second write transistor M12, the third compensation transistor M15, and the fourth compensation transistor M16. The second light-emitting control signal PAM_EM line can provide the second light-emitting control signal PAM_EM, which is used to control the third control transistor M13 and the fourth control transistor M14. The sweep signal SWEEP line can provide the sweep signal SWEEP, which is used to control the first drive transistor M1.

[0093] The inventors have found that if the overlapping area between the oscillating signal line and the data signal line bundle is too large, the parasitic capacitance of the oscillating signal line will be too large, and the oscillating signal will crosstalk to the corresponding overlapping data signal line bundle through the parasitic capacitance, thereby affecting the display effect.

[0094] To address this problem, in one embodiment of the present invention, the parasitic capacitance of the oscillating signal line can be reduced by reducing the overlapping area between the oscillating signal line and the data signal line bundle, thereby improving the crosstalk situation.

[0095] In a specific implementation, various methods can be used to reduce the overlapping area between the oscillation signal line and the data signal line bundle, which are not limited here.

[0096] In one embodiment of the present invention, at least one of the first data signal line bundle and the second data signal line bundle may have a line width greater than a line width at an intersection with the constant voltage signal line.

[0097] Specifically, the line width of the first data signal line bundle at the intersection with the constant voltage signal line can be set to be greater than the line width of the first data signal line bundle at the intersection with the fluctuating signal line. Alternatively, the line width of the second data signal line bundle at the intersection with the constant voltage signal line can be set to be greater than the line width of the second data signal line bundle at the intersection with the fluctuating signal line. Alternatively, the line widths of the first and second data signal line bundles at the intersection with the constant voltage signal line can be set to be greater than the line widths of their respective data signal line bundles at the intersection with the fluctuating signal line.

[0098] In a specific implementation, if the line width of the first data signal line bundle at the intersection with the fluctuating signal line is smaller than its line width at the intersection with the constant-voltage signal line, the line width of the first data signal line bundle at the intersection without overlapping with the fluctuating signal line and the constant-voltage signal line can be set to be equal to its line width at the intersection with the constant-voltage signal line. In this case, the line width of the first data signal line bundle at the intersection with the fluctuating signal line is equivalent to a "neck-down" setting relative to the line width of the first data signal line bundle at the intersection with the constant-voltage signal line.

[0099] Among them, it is possible to set the line width of only some of the first data signal lines in the first data signal line bundle at the overlap with the constant voltage signal line to be larger than the line width at the overlap with the fluctuation signal line, or it is possible to set the line width of all the first data signal lines at the overlap with the constant voltage signal line to be larger than the line width at the overlap with the fluctuation signal line.

[0100] If the line width of the second data signal line bundle at the intersection with the fluctuating signal line is smaller than the line width at the intersection with the constant-voltage signal line, the line width of the second data signal line bundle at the intersection without overlapping with the fluctuating signal line and the constant-voltage signal line can be set equal to the line width at the intersection with the constant-voltage signal line. In this case, the line width of the second data signal line bundle at the intersection with the fluctuating signal line is equivalent to a "neck-down" setting relative to the line width of the second data signal line bundle at the intersection with the constant-voltage signal line.

[0101] The line widths of only some of the second data signal lines in the second data signal line bundle at the intersection with the constant voltage signal line may be greater than the line widths at the intersection with the fluctuating signal line, or the line widths of all the second data signal lines at the intersection with the constant voltage signal line may be greater than the line widths at the intersection with the fluctuating signal line. In a specific implementation, the line widths of the second data signal line bundle corresponding to the fluctuating signal lines having a smaller line width (e.g., a line width between 1 μm and 5 μm) may be greater at the intersection with the constant voltage signal line than at the intersection with the fluctuating signal line.

[0102] For example, refer to Figure 7 , the line width of each of the first data signal lines 201 to 203 in the first data signal line bundle 20 at the intersection with the first scanning signal PWM_S1 line can be set to be smaller than the line width at the intersection with the constant voltage signal line (such as the sweep reset signal SWEEP_GND line, the first power supply voltage signal PWM_VDD line, the first gate reset signal PWM_REF, etc.).

[0103] Reference Figure 8, the line width of each of the second data signal lines 301 to 303 in the second data signal line bundle 30 at the intersection with the first scanning signal PWM_S1 line can be set to be smaller than the line width at the intersection with the constant voltage signal line (such as the sweep reset signal SWEEP_GND line, the first power supply voltage signal PWM_VDD line, the first gate reset signal PWM_REF, etc.).

[0104] For example, refer to Figure 7 The line widths of the first data signal lines 201 to 203 in the first data signal line bundle 20 at the locations where they overlap with the second scan signal PWM_S2 line may be smaller than the line widths at the locations where they overlap with the constant voltage signal line.

[0105] Reference Figure 8 The line widths of the second data signal lines 301 to 303 in the second data signal line bundle 30 at the locations where they overlap with the second scan signal PWM_S2 line can be smaller than the line widths at the locations where they overlap with the constant voltage signal line.

[0106] In one embodiment of the present invention, the overlapping area between the oscillating signal line and the data signal line bundle can be reduced by providing a slot on the oscillating signal line.

[0107] Specifically, some of the fluctuating signal lines may be provided with second slots at locations where they overlap with at least one of the first and second data signal line bundles. Providing the second slots at the locations where the fluctuating signal lines overlap with the data signal line bundles can reduce the overlapping area between the fluctuating signal lines and the data signal line bundles. This significantly reduces the area of the fluctuating signal lines where they overlap with the data signal line bundles without changing the width of the fluctuating signal lines, thereby reducing parasitic capacitance of the fluctuating signal lines.

[0108] In a specific implementation, the second slot may be provided only at the intersection with the first data signal line bundle, only at the intersection with the second data signal line bundle, or both at the intersection with the first data signal line bundle and the intersection with the second data signal line bundle. The second slot is provided on the constant voltage signal lines whose width exceeds a set line width threshold (e.g., >12 μm).

[0109] In a specific implementation, the second slot can be a through-hole formed in the oscillation signal line. The second slot is surrounded by the remaining portion of the oscillation signal line. The data signal line bundle covers the second slot and overlaps with the oscillation signal line outside the second slot. The shape of the second slot can be regular or irregular, depending on the line width of the constant voltage signal line. For example, the second slot can be square or rectangular, but this is not limited here.

[0110] In one embodiment of the present invention, the second slot may overlap with each first data signal line in the first data signal line bundle or overlap with each second data signal line in the second data signal line bundle along the extension direction of the oscillation signal line.

[0111] That is, each first data signal line in the first data signal line bundle covers the second slot, and each second data signal line in the second data signal line bundle also covers the second slot, thereby minimizing the overlap area between the fluctuation signal line and the first data signal line or the second data signal line.

[0112] Specifically, refer to Figure 7 , a second slot 63 may be provided at the intersection of the sweep signal SWEEP line and the first data signal line 20, and the first data signal lines 201 to 203 all cover the second slot 63. Figure 8 A second slot 64 may be further provided at the intersection of the sweep signal SWEEP line and the second data signal line bundle 30 , and the second data signal lines 301 to 303 all cover the second slot 64 .

[0113] Figure 9 Figure 5 FIG. 1 is an enlarged schematic diagram of area A on the first data signal harness 20 . Figure 10 for Figure 5 Schematic diagram of the enlarged area B on the first data signal harness 30. Figure 9 , a second slot 65 may be provided at the intersection of the second light emitting control signal PAM_EM line and the first data signal line 20, and the first data signal lines 201 to 203 all cover the second slot 65. Figure 10 A second slot 66 may be further provided at the intersection of the second light emitting control signal PAM_EM line and the second data signal line bundle 30 , and the second data signal lines 301 to 303 all cover the second slot 66 .

[0114] As can be seen from the above, the present invention's solution can employ a capacitance-increasing design to increase the parasitic capacitance of the first data signal PWM_DATA line to meet the technical requirements of the data signal harness. To reduce crosstalk, the PWM signal line can employ a grooved or tapered design based on the thickness of the overlapped area. This can improve display quality.

[0115] An embodiment of the present invention further provides a display panel, which includes a pixel array. The pixel array can be formed by arranging the pixel structures in the above embodiments in an array.

[0116] The present invention further provides a display device, which includes the above-mentioned display panel.

[0117] In a specific implementation, the display device includes but is not limited to any electronic device with a display function, such as a touch screen display, a mobile phone, a tablet computer, a laptop computer, an e-reader or a television.

[0118] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A sub-pixel circuit, characterized in that: include: A light emitting device, and a first driving circuit and a second driving circuit connected to the light emitting device; The first driving circuit is used to provide a duration of a driving current to the light emitting device under the voltage control of a first data signal, and the second driving circuit is used to provide an amplitude of a driving current to the light emitting device under the voltage control of a second data signal; The first drive circuit and the second drive circuit are connected to the constant voltage signal through the constant voltage signal line and the data signal through the data signal harness; The first area where the first data signal line bundle connected to the first driving circuit overlaps with the constant voltage signal line is larger than the second area where the second data signal line bundle connected to the second driving circuit overlaps with the same constant voltage signal line.

2. The sub-pixel circuit according to claim 1, wherein: The line width of the first data signal line bundle at the overlapping portion with the constant voltage signal line is greater than the line width of the second data signal line bundle at the overlapping portion with the same constant voltage signal line.

3. The sub-pixel circuit according to claim 2, wherein: The line width of each first data signal line in the first data signal line bundle at the intersection with the constant voltage signal line is greater than the line width of each second data signal line in the second data signal line bundle at the intersection with the same constant voltage signal line.

4. The sub-pixel circuit according to claim 3, wherein: The line width of each first data signal line in the first data signal line bundle at the overlapping portion with the constant voltage signal line ranges from 6 μm to 8 μm.

5. The sub-pixel circuit according to claim 3, wherein: The line width of each second data signal line in the second data signal line bundle at the overlapping portion with the constant voltage signal line ranges from 3 μm to 5.6 μm.

6. The sub-pixel circuit according to claim 1, wherein: An area of the constant voltage signal line at a location where it overlaps with the first data signal line bundle is larger than an area of the same constant voltage signal line at a location where it overlaps with the second data signal line bundle.

7. The sub-pixel circuit according to claim 6, wherein: The same constant voltage signal line has the same line width at a location where it overlaps with the first data signal line bundle and at a location where it overlaps with the second data signal line bundle, and has a first slot at a location where it overlaps with the second data signal line bundle.

8. The sub-pixel circuit according to claim 7, wherein: The first slot overlaps with each second data signal line in the second data signal line bundle along an extending direction of the constant voltage signal line where the first slot is located.

9. The sub-pixel circuit according to claim 1, wherein: The first driving circuit and the second driving circuit are connected to the fluctuation signal through the fluctuation signal line; At least one of the first data signal line bundle and the second data signal line bundle has a line width at an intersection with the constant voltage signal line that is greater than a line width at an intersection with the fluctuation signal line.

10. The sub-pixel circuit according to claim 1, wherein: The first driving circuit and the second driving circuit are connected to the oscillation signal through the oscillation signal line; part of the oscillation signal line has a second slot at the intersection with at least one of the first data signal line bundle and the second data signal line bundle.

11. The sub-pixel circuit according to claim 10, wherein: The second slot overlaps with each first data signal line in the first data signal line bundle or overlaps with each second data signal line in the second data signal line bundle along an extending direction of the oscillating signal line where the second slot is located.

12. The sub-pixel circuit according to claim 9 or 10, wherein: The oscillation signal lines include: a first scanning signal line, a second scanning signal line, and a first light-emitting control signal line connected to the first driving circuit; and a third scanning signal line, a fourth scanning signal line, a second light-emitting control signal line, and a frequency scanning signal line connected to the second driving circuit.

13. The sub-pixel circuit according to claim 1, wherein: The constant voltage signal line extends along a first direction, and the first data signal line and the second data signal line extend along a second direction. The first direction and the second direction are located in the same plane and are perpendicular to each other.

14. The sub-pixel circuit according to claim 1, wherein: The constant voltage signal line includes: a first power supply voltage signal line and a first gate reset signal line connected to the first driving circuit; and a second power supply voltage signal line, a second gate reset signal line, an anode reset signal line and a swept frequency reset signal line connected to the second driving circuit.

15. A pixel structure, characterized in that: include: A red sub-pixel circuit, a green sub-pixel circuit, and a blue sub-pixel circuit distributed along a first direction, wherein any sub-pixel circuit among the red sub-pixel circuit, the green sub-pixel circuit, and the blue sub-pixel circuit is as described in any one of claims 1 to 14.

16. A display panel, characterized in that: include: A pixel array, wherein the pixel array is formed by arranging the pixel structures according to claim 15 in an array.

17. A display device, characterized in that: The display panel according to claim 16 is included.

Images