Display device

Abstract

The invention relates to a display device. The display device may include a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels, at least one of the plurality of pixels including a main sub-pixel group having a 1-1 sub-pixel, a 2-1 sub-pixel, and a 3-1 sub-pixel, and a redundant sub-pixel group having a (1-2) th sub-pixel, a (2-2) th sub-pixel, and a (3-2) th sub-pixel. And a controller configured to drive the main sub-pixel group and the redundant sub-pixel group in an alternating manner to display an image. Further, the (1-1) th sub-pixel and the (1-2) th sub-pixel are configured to emit light of the same first color, the (2-1) th sub-pixel and the (2-2) th sub-pixel are configured to emit light of the same second color, and the (3-1) th sub-pixel and the (3-2) th sub-pixel are configured to emit light of the same third color.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] Various flat panel display devices, such as liquid crystal displays (LCDs) and electroluminescent displays (ELDs), can be used to display information to users. ELDs can display input images without a backlight by using a light-emitting element (LED) located in each pixel to emit light. The light-emitting elements of ELDs can be categorized as organic or inorganic, depending on the material used in the light-emitting layer.

[0003] In recent years, display devices using light-emitting diodes (LEDs), a type of inorganic light-emitting device, as the light-emitting element of pixels have attracted attention as next-generation display devices. Because LEDs are made of inorganic materials, they do not require a separate encapsulation layer to protect the organic material from moisture, and they have excellent reliability and a longer lifespan than OLEDs. LEDs also have a fast lighting speed, excellent luminous efficiency, and are impact-resistant. Summary of the Invention

[0004] The pixel circuit drive period within a frame period can be divided into a period for writing pixel data and a period for emitting light from the input image. However, since the pixel data of the input image, scanning signals, and emitting signals must be continuously supplied for each frame to drive the pixel circuit, it consumes a large amount of power, requires a large amount of response power, and causes various heating issues. Therefore, there is a need for a display device with a configuration that can reduce power consumption, improve image quality, and extend the life of the device.

[0005] The present disclosure is directed to addressing all of the above-mentioned needs and problems.

[0006] The present disclosure provides a display device.

[0007] It should be noted that the objects of the present disclosure are not limited to the above objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following description.

[0008] A display device according to an embodiment of the present disclosure may include a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged, wherein each of the plurality of pixels includes a sub-pixel of a first color, which includes a 1-1th sub-pixel and a 1-2th sub-pixel; a sub-pixel of a second color, which includes a 2-1th sub-pixel and a 2-2nd sub-pixel; and a sub-pixel of a third color, which includes a 3-1th sub-pixel and a 3-2nd sub-pixel, and wherein the 1-1th sub-pixel, the 2-1st sub-pixel, and the 3-1st sub-pixel are alternately driven with the 1-2nd sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel at intervals of at least one frame period.

[0009] A display device according to an embodiment of the present disclosure may include: a display panel in which a plurality of data lines, a plurality of gate lines, and a plurality of pixels are arranged; a data driver configured to output a data voltage to the data lines; a gate driver configured to output a gate signal to the gate lines; and a timing controller configured to apply pixel data of an input image and a data timing control signal to the data driver and to apply a gate timing control signal to the gate driver, wherein the timing controller determines whether the pixel data of the input image is a still image for each frame, and as a result of the determination, modulates the data timing control signal and the gate timing control signal if the pixel data of the input image is a still image.

[0010] The present disclosure can reduce power consumption by alternately driving the main sub-pixels and the redundant sub-pixels for each color, but synchronizing the data signal and the scan signal so that they are turned on or off at the same time for at least each frame when the input image has a still image or the driving frequency is low.

[0011] The present disclosure can also reduce power consumption by turning off the light emitting signal at least for each frame when the image is a still image or the driving frequency is low.

[0012] In the present disclosure, since power consumption can be reduced, low-power driving is enabled.

[0013] The effects of the present specification are not limited to the above-mentioned effects, and other effects that are not mentioned will be clearly understood by those skilled in the art from the following description and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0015] Figure 1A and Figure 1B is a block diagram illustrating a display device according to one embodiment of the present disclosure;

[0016] Figure 2 is a diagram showing an example of a tiled display;

[0017] Figure 3 is a diagram showing a unit pixel structure according to a first embodiment of the present disclosure;

[0018] Figure 4 is a circuit diagram showing a pixel circuit according to one embodiment of the present disclosure;

[0019] Figure 5 It is shown that it is applicable to Figure 4A circuit diagram of an example of a pixel circuit is shown;

[0020] Figure 6 It shows Figure 5 A diagram showing the driving timing of the pixel circuit shown;

[0021] 7A to 7D Is used to illustrate Figure 5 A circuit diagram illustrating the operating principle of a pixel circuit;

[0022] Figure 8A and Figure 8B is a diagram for explaining the operating principle of the timing controller;

[0023] Figure 9 is a flowchart illustrating a pixel driving method according to an embodiment of the present disclosure;

[0024] Figure 10 and Figure 11 is a diagram for explaining the pixel driving principle according to the first embodiment;

[0025] Figures 12 to 14 is a diagram for explaining a pixel driving principle according to a second embodiment;

[0026] Figure 15 is a diagram showing a unit pixel structure according to a second embodiment of the present disclosure; and

[0027] Figure 16 and Figure 17 A diagram for explaining the pixel driving principle according to the third embodiment. DETAILED DESCRIPTION

[0028] The advantages and features of this specification and the methods for achieving them will become apparent by referring to the embodiments described in detail in conjunction with the accompanying drawings. However, this specification is not limited to the embodiments to be described below and can be implemented in different forms. The embodiments are provided only to fully disclose this disclosure and fully convey the scope of this disclosure to those skilled in the art, and this specification is limited only by the claims disclosed.

[0029] Since the shapes, sizes, proportions, angles, quantities, etc. disclosed in the drawings for describing the embodiments of the present disclosure are merely exemplary, the present disclosure is not limited to the items shown. Throughout the specification, the same reference numerals indicate the same components. In addition, when describing the present disclosure, if it is determined that a detailed description of a related known technology may unnecessarily obscure the key points of the present disclosure, its detailed description will be omitted.

[0030] When “including,” “having,” “consisting of,” etc. are used in this specification, other parts may be added unless “only” is used. Unless otherwise clearly stated, the case of expressing a component in the singular includes the plural form.

[0031] When explaining the components, it should be understood that the error range is included even when there is no separate explicit description.

[0032] In the case of describing a positional relationship, for example, when the positional relationship of two parts is described as "on...", "upper", "lower", "next to", etc., unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0033] Although the terms "first," "second," and so on are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below can also be the second component within the technical spirit of the present disclosure.

[0034] Like reference numerals may refer to substantially like elements throughout this disclosure.

[0035] The following embodiments may be partially or completely combined or combined with each other, and may be linked and operated in various ways in terms of technology. The embodiments may be performed independently or in association with each other.

[0036] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0037] In the display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polysilicon TFTs including low temperature polysilicon (LTPS), etc.

[0038] A transistor is a three-electrode device consisting of a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers begin flowing from the source. The drain is the electrode through which carriers exit the transistor. In a transistor, carriers flow from the source to the drain. In an n-channel transistor, since the carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current flow direction from the drain to the source. In a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, the present disclosure is not limited by the source and drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0039] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than a threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0040] The transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage, and the gate-off voltage may be a gate low voltage. In the case of a p-channel transistor, the gate-on voltage may be a gate low voltage, and the gate-off voltage may be a gate high voltage.

[0041] Figure 1A and Figure 1B is a block diagram illustrating a display device according to one embodiment of the present disclosure. Figure 2 is a diagram showing an example of a tiled display. Figure 3 is a diagram illustrating a unit pixel structure according to a first embodiment of the present disclosure.

[0042] Reference Figure 1A and Figure 1B A display device according to one embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data to pixels 101 of the display panel 100, and a power supply 140 for generating power required to drive the pixels 101 and the display panel driving circuit.

[0043] The substrate of the display panel 100 may be a plastic substrate, a thin glass substrate, or a metal substrate, but is not limited thereto. The display panel 100 may be a rectangular panel having a length in the X-axis direction (or the first direction), a width in the Y-axis direction (or the second direction), and a thickness in the Z-axis direction (or the third direction), but is not limited thereto. For example, at least a portion of the display panel 100 may have a curved periphery.

[0044] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be applied to a transparent display device, where an image is displayed on a screen and a real object is visible outside the display panel. The display panel 100 can be manufactured as a flexible display panel. In addition, the display panel 100 can be manufactured as a stretchable panel that can be extended.

[0045] The display area AA of the display panel 100 includes a pixel array that displays an input image. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels 101 arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels 101. The power lines are commonly connected to the pixels 101 to supply the pixels with a constant voltage required to drive the pixels 101. The power lines can be implemented as long strips of wiring along the first direction or the second direction, or can be implemented as grid wiring in which wiring in the first direction is electrically connected to wiring in the second direction.

[0046] Each of the pixels 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color realization. Each of the pixels can also include a white sub-pixel. Each of the sub-pixels includes a pixel circuit for driving a light-emitting element. The pixel circuit is connected to a data line, a gate line, and a power line. Hereinafter, "pixel" may be interpreted as "sub-pixel."

[0047] The pixel array includes a plurality of pixel rows L(1) to L(N). Each of the pixel rows L(1) to L(N) includes a row of pixels arranged along a gate line direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel row can share a gate line 103. The pixels arranged in a column direction (Y-axis direction) along a data line direction can share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of pixel rows L(1) to L(N).

[0048] The power supply 140 uses a direct current (DC)-DC converter to generate a constant voltage (or DC voltage) required to drive the pixel array and display panel driving circuit of the display panel 100. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. The power supply 140 can adjust the level of the input voltage input from the host system 200 to output a constant voltage, such as a gamma reference voltage, a data drive voltage, a gate low voltage, a gate high voltage, a pixel drive voltage, and a pixel base voltage. The gamma reference voltage and the data drive voltage are supplied to the data driver 110. The dynamic range of the data voltage output from the data driver 110 is determined by the voltage range of the gamma reference voltage. The dynamic range of the data voltage is the voltage range between the highest grayscale voltage and the lowest grayscale voltage. The data drive voltage is a voltage supplied from each channel of the data driver 110 to the VDD terminal of the output buffer to drive the output buffer.

[0049] The gate high voltage and the gate low voltage are supplied to the level shifter 150 and the gate driver 120. Constant voltages such as the pixel driving voltage and the pixel base voltage are supplied to the pixels 101 through power supply lines commonly connected to the pixels 101. The pixel driving voltage can be supplied to the display panel 100 from the main power supply of the host system 200. In this case, the power supply 140 does not need to output the pixel driving voltage.

[0050] The display panel driving circuit writes pixel data of an input image into pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0051] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1A and Figure 1B The touch sensor driver is omitted. The data driver 110 and the touch sensor driver can be integrated into a single driver integrated circuit (IC). The timing controller 130, power supply 140, level shifter 150, data driver 110, touch sensor driver, etc. can also be integrated into the driver IC.

[0052] The data driver 110 receives pixel data of an input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 converts the pixel data of the input image into a gamma compensation voltage using a digital-to-analog converter (DAC) and outputs the data voltage. The gamma reference voltage is divided into gamma compensation voltages for each grayscale by a voltage divider circuit of the data driver 110 and supplied to the DAC. The DAC generates a data voltage having a gamma compensation voltage corresponding to the grayscale value of the pixel data. The data voltage output from the DAC is output to the data line 102 via an output buffer in each of the data output channels of the data driver 110.

[0053] The gate driver 120 may be formed in the display panel 100 together with the TFT array and wiring of the pixel array. The gate driver 120 may be disposed in the non-display area NA outside the display area AA in the display panel 100, or at least a portion thereof may be disposed in the display area AA. For example, the gate driver 120 may be embedded in the display area AA, as shown in FIG. Figure 1B In this case, the pixel circuit and the light emitting element of the pixel 101 may overlap with the circuit of the gate driver 120 in the Z-axis direction of the display panel 100 .

[0054] The gate driver 120 may be disposed in the left non-display area NA or the right non-display area NA outside the display area AA in the display panel 100 to supply a gate signal to the gate line 103 using a single-feed method. In the single-feed method, the gate signal is applied to one end of the gate line. The gate driver 120 may be disposed in the left non-display area NA and the right non-display area NA in the display panel 100 to apply a gate signal to the gate line 103 using a single-feed method or a dual-feed method. In the dual-feed method, the gate signal is applied to both ends of the gate line 103 simultaneously. At least some circuits of the gate driver 120 may be disposed within the display area AA.

[0055] The gate driver 120 may include a shift register and / or an edge trigger to output and shift the pulse of the gate signal under the control of the timing controller 130. The gate driver 120 may output a plurality of gate signals having different waveforms. In this case, the gate driver 120 may include a plurality of gate drivers that output different gate signals.

[0056] The gate signal may include a first scan signal SCAN1, a second scan signal SCAN2, and an emission signal (hereinafter referred to as an "EM signal") EM. In this case, the gate driver may include a first gate driver that outputs the first scan signal SCAN1, a second gate driver that outputs the second scan signal SCAN2, and a third gate driver that outputs the EM signal.

[0057] The timing controller 130 receives pixel data of an input image and timing signals synchronized with the pixel data from the host system 200. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. The vertical synchronization signal Vsync indicates a frame period including a pulse generated once per frame period. The pulses of the horizontal synchronization signal Hsync and the data enable signal DE may be one horizontal period (1H). The timing controller 130 may determine a frame period (or vertical period) and a horizontal period by counting the data enable signal DE. In this case, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync may be omitted. The timing controller 130 may determine the number of frame periods in the current frame period by counting the rising edge or falling edge of the pulses in the starting pulses of the timing signals Vsync, Hsync, and DE or the strobe timing signal.

[0058] The timing controller 130 can control the operation timing of the data driver 110 and the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 200. The gate timing signal includes a clock and a start pulse for controlling the operation timing of the gate driver 120. The gate timing signal output from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 150 and can be used to control the pulse of the gate signal output from the gate driver 120. The level shifter 150 can receive the gate timing signal and generate a clock to provide it to the gate driver 120. The level shifter 150 can be mounted on a control printed circuit board (PCB) together with the timing controller 130 and the power supply 140, or can be mounted on a source PCB that is electrically connected to a chip on film (COF) on which the data driver 110 is mounted. The input signal of the level shifter 150 is a signal with a digital signal voltage level. The clock output from the level shifter 150 can swing between a gate high voltage and a gate low voltage. The data timing control signal generated from the timing controller 130 is transmitted to the data driver 110 .

[0059] The host system 200 may scale the image signal from the video source to match the resolution of the display panel 100 and may send it to the timing controller 130 along with the timing control signal.

[0060] The display device may be implemented as a tiled display (TD) in which a plurality of display panels are combined in the same plane to provide a wide screen, such as Figure 2 shown.

[0061] Reference Figure 2The widescreen tiled display TD includes a plurality of display panels PNL1 to PNL4 arranged on an XY plane. When the non-display area NA is minimized at the periphery of each display panel PNL1 to PNL4, a widescreen image can be reproduced without visible seams between adjacent display panels PNL1 to PNL4. The gate driver 120 can be embedded in the display area AA of the display panels PNL1 to PNL4 to minimize the peripheral non-display area NA of the display panels PNL1 to PNL4.

[0062] The display panels 100 can be assembled on a plane so that the distance D1 between the outermost pixels 101 adjacent to each other at the boundaries between adjacent display panels PNL1 to PNL4 is substantially the same as the distance D2 between adjacent pixels 101 within the display area AA of a single display panel PNL1 to PNL4. As a result, the distances D1 and D2 between the pixels 101 are the same throughout the entire widescreen display area of the tiled display TD, and thus the seam area is invisible.

[0063] The pixel 101 may include two sub-pixels for each color, such as Figure 3 As shown (for example, pixel 101 may include six subpixels). Each pixel 101 includes a first-first subpixel S1 and a first-second subpixel S4 adjacent in a second direction Y parallel to data lines 1021 to 1026 and having pixel data of a first color written therein, a second-first subpixel S2 and a second-second subpixel S5 adjacent in a second direction Y and having pixel data of a second color written therein, and a third-first subpixel S3 and a third-second subpixel S6 adjacent in the second direction Y and having pixel data of a third color written therein. The first color may be, but is not limited to, red, the second color may be green, and the third color may be blue. For example, the first-first subpixel S1 and the first-second subpixel S4 may be red subpixels SP_R to which a data voltage of red data is applied. The second-first subpixel S2 and the second-second subpixel S5 may be green subpixels SP_G to which a data voltage of green data is applied. The third-first subpixel S3 and the third-second subpixel S6 may be blue subpixels SP_B to which a data voltage of blue data is applied.

[0064] The first-first subpixel S1, the second-first subpixel S2, and the third-first subpixel S3 may be interpreted as main subpixels, and the first-second subpixel S4, the second-second subpixel S5, and the third-second subpixel S6 may be interpreted as redundant subpixels or auxiliary subpixels.

[0065] In this case, sub-pixels S1 and S4 may be connected to different data lines, sub-pixels S2 and S5 may be commonly connected to one data line, and sub-pixels S3 and S6 may be commonly connected to one data line.

[0066] In addition, for each pixel row, the gate lines connected to sub-pixels of the same color can be separated. For example, sub-pixels S1, S2, and S3 arranged in the n-th pixel row L(n) (where n is a natural number) can be connected to the first gate line or the first group of gate lines 1031, 1032, and 1033, and sub-pixels S4, S5, and S6 arranged in the n+1-th pixel row L(n+1) can be connected to the second gate line or the second group of gate lines 1034, 1035, and 1036.

[0067] Figure 4 is a circuit diagram illustrating a pixel circuit according to one embodiment of the present disclosure.

[0068] Reference Figure 4 The pixel circuit includes a light emitting element LD, a driving transistor DR, switching transistors M1 and M2, and a compensation circuit 300. The driving transistor DR and the switching transistor M1 may be implemented as p-channel transistors, but are not limited thereto.

[0069] The light-emitting element LD may include an anode electrode, a cathode electrode, and a light-emitting layer. A pixel drive voltage EVDD may be applied to the anode electrode of the light-emitting element LD. The cathode electrode of the light-emitting element LD may be connected to a drive transistor DR. The light-emitting element LD may be, but is not limited to, a light-emitting element such as an OLED, a mini-LED, or a micro-LED. The mini-LED or micro-LED may have a vertical structure in which electrodes are arranged above and below a semiconductor chip on which the light-emitting element LD is integrated. The semiconductor chip in which the light-emitting element LD is integrated may be implemented in a lateral structure or a flip-chip structure.

[0070] The light emitting element LD, the driving transistor DR, and the switching transistor M1 may be connected in series between a pixel driving voltage EVDD and a ground voltage EVSS.

[0071] The drive transistor DR regulates the current flowing through the drain-source channel according to its gate-source voltage. The gate-source voltage of the drive transistor DR varies with the data voltage Vdata of the pixel data applied to the gate electrode of the drive transistor DR. Therefore, the current flowing through the drive transistor DR varies with the data voltage Vdata. The light-emitting element LD can be driven by the current from the drive transistor DR to emit light.

[0072] The driving transistor DR may be connected between the light emitting element LD and the first switching transistor M1. The driving transistor DR includes a gate electrode to which the data voltage Vdata is applied, a first electrode connected to the cathode electrode of the light emitting element LD, and a second electrode connected to the first electrode of the first switching transistor M1.

[0073] The first switching transistor M1 can be connected between the drive transistor DR and the ground voltage EVSS to switch the current path between the pixel drive voltage EVDD and the ground voltage EVSS. The first switching transistor M1 can be turned on in response to the gate-on voltage of the color-specific EM signal EM_R / G / B and turned off in response to the gate-off voltage of the color-specific EM signal EM_R / G / B. When the first switching transistor M1 is turned on, the drive transistor DR and the light-emitting element LD can be electrically connected, thereby supplying current to the light-emitting element LD. When the first switching transistor M1 is turned off, the current path between the pixel drive voltage EVDD and the ground voltage EVSS is blocked, and no current is supplied to the light-emitting element LD.

[0074] The pixel circuit may further include a second switching transistor M2. The second switching transistor M2 is connected between the cathode electrode and the anode electrode of the light-emitting element LD and can be turned on in response to the gate-on voltage of the first scan signal SCAN1 and turned off in response to the gate-off voltage. When the second switching transistor M2 is turned on, the cathode electrode and the anode electrode of the light-emitting element LD are short-circuited, so that the light-emitting element LD does not emit light. When the second switching transistor M2 is turned off, current can flow to the light-emitting element LD. The second switching transistor M2 can prevent the light-emitting element LD from emitting light when the pixel circuit is initialized and when the threshold voltage of the drive transistor DR is sampled.

[0075] The compensation circuit 300 can be connected to a data line to which a data voltage Vdata is applied, a gate line to which select signals SCAN1, SCAN2, and EM_R / G / B are applied, a gate electrode of the drive transistor DR, and gate electrodes of the switching transistors M1 and M2. The compensation circuit 300 can include a plurality of transistors and one or more capacitors. The compensation circuit 300 transmits the data voltage Vdata to the gate electrode of the drive transistor DR. The compensation circuit 500 samples the threshold voltage of the drive transistor DR into the capacitor to compensate the gate voltage of the drive transistor DR by the threshold voltage of the drive transistor DR.

[0076] The compensation circuit 300 may perform compensation by sampling the threshold voltage of the driving transistor DR using a source follower or a diode connection circuit.

[0077] Figure 5 It is shown that it is applicable to Figure 4A circuit diagram of an example of a pixel circuit is shown. Figure 6 It shows Figure 5 A diagram showing the driving timing of the pixel circuit shown. 7A to 7D Is used to illustrate Figure 5 A circuit diagram showing the operating principle of the pixel circuit.

[0078] Reference Figure 5 According to an embodiment, a pixel circuit includes a driving transistor DR for driving a light-emitting element LD, a plurality of switching transistors M1 to M6, and a first capacitor Cst. The pixel circuit may further include a second capacitor C2 and a third capacitor C3. The transistors DR and M1 to M6 of the pixel circuit may be p-channel transistors, but are not limited thereto.

[0079] A pixel driving voltage EVDD, a ground voltage EVSS, and a reference voltage Vref may be applied to the pixel circuit. The pixel driving voltage EVDD may be a constant voltage selected between 8 V and 13 V, and the ground voltage EVSS and the reference voltage Vref may be constant voltages selected between -2 V and 1 V. The reference voltage Vref may be a constant voltage equal to or higher than the ground voltage EVSS, but is not limited thereto.

[0080] The data voltage Vdata and the select signals SCAN1, SCAN2, and EM can be input to the pixel circuit. The data voltage Vdata can be a dynamic range voltage between 0V and SVDD, but is not limited thereto. SVDD is a data drive voltage for driving the output buffer of the data driver 110. The data drive voltage SVDD can be a constant voltage selected from 12V to 18V, but is not limited thereto. The select high voltage VGH of the select signals SCAN1, SCAN2, and EM can be a constant voltage selected from 10V to 13V, and the select low voltage VGL can be a constant voltage selected from -13V to -10V, but is not limited thereto. Hereinafter, the select low voltage VGL will be referred to as the select on voltage, and the select high voltage VGH will be referred to as the select off voltage.

[0081] An anode electrode of the light emitting element LD may be connected to a first power line PL1 to which a pixel driving voltage EVDD is applied, and a cathode electrode of the light emitting element LD may be connected to a first node n1.

[0082] The driving transistor DR may include a first electrode connected to the first node n1, a gate electrode connected to the second node n2, and a second electrode connected to the third node n3. The first capacitor Cst may be connected between the second node n2 and a fourth node n4.

[0083] The first switching transistor M1 is turned on in response to a gate-on voltage VGL of the EM signal EM and is turned off in response to a gate-off voltage VGH of the EM signal EM. The first switching transistor M1 includes a first electrode connected to the third node n3, a gate electrode connected to a third gate line GL3 to which the EM signal EM is applied, and a second electrode connected to a second power line PL2.

[0084] The second switching transistor M2 is turned on in response to a gate-on voltage VGL of the first scan signal SCAN1 and is turned off in response to a gate-off voltage VGH of the first scan signal SCAN1. When the second switching transistor M2 is turned on, the first power line PL1 to which the pixel drive voltage EVDD is applied can be electrically connected to the first node n1. The second switching transistor M2 includes a first electrode connected to the first power line PL1, a gate electrode connected to the first gate line GL1 to which the first scan signal SCAN1 is applied, and a second electrode connected to the first node n1.

[0085] The third switching transistor M3 is turned on in response to the gate-on voltage VGL of the EM signal EM and is turned off in response to the gate-off voltage VGH of the EM signal EM. When the third switching transistor M3 is turned on, the fourth node n4 can be electrically connected to the third power line PL3 to which the reference voltage Vref is applied. The third switching transistor M3 includes a first electrode connected to the fourth node n4, a gate connected to the third gate line GL3, and a second electrode connected to the third power line PL3.

[0086] The fourth switching transistor M4 is turned on in response to the gate-on voltage VGL of the second scan signal SCAN2 and is turned off in response to the gate-off voltage VGH of the second scan signal SCAN2. When the fourth switching transistor M4 is turned on, the third node n3 can be electrically connected to the third power line PL3 to which the reference voltage Vref is applied. The fourth switching transistor M4 includes a first electrode connected to the third power line PL3, a gate electrode connected to the second gate line GL2 to which the second scan signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0087] The fifth switching transistor M5 is turned on in response to the gate-on voltage VGL of the first scan signal SCAN1 and is turned off in response to the gate-off voltage VGH of the first scan signal SCAN1. When the fifth switching transistor M5 is turned on, the data line DL to which the data voltage Vdata is applied can be electrically connected to the fourth node n4. The fifth switching transistor M5 includes a first electrode connected to the data line DL, a gate electrode connected to the first gate line GL1 to which the first scan signal SCAN1 is applied, and a second electrode connected to the fourth node n4.

[0088] The sixth switching transistor M6 is turned on in response to the gate-on voltage VGL of the first scan signal SCAN1 and is turned off in response to the gate-off voltage VGH of the first scan signal SCAN1. When the sixth switching transistor M6 is turned on, the second node n2 can be electrically connected to the third node n3. The sixth switching transistor M6 includes a first electrode connected to the second node n2, a gate electrode connected to the first gate line GL1, and a second electrode connected to the third node n3.

[0089] The second capacitor C2 may be connected between the first power line PL1 and the first node n1. The third capacitor C3 may be connected between the first node n1 and the second node n2.

[0090] The pixel circuit may be driven in an initialization step, a sampling step, and a light emitting step during a first frame period. The initialization step may be divided into a first initialization step and a second initialization step.

[0091] Reference Figure 6 and Figure 7A , a first initialization step is performed during the first period Pi1. During the first period Pi1, the voltage of the second scan signal SCAN2 may be the gate-on voltage VGL, and the voltages of the first scan signal SCAN1 and the EM signal EM may be the gate-off voltage VGH. Therefore, during the first period Pi1, when the fourth switching transistor M4 is turned on, the other switching transistors M1, M2, M3, M5, and M6 are in the off state. During the first period Pi1, the drive transistor DR is in the off state.

[0092] During the first period Pi1, the voltage of the third node n3 is initialized to the reference voltage Vref. During the first period Pi1, the other nodes n1, n2 and n4 are floated. During the first period Pi1, the voltage of the first node n1 and the voltage of the second node n2 can be maintained at the voltage charged in the previous frame period. The voltage of the fourth node n4 can be maintained at the reference voltage Vref charged in the light-emitting step of the previous frame. During the first period Pi1, the data voltage Vdata(n-1) of the previous pixel row (for example, the n-1 pixel row) can be applied to the data line DL.

[0093] Reference Figure 6 and Figure 7BDuring the second period Pi2, a second initialization step is performed. During the second period Pi2, the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 may be the gate-on voltage VGL, and the voltage of the EM signal EM may be the gate-off voltage VGH. For example, the second period Pi2 may be initiated by transitioning the first scan signal SCAN1 from the gate-off voltage VGH to the gate-on voltage VGL while the second scan signal SCAN2 remains at the gate-on voltage VGL and the EM signal EM remains at the gate-off voltage VGH. Therefore, during the second period Pi2, the second switching transistor M2, the fifth switching transistor M5, and the sixth switching transistor M6 are turned on, and the fourth switching transistor M4 is in an on state. In contrast, during the second period Pi2, the first switching transistor M1 and the third switching transistor M3 are in an off state due to the EM signal EM being at the gate-off voltage VGH. During the second period Pi2, the voltage of the first node n1 rises, turning on the drive transistor DR.

[0094] During the second period Pi2, the data voltage Vdata(n) is applied to the data line DL. The data voltage Vdata(n) is applied to the fourth node n4 via the fifth switching transistor M5. During the second period Pi2, the reference voltage Vref is applied to the second node n2 and the third node n3 via the fourth transistor M4 and the sixth transistor M6. Therefore, during the second period Pi2, the voltage of the second node n2 is initialized to the reference voltage Vref, and the voltage of the fourth node n4 is the data voltage Vdata(n).

[0095] Reference Figure 6 and Figure 7C , a sampling step is performed during the third period Ps. During the third period Ps, the voltage of the first scan signal SCAN1 can be the gate-on voltage VGL, and the voltage of the second scan signal SCAN2 and the voltage of the EM signal EM can be the gate-off voltage VGH. Therefore, during the third period Ps, the second switching transistor M2, the fifth switching transistor M5, and the sixth switching transistor M6 are in an on state, and the fourth switching transistor M4 is off. During the third period Ps, the first switching transistor M1 and the third switching transistor M3 are in an off state. During the third period Ps, the voltage at the first node n1 is EVDD, and the voltage at the second node n2 is EVDD+Vth. The drive transistor DR is in an on state upon entering the third period Ps and is turned off when the turn-off condition (Vs-Vg)+Vth<0 is met. Here, (Vs-Vg) is the gate-source voltage of the drive transistor DR, that is, the voltage difference between the voltage Vs at the second node n2 and the voltage Vn2=Vg at the first node n1.

[0096] When the driving transistor DR is turned off, the threshold voltage Vth of the driving transistor DR may be sampled and stored in the first capacitor Cst. During the third period Ps, the voltage of the fourth node n4 is the data voltage Vdata(n).

[0097] The first capacitor Cst is charged by a voltage difference between the voltage of the fourth node n4 and the voltage of the second node n2 .

[0098] Reference Figure 6 and Figure 7D , the light-emitting step is performed during the fourth period (Pem). For example, the fourth period (Pem) can be initiated by causing the EM signal EM to transition from the gate-off voltage VGH to the gate-on voltage VGL while both the first scan signal SCAN1 and the second scan signal SCAN2 remain at the gate-off voltage VGH. During the fourth period (Pem), the voltage of the EM signal EM can be the gate-on voltage (VGL), and the voltages of the first scan signal SCAN1 and the second scan signal SCAN2 can be the gate-off voltage (VGH). Therefore, during the fourth period (Pem), the first switching transistor M1 and the third switching transistor M3 are turned on, while the other switching transistors M2, M4, M5, and M6 are turned off. During the fourth period (Pem), the drive transistor DR generates a current based on the gate-source voltage (Vgs) to drive the light-emitting element LD. During the fourth period (Pem), the DR current ILD from the drive transistor controls the light-emitting element LD to emit light.

[0099] Figure 8A and Figure 8B It is a diagram for explaining the operating principle of the timing controller.

[0100] Reference Figure 8A , the timing controller 130 may transmit pixel data of the input image to the data driver 110 , and transmit first to third gate timing control signals to the first and second gate drivers 121 and 122 .

[0101] For example, the first strobe timing control signal may be a first scan clock signal SC1_CLK for generating a first scan signal SCAN1, the second strobe timing control signal may be a second scan clock signal SC2_CLK for generating a second scan signal SCAN2, and the third strobe timing control signal may be a light-emitting clock signal EM_CLK for generating a light-emitting signal EM.

[0102] The first and second gate drivers 121 and 122 may respectively include first scan drivers 121 a and 122 a for outputting a first scan signal SCAN1 , second scan drivers 121 b and 122 b for outputting a second scan signal SCAN2 , and EM drivers 121 c and 122 c for outputting an emission signal EM.

[0103] The first scan drivers 121a and 122a may each output a first scan signal SCAN1 according to a first gate timing control signal, the second scan drivers 121b and 122b may each output a second scan signal SCAN2 according to a second gate timing control signal, and the EM drivers 121c and 122c may each output an emission signal EM according to a third gate timing control signal.

[0104] The level shifter 150 may be disposed between the timing controller 130 and the first and second gate drivers 121 and 122. The level shifter 150 may convert an input signal of a first voltage level into a signal of a second voltage level greater than the first voltage level and output the signal.

[0105] Reference Figure 8B , the timing controller 130 may transmit pixel data of the input image to the data driver 110 , transmit the first gate timing control signal and the second gate timing control signal to the first gate driver 121 and the second gate driver 122 , and transmit the third gate timing control signal to each of the sub-pixels.

[0106] Here, the third gate timing control signal may be directly supplied to the sub-pixel through the level shifter 150 without being transmitted to the first gate driver 121 and the second gate driver 122 .

[0107] Figure 9 is a flowchart illustrating a pixel driving method according to an embodiment of the present disclosure.

[0108] Reference Figure 9 , when an input image is received, the timing controller 130 may analyze pixel data of the input image (S10) to determine whether the input image is a still image (S20), and as a result of the determination, if the input image is not a still image, generate a first strobe timing control signal, a second strobe timing control signal, and a third strobe timing control signal (S40).

[0109] Next, the timing controller 130 may transmit the pixel data of the current frame to the data driver 110, and transmit the first to third gate timing control signals to the first gate driver 121 and the second gate driver 122 (S50). Each of the first gate driver and the second gate driver may include a first scan driver that generates a first scan signal, a second scan driver that generates a second scan signal, and an EM driver that generates a light emitting signal.

[0110] In this case, the first to third gate timing control signals may be supplied such that the main sub-pixels and the redundant sub-pixels of the same color are alternately driven at least every one frame.

[0111] Next, if the input image is a still image, the timing controller 130 determines whether it is the first frame of the still image (S30), and as a result of the determination, if it is the first frame of the still image, pixel data and first to third selection timing control signals are generated (S40), the pixel data of the current frame can be transmitted to the data driver 110, and the first to third selection timing control signals can be transmitted to the first selection driver 121 and the second selection driver 122 (S50).

[0112] On the other hand, if it is not the first frame of the still image, the timing controller 130 may modulate the first to third gate timing control signals without transmitting pixel data of the current frame (S60), and may transmit the modulated first to third gate timing control signals to the first gate driver 121 and the second gate driver 122 (S70).

[0113] In this case, the first to third gate timing control signals may be modulated so that the main sub-pixels and the redundant sub-pixels of the same color are alternately driven at least every other frame.

[0114] The first to third gate timing control signals may be modulated so that the first gate driver and the second gate driver do not output a gate signal for at least one frame. Here, modulating the first to third gate timing control signals means changing the first to third gate timing control signals to signals having a gate cutoff voltage (for example, the first to third gate timing control signals may be maintained at a gate medium voltage VGH).

[0115] In addition, the timing controller 130 may modulate the data timing control signal and may not transmit pixel data of a corresponding frame according to the modulated data timing control signal.

[0116] The method of outputting the first to third gate timing control signals from the timing controller of this embodiment may be implemented in various ways, and various embodiments will be described below.

[0117] Figure 10 and Figure 11 A diagram for explaining the pixel driving principle according to the first embodiment.

[0118] Reference Figure 10 In the case of displaying a normal image, the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 may be alternately driven at intervals of a predetermined time (e.g., 1 frame period (where 1 is a natural number)). An example will be described in which it is assumed that the predetermined time is 1 frame period.

[0119] During the n-th frame period FR_n, the timing controller may output the n-th frame image A for the main sub-pixels S1, S2, and S3, as well as pulses of the first, second, and third gate timing control signals SC1_CLK, SC2_CLK, and EM_CLK. In this case, the main sub-pixels S1, S2, and S3 may display the n-th frame image A.

[0120] During the n+1th frame period FR_(n+1), the timing controller may output the n+1th frame image B for the redundant sub-pixels S4, S5, and S6, as well as pulses of the first, second, and third strobe timing control signals SC1_CLK, SC2_CLK, and EM_CLK. In this case, the redundant sub-pixels S4, S5, and S6 may display the n+1th frame image B.

[0121] During the n+2 frame period FR_(n+2), the timing controller may output the n+2 frame image C for the main sub-pixels S1, S2, and S3, as well as pulses of the first, second, and third gate timing control signals SC1_CLK, SC2_CLK, and EM_CLK. In this case, the main sub-pixels S1, S2, and S3 may display the n+2 frame image C.

[0122] During the n+3 frame period FR_(n+3), the timing controller may output the n+3 frame image D for the redundant sub-pixels S4, S5, and S6, as well as pulses of the first, second, and third strobe timing control signals SC1_CLK, SC2_CLK, and EM_CLK. In this case, the redundant sub-pixels S4, S5, and S6 may display the n+3 frame image D.

[0123] As described above, the primary sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 can be alternately driven within a frame period, and normal images A, B, C, and D can be displayed in sequence. For example, during normal display driving (e.g., for a moving video image), image data can be updated once per frame, and the primary sub-pixels S1, S2, S3 and the redundant sub-pixels S4, S5, and S6 can be switched back and forth in turn to display the updated image for each frame.

[0124] Reference Figure 11 In the case of a still image, the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 may be alternately driven at intervals of a predetermined time (e.g., 1 frame period (where 1 is a natural number)). An example will be described in which it is assumed that the predetermined time is 2 frame periods.

[0125] During the n-th frame period FR_n, the timing controller may output the n-th frame image A for the main sub-pixels S1, S2, and S3, as well as pulses of the first, second, and third gate timing control signals SC1_CLK, SC2_CLK, and EM_CLK. In this case, the main sub-pixels S1, S2, and S3 may display the n-th frame image A.

[0126] The timing controller does not output any pulse during the n+1 frame period FR_(n+1). Therefore, the main sub-pixels S1, S2, and S3 can display the n-th frame image A.

[0127] During the n+2 frame period FR_(n+2), the timing controller may output the n+2 frame image B for the redundant sub-pixels S4, S5, and S6, as well as pulses of the first, second, and third strobe timing control signals SC1_CLK, SC2_CLK, and EM_CLK. In this case, the redundant sub-pixels S4, S5, and S6 may display the n+2 frame image B.

[0128] During the n+3 frame period FR_(n+3), the timing controller does not output any signal. Therefore, the redundant sub-pixels S4, S5, and S6 can display the n+2 frame image B.

[0129] As described above, when the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 are alternately driven at intervals of two frame periods, still images A and B can be sequentially displayed. For example, the refresh period or driving frequency for displaying still images may be lower than the refresh period or driving frequency for displaying normal images.

[0130] Figures 12 to 14 A diagram for explaining the pixel driving principle according to the second embodiment.

[0131] Reference Figure 12 and Figure 13 In the case of displaying a normal image, the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 may be alternately driven at intervals of a predetermined time (e.g., 1 frame period (where 1 is a natural number)). An example will be described in which it is assumed that the predetermined time is 1 frame period.

[0132] During the n-th frame period FR_n, the timing controller may output the n-th frame image A for the main sub-pixels S1, S2, and S3, as well as pulses of the first and second strobe timing control signals SC1_CLK and SC2_CLK. In this case, the main sub-pixels S1, S2, and S3 may perform initialization and sampling steps to charge the data voltages of the n-th frame image A.

[0133] During the n+1 frame period FR_(n+1), the timing controller may output a pulse of the third strobe timing control signal EM_CLK for the main sub-pixels S1, S2, and S3, and output a pulse of the n+1 frame image B, as well as the first strobe timing control signal SC1_CLK and the second strobe timing control signal SC2_CLK for the redundant sub-pixels S4, S5, and S6. In this case, the redundant sub-pixels S4, S5, and S6 may perform initialization and sampling steps to charge the data voltage of the n+1 frame image B, and the light-emitting elements of the main sub-pixels S1, S2, and S3 may emit light using the data voltage of the n frame image A to display the n frame image A.

[0134] During the n+2 frame period FR_(n+2), the timing controller may output the n+2 frame image C for the main sub-pixels S1, S2, and S3, as well as pulses of the first and second gate timing control signals SC1_CLK and SC2_CLK, and output pulses of the third gate timing control signal EM_CLK for the redundant sub-pixels S4, S5, and S6. In this case, the main sub-pixels S1, S2, and S3 perform an initialization step and a sampling step to charge the data voltage of the n+2 frame image C, and the light-emitting elements of the redundant sub-pixels S4, S5, and S6 may emit light using the data voltage of the n+1 frame image B to display the n+1 frame image B.

[0135] During the n+3 frame period FR_(n+3), the timing controller may output the third strobe timing control signal EM_CLK for the main sub-pixels S1, S2, and S3, and output the n+3 frame image D, as well as the pulses of the first strobe timing control signal SC1_CLK and the second strobe timing control signal SC2_CLK for the redundant sub-pixels S4, S5, and S6. In this case, the redundant sub-pixels S4, S5, and S6 may perform initialization and sampling steps to charge the data voltage of the n+3 frame image D, and the light-emitting elements of the main sub-pixels S1, S2, and S3 may emit light using the data voltage of the n+2 frame image C to display the n+2 frame image C.

[0136] As described above, the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 can be driven alternately at intervals of one frame period, and can sequentially display normal images A, B, C, and D. In this way, an image is constantly displayed by switching between displaying an image using the main sub-pixels S1, S2, and S3 and displaying an image using the redundant sub-pixels S4, S5, and S6. In other words, each pixel unit can include two groups of sub-pixels, for example, a first group of sub-pixels includes the main sub-pixels S1, S2, and S3, and a second group of sub-pixels includes the redundant sub-pixels S4, S5, and S6. Therefore, while the first group of sub-pixels is preparing and busy performing initialization and sampling operations, the second group of sub-pixels can display image data, and vice versa. For example, sub-pixels from two different groups can overlap each other so that image data is always and continuously displayed to the viewer. In addition, since the two different groups of sub-pixels can perform display operations in an alternating manner, the service life of the pixel unit can be extended.

[0137] In such Figure 2 In the case of a tiled display TD shown, data sampling or addressing of sub-pixels can be performed as the pulses of a scan signal sequentially shift in pixel rows across the display panel. When the display panels of a tiled display TD have different data sampling timings, the positions of the pixel rows displaying data of the previous frame image may differ between the display panels when reproducing an image, and the positions of the pixel rows displaying data of the current frame image may also differ between the display panels. In this case, the image of a moving object between adjacent display panels in the tiled display may have boundaries or discontinuities perceptible to the viewer, which may affect the viewing experience.

[0138] When the general Figure 12 and Figure 13 When the alternate driving shown is applied to a tiled display, all pixels of the display panel emit light for each frame period, thereby preventing object tearing or a phenomenon in which a boundary is visible within an object in an image of the boundary, and improving image quality.

[0139] Reference Figure 14 In the case of displaying a still image, the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 may be alternately driven at intervals of a predetermined time (e.g., 1 frame period (where 1 is a natural number)). An example will be described in which it is assumed that the predetermined time is 2 frame periods.

[0140] During the n-th frame period FR_n, the timing controller may output the n-th frame image A for the main sub-pixels S1, S2, and S3, as well as pulses of the first and second strobe timing control signals SC1_CLK and SC2_CLK. In this case, the main sub-pixels S1, S2, and S3 may perform an initialization step and a sampling step to charge the data voltage of the n-th frame image A.

[0141] During the n+1 frame period FR_(n+1), the timing controller may output a pulse of the third gate timing control signal EM_CLK to the master sub-pixels S1, S2, and S3. In this case, the light-emitting elements of the master sub-pixels S1, S2, and S3 may emit light using the data voltage of the n-th frame image A to display the n-th frame image A.

[0142] During the n+2 frame period FR_(n+2), the timing controller may output the n+2 frame image B for the redundant sub-pixels S4, S5, and S6, as well as pulses of the first and second strobe timing control signals SC1_CLK and SC2_CLK. In this case, the redundant sub-pixels S4, S5, and S6 may perform an initialization step and a sampling step to charge the data voltage of the n+2 frame image B.

[0143] During the n+3 frame period FR_(n+3), the timing controller may output a pulse of the third gate timing control signal EM_CLK for the redundant sub-pixels S4, S5, and S6. In this case, the light-emitting elements of the redundant sub-pixels S4, S5, and S6 may emit light using the data voltage of the n+2 frame image B to display the n+2 frame image B.

[0144] As described above, when the main sub-pixels S1 , S2 , and S3 and the redundant sub-pixels S4 , S5 , and S6 are alternately driven with two frame periods, still images A and B can be sequentially displayed, and power consumption can be reduced.

[0145] Figure 15 is a diagram illustrating a unit pixel structure according to a second embodiment of the present disclosure, which can reduce gate line wiring and save space.

[0146] Reference Figure 15, a pixel may include two subpixels for each color. For example, the 1-1 subpixel S1 and the 1-2 subpixel S4 may be red subpixels to which a data voltage for red data is applied. The 2-1 subpixel S2 and the 2-2 subpixel S5 may be green subpixels to which a data voltage for green data is applied. The 3-1 subpixel S3 and the 3-2 subpixel S6 may be blue subpixels to which a data voltage for blue data is applied.

[0147] The 1-1st sub-pixel S1, the 2-1st sub-pixel S2, and the 3-1st sub-pixel S3 can be interpreted as primary sub-pixels, and the 1-2nd sub-pixel S4, the 2-2nd sub-pixel S5, and the 3-2nd sub-pixel S6 can be interpreted as redundant sub-pixels or auxiliary sub-pixels.

[0148] In this case, the 1-1th subpixel S1 and the 1-2nd subpixel S4 can be connected to different data lines 1021 and 1022, the 2-1st subpixel S2 and the 2-2nd subpixel S5 can be commonly connected to one data line 1023, and the 3-1st subpixel S3 and the 3-2nd subpixel S6 can be commonly connected to one data line 1024.

[0149] In addition, sub-pixels of the same color in different pixel rows share a selection line to which the first scan signal SCAN1 and the second scan signal SCAN2 and the EM signal EM are applied, but the selection line can be branched through the first selection switch element (including the 1-1th selection switch element S1-1, the 1-2nd selection switch element S1-2 and the 1-3rd selection switch element S1-3) and the second selection switch element (including the 2-1st selection switch element S2-1, the 2-2nd selection switch element S2-2 and the 2-3rd selection switch element S2-3). For example, the sub-pixels S1, S2 and S3 set in the nth pixel row L(n) (where n is a natural number) are connected to the 1-1th gate line 1031, the 2-1th gate line 1032 and the 3-1st gate line 1033, and the sub-pixels S4, S5 and S6 set in the n+1th pixel row L(n+1) can be connected to the 1-2nd gate line 1034, the 2-2nd gate line 1035 and the 3-2nd gate line 1036.

[0150] The 1-1st selection switching element S1-1, the 1-2nd selection switching element S1-2, and the 1-3rd selection switching element S1-3 can connect the first to third gate lines, to which the first and second scan signals SCAN1 and SCAN2 and the EM signal EM are applied, to the primary sub-pixels S1, S2, and S3 via a first masking signal MSK1 applied from the timing controller. The 1-1st selection switching element S1-1 is turned on by the gate-on voltage of the first masking signal MSK1 and includes a gate electrode to which the first masking signal MSK1 is applied, a first electrode connected to the first gate line to which the first scan signal SCAN1 is applied, and a second electrode connected to the 1-1st gate line 1031. The 1-2nd selection switching element S1-2 is turned on by the gate-on voltage of the first masking signal MSK1 and includes a gate electrode to which the first masking signal MSK1 is applied, a first electrode connected to the second gate line to which the second scan signal SCAN2 is applied, and a second electrode connected to the 2-1st gate line 1032. The 1-3 th selection switch element S1-3 is turned on by the gate-on voltage of the first masking signal MSK1 and includes a gate electrode to which the first masking signal MSK1 is applied, a first electrode connected to the third gate line to which the EM signal EM is applied, and a second electrode connected to the 3-1 th gate line 1033.

[0151] The 2-1st selection switch element S2-1, the 2-2nd selection switch element S2-2, and the 2-3rd selection switch element S2-3 can connect the first to third gate lines, to which the first and second scan signals SCAN1 and SCAN2 and the EM signal EM are applied, to the redundant sub-pixels S4, S5, and S6 via a second masking signal MSK2 applied from the timing controller. The 2-1st selection switch element S2-1 is turned on by the gate-on voltage of the second masking signal MSK2 and includes a gate to which the second masking signal MSK2 is applied, a first electrode connected to the first gate line to which the first scan signal SCAN1 is applied, and a second electrode connected to the 1-2nd gate line 1034. The 2-2nd selection switch element S2-2 is turned on by the gate-on voltage of the second masking signal MSK2 and includes a gate to which the second masking signal MSK2 is applied, a first electrode connected to the second gate line to which the second scan signal SCAN2 is applied, and a second electrode connected to the 2-2nd gate line 1035. The 2-3 th selection switch element S2-3 is turned on by the gate-on voltage of the second masking signal MSK2 and includes a gate to which the second masking signal MSK2 is applied, a first electrode connected to the third gate line to which the EM signal EM is applied, and a second electrode connected to the 3-2 th gate line 1036.

[0152] Figure 16 and Figure 17A diagram for explaining the pixel driving principle according to the third embodiment.

[0153] Reference Figure 16 In the case of displaying a normal image (e.g., moving video image data), the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 may be alternately driven at intervals of a predetermined time (e.g., 1 frame period (where 1 is a natural number)). An example assuming that the predetermined time is 1 frame period may be described.

[0154] During the n-th frame period FR_n, the timing controller may output the n-th frame image A and pulses of the first, second, and third strobe timing control signals SC1_CLK, SC2_CLK, and EM_CLK, and output a first mask signal MSK1 having a first voltage level for selectively driving the main sub-pixels S1, S2, and S3 and a second mask signal MSK2 having a second voltage level for not driving the redundant sub-pixels S4, S5, and S6. In this case, the main sub-pixels S1, S2, and S3 may display the n-th frame image A.

[0155] During the n+1 frame period FR_(n+1), the timing controller may output the n+1 frame image B and pulses of the first, second, and third strobe timing control signals SC1_CLK, SC2_CLK, and EM_CLK, and output the second mask signal MSK2 having a first voltage level for selectively driving the redundant sub-pixels S4, S5, and S6 and the first mask signal MSK1 having a second voltage level for not driving the main sub-pixels S1, S2, and S3. In this case, the redundant sub-pixels S4, S5, and S6 may display the n+1 frame image B.

[0156] During the n+2 frame period FR_(n+2), the timing controller may output the n+2 frame image C and pulses of the first, second, and third strobe timing control signals SC1_CLK, SC2_CLK, and EM_CLK, and output a first mask signal MSK1 having a first voltage level for selectively driving the main sub-pixels S1, S2, and S3 and a second mask signal MSK2 having a second voltage level for not driving the redundant sub-pixels S4, S5, and S6. In this case, the main sub-pixels S1, S2, and S3 may display the n+2 frame image C.

[0157] During the n+3 frame period FR_(n+3), the timing controller may output the n+3 frame image D and pulses of the first, second, and third strobe timing control signals SC1_CLK, SC2_CLK, and EM_CLK, and output the second mask signal MSK2 having a first voltage level for selectively driving the redundant sub-pixels S4, S5, and S6 and the first mask signal MSK1 having a second voltage level for not driving the main sub-pixels S1, S2, and S3. In this case, the redundant sub-pixels S4, S5, and S6 may display the n+3 frame image D.

[0158] As described above, the main sub-pixels S1 , S2 , and S3 and the redundant sub-pixels S4 , S5 , and S6 may be alternately driven at intervals of one frame period, and normal images A, B, C, and D may be sequentially displayed.

[0159] Reference Figure 17 In the case of displaying a still image (e.g., static image data), the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 may be alternately driven at intervals of a predetermined time (e.g., 1 frame period (where 1 is a natural number)). An example will be described in which it is assumed that the predetermined time is 2 frame periods.

[0160] During the n-th frame period FR_n, the timing controller may output the n-th frame image A and pulses of the first, second, and third strobe timing control signals SC1_CLK, SC2_CLK, and EM_CLK, and output a first mask signal MSK1 having a first voltage level for selectively driving the main sub-pixels S1, S2, and S3 and a second mask signal MSK2 having a second voltage level for not driving the redundant sub-pixels S4, S5, and S6. In this case, the main sub-pixels S1, S2, and S3 may display the n-th frame image A.

[0161] During the n+1th frame period FR_(n+1), the timing controller may output a first masking signal MSK1 having a second voltage level for not driving the main sub-pixels S1, S2, and S3 and a second masking signal MSK2 having a second voltage level for not driving the redundant sub-pixels S4, S5, and S6. Thus, the main sub-pixels S1, S2, and S3 may display the nth frame image A.

[0162] During the n+2 frame period FR_(n+2), the timing controller may output the n+2 frame image B and pulses of the first, second, and third strobe timing control signals SC1_CLK, SC2_CLK, and EM_CLK, and output the second mask signal MSK2 having a first voltage level for selectively driving the redundant sub-pixels S4, S5, and S6 and the first mask signal MSK1 having a second voltage level for not driving the main sub-pixels S1, S2, and S3. In this case, the redundant sub-pixels S4, S5, and S6 may display the n+2 frame image B.

[0163] During the (n+3)th frame period FR_(n+3), the timing controller may output a first masking signal MSK1 having a second voltage level for not driving the main sub-pixels S1, S2, and S3 and a second masking signal MSK2 having a second voltage level for not driving the redundant sub-pixels S4, S5, and S6. Thus, the main sub-pixels S1, S2, and S3 may display the (n+2)th frame image B.

[0164] As described above, when the main sub-pixels S1, S2, and S3 and the redundant sub-pixels S4, S5, and S6 are alternately driven at intervals of two frame periods, still images A and B can be sequentially displayed. Furthermore, the number of wirings and gate lines associated with the pixel unit can be reduced, space can be saved, and higher resolution can be provided.

[0165] Although the embodiments of the present disclosure have been described in greater detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all aspects and do not limit the present disclosure.

[0166] CROSS-REFERENCE TO RELATED APPLICATIONS

[0167] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0021452, filed on February 15, 2024, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A display device, comprising: A display panel comprising a plurality of data lines, a plurality of gate lines and a plurality of pixels, Each of the plurality of pixels comprises: a 1-1th sub-pixel configured to emit light of a first color and a 1-2th sub-pixel configured to emit light of the first color; a 2-1th sub-pixel configured to emit light of a second color and a 2-2th sub-pixel configured to emit light of the second color; and a 3-1st sub-pixel configured to emit light of a third color and a 3-2nd sub-pixel configured to emit light of the third color, and The 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel are alternately driven with the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel at intervals of at least one frame period.

2. The display device according to claim 1, wherein The 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel, and the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel are connected to a plurality of different gate lines among the plurality of gate lines, and The plurality of different gate lines include a first gate line configured to receive a first scan signal, a second gate line configured to receive a second scan signal, and a third gate line configured to receive a light emitting signal.

3. The display device according to claim 2, wherein: During the n-th frame period, the data voltage of the n-th frame is applied to the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel, and the pulses of the first scanning signal, the second scanning signal, and the light emitting signal are applied to the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel. wherein, during the (n+1)th frame period after the (n)th frame period, while the data voltage of the (n+1)th frame is applied to the (1-2)th sub-pixel, the (2-2)th sub-pixel, and the (3-2)th sub-pixel, the pulse of the first scanning signal, the pulse of the second scanning signal, and the pulse of the light emitting signal are applied to the (1-2)th sub-pixel, the (2-2)th sub-pixel, and the (3-2)th sub-pixel, and Wherein, n is a positive integer.

4. The display device according to claim 2, wherein During the n-th frame period, the data voltage of the n-th frame is applied to the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel, and the pulses of the first scanning signal, the second scanning signal, and the light emitting signal are applied to the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel. wherein, during the (n+1)th frame period after the (n)th frame period, none of the pulses of the first scanning signal, the pulses of the second scanning signal, and the pulses of the light emitting signal are applied to the 1-1th sub-pixel, the 2-1th sub-pixel, the 3-1st sub-pixel, the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, wherein, during the n+2th frame period after the n+1th frame period, the data voltage of the n+2th frame is applied to the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and the pulse of the first scanning signal, the pulse of the second scanning signal, and the pulse of the light emitting signal are applied to the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and Wherein, n is a positive integer.

5. The display device according to claim 2, wherein During the n-th frame period, the pulse of the first scanning signal and the pulse of the second scanning signal are applied to the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel, and the pulse of the light emitting signal is applied to the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, wherein, during the (n+1)th frame period after the (n)th frame period, the pulse of the light emitting signal is applied to the 1-2nd sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and the pulse of the first scanning signal and the pulse of the second scanning signal are applied to the 1-2nd sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and Wherein, n is a positive integer. The display device according to claim 2 , wherein: During an n-th frame period, the data voltage of the n-th frame is applied to the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel, and the first scanning signal and the second scanning signal are applied to the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel, wherein, during the (n+1)th frame period following the (n)th frame period, the pulse of the light emitting signal is applied to the 1-2 th sub-pixel, the 2-2 th sub-pixel, and the 3-2 th sub-pixel, wherein, during the n+2th frame period after the n+1th frame period, the data voltage of the n+2th frame is applied to the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and the pulse of the first scanning signal and the pulse of the second scanning signal are applied to the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, wherein, during the n+3th frame period following the n+2th frame period, the pulse of the light emitting signal is applied to the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and Wherein, n is a positive integer.

7. The display device according to claim 2, wherein: The 1-1th sub-pixel and the 1-2th sub-pixel are respectively connected to a 1-1th gate line and a 1-2th gate line branched from the first gate line and configured to receive the first scan signal, wherein the 2-1st sub-pixel and the 2-2nd sub-pixel are respectively connected to the 2-1st gate line and the 2-2nd gate line branched from the second gate line and configured to receive the second scan signal, and The 3-1st sub-pixel and the 3-2nd sub-pixel are respectively connected to a 3-1st gate line and a 3-2nd gate line branched from the third gate line and configured to receive the light emitting signal.

8. The display device according to claim 7, further comprising: a first-first selection switch element connected between the first gate line and the 1-1th gate line, a second-first selection switch element connected between the second gate line and the 2-1th gate line, and a third-first selection switch element connected between the third gate line and the 3-1th gate line, wherein the first-first selection switch element, the second-first selection switch element, and the third-first selection switch element are configured to be turned on in response to a first masking signal; as well as a first-second selection switch element connected between the first gate line and the 1-2 gate line, a second-second selection switch element connected between the second gate line and the 2-2 gate line, and a third-second selection switch element connected between the third gate line and the 3-2 gate line, wherein the first-second selection switch element, the second-second selection switch element, and the third-second selection switch element are configured to be turned on in response to a second masking signal, and The first mask signal and the second mask signal are applied from a timing controller.

9. The display device according to claim 8, wherein During an n-th frame period, a data voltage of the n-th frame is applied to the 1-1th subpixel, the 2-1th subpixel, the 3-1th subpixel, the 1-2th subpixel, the 2-2nd subpixel, and the 3-2nd subpixel, a pulse of the first scanning signal, a pulse of the second scanning signal, and a pulse of the light emitting signal are applied to the 1-1th subpixel, the 2-1th subpixel, the 3-1st subpixel, the 1-2nd subpixel, the 2-2nd subpixel, and the 3-2nd subpixel, a first masking signal having a first voltage level is applied to the first-first selection switching element, the second-first selection switching element, and the third-first selection switching element, and a second masking signal having a second voltage level is applied to the first-second selection switching element, the second-second selection switching element, and the third-second selection switching element. wherein, during the (n+1)th frame period after the (n)th frame period, the data voltage of the (n+1)th frame is applied to the 1-1th, 2-1st, and 3-1st subpixels, as well as the 1-2nd, 2-2nd, and 3-2nd subpixels; the pulse of the first scanning signal, the pulse of the second scanning signal, and the pulse of the light-emitting signal are applied to the 1-1th, 2-1st, and 3-1st subpixels, as well as the 1-2nd, 2-2nd, and 3-2nd subpixels; the first masking signal having the second voltage level is applied to the first-first selection switching element, the second-first selection switching element, and the third-first selection switching element; and the second masking signal having the first voltage level is applied to the first-second selection switching element, the second-second selection switching element, and the third-second selection switching element. Where n is a positive integer, and The first voltage level is lower than the second voltage level.

10. The display device according to claim 8, wherein During an n-th frame period, a data voltage of the n-th frame is applied to the 1-1th subpixel, the 2-1th subpixel, the 3-1th subpixel, the 1-2th subpixel, the 2-2nd subpixel, and the 3-2nd subpixel, a pulse of the first scanning signal, a pulse of the second scanning signal, and a pulse of the light emitting signal are applied to the 1-1th subpixel, the 2-1th subpixel, the 3-1st subpixel, the 1-2nd subpixel, the 2-2nd subpixel, and the 3-2nd subpixel, a first masking signal having a first voltage level is applied to the first-first selection switching element, the second-first selection switching element, and the third-first selection switching element, and a second masking signal having a second voltage level is applied to the first-second selection switching element, the second-second selection switching element, and the third-second selection switching element. wherein, during the (n+1)th frame period following the (n)th frame period, the pulse of the first scanning signal, the pulse of the second scanning signal, and the pulse of the light emitting signal are applied to the 1-1th sub-pixel, the 2-1th sub-pixel, the 3-1st sub-pixel, the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, the first masking signal having the second voltage level is applied to the first-first selection switching element, the second-first selection switching element, and the third-first selection switching element, and the second masking signal having the second voltage level is applied to the first-second selection switching element, the second-second selection switching element, and the third-second selection switching element, wherein, during the n+2th frame period after the n+1th frame period, the data voltage of the n+2th frame is applied to the 1-1th subpixel, the 2-1th subpixel, the 3-1th subpixel, the 1-2th subpixel, the 2-2nd subpixel, and the 3-2nd subpixel, the pulse of the first scanning signal, the pulse of the second scanning signal, and the pulse of the light emitting signal are applied to the 1-1th subpixel, the 2-1st subpixel, the 3-1st subpixel, the 1-2nd subpixel, the 2-2nd subpixel, and the 3-2nd subpixel, the first masking signal having the second voltage level is applied to the first-first selection switching element, the second-first selection switching element, and the third-first selection switching element, and the second masking signal having the first voltage level is applied to the first-second selection switching element, the second-second selection switching element, and the third-second selection switching element, wherein, during the n+3th frame period after the n+2th frame period, the pulse of the first scanning signal, the pulse of the second scanning signal, and the pulse of the light emitting signal are applied to the 1-1th sub-pixel, the 2-1th sub-pixel, the 3-1st sub-pixel, the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, the first masking signal having the second voltage level is applied to the first-first selection switching element, the second-first selection switching element, and the third-first selection switching element, and the second masking signal having the second voltage level is applied to the first-second selection switching element, the second-second selection switching element, and the third-second selection switching element, Where n is a positive integer, and The first voltage level is set to be lower than the second voltage level.

11. A display device, comprising: A display panel comprising a plurality of data lines, a plurality of gate lines and a plurality of pixels; a data driver configured to output data voltages to the plurality of data lines; a gate driver configured to output a gate signal to the plurality of gate lines; as well as A timing controller, wherein the timing controller is configured to: In response to determining that the pixel data of the input image corresponds to a motion image, supplying a gate timing control signal to the gate driver at a first driving frequency, and In response to determining that the pixel data of the input image corresponds to a still image to be displayed for a plurality of frames, the gate timing control signal is supplied to the gate driver at a second driving frequency lower than the first driving frequency.

12. The display device according to claim 11, wherein Each pixel of the plurality of pixels comprises: a 1-1th sub-pixel configured to emit light of a first color and a 1-2th sub-pixel configured to emit light of the first color; a 2-1th sub-pixel configured to emit light of a second color and a 2-2th sub-pixel configured to emit light of the second color; and a 3-1st sub-pixel configured to emit light of a third color and a 3-2nd sub-pixel configured to emit light of the third color, and The 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel, and the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel are connected to a plurality of different gate lines among the plurality of gate lines.

13. The display device according to claim 12, wherein: The timing controller is further configured to: During the n-th frame period, the data voltage of the n-th frame is output for the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel, and the pulse of the gate timing control signal is output, and During the (n+1)th frame period after the (n)th frame period, the data voltage of the (n+1)th frame is output for the (1-2)th sub-pixel, the (2-2)th sub-pixel, and the (3-2)th sub-pixel, and the pulse of the gate timing control signal is output, and Wherein, n is a positive integer.

14. The display device according to claim 12, wherein: The timing controller is further configured to: During an n-th frame period, outputting the data voltage of the n-th frame for the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel, and outputting a pulse of the gate timing control signal, During the (n+1)th frame period following the (n)th frame period, the data voltage and the pulse of the gate timing control signal are not output, and During the n+2th frame period after the n+1th frame period, the data voltage of the n+2th frame is output for the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and the pulse of the gate timing control signal is output, and Wherein, n is a positive integer.

15. The display device according to claim 12, wherein The strobe timing control signal includes a first strobe timing control signal for generating a first scanning signal, a second strobe timing control signal for generating a second scanning signal, and a third strobe timing control signal for generating a light emitting signal. Wherein, the timing controller is further configured to: During the n-th frame period, a pulse of the first strobe timing control signal and a pulse of the second strobe timing control signal are output for the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1st sub-pixel, and a pulse of the third strobe timing control signal is output for the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and During an (n+1)th frame period following the (n)th frame period, the pulse of the third strobe timing control signal is output for the 1-2nd sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and the pulse of the first strobe timing control signal and the pulse of the second strobe timing control signal are output for the 1-2nd sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and Wherein, n is a positive integer.

16. The display device according to claim 12, wherein: The strobe timing control signal includes a first strobe timing control signal for generating a first scanning signal, a second strobe timing control signal for generating a second scanning signal, and a third strobe timing control signal for generating a light emitting signal. Wherein, the timing controller is further configured to: During an n-th frame period, outputting data voltages of the n-th frame for the 1-1th sub-pixel, the 2-1th sub-pixel, and the 3-1th sub-pixel, and outputting pulses of the first gate timing control signal and the second gate timing control signal, During an (n+1)th frame period following the (n)th frame period, pulses of the third gate timing control signal are output for the 1-2nd sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, During the n+2th frame period after the n+1th frame period, the data voltage of the n+2th frame is output for the 1-2th sub-pixel, the 2-2nd sub-pixel, and the 3-2nd sub-pixel, and the pulse of the first gate timing control signal and the pulse of the second gate timing control signal are output, and During the (n+3)th frame period following the (n+2)th frame period, the pulse of the third gate timing control signal is output for the 1-2 th sub-pixel, the 2-2 th sub-pixel, and the 3-2 th sub-pixel, and Wherein, n is a positive integer.

17. The display device according to claim 12, wherein: The 1-1th sub-pixel and the 1-2th sub-pixel are respectively connected to a 1-1th gate line and a 1-2th gate line branched from a first gate line configured to receive a first scan signal, wherein the 2-1st sub-pixel and the 2-2nd sub-pixel are respectively connected to the 2-1st gate line and the 2-2nd gate line branched from the second gate line configured to receive the second scan signal, and The 3-1st sub-pixel and the 3-2nd sub-pixel are respectively connected to a 3-1st gate line and a 3-2nd gate line branched from a third gate line configured to receive a light emitting signal.

18. The display device according to claim 17, further comprising: a first-first selection switch element connected between the first gate line and a first-first gate line, a second-first selection switch element connected between the second gate line and the second-first gate line, and a third-first selection switch element connected between the third gate line and the third-first gate line, wherein the first-first selection switch element, the second-first selection switch element, and the third-first selection switch element are configured to be turned on in response to a first masking signal; as well as a first-second selection switch element connected between the first gate line and a first-second gate line, a second-second selection switch element connected between the second gate line and the second-second gate line, and a third-second selection switch element connected between the third gate line and the third-second gate line, wherein the first-second selection switch element, the second-second selection switch element, and the third-second selection switch element are configured to be turned on in response to a second masking signal, and The first mask signal and the second mask signal are applied from a timing controller.

19. The display device according to claim 18, wherein The strobe timing control signal includes a first strobe timing control signal for generating the first scanning signal, a second strobe timing control signal for generating the second scanning signal, and a third strobe timing control signal for generating the light emitting signal, and Wherein, the timing controller is further configured to: During an n-th frame period, outputting the data voltage of the n-th frame for the 1-1th subpixel, the 2-1th subpixel, the 3-1th subpixel, and the 1-2th subpixel, the 2-2nd subpixel, and the 3-2nd subpixel, the pulse of the first strobe timing control signal, the pulse of the second strobe timing control signal, and the pulse of the third strobe timing control signal, and the first masking signal having a first voltage level and the second masking signal having a second voltage level, and outputting, during an (n+1)th frame period following the (n)th frame period, data voltages of the (n+1)th frame for the 1-1th, 2-1th, and 3-1st subpixels, and the 1-2th, 2-2th, and 3-2nd subpixels, the pulses of the first, second, and third strobe timing control signals, and the first, second, and third masking signals having the second voltage level, for the 1-1th, 2-1th, and 3-1st subpixels, respectively. Where n is a positive integer, and The first voltage level is set to be lower than the second voltage level.

20. The display device according to claim 18, wherein The strobe timing control signal includes a first strobe timing control signal for generating the first scanning signal, a second strobe timing control signal for generating the second scanning signal, and a third strobe timing control signal for generating the light emitting signal, and Wherein, the timing controller is further configured to: outputting, during an n-th frame period, data voltages of the n-th frame for the 1-1th subpixel, the 2-1th subpixel, the 3-1st subpixel, and the 1-2th subpixel, the 2-2nd subpixel, and the 3-2nd subpixel, a pulse of the first strobe timing control signal, a pulse of the second strobe timing control signal, and a pulse of the third strobe timing control signal, and the first masking signal having a first voltage level and the second masking signal having a second voltage level, during an (n+1)th frame period following the (n)th frame period, outputting the pulse of the first strobe timing control signal, the pulse of the second strobe timing control signal, and the pulse of the third strobe timing control signal for the 1-1th subpixel, the 2-1th subpixel, and the 3-1st subpixel, and outputting the first mask signal having the second voltage level and the second mask signal having the second voltage level for the 1-2th subpixel, the 2-2nd subpixel, and the 3-2nd subpixel, outputting, during an n+2-th frame period following the n+1-th frame period, the data voltage of the n+2-th frame for the 1-1-th subpixel, the 2-1-th subpixel, the 3-1-th subpixel, and the 1-2-th subpixel, the 2-2-th subpixel, and the 3-2-th subpixel, the pulse of the first strobe timing control signal, the pulse of the second strobe timing control signal, and the pulse of the third strobe timing control signal, and the first mask signal having the second voltage level and the second mask signal having the first voltage level, during an n+3 th frame period following the n+2 th frame period, outputting the pulse of the first strobe timing control signal, the pulse of the second strobe timing control signal, and the pulse of the third strobe timing control signal for the 1-1 th sub-pixel, the 2-1 th sub-pixel, and the 3-1 th sub-pixel, and outputting the first mask signal having the second voltage level and the second mask signal having the second voltage level for the 1-2 th sub-pixel, the 2-2 th sub-pixel, and the 3-2 th sub-pixel, Where n is a positive integer, and The first voltage level is set to be lower than the second voltage level.

21. A display device, comprising: a display panel comprising a plurality of data lines, a plurality of gate lines, and a plurality of pixels, at least one of the plurality of pixels comprising a main subpixel group including a first-first subpixel, a second-first subpixel, and a third-first subpixel, and a redundant subpixel group including a first-second subpixel, a second-second subpixel, and a third-second subpixel; as well as a controller configured to drive the main sub-pixel group and the redundant sub-pixel group in an alternating manner to display an image, In which, the first-first subpixel and the first-second subpixel are configured to emit light of the same first color, the second-first subpixel and the second-second subpixel are configured to emit light of the same second color, and the third-first subpixel and the third-second subpixel are configured to emit light of the same third color.

22. The display device according to claim 21, wherein The controller is further configured to: In response to determining that pixel data of the input image corresponds to a moving image, alternately driving the main sub-pixel group and the redundant sub-pixel group at a first driving frequency to display the pixel data, and In response to determining that the pixel data of the input image corresponds to a still image to be displayed for multiple frames, the main subpixel group and the redundant subpixel group are alternately driven at a second driving frequency lower than the first driving frequency to display the pixel data.

23. The display device according to claim 21, wherein The first-first subpixel, the second-first subpixel, and the third-first subpixel, and the first-second subpixel, the second-second subpixel, and the third-second subpixel are connected to a plurality of different gate lines among the plurality of gate lines, and The plurality of different gate lines include a first gate line configured to receive a first scan signal, a second gate line configured to receive a second scan signal, and a third gate line configured to receive a light emitting signal.

Images