Storage device and electronic equipment

Abstract

The invention provides a storage device and electronic equipment. The storage device comprises a reference module, a fine adjustment module, a time sequence calculation module, a timing module and a refresh control module, the reference module is configured to store a reference time sequence parameter; the fine tuning module is configured to generate a time sequence fine tuning parameter; the time sequence calculation module is electrically connected to the reference module and the fine adjustment module, and the time sequence calculation module is configured to perform fine adjustment on the reference time sequence parameter based on the time sequence fine adjustment parameter to obtain a target clock signal and a target clock cycle number; the timing module is electrically connected to the time sequence calculation module and is configured to perform timing according to the target clock signal and output an indication signal when the timing time is matched with the target clock cycle number; the refresh control module is electrically connected to the timing module and generates a refresh control signal based on the indication signal. According to the scheme, the time consumption for adjusting the refresh operation time sequence can be reduced, and the efficiency is improved.

Description

Technical Field

[0001] The disclosed embodiments of the present application relate to the field of storage technology, and more particularly, to a storage device and an electronic device. Background Art

[0002] Because the capacitors that store data in a storage device naturally discharge over time, if the charge is not replenished in a timely manner, the stored data will be lost. To ensure that the refresh operation can maintain data accuracy under different operating conditions (such as process, temperature, voltage, etc.), the optimal performance balance can be found by adjusting the timing of the refresh operation. For example, when adjusting the timing of the refresh operation, different timings can be written to determine the timing that achieves the optimal performance balance.

[0003] However, currently, adjusting the timing of the refresh operation by writing different timings is relatively complex and time-consuming, resulting in low efficiency. Summary of the Invention

[0004] According to an embodiment of the present application, the present invention provides a storage device and an electronic device to reduce the time consumption of adjusting the refresh operation timing and improve efficiency.

[0005] According to one aspect of the present application, a storage device is disclosed, comprising: a reference module, a fine-tuning module, a timing calculation module, a timing module, and a refresh control module; the reference module is configured to save reference timing parameters; the fine-tuning module is configured to generate timing fine-tuning parameters; the timing calculation module is electrically connected to the reference module and the fine-tuning module, and the timing calculation module is configured to fine-tune the reference timing parameters based on the timing fine-tuning parameters to obtain a target clock signal and a target number of clock cycles; the timing module is electrically connected to the timing calculation module, and is configured to time according to the target clock signal, and output an indication signal when the timed time matches the target number of clock cycles; the refresh control module is electrically connected to the timing module, and generates a refresh control signal based on the indication signal.

[0006] The above scheme obtains the reference timing parameters from the reference module and the timing fine-tuning parameters from the fine-tuning module, thereby fine-tuning the reference timing parameters in the timing calculation module based on the timing fine-tuning parameters to obtain the target clock signal and the target number of clock cycles. Therefore, when adjusting the timing parameters, there is no need to manually write the new target clock signal and the target number of clock cycles. The timing calculation module can calculate the new target clock signal and the target number of clock cycles based on the parameters provided by the reference module and the fine-tuning module. Therefore, the time spent on adjusting the refresh operation timing can be reduced, thereby improving efficiency.

[0007] In which, the timing calculation module is also configured to save the target clock signal and the target clock cycle number to the reference module when the refresh margin when refreshing all storage units in the library of the storage device based on the target clock signal and the target clock cycle number meets the target margin requirement.

[0008] Among them, the reference timing parameters include the reference row address enable time and the reference row address pre-charge time; the timing fine-tuning parameters include the row address enable fine-tuning time and the row address pre-charge fine-tuning time; the target clock cycle number includes the target row address enable clock cycle number and the target row address pre-charge clock cycle number.

[0009] In which, the timing module includes a first timer and a second timer; the first timer is configured to use the target clock signal as a clock count, and when the count reaches the target row address enable clock cycle number, output a first indication signal to enable the refresh control module to generate a pre-charge signal based on the first indication signal; the second timer is configured to use the target clock signal as a clock count, and when the count reaches the target row address pre-charge clock cycle number or the sum of the target row address pre-charge clock cycle number and the target row address enable clock cycle number, output a second indication signal to enable the refresh control module to generate a row activation signal based on the second indication signal.

[0010] Among them, the reference timing parameters include a reference clock signal; the timing fine-tuning parameters include a clock signal fine-tuning value; the timing calculation module is further configured to fine-tune the reference clock signal based on the clock signal fine-tuning value to obtain the target clock signal.

[0011] Among them, the reference timing parameters also include the reference row address enable clock cycle number and the reference row address pre-charge clock cycle number; the timing fine-tuning parameters include the row address enable clock cycle number fine-tuning value and the row address pre-charge clock cycle number fine-tuning value; the timing calculation module is also configured to fine-tune the reference row address enable clock cycle number and the reference row address pre-charge clock cycle number based on the row address enable clock cycle number fine-tuning value and the row address pre-charge clock cycle number fine-tuning value to obtain the target clock cycle number.

[0012] The timing module includes a counter for accessing the target clock signal and counting the number of cycles of the target clock signal.

[0013] The timing calculation module is configured to add / subtract the timing fine-tuning parameter on the basis of the reference timing parameter to obtain the target clock signal and the target number of clock cycles.

[0014] The reference module includes an electronic fuse, and the fine-tuning module includes a DFT test circuit, which is used to generate the timing fine-tuning parameter according to the working condition of the storage device.

[0015] The refresh control module triggers different numbers of refresh control signals in a single row refresh cycle to trigger different times of activation-precharge operations according to different working conditions of the storage device.

[0016] The present application also provides an electronic device comprising the above-mentioned storage device.

[0017] The above scheme obtains the reference timing parameters from the reference module and the timing fine-tuning parameters from the fine-tuning module, thereby fine-tuning the reference timing parameters in the timing calculation module based on the timing fine-tuning parameters to obtain the target clock signal and the target number of clock cycles. Therefore, when adjusting the timing parameters, there is no need to manually write the new target clock signal and the target number of clock cycles. The timing calculation module can calculate the new target clock signal and the target number of clock cycles based on the parameters provided by the reference module and the fine-tuning module. Therefore, the time spent on adjusting the refresh operation timing can be reduced, thereby improving efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present application will be further described below with reference to the accompanying drawings and implementation methods, in which:

[0019] Figure 1 is a schematic diagram of a frame of a storage device in an embodiment of the present application;

[0020] Figure 2 1 is a timing diagram of a refresh operation in an embodiment of the present application;

[0021] Figure 3 is a schematic diagram of a frame of a storage device in another embodiment of the present application;

[0022] Figure 4 is a schematic diagram of a frame of a storage device in another embodiment of the present application;

[0023] Figure 5 is a signal timing diagram of a refresh operation in an embodiment of the present application;

[0024] Figure 6 It is a schematic diagram of the framework of an embodiment of an electronic device in this application. DETAILED DESCRIPTION

[0025] To help those skilled in the art better understand the technical solutions of this application, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and specific implementation methods. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of this application.

[0026] The terms used in the examples of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in the examples of this application and the appended claims are also intended to include plural forms. Unless otherwise clearly indicated above, "a plurality" generally includes at least two, but does not exclude the inclusion of at least one.

[0027] It should be understood that the term "and / or" as used herein is merely a description of the association relationship between associated objects, indicating that three possible relationships exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship. The terms "first," "second," etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0028] It should be understood that the terms "comprises," "comprising," or any other variations thereof as used herein are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0029] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0030] Since capacitors storing data naturally discharge over time, if the charge is not replenished in time, the stored data will be lost. To ensure that refresh operations can maintain data accuracy under different operating conditions (such as process, temperature, voltage, etc.), the optimal performance balance can be found by adjusting the timing of the refresh operation. For example, when adjusting the timing of the refresh operation, different timings can be written to determine the timing that achieves the optimal performance balance.

[0031] However, currently, adjusting the timing of the refresh operation by writing different timings is relatively complex and time-consuming, resulting in low efficiency.

[0032] To this end, the present application provides a storage device and an electronic device to reduce the time consumption of adjusting the refresh operation timing and improve efficiency. Figure 1 , including: a reference module 110, a fine-tuning module 120, a timing calculation module 130, a timing module 140, and a refresh control module 150; the reference module 110 is configured to save reference timing parameters; the fine-tuning module 120 is configured to generate timing fine-tuning parameters; the timing calculation module 130 is electrically connected to the reference module 110 and the fine-tuning module 120, and the timing calculation module 130 is configured to fine-tune the reference timing parameters based on the timing fine-tuning parameters to obtain a target clock signal and a target number of clock cycles; the timing module 140 is electrically connected to the timing calculation module 130, and is configured to time according to the target clock signal, and output an indication signal when the timed time matches the target number of clock cycles; the refresh control module 150 is electrically connected to the timing module 140, and generates a refresh control signal based on the indication signal.

[0033] It is understood that in the storage device, timing can be performed based on a clock signal, for example, based on the number of received clock signals. Therefore, the timing time matches the target number of clock cycles, and the number of target clock signals received by the timing module 140 can be the same as the target number of clock cycles.

[0034] The above scheme obtains the reference timing parameters from the reference module 110 and the timing fine-tuning parameters from the fine-tuning module 120, so that the reference timing parameters are fine-tuned in the timing calculation module 130 based on the timing fine-tuning parameters to obtain the target clock signal and the target number of clock cycles. Therefore, when adjusting the timing parameters, there is no need to manually write the new target clock signal and the target number of clock cycles. The timing calculation module 130 can calculate the new target clock signal and the target number of clock cycles based on the parameters provided by the reference module 110 and the fine-tuning module 120. Therefore, the time spent on adjusting the refresh operation timing can be reduced, thereby improving efficiency.

[0035] Please note that, please refer to Figure 2 In this article, "timing" (or timing parameters) refers to the time for each stage of refreshing a row or multiple rows within a row refresh cycle time (the full name in English is Row Refresh Cycle Time, which is "tRFC" specified in the industry standard). For example, when refreshing a row within a tRFC time, it can include the row address enable time (Row Address Strobe Active Time, tRAS) and the row address precharge time (RowPrecharge Time, tRP). Therefore, "timing" (or timing parameters) can include the duration of tRAS and tRP, and adjusting the timing (or timing parameters) can be adjusting the duration of tRAS and / or tRP. "Timing" (or timing parameters) can also include other times, such as tRCD, etc., which are not limited in this application. The definitions of tRFC, tRCD, tRAS and tRP mentioned above are known to those skilled in the art and will not be repeated here.

[0036] The following combination Figure 1 and Figure 2 , the timing of the refresh operation in an embodiment of the present application is exemplified. Figure 2In this diagram, Gnd on the vertical axis represents the ground (typically 0V); Vcc is the power supply voltage; Vref represents the reference voltage, which is typically half of Vcc; Vcc+Vt represents the wordline overdrive voltage, where Vt is the transistor threshold voltage. The horizontal axis shows the different stages of a refresh operation, such as the precharge stage, access stage, sense stage, and data recovery (Rstore) stage. Among them, tRAS defines the minimum interval time from the start of the Access phase to the start of the precharge phase, corresponding to the row activation (Activate) and data recovery (Restore) phases in the refresh operation. Within tRAS, the memory completes the charge refresh and data recovery of the first row (or wordline). Therefore, after waiting for tRAS, the refresh control module 150 considers the refresh complete, thereby closing the first row and preparing for the next refresh; tRP includes the time corresponding to the precharge phase. After waiting for tRP, the refresh control module 150 considers the next precharge operation to be complete and opens the second row; tRCD defines the delay time from row strobe to column strobe. The row refresh cycle time (tRFC) is the sum of tRAS and tRP. The refresh control module 150 must wait for at least tRFC to end before initiating the next refresh or read / write operation (this interval can be called the Refresh Interval). In the Access phase, the voltage of the wordline rises to Vcc+Vt and remains high in the Sense phase to maintain data reading. The bitline voltage is precharged to Vref during the Precharge phase. During the Access phase, a voltage difference is generated based on the charge on the memory cell capacitor. This voltage difference is amplified to its full swing by the sense amplifier during the Sense phase. SAP / SAN are the sense amplifier control signals used to control the operation of the sense amplifier. They are activated during the Sense phase, where the SAP signal is pulled high (e.g., to Vcc) and the SAN signal is pulled low (e.g., to Gnd). This amplifies the tiny bitline voltage difference to a logic level through positive feedback. CSL is the column select signal used to select the column containing the target memory cell and is activated during the Restore phase.

[0037] The storage device of the present application can be a dynamic random access memory (DRAM) or other types of storage devices, including but not limited to SRAM, ROM, PROM, EEPROM, SDRAM, DDR / 2SDRAM, DDR / 3SDRAM, DDR / 4SDRAM, GDDRx, EDO / FPMS, FeRAM, ReRAM, RLDRAM, etc.

[0038] During both the pre-shipment test phase and the post-shipment usage phase, the timing calculation module 130 , the reference module 110 , the fine-tuning module 120 , the timing module 140 , and the refresh control module 150 can be used to determine the appropriate refresh operation timing under certain operating conditions.

[0039] During the pre-shipment testing phase, when determining the timing of the refresh operation of the storage device under different operating conditions, the storage device can be operated under different operating conditions to debug the appropriate timing under various operating conditions. For example, the storage device can be operated at different temperatures to debug the appropriate timing at different temperatures. Since the appropriate timing is different at different temperatures, in order to improve debugging efficiency, when determining the timing under the current temperature conditions, fine-tuning can be performed on the basis of a known appropriate timing under a similar temperature condition to obtain the timing parameters to be tested. The known appropriate timing under the similar temperature condition is the reference timing parameter. Assuming that the appropriate refresh operation timing at 25 degrees Celsius has been determined, when determining the appropriate refresh operation timing at 30 degrees Celsius, the appropriate refresh operation timing at 25 degrees Celsius can be used as the reference timing parameter. Based on the reference timing parameter, fine-tuning can be performed to obtain several timing parameters to be tested, so as to obtain the appropriate refresh operation timing at 30 degrees Celsius from the several timing parameters to be tested.

[0040] The reference module 110 may store only one timing parameter, which is the reference timing parameter. For example, the appropriate refresh operation timing under the condition closest to the current test condition may be stored. For example, if the current test condition is 30 degrees Celsius, and appropriate refresh operation timings under 15 degrees Celsius, 20 degrees Celsius, and 25 degrees Celsius have been previously determined, the appropriate refresh operation timing under 25 degrees Celsius may be stored as the reference timing parameter in the reference module 110. The reference module 110 may also store multiple timing parameters. For example, the appropriate refresh operation timings under 15 degrees Celsius, 20 degrees Celsius, and 25 degrees Celsius may be stored. When determining the appropriate refresh operation timing under 30 degrees Celsius, the appropriate refresh operation timing under 25 degrees Celsius may be selected as the reference timing parameter.

[0041] It can be understood that the reference timing parameters correspond to the target clock signal and the target clock cycle number, that is, the reference timing parameters include the reference clock signal and the reference clock cycle number.

[0042] The timing calculation module 130 can obtain one or more target clock signals and target clock cycle numbers based on the reference timing parameters provided by the reference module 110 and the timing fine-tuning parameters provided by the fine-tuning module 120, so as to directly determine the appropriate refresh operation timing based on the target clock signals and target clock cycle numbers.

[0043] During the pre-shipment test phase, after obtaining a suitable refresh operation timing (ie, target clock signal and target clock cycle number) under a certain operating condition according to the above embodiment, the target clock signal and target clock cycle number may be saved to the reference module 110 .

[0044] In the use phase after leaving the factory, since the appropriate refresh operation timing under various operating conditions has been basically determined in the test phase before leaving the factory, the timing obtained in the test phase can be used directly. However, the timing determined in the test phase may still not meet the requirements of actual use. For example, some usage scenarios have high requirements for the accuracy of the refresh operation. Therefore, in the use phase, it may be necessary to further fine-tune the appropriate timing determined in the test phase to obtain a more appropriate refresh operation timing. At this time, the appropriate refresh operation timing corresponding to the current operating condition determined in the test phase can be used as a reference timing parameter. For example, assuming that the current operating condition is 25 degrees Celsius, the appropriate refresh operation timing at 25 degrees Celsius is determined in the test phase (referred to as the first timing here). In the use phase, the first timing can be used as a reference timing parameter and fine-tuned based on the first timing. The specific process of fine-tuning the reference timing parameters to obtain the target clock signal and the target number of clock cycles can refer to the description of the test phase before leaving the factory in the aforementioned embodiment. The only difference is that in the use phase after leaving the factory, after obtaining the appropriate refresh operation timing (i.e., the target clock signal and the target number of clock cycles) under the current operating conditions, the target clock signal and the target number of clock cycles will not be saved to the reference module 110.

[0045] If the appropriate refresh operation timing under the current operating conditions is not recorded during the pre-factory testing phase, then the appropriate refresh operation timing under similar operating conditions can be selected as the baseline timing parameter during the post-factory usage phase. For example, if the current operating condition is 28 degrees Celsius, and the pre-factory testing phase only records the appropriate refresh operation timing at 25 degrees Celsius or 30 degrees Celsius, then the appropriate refresh operation timing at 25 degrees Celsius or 30 degrees Celsius can be used as the baseline timing parameter. Based on the baseline timing parameters, fine-tuning can be performed to obtain the target clock signal and target clock cycle number. For details, please refer to the previous embodiment and will not be repeated here.

[0046] In some embodiments, the timing calculation module 130 is further configured to save the target clock signal and the target clock cycle number to the reference module 110 when the refresh margin when refreshing all storage cells in the library based on the target clock signal and the target clock cycle number meets the target margin requirement.

[0047] Since the JEDEC standard requires a maximum refresh time for a bank in a storage device, that is, the maximum refresh time for refreshing a bank cannot exceed a predetermined standard value. For example, at room temperature, the predetermined standard value is 64ms. When determining a more appropriate refresh operation timing under certain operating conditions, if the refresh cycle when refreshing the bank according to a certain target clock signal and target clock cycle number does not exceed the predetermined standard value, and there is a certain margin from the predetermined standard value, then the target clock signal and target clock cycle number can be considered to be the appropriate refresh operation timing under the current operating conditions. Then, during the pre-shipment testing phase, the target clock signal and target clock cycle number can be saved in the reference module 110; or, during the post-shipment use phase, subsequent refresh operations can be performed based on the target clock signal and target clock cycle number.

[0048] It should be noted that when the refresh period when refreshing the library according to a certain target clock signal and target clock cycle number does not exceed the predetermined standard value, and there is a certain margin from the predetermined standard value, it can be determined that the refresh margin when refreshing all the storage units in the library based on the target clock signal and target clock cycle number meets the target margin requirement. The target margin requirement can be 4ms, 5ms, etc., which is not limited here. For example, assuming that the target margin requirement is 4ms (i.e., the margin is required to be greater than or equal to 4ms), the time required to refresh all the storage units in the library according to the target clock signal and target clock cycle number is 60ms, and the margin is 4ms at this time, it is considered that the target margin requirement is met.

[0049] In some embodiments, the reference timing parameters include a reference row address enable time and a reference row address pre-charge time; the timing fine-tuning parameters include a row address enable fine-tuning time and a row address pre-charge fine-tuning time; the target clock cycle number includes a target row address enable clock cycle number and a target row address pre-charge clock cycle number.

[0050] The timing fine-tuning parameters are used to fine-tune the reference timing parameters. Assuming that the reference timing parameters include the reference durations of tRAS and tRP (i.e., the reference row address enable time and the reference row address precharge time), the timing fine-tuning parameters can be used to fine-tune tRAS and tRP. One or more timing fine-tuning parameters, such as 0.5μs, 1μs, 2μs, etc., can be generated in the fine-tuning module 120. A timing fine-tuning parameter also includes a pair of timing fine-tuning sub-parameters (i.e., row address enable fine-tuning time and row address precharge fine-tuning time). The row address enable fine-tuning time is used to fine-tune tRAS, and the row address precharge fine-tuning time is used to fine-tune tRP. The row address enable fine-tuning time and the row address precharge fine-tuning time can be equal or unequal.

[0051] In some embodiments, when fine-tuning tRAS and tRP, if tRAS increases, tRP can be reduced accordingly; if tRAS decreases, tRP can be increased accordingly, i.e., the total duration of tRAS and tRP remains unchanged. For example, if tRAS increases by 1 μs, tRP can be reduced by 1 μs. In some embodiments, the total duration of tRAS and tRP can vary, for example, tRAS and tRP can be increased or decreased simultaneously.

[0052] In some embodiments, please refer to Figure 2 The timing module 140 includes a first timer 141 and a second timer 142; the first timer 141 is configured to use the target clock signal as a clock count, and when the count reaches the target row address enable clock cycle number, output a first indication signal to enable the refresh control module 150 to generate a precharge signal based on the first indication signal; the second timer 142 is configured to use the target clock signal as a clock count, and when the count reaches the target row address precharge clock cycle number or the sum of the target row address precharge clock cycle number and the target row address enable clock cycle number, output a second indication signal to enable the refresh control module 150 to generate a row activation signal based on the second indication signal.

[0053] Timing module 140 may be connected to a gating circuit (not shown), which may provide a gating signal to timing module 140. Timing module 140 may be enabled upon receiving the gating signal. For example, first timer 141 and second timer 142 may be enabled upon receiving the gating signal. In some embodiments, the gating signal may be generated based on a clock signal generated by an oscillator circuit (not shown).

[0054] The first timer 141 and the second timer 142 can start counting after receiving the gating signal. For example, when the count value of the first timer 141 reaches the target row address enable clock cycle number, a first indication signal is output, indicating that a time equivalent to the target row address enable clock cycle number has elapsed. When the count time of the second timer 142 reaches the target row address precharge clock cycle number or the sum of the target row address precharge clock cycle number and the target row address enable clock cycle number, a second indication signal is output, indicating that a time equivalent to the target row address precharge clock cycle number or the sum of the target row address precharge clock cycle number and the target row address enable clock cycle number has elapsed.

[0055] In some embodiments, the timing module 140 may further include a comparison circuit, which may be connected to the first timer 141, the second timer 142, and the timing calculation module 130, so as to compare the count values of the first timer 141 / the second timer 142 with the target clock signal and the target number of clock cycles provided by the timing calculation module 130. The comparison circuit may include a comparator or other integrated circuit with a comparison function.

[0056] In some embodiments, the reference timing parameters include a reference clock signal, a reference row address enable clock cycle number, and a reference row address pre-charge clock cycle number; the timing fine-tuning parameters include a clock signal fine-tuning value, a row address enable clock cycle number fine-tuning value, and a reference row address pre-charge clock cycle number fine-tuning value; the timing calculation module 130 is also configured to fine-tune the reference clock signal based on the clock signal fine-tuning value to obtain the target clock signal, or to fine-tune the reference row address enable clock cycle number and the reference row address pre-charge clock cycle number based on the row address enable clock cycle number fine-tuning value and the row address pre-charge clock cycle number fine-tuning value to obtain the target clock cycle number.

[0057] The clock signal can be provided by an oscillator circuit (not shown in the figure). In some embodiments, the period of the clock signal provided by the oscillator circuit can be fixed. Therefore, the reference row address start clock cycle number and the reference row address pre-charge clock cycle number can be fine-tuned by fine-tuning the row address start clock cycle number and the row address pre-charge clock cycle number to obtain the target clock cycle number (for example, the target row address start clock cycle number and the target row address pre-charge clock cycle number). The timing module 140 counts based on the fine-tuned target clock cycle number, and generates a first indication signal and a second indication signal when the count value reaches the target clock cycle number, thereby achieving the effect of adjusting the timing parameters.

[0058] In some embodiments, the clock signal can be fine-tuned, that is, the timing calculation module is configured to fine-tune the reference clock signal based on the clock signal fine-tuning value to obtain the target clock signal; for example, the period of the clock signal is fine-tuned, so as to achieve the effect of adjusting the timing parameters by changing the period of the clock signal without changing the number of reference row address start clock cycles and the number of reference row address pre-charge clock cycles.

[0059] In some embodiments, the clock signal and the reference row address enable clock cycle number and the reference row address pre-charge clock cycle number can also be fine-tuned simultaneously, that is, the timing calculation module can also be configured to fine-tune the reference clock signal based on the clock signal fine-tuning value to obtain the target clock signal, and to fine-tune the reference row address enable clock cycle number and the reference row address pre-charge clock cycle number based on the row address enable clock cycle number fine-tuning value and the row address pre-charge clock cycle number fine-tuning value to obtain the target clock cycle number, thereby achieving the effect of adjusting the timing parameters by adjusting the period of the clock signal and adjusting the target clock cycle number.

[0060] In some embodiments, the timing module 140 includes a counter (not shown) for receiving a target clock signal and counting the number of cycles of the target clock signal.

[0061] In some embodiments, the timing calculation module 130 is configured to add / subtract the timing fine-tuning parameter on the basis of the reference timing parameter to obtain the target clock signal and the target number of clock cycles.

[0062] As described in the above embodiments, the timing fine-tuning parameters are used to fine-tune the reference timing parameters, and thus can be used to fine-tune the period of the reference clock signal. The timing calculation module 130 can include an addition circuit, a subtraction circuit, or other integrated circuits capable of performing addition and subtraction operations.

[0063] In some embodiments, the timing calculation module 130 is configured to multiply the reference timing parameter by the timing fine-tuning parameter to obtain the target clock signal and the target number of clock cycles.

[0064] Unlike the previous embodiment, the timing fine-tuning parameter in this embodiment is used to multiply the reference timing parameter to obtain the target clock signal and target number of clock cycles. For example, the reference timing parameter can be adjusted in 5% increments, so the timing fine-tuning parameter can be 1.05, 1.1, 0.95, etc. Alternatively, the timing fine-tuning parameter can be adjusted unevenly, for example, the timing fine-tuning parameter can be 1.01, 1.03, 1.06, 1.10, etc. In other words, the timing fine-tuning parameter can be a fine-tuning ratio value, and the target clock signal and target number of clock cycles can be obtained by multiplying the reference timing parameter by the fine-tuning ratio value. In this case, the timing calculation module 130 can include a multiplication circuit or other integrated circuit capable of performing multiplication functions.

[0065] In some embodiments, reference module 110 includes electronic fuses, and trim module 110 includes a Design For Test (DFT) test circuit for generating timing trimming parameters based on the operating conditions of the storage device. During pre-shipment testing, the target clock signal and target clock cycle count can be stored in reference module 110 via electronic fuses.

[0066] Please refer to Figure 4 and combined Figure 5 The memory device 100 communicates with the outside world via an input pin (eg, a command pin PAD_CMD<3:0> of a DDR interface) 410, for example, receiving a refresh instruction REF from a controller, a host, or a system bus (for details, see Figure 5The command latch 420 temporarily stores the external refresh command REF and converts it into a refresh command signal CMD_REF recognizable within the memory device 100. The command latch 420 then stably outputs the refresh command signal CMD_REF to the command counter 430. The command counter 430 receives the refresh instruction signal CMD_REF output by the command latch 420, counts the refresh instruction signal CMD_REF, and generates a target row address of the refresh instruction based on the number of times the refresh instruction signal CMD_REF is received. For example, the target row address can be generated by gradually increasing according to a preset step size when the refresh instruction signal CMD_REF is received; and, after receiving the refresh instruction signal CMD_REF, the command counter 430 further sends a refresh stage indication signal REF_STA to the timing module 140 to indicate entering the refresh stage (or refresh state); the timing module 140 can receive the refresh stage indication signal REF_STA, for example, when the refresh stage indication signal REF_STA is at a high level, it indicates that the current state is in the refresh stage. The timing module 140 can start counting the received clock signal after receiving the refresh phase indication signal REF_STA. For example, when the count value reaches the target row address start clock cycle number and the target row address precharge clock cycle number, it generates a first indication signal and a second indication signal respectively, so that the refresh control module 150 generates a refresh control signal REF_BAC to the refresh module 400, and the refresh module 400 is used to perform a refresh operation according to the refresh control signal REF_BAC. For example, when the count value of the first timer 141 reaches the target row address start clock cycle number, the first timer 141 generates a first indication signal (combined with Figure 2 , the first indication signal can be used to indicate that a time equivalent to tRAS has passed, at which time the Precharge phase can be entered). After receiving the first indication signal, the refresh control module 150 generates a corresponding refresh control signal REF_BAC (for example, a precharge signal) to enable the refresh module 400 to perform a refresh operation under the Precharge phase, that is, to perform precharge. When the count value of the second timer 142 reaches the number of precharge clock cycles of the target row address, or reaches the sum of the number of precharge clock cycles of the target row address and the number of enable clock cycles of the target row address, the second timer 142 generates a second indication signal (combined with Figure 2The second indication signal can be used to indicate that a time equivalent to tRP has elapsed, at which point the Access phase can be entered. Upon receiving the second indication signal, the refresh control module 150 generates a corresponding refresh control signal REF_BAC (e.g., a row activation signal) to cause the refresh module 400 to perform a refresh operation in the Access phase, i.e., perform row activation. The refresh control signal REF_BAC is used within the memory device 100 to control the refresh module 400's actions during different phases of the refresh operation. For example, it controls the refresh module 400's actions during the precharge phase (Precharge) and the activation phase (Active).

[0067] In some embodiments, the refresh control module 150 further triggers different numbers of refresh control signals in a single row refresh cycle to trigger different times of activate-precharge operations according to different operating conditions of the storage device 100 .

[0068] Please refer to Figure 5 , Figure 5 The signal waveform diagram of the refresh operation of an embodiment of the present invention, wherein PAD_CLK is a clock signal. In a further embodiment, within a row refresh cycle, if the refresh control module 150 determines that a low temperature or other working condition is detected, the number of RC triggers can be reduced to reduce the number of times the refresh control signal REF_BAC is triggered, thereby saving dynamic power consumption within the tRFEI (Refresh Interval) cycle. Figure 5 As shown in the upper and lower groups of signal waveforms, the second group of signal waveforms reduces the number of times the refresh control signal REF_BAC is triggered compared to the first group of signal waveforms. Among them, the RC number is the number of active-precharge operations triggered within a row refresh cycle, which can also be said to be the number of word lines that rise and fall within a row refresh cycle. Figure 5 As shown, low-temperature operating conditions reduce the number of RC cycles compared to high-temperature operating conditions. This decreases the number of RC cycles as the temperature decreases, reducing the number of word lines that are activated and deactivated during a single refresh operation. Furthermore, reducing the number of RC cycles increases the row refresh cycle time within the tREFI period, thereby increasing the adjustable range of tRAS and tRP.

[0069] This application also provides an electronic device 300, please refer to Figure 6 , the electronic device 300 includes the storage device 100 in any of the above embodiments.

[0070] The electronic device 300 may include computer devices such as desktop computers, laptop computers, and tablet computers, communication devices such as mobile phones and smart phones, and home appliances such as televisions and stereos, and this application does not impose any restrictions.

[0071] It is easy for a person skilled in the art to know that many modifications and variations can be made to the apparatus and method while maintaining the teaching content of the present application.Therefore, the above disclosure should be considered as being limited only by the scope of the appended claims.

Claims

1. A storage device, characterized in that: include: a benchmark module configured to save benchmark timing parameters; A fine-tuning module is configured to generate timing fine-tuning parameters; a timing calculation module, electrically connected to the reference module and the fine-tuning module, the timing calculation module being configured to fine-tune the reference timing parameter based on the timing fine-tuning parameter to obtain a target clock signal and a target number of clock cycles; a timing module, electrically connected to the timing calculation module, configured to count time according to the target clock signal and output an indication signal when the counted time matches the target clock cycle number; The refresh control module is electrically connected to the timing module and generates a refresh control signal based on the indication signal.

2. A storage device according to claim 1, characterized in that: The timing calculation module is further configured to save the target clock signal and the target clock cycle number to the reference module when a refresh margin when refreshing all storage cells in the library of the storage device based on the target clock signal and the target clock cycle number meets a target margin requirement.

3. The storage device according to claim 1, wherein: The reference timing parameters include a reference row address enable time and a reference row address precharge time; the timing fine-tuning parameters include a row address enable fine-tuning time and a row address precharge fine-tuning time; The target number of clock cycles includes a target row address enable clock cycle number and a target row address precharge clock cycle number.

4. A storage device according to claim 3, characterized in that: The timing module includes: a first timer configured to use the target clock signal as a clock count, and when the count reaches the target row address enable clock cycle number, output a first indication signal to enable the refresh control module to generate a precharge signal based on the first indication signal; The second timer is configured to use the target clock signal as a clock count, and when the count reaches the number of pre-charge clock cycles of the target row address or the sum of the number of pre-charge clock cycles of the target row address and the number of enable clock cycles of the target row address, output a second indication signal to enable the refresh control module to generate a row activation signal based on the second indication signal.

5. The storage device according to claim 1, wherein: The reference timing parameters include a reference clock signal; the timing fine-tuning parameters include a clock signal fine-tuning value; The timing calculation module is further configured to fine-tune the reference clock signal based on the clock signal fine-tuning value to obtain the target clock signal.

6. A storage device according to claim 1 or 5, characterized in that: The reference timing parameters also include the reference row address enable clock cycle number and the reference row address precharge clock cycle number; the timing fine-tuning parameters include the row address enable clock cycle number fine-tuning value and the row address precharge clock cycle number fine-tuning value; The timing calculation module is further configured to fine-tune the reference row address enable clock cycle number and the reference row address pre-charge clock cycle number based on the row address enable clock cycle number fine-tuning value and the row address pre-charge clock cycle number fine-tuning value to obtain the target clock cycle number.

7. A storage device according to claim 6, characterized in that: The timing module includes a counter, which is used to access the target clock signal and count the number of cycles of the target clock signal.

8. The storage device according to claim 1, wherein: The timing calculation module is used to add / subtract the timing fine-tuning parameter on the basis of the reference timing parameter to obtain the target clock signal and the target number of clock cycles.

9. The storage device according to claim 1, wherein: The reference module includes an electronic fuse, and the fine-tuning module includes a DFT test circuit, which is used to generate the timing fine-tuning parameter according to the working condition of the storage device.

10. The storage device according to claim 1, wherein: The refresh control module triggers different numbers of refresh control signals in a single row refresh cycle time according to different working conditions of the storage device to trigger different times of activation-precharge operations.

11. An electronic device, characterized in that: The storage device comprises the storage device according to any one of claims 1 to 10.

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