Storage test circuit, chip and vehicle

Abstract

The invention provides a storage test circuit, a chip and a vehicle, the storage test circuit comprises a conversion module and a test module, the conversion module and the test module are arranged in the chip, the conversion module is connected with test pins of the test module and the chip, and the test module is connected with a plurality of storage modules in the chip; the conversion module is used for receiving the test signal and the key signal through the test pin, and converting the test signal into a test instruction when the key signal is successfully matched; and the test module is used for testing a target storage module in the plurality of storage modules according to the test instruction. A designer can set the key signal by himself / herself, and a stranger cannot know the key signal, so that the content of the storage module in the chip cannot be tampered, and the security of the chip is improved.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a storage test circuit, a chip and a vehicle. Background Art

[0002] Many chips currently have storage functions, such as MCU (Microcontroller Unit) chips, DSP (Digital Signal Process) chips, and SOC (System on Chip) chips. Testing the memory modules in these chips requires the use of the MBIST (Memory Build In Self-Test) circuit provided by the memory module manufacturer. This requires reserving a test interface on the chip, which is equivalent to leaving a backdoor in the chip and poses a security risk. Summary of the Invention

[0003] The embodiments of the present application provide a storage test circuit, chip and vehicle, which can solve the problem that the chip storage module test reserves a test interface for the chip, resulting in safety hazards to the chip.

[0004] In a first aspect, an embodiment of the present application provides a storage test circuit, comprising a conversion module and a test module, wherein the conversion module and the test module are both arranged in a chip, the conversion module being connected to the test module and the test pins of the chip, respectively, and the test module being connected to a plurality of storage modules in the chip, respectively;

[0005] The conversion module is used to receive a test signal and a key signal through the test pin, and convert the test signal into a test instruction when the key signal matches successfully; the test module is used to test a target storage module among the multiple storage modules according to the test instruction.

[0006] In a possible implementation of the first aspect, the test module is also used to transmit the test result signal of the target storage module to the conversion module; the conversion module is also used to convert the test result signal and transmit the converted test result signal to the test pin of the chip.

[0007] In a possible implementation of the first aspect, the test signal includes a test operation signal and a selection signal, the test instruction includes a test operation instruction and a selection instruction, the test module includes a selection unit and a plurality of test units, the selection unit is connected to the conversion module and all the test units respectively, and the plurality of test units are connected to the plurality of storage modules in a one-to-one correspondence;

[0008] The conversion module is also used to convert the test operation signal into a test operation instruction and convert the selection signal into a selection instruction when the key signal matches successfully; the selection unit is also used to transmit the test operation instruction to the target test unit corresponding to the target storage module according to the selection instruction, and the target test unit is used to test the target storage module according to the test operation instruction.

[0009] In a possible implementation of the first aspect, the test signal includes a plurality of test operation signals, and the selection signal includes a timing signal;

[0010] The conversion module is also used to convert each of the test operation signals into a test operation instruction and convert the timing signal into a timing instruction when the key signal matches successfully; the selection unit is also used to transmit multiple test operation instructions in sequence to multiple target test units corresponding to multiple target storage modules according to the timing instructions; each target test unit is used to test the target storage module corresponding to it according to the received test operation instruction.

[0011] In a possible implementation of the first aspect, the conversion module is further configured to adjust the timing of the timing signal when the key signal matches successfully, and convert the adjusted timing signal to obtain the timing instruction.

[0012] In a possible implementation of the first aspect, the selection unit is used to obtain the test result signals output by multiple target test units in sequence according to the timing instructions, and transmit the multiple test result signals to the conversion module in sequence; the conversion module is also used to convert the multiple test result signals, and transmit the converted test result signals to the test pins of the chip in sequence.

[0013] In a possible implementation of the first aspect, the storage test circuit further includes an interface module disposed in the chip, the interface module being connected to the conversion module and the test pin respectively;

[0014] The interface module is used to receive the test signal and the key signal, and transmit the test signal and the key signal to the conversion module.

[0015] In a possible implementation manner of the first aspect, the interface module is a parallel interface, a serial interface, or a custom communication interface.

[0016] In a second aspect, an embodiment of the present application provides a chip comprising the storage test circuit described in any one of the first aspects.

[0017] In a third aspect, an embodiment of the present application provides a vehicle comprising the chip described in the second aspect.

[0018] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0019] The storage test circuit provided in the embodiment of the present application includes a conversion module and a test module. The conversion module and the test module are both arranged in the chip. The conversion module is respectively connected to the test pins of the test module and the chip, and the test module is respectively connected to multiple storage modules in the chip.

[0020] When testing a memory module in a chip, a test device is connected to the chip's test pins. The test device transmits a test signal and a key signal. After receiving the test signal and key signal via the chip's test pins, the conversion module first matches the key signal. If the key signal match fails, the conversion module does not convert the test signal, and subsequent testing of the memory module cannot proceed. If the key signal match succeeds, the test signal is converted into a test instruction. The test module is used to test a target memory module among multiple memory modules according to the test instruction.

[0021] Because the conversion module requires a key signal match before converting the signal, if the key signal matches, the conversion module converts the test signal into the corresponding instruction, allowing subsequent testing of the storage module. If the key signal matches, the conversion module does not convert the test signal, and subsequent testing of the storage module is impossible. Therefore, designers can set the key signal themselves, making it impossible for outsiders to obtain the key signal and tamper with the contents of the storage module in the chip, thereby improving chip security.

[0022] It can be understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0024] Figure 1 This is a principle block diagram of a storage test circuit provided in one embodiment of the present application;

[0025] Figure 2 is a principle block diagram of a storage test circuit provided in another embodiment of the present application;

[0026] Figure 3is a principle block diagram of a storage test circuit provided in yet another embodiment of the present application;

[0027] Figure 4 This is a flowchart of a storage testing method provided in one embodiment of the present application. DETAILED DESCRIPTION

[0028] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0029] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0030] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0031] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0032] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0033] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0034] Testing the memory modules in a chip requires the use of the MBIST circuit provided by the memory module manufacturer. This requires a test interface on the chip, creating a backdoor that allows outsiders to tamper with the program in the memory module through the test interface, posing a security risk to the chip. Furthermore, the MBIST circuit provided by the memory module manufacturer is complex, increasing the cost of chip testing.

[0035] Based on the above problems, the present invention provides a storage test circuit. Figure 1 As shown, the storage test circuit includes a conversion module 100 and a test module 200. The conversion module 100 and the test module 200 are both arranged in the chip 10. The conversion module 100 is respectively connected to the test module 200 and the test pin A of the chip 10, and the test module 200 is respectively connected to multiple storage modules 300 in the chip 10.

[0036] Specifically, when testing the storage module 300 in the chip 10, the test equipment is connected to the test pin A of the chip 10. The test equipment transmits a test signal and a key signal. After receiving the test signal and key signal via the test pin A of the chip 10, the conversion module 100 first matches the key signal with a pre-stored key signal. If the key signal does not match, the conversion module 100 does not convert the test signal, and subsequent testing of the storage module 300 cannot be performed. If the key signal matches successfully, the test signal is converted into a test instruction. The test module 200 is configured to test a target storage module 300 among the multiple storage modules 300 according to the test instruction. The test module 200 is also configured to transmit a test result signal for the target storage module 300 to the conversion module 100. The conversion module 100 is also configured to convert the test result signal and transmit the converted test result signal to the test pin A of the chip 10. The test equipment receives the test result signal and displays it. The tester can learn the test result through the displayed information, thereby completing the test of the storage module 300.

[0037] Since the conversion module 100 needs to match the key signal before converting the signal, if the key signal matches successfully, the conversion module 100 converts the test signal into the corresponding instruction, and the storage module 300 can be tested subsequently. If the key signal matches unsuccessfully, the conversion module 100 will not convert the test signal, and the storage module 300 cannot be tested subsequently. Designers can set the key signal and store it by themselves, and outsiders cannot know the key signal. Therefore, when an outsider inputs a modification signal to the chip, due to the unsuccessful matching of the secret key signal, the conversion module 100 will not convert the modification signal into the corresponding modification instruction, the storage module 300 cannot receive the modification instruction, and the content in the storage module 300 cannot be modified. Therefore, through the design of the secret key signal, outsiders cannot tamper with the content of the storage module 300 in the chip 10, thereby improving the security of the chip 10.

[0038] At the same time, the storage test circuit provided in the embodiment of the present application can test the storage module 300 in the chip 10 by setting the conversion module 100 and the test module 200 in the chip 10, without using the MBIST circuit provided by the manufacturer of the storage module 300, thereby reducing the testing cost of the chip 10.

[0039] In one embodiment of the present application, Figure 2 As shown, the test signal includes a test operation signal and a selection signal, the test instruction includes a test operation instruction and a selection instruction, the test module 200 includes a selection unit 201 and multiple test units 202, the selection unit 201 is respectively connected to the conversion module 100 and all test units 202, and the multiple test units 202 are connected one-to-one with multiple storage modules 300.

[0040] Specifically, the conversion module 100 is further configured to convert the test operation signal into a test operation instruction and the selection signal into a selection instruction when the key signal successfully matches. The selection unit 201 is further configured to transmit the test operation instruction to the target test unit 202 corresponding to the target storage module 300 based on the selection instruction. The target test unit 202 is configured to test the target storage module 300 based on the test operation instruction. By configuring the selection unit 201 and the multiple test units 202, a tester can select any target storage module 300 from the multiple storage modules 300 within the chip 10 for testing, thereby enabling the tester to determine the status of each target storage module 300, thereby improving the accuracy of the test.

[0041] Currently, when testers test the memory modules 300 in the chip 10, they can usually only test one memory module 300 at a time. After testing one memory module 300, they test another memory module 300, which results in low test efficiency.

[0042] Based on the above problem, in one embodiment of the present application, the test signal includes a plurality of test operation signals, and the selection signal includes a timing signal.

[0043] Specifically, when testing the storage module 300 in the chip 10, the test device is connected to the test pin A of the chip 10. The test device sends multiple test operation signals, timing signals and key signals. After the conversion module 100 receives multiple test operation signals, timing signals and key signals through the test pin A of the chip 10, it first matches the key signal. When the key signal is successfully matched, each test operation signal is converted into a test operation instruction, and the timing signal is converted into a timing instruction. The selection unit 201 determines multiple target storage modules 300 in the multiple storage modules 300 according to the timing instruction, and transmits the multiple test operation instructions to the multiple target test units 202 corresponding to the multiple target storage modules 300 in sequence according to the timing of the timing instruction. Each target test unit 202 controls the corresponding target storage module 300 to perform a test according to the received test operation instruction, and transmits the test result signal to the selection unit 201. The selection unit 201 is configured to sequentially acquire the test result signals output by the multiple target test units 202 according to the timing instructions and transmit the multiple test result signals sequentially to the conversion module 100. The conversion module 100 is further configured to convert each test result signal and transmit the converted test result signals sequentially to the test pin A of the chip 10. The test equipment sequentially receives the multiple test result signals via the test pin A, processes the multiple test result signals, and then displays the test result information of the multiple target memory modules 300. This allows multiple memory modules 300 to be tested simultaneously, helping to improve the testing efficiency of the chip 10.

[0044] Although designers can set the secret key signal by themselves, there is a risk of leakage of the secret key signal. Once an outsider knows the set secret key signal, they can still tamper with the content of the storage module 300 in the chip 10.

[0045] Based on the above problem, in one embodiment of the present application, the conversion module 100 is further configured to adjust the timing of the timing signal when the key signal matches successfully, and convert the adjusted timing signal to obtain a timing instruction.

[0046] Specifically, when converting the timing signal, the conversion module 100 changes the timing of the timing signal according to a preset rule, that is, the timing of the timing instruction generated by the conversion module 100 is different from the timing of the timing signal. Exemplarily, the timing of the timing signal is 1-2-3-4, that is, the first storage module, the second storage module, the third storage module, and the fourth storage module are tested in sequence. After the conversion module 100 converts the timing signal into a timing instruction, the timing of the timing instruction is 2-4-1-3, that is, the second storage module, the fourth storage module, the first storage module, and the third storage module are tested in sequence. Thus, when testing multiple storage modules, the conversion module 100 can change the timing of the test signal. Even if an outsider knows the preset secret key signal, the outsider cannot correctly operate the storage module 300 in the chip 10 if they do not know the conversion rules of the conversion module 100, further improving the security of the chip 10.

[0047] In addition to improving the security of the chip 10 by setting the conversion rules in software, the security of the chip 10 can also be improved by hardware design. In some embodiments, the test unit 202 is packaged together with the corresponding storage module 300.

[0048] Specifically, the test unit 202 is packaged together with the corresponding storage module 300 to form a new storage module 300. That is, the storage module 300 is improved by adding the test unit 202 to the original storage module 300. The test unit 202 can control the storage module 300 to perform tests according to the test operation instructions. Outsiders are unaware of the testing principles of the test unit 202, which can prevent outsiders from tampering with the content stored in the storage module 300, thereby improving the security of the chip 10.

[0049] In some embodiments, as Figure 3 As shown, the storage test circuit further includes an interface module 400 disposed in the chip 10 , and the interface module 400 is connected to the conversion module 100 and the test pin A respectively.

[0050] Specifically, interface module 400 is used to receive test signals and key signals and transmit them to conversion module 100. Interface module 400 performs signal transmission, namely, it can transmit the test signals and key signals output by the test equipment to conversion module 100. It can also transmit the test result signal output by conversion module 100 to test pin A of chip 10, and then to the test equipment. Interface module 400 can achieve stable signal transmission, improving the stability of data exchange between the test equipment and chip 10.

[0051] For example, the interface module 400 may be a parallel interface, a serial interface (eg, an SPI interface or an IIC interface), or a custom communication interface. In addition, the interface module 400 may be multiplexed with the IO interface on the chip 10, thereby reducing the cost of the chip 10.

[0052] Exemplarily, the storage module 300 in the chip 10 may include multiple types of memories, for example, FLASH memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), OPT (One Time Programmable), MTP (Multiple Time Programmable), SRAM (Static Random Access Memory) and ROM (Read-Only Memory), etc.

[0053] Each storage module 300 is provided with a corresponding test unit 202. When the test unit 202 receives a test operation instruction, it inputs the test operation instruction into the storage module 300. After receiving the unlock instruction in the test operation instruction, the storage module 300 unlocks. When the unlocking is successful, it identifies whether the test operation instruction is a read instruction or a write instruction, and then performs the corresponding read and write operations based on the identification result. After completing the read and write operations, the storage module 300 returns a test result signal, and the test unit 202 transmits the test signal to the selection unit 201. The selection unit 201 transmits the test result signal to the conversion module 100. The conversion module 100 converts the test result signal and transmits the converted test result signal to the test pin A of the chip 10, thereby implementing the test of the storage module 300.

[0054] Figure 4 FIG2 shows a flow chart of a storage test method provided by an embodiment of the present application. Figure 3 The storage test method shown includes steps S301 to S303.

[0055] Step S301: Acquire a test signal and a key signal.

[0056] Specifically, when testing the memory module in the chip, a test device is connected to the test pin of the chip, and the test device sends a test signal and a key signal. The test pin of the chip can receive the test signal and the key signal.

[0057] Step S302: When the key signal matches successfully, convert the test signal into a test instruction.

[0058] Specifically, after acquiring the key signal, a key signal match is first performed. If the key signal match is successful, the test signal is converted into a test instruction. If the key signal match is unsuccessful and the test signal is not converted, the storage module cannot be operated. This allows designers to set the key signal themselves, making it impossible for outsiders to obtain the key signal and tamper with the contents of the storage module in the chip, thereby improving chip security.

[0059] Step S303: Control the target memory module to perform a test according to the test instruction, and transmit the test result signal to the test pin of the chip.

[0060] Specifically, after receiving a test instruction, the test module controls the target storage module to perform corresponding read and write operations based on the test instruction. After completing the corresponding read and write operations, the target storage module returns a test result signal. The test module obtains this test result signal and transmits it to the conversion module. The conversion module converts the test result signal and transmits the converted test result signal to the chip's test pin. The test equipment obtains the test result signal through the chip's test pin and then compares the test signal output by the chip's test pin with the expected signal. Based on the comparison result, it determines whether the target storage module is normal, thereby completing the test of the target storage module within the chip.

[0061] Because the conversion module requires a key signal match before converting the signal, if the key signal matches, the conversion module converts the test signal into the corresponding instruction, allowing subsequent read and write operations to the storage module. If the key signal matches, the conversion module does not convert the test signal, and subsequent read and write operations to the storage module are impossible. Therefore, designers can set the key signal themselves, and outsiders cannot know the key signal and tamper with the contents of the chip's storage module, thereby improving chip security.

[0062] In some embodiments, the test signal includes a test operation signal and a selection signal, the test instruction includes a test operation instruction and a selection instruction, the test signal includes multiple test operation signals, and the selection signal includes a timing signal. The test module includes a selection unit and multiple test units, the selection unit is respectively connected to the conversion module and all the test units, and the multiple test units are connected to the multiple storage modules in a one-to-one correspondence.

[0063] When the key signal matches successfully, each test operation signal is converted into a test operation instruction, the timing signal is converted into a timing instruction, and a plurality of target storage modules are determined from the plurality of storage modules according to the timing instructions.

[0064] Specifically, when testing a memory module in a chip, a test device is connected to the chip's test pins. The test device transmits a test signal, a selection signal, and a key signal. After receiving the test signal, selection signal, and key signal via the chip's test pins, a conversion module first matches the key signal. Upon a successful key signal match, each test operation signal is converted into a test operation instruction and the timing signal is converted into a timing instruction. A selection unit identifies multiple target memory modules from the multiple memory modules based on the timing instructions and sequentially transmits the multiple test operation instructions to the multiple test units corresponding to the multiple target memory modules in accordance with the timing of the timing instructions.

[0065] The test unit controls the corresponding target memory module to perform tests according to the test operation instructions and transmits the test result signal to the selection unit. The selection unit sequentially transmits the multiple test result signals to the conversion module. The conversion module sequentially converts the multiple test result signals and transmits the converted test result signals to the chip's test pins. This allows multiple memory modules to be tested simultaneously, helping to improve chip testing efficiency.

[0066] In some embodiments, when converting the timing signal, the conversion module will change the timing of the timing signal according to the preset requirements, that is, the timing of the timing instruction generated by the conversion module is different from the timing of the timing signal. Exemplarily, the timing of the timing signal is 1-2-3-4, that is, the first storage module, the second storage module, the third storage module and the fourth storage module are tested in sequence. After the conversion module converts the timing signal into a timing instruction, the timing of the timing instruction is 2-4-1-3, that is, the second storage module, the fourth storage module, the first storage module and the third storage module are tested in sequence. Thus, when testing multiple storage modules, the conversion module can change the timing of the test signal. Even if an outsider knows the preset secret key signal, the outsider cannot correctly operate the storage module in the chip if he does not know the conversion rules of the conversion module, which further improves the security of the chip.

[0067] The present application also provides a chip including the aforementioned storage test circuit. When testing a storage module in the chip, a test device is connected to a test pin of the chip. The test device transmits a test signal and a key signal. After receiving the test signal and key signal via the chip's test pin, a conversion module first matches the key signal. If the key signal match fails, the conversion module does not convert the test signal, and subsequent testing of the storage module cannot proceed. If the key signal match succeeds, the conversion module converts the test signal into a test instruction. The test module is configured to test a target storage module among multiple storage modules according to the test instruction. Because the conversion module requires a key signal match before converting the signal, if the key signal match succeeds, the conversion module converts the test signal into a corresponding instruction, allowing subsequent testing of the storage module. If the key signal match fails, the conversion module does not convert the test signal, and subsequent testing of the storage module cannot proceed. Therefore, designers can set the key signal themselves, and outsiders cannot access the key signal and tamper with the contents of the storage module in the chip, thereby improving the security of the chip.

[0068] The present application also provides a vehicle including the aforementioned chip. When testing a storage module in the chip, a test device is connected to the chip's test pins. The test device transmits a test signal and a key signal. After receiving the test signal and key signal via the chip's test pins, a conversion module first matches the key signal. If the key signal match fails, the conversion module does not convert the test signal, and subsequent testing of the storage module cannot proceed. If the key signal match succeeds, the conversion module converts the test signal into a test instruction. The test module is configured to test a target storage module among multiple storage modules according to the test instruction. Because the conversion module requires a key signal match before converting the signal, if the key signal match succeeds, the conversion module converts the test signal into a corresponding instruction, allowing subsequent testing of the storage module. If the key signal match fails, the conversion module does not convert the test signal, and subsequent testing of the storage module cannot proceed. Therefore, designers can set the key signal themselves, and outsiders cannot access the key signal or tamper with the contents of the storage module in the chip, thereby improving the security of the chip.

[0069] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A storage test circuit, characterized in that: The chip comprises a conversion module and a test module, wherein the conversion module and the test module are both arranged in the chip, the conversion module is connected to the test module and the test pins of the chip respectively, and the test module is connected to the plurality of storage modules in the chip respectively; The conversion module is used to receive a test signal and a key signal through the test pin, and convert the test signal into a test instruction when the key signal matches successfully; the test module is used to test a target storage module among the multiple storage modules according to the test instruction.

2. The storage test circuit according to claim 1, wherein: The test module is further used to transmit the test result signal of the target storage module to the conversion module; the conversion module is further used to convert the test result signal and transmit the converted test result signal to the test pin of the chip.

3. The storage test circuit according to claim 1, wherein: The test signal includes a test operation signal and a selection signal, the test instruction includes a test operation instruction and a selection instruction, the test module includes a selection unit and a plurality of test units, the selection unit is connected to the conversion module and all the test units respectively, and the plurality of test units are connected to the plurality of storage modules in a one-to-one correspondence; The conversion module is also used to convert the test operation signal into a test operation instruction and convert the selection signal into a selection instruction when the key signal matches successfully; the selection unit is also used to transmit the test operation instruction to the target test unit corresponding to the target storage module according to the selection instruction, and the target test unit is used to test the target storage module according to the test operation instruction.

4. The storage test circuit according to claim 3, wherein: The test signal includes a plurality of test operation signals, and the selection signal includes a timing signal; The conversion module is also used to convert each of the test operation signals into a test operation instruction and convert the timing signal into a timing instruction when the key signal matches successfully; the selection unit is also used to transmit multiple test operation instructions in sequence to multiple target test units corresponding to multiple target storage modules according to the timing instructions; each target test unit is used to test the target storage module corresponding to it according to the received test operation instruction.

5. The storage test circuit according to claim 4, wherein: The conversion module is further configured to adjust the timing of the timing signal when the key signal matches successfully, and convert the adjusted timing signal to obtain the timing instruction.

6. The storage test circuit according to claim 5, characterized in that: The selection unit is used to obtain the test result signals output by multiple target test units in sequence according to the timing instructions, and transmit the multiple test result signals to the conversion module in sequence; the conversion module is also used to convert the multiple test result signals, and transmit the converted test result signals to the test pins of the chip in sequence.

7. The storage test circuit according to any one of claims 1 to 6, characterized in that: The storage test circuit further includes an interface module disposed in the chip, the interface module being connected to the conversion module and the test pin respectively; The interface module is used to receive the test signal and the key signal, and transmit the test signal and the key signal to the conversion module.

8. The storage test circuit according to claim 7, wherein: The interface module is a parallel interface, a serial interface or a custom communication interface.

9. A chip, characterized in that: The storage test circuit comprises the storage test circuit according to any one of claims 1 to 8.

10. A vehicle, characterized in that: Comprising the chip according to claim 9.

Images