FPGA-based BLDC motor speed calculation method

Abstract

The application discloses a BLDC motor rotating speed calculation method based on FPGA, and belongs to the field of motor control technology and FPGA digital system design, and comprises the following steps: collecting three-way Hall signals in a BLDC motor and pre-processing the three-way Hall signals to obtain pre-processed three-way Hall signals; judging whether the pre-processed three-way Hall signals have static faults and line sequence faults; judging the rotating state of the BLDC motor, including forward rotation, reverse rotation and stop; fusing the pre-processed three-way Hall signals to obtain one-way low-frequency signals; performing sliding frequency counting on high-frequency signals and low-frequency signals to obtain high-frequency accumulated values and low-frequency counting values respectively; wherein the high-frequency signals are system clock frequency signals; and calculating the rotating speed of the BLDC motor according to the high-frequency accumulated values and the low-frequency counting values. The application can simultaneously adapt to high-speed and low-speed use scenarios, can simultaneously control multiple motors to realize rotating speed calculation, and has strong real-time performance, high calculation precision and high reliability.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of motor control technology and FPGA digital system design, and particularly relates to a BLDC motor speed calculation method based on FPGA. BACKGROUND

[0002] BLDC motor is the abbreviation of brushless direct current motor. Due to its advantages of high efficiency, low noise and long service life, it is widely used in industrial automation, consumer electronics, electric vehicles and other fields. Its speed control is the core link to realize precise speed regulation, torque stability and energy efficiency optimization, and needs to maintain dynamic balance through real-time feedback adjustment of PWM duty cycle or optimization of commutation strategy. The common control method of BLDC motor is six-step commutation control, which realizes the process of controlling motor movement by switching the current in each phase of the motor.

[0003] In terms of control chips, four kinds of chips, namely single-chip microcomputer, special integrated chip, DSP and FPGA, are mainly used to realize the control core of the motor system. The main advantage of BLDC motor controller based on single-chip microcomputer in the market is low price, but the single-chip microcomputer runs slowly and is difficult to meet the system operation accuracy requirements. Although the special integrated chip has high integration degree, low price and strong anti-interference ability, the existing special integrated chip can only realize some relatively simple control algorithms and cannot meet the special requirements. The internal structure of DSP chip adopts Harvard structure, and its data processing speed and processing capacity are stronger than those of traditional single-chip microcomputer. In the field of high-speed acquisition and fast operation, it is an ideal motor controller, but the price of DSP is expensive, more peripheral components are required, and the system data need to be processed in time series, which reduces the response speed of the system. The internal resources of FPGA chip are rich, the interface design is flexible, and it can be programmed repeatedly. The control logic is realized in hardware, the data is processed in parallel, the system efficiency is improved, the implementation cost is reduced, the portability and reliability are high, therefore, using FPGA to realize motor control has obvious advantages.

[0004] The traditional BLDC motor speed calculation method mainly includes period method (T method) and frequency method (M method). The T method calculates the speed by measuring the number of clock pulses in a fixed period, which is suitable for low-speed (<10K RPM) scenarios, but the resolution is insufficient at high speed. The M method calculates the speed by counting the number of periods in a fixed time, which is suitable for high speed, but the error is significant at low speed. The T method has insufficient resolution at high speed due to the small number of pulses, and the M method has poor performance at low speed. The M / T hybrid method can be used to make up for it, but the algorithm complexity increases, the resource occupation is more, and the use cost is higher. SUMMARY

[0005] In view of the above problems in the prior art, the BLDC motor rotating speed calculation method based on FPGA provided by the application solves the problems of low applicability, slow response speed, high resource occupation, poor portability, poor modifiability, poor verifiability, and uncertain reliability in the prior art.

[0006] To achieve the above-mentioned application purposes, the application adopts the technical scheme of a BLDC motor rotating speed calculation method based on FPGA, comprising:

[0007] Collecting three-channel Hall signals in the BLDC motor and pre-processing the three-channel Hall signals to obtain pre-processed three-channel Hall signals;

[0008] Determining whether the pre-processed three-channel Hall signals have static faults and line sequence faults;

[0009] Determining the rotating state of the BLDC motor, including forward rotation, reverse rotation, and stop rotation;

[0010] Obtaining one low-frequency signal by fusing the pre-processed three-channel Hall signals;

[0011] Carrying out sliding frequency counting on the high-frequency signal and the low-frequency signal to obtain high-frequency cumulative values and low-frequency counting values, respectively; wherein the high-frequency signal is a system clock frequency signal;

[0012] Calculating the BLDC motor rotating speed according to the high-frequency cumulative values and the low-frequency counting values.

[0013] Further, the pre-processing comprises:

[0014] Beating twice on the collected three-channel Hall signals in the clock domain;

[0015] Carrying out shift filtering processing on the three-channel Hall signals after beating, and outputting filtered three-channel Hall signals and one Hall effective signal.

[0016] Further, the specific method for determining whether the pre-processed three-channel Hall signals have static faults and line sequence faults is:

[0017] Determining the state of the three-channel Hall signals at the rising edge of each Hall effective signal; wherein the three-channel Hall signals have 8 states, including 000, 001, 010, 011, 100, 101, 110, and 111, and 000 and 111 are invalid states;

[0018] When the number of continuous appearance of the invalid state of the three-channel Hall signals reaches a preset value, the Hall signal is determined as a static fault;

[0019] The phase conversion sequence of the filtered three Hall signals is obtained, and when the phase conversion sequence is inconsistent with the fixed phase conversion sequence of the BLDC motor, it is determined that it is a line sequence fault; when the determination results of the continuous preset number of times are all line sequence faults, it is determined that the Hall signal is a line sequence fault.

[0020] Further, the specific method for judging the rotation state of the BLDC motor is:

[0021] The state machine jump sequence number is set, wherein the jump sequence number in the forward rotation state is 001-011-010-110-100-101-001 in turn, and the jump sequence number in the reverse rotation state is 001-101-100-110-010-011-001 in turn.

[0022] The state machine jump sequence number is determined according to the signal value of the filtered three Hall signals within the determination stop time, and the rotation state of the BLDC motor is obtained according to the state machine jump sequence number; when the change of the three Hall signals is not detected within the determination stop time, it is determined that the motor is in a stopped state.

[0023] Further, the calculation expression of the determination stop time is:

[0024] =(rotational speed*clock frequency (Hz)) / (number of pole pairs*6)

[0025] wherein, is the determination stop time.

[0026] Further, the specific method for fusing the preprocessed three Hall signals to obtain a low-frequency signal is:

[0027] The preprocessed three Hall signals are combined into a three-bit register, and the signals in the three-bit register are tapped under the clock domain to obtain a group of register signals.

[0028] The register signals are compared with the preprocessed three Hall signals, and when any one of the preprocessed three Hall signals changes, the changed signal is flipped under the control of the clock through a flip-flop to generate a low-frequency signal.

[0029] Further, the specific method for performing sliding frequency counting on the high-frequency signal and the low-frequency signal to obtain high-frequency cumulative values and low-frequency count values is:

[0030] The rotation state of the BLDC motor is monitored; when the rotation state of the BLDC motor changes, a state change signal is generated; when the state change signal is valid, the conversion of high and low frequencies is stopped, and the high-frequency accumulated value and the low-frequency count value are emptied; the rising edge of a low-frequency signal is collected, and the high and low frequency conversion is started when the rising edge occurs; the sliding order is set to M; the low-frequency count value is initialized to 0, and when the low-frequency signal rising edge is valid, the low-frequency count value is sequentially increased from 0 to M, and when the low-frequency count value is M, the low-frequency count value is kept as M; the high-frequency accumulated value is initialized to 1, and when the low-frequency signal rising edge is valid, the high-frequency accumulated value is started to be counted, and one counting period is the frequency period of the low-frequency signal; the high-frequency count value of M counting periods is accumulated to obtain the high-frequency accumulated value.

[0031] Further, the specific method for calculating the BLDC motor speed according to the high-frequency accumulated value and the low-frequency count value is:

[0032] The low-frequency fixed-point number is obtained, and the calculation expression is: low-frequency fixed-point number = low-frequency count value * clock frequency (Hz) * 60s / 3;

[0033] The high-frequency fixed-point number is obtained, and the calculation expression is: high-frequency fixed-point number = high-frequency accumulated value * pole pair number;

[0034] The low-frequency fixed-point number and the high-frequency fixed-point number are converted into low-frequency floating-point number and high-frequency floating-point number through the fixed-point number to floating-point number IP core;

[0035] The ratio of the low-frequency floating-point number to the high-frequency floating-point number is calculated through the floating-point division IP core to obtain the BLDC motor speed, and the expression is: BLDC motor speed (turn / min) = low-frequency floating-point number / high-frequency floating-point number.

[0036] The beneficial effects of the present application are:

[0037] 1. The calculated motor speed of the present application depends on the generation period of the BLDC motor Hall signal, and the shorter the generation period of the Hall signal, the faster the speed calculation, so it can simultaneously compatible with high-speed and low-speed use scenarios. After the BLDC motor is stable, the FPGA can update the speed in real time, with a delay of less than 1us, and has strong real-time performance.

[0038] 2. The present application can output the speed result through one round of operation, compared with the M / T method, it does not need to be divided into high-speed algorithm and low-speed algorithm, and also does not need to operate three Hall signals respectively, saves resource occupation, and improves the calculation rate.

[0039] 3. The present application is completed using Verilog HDL. Verilog HDL is a hardware description language that can be recognized by various FPGA development tools, so the present application can be used, transplanted and copied in all FPGAs, and has strong portability. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 The following is a flow chart of a method for calculating the speed of a BLDC motor based on FPGA provided in an embodiment. DETAILED DESCRIPTION

[0041] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0042] like Figure 1 As shown, in one embodiment of the present invention, a method for calculating the speed of a BLDC motor based on FPGA includes the following steps:

[0043] S1. Collect the three Hall signals W, V, and U from the BLDC motor and preprocess them to obtain the preprocessed three Hall signals.

[0044] Preprocessing includes: using Verilog HDL, a hardware description language that can be recognized by all FPGA development tools, to double-beat the three collected Hall signals in the clock domain to achieve clock synchronization and metastability suppression;

[0045] The three Hall signals after beating are shifted and filtered. The number of shifts and the signal acquisition cycle can be configured according to specific needs. When the data collected in each cycle are consistent, the data collected for the last time is stored, and the three Hall signals after filtering and one Hall valid signal are output.

[0046] S2. Determine whether the three Hall signals after preprocessing have static faults and line sequence faults;

[0047] The specific method is:

[0048] The states of the three Hall signals are determined on the rising edge of each Hall valid signal; the three Hall signals have 8 states: 000, 001, 010, 011, 100, 101, 110, and 111, with 000 and 111 being invalid states.

[0049] When the three filtered Hall signals collected for 100 consecutive times are all in an invalid state, the Hall signal is judged to be a static fault. The number of judgments can be configured through parameters according to actual needs;

[0050] Obtaining the commutation sequence of the filtered three Hall signals, when the commutation sequence is inconsistent with the fixed commutation sequence of the BLDC motor, determining that it is a line sequence fault; when the determination result is line sequence fault for 100 times in succession, determining that the Hall signal is a line sequence fault, and the determination times can be configured by parameters according to actual needs.

[0051] Because the Hall signal may be unstable when the motor is just started, after power-on, a delay of 10 ms is added before determining the static fault or line sequence fault, wherein the delay time can be configured by parameters.

[0052] If the Hall signal fails, directly using these signals to calculate the motor speed may lead to incorrect results, and even may cause damage to the motor system, therefore, before calculating the speed, the Hall signal fault needs to be checked to find the signal anomaly in time and avoid using the incorrect signal to calculate the speed.

[0053] S3, judging the rotation state of the BLDC motor, including forward rotation, reverse rotation and stop rotation;

[0054] The specific method is:

[0055] Setting the state machine jump sequence number, wherein the jump sequence number in the forward rotation state is: 001-011-010-110-100-101-001, and the jump sequence number in the reverse rotation state is: 001-101-100-110-010-011-001;

[0056] According to the signal value of the filtered three Hall signals, the state machine jump sequence number is determined within the determination stop time, and the rotation state of the BLDC motor is obtained according to the state machine jump sequence number; when the change of the three Hall signals is not detected after the determination stop time, it is determined that the motor is in the stop state. The calculation expression of the determination stop time is:

[0057] = (speed * clock frequency (Hz)) / (pole pair number * 6).

[0058] S4, obtaining a low-frequency signal by fusing the preprocessed three Hall signals;

[0059] Specifically,

[0060] Combining the preprocessed three Hall signals into a three-bit register, and hitting the signal in the three-bit register once under the clock domain to obtain a group of register signals;

[0061] ​The register signal is compared with the preprocessed three-way Hall signal, when any one of the preprocessed three-way Hall signal changes, the changed signal is flipped under the control of the clock through a flip-flop, and a low frequency signal is generated.

[0062] S5, the high frequency signal and the low frequency signal are counted, and the high frequency cumulative value and the low frequency count value are obtained; wherein the high frequency signal is a system clock frequency signal, and the low frequency signal is a frequency signal generated according to the three-way Hall signal;

[0063] The specific method is:

[0064] The rotation state of the BLDC motor is monitored; when the rotation state of the BLDC motor changes, a state change signal is generated; when the state change signal is valid, the high-low frequency conversion is stopped, and the high frequency cumulative value and the low frequency count value are cleared; the rising edge of a low frequency signal is collected, and the high-low frequency conversion is started when the rising edge appears; the sliding order is set to M; the low frequency count value is initialized to 0, and when the rising edge of the low frequency signal is valid, the low frequency count value is increased from 0 to M in turn, and when the low frequency count value is M, the low frequency count value is kept as M; the high frequency cumulative value is initialized to 1, and when the rising edge of the low frequency signal is valid, the high frequency cumulative value is counted, and the counting period is the frequency period of the low frequency signal, that is, the number of system clocks in the low frequency period is counted as a high frequency count value; the high frequency count values of M counting periods are accumulated to obtain the high frequency cumulative value.

[0065] S6, the BLDC motor speed is calculated according to the high frequency cumulative value and the low frequency count value;

[0066] The specific method is:

[0067] The low frequency fixed point number is obtained and latched, and its calculation expression is: low frequency fixed point number = low frequency count value * clock frequency (Hz) * 60s / 3;

[0068] The high frequency fixed point number is obtained and latched, and its calculation expression is: high frequency fixed point number = high frequency cumulative value * pole pair number;

[0069] The low frequency fixed point number and the high frequency fixed point number are converted into low frequency floating point number and high frequency floating point number through the fixed point number to floating point number IP core;

[0070] The ratio of the low frequency floating point number to the high frequency floating point number is calculated through the floating point division IP core to obtain the BLDC motor speed, and its expression is: BLDC motor speed (r / min) = low frequency floating point number / high frequency floating point number.

[0071] All the above steps are completed using Verilog HDL. Verilog HDL is a hardware description language that can be recognized by various FPGA development tools, so the application can be used, transplanted and copied in all FPGAs, embodying the portability and applicability of the application.

[0072] In conclusion, the application can simultaneously compatible with high-speed and low-speed use scenarios, has strong real-time speed, high calculation precision and high reliability, and solves the problems of the traditional BLDC motor speed calculation method, such as the inability to simultaneously compatible with high-speed and low-speed use scenarios, slow response speed, high resource occupation, poor portability, poor modifiability, poor verifiability, uncertain reliability, etc.

Claims

1. A BLDC motor speed calculation method based on FPGA, characterized in that: include: Collecting three-way Hall signals from the BLDC motor and preprocessing them to obtain preprocessed three-way Hall signals; Determine whether the three Hall signals after preprocessing have static faults and line sequence faults; Determine the rotation state of the BLDC motor, including forward, reverse and stop; The three pre-processed Hall signals are integrated to obtain a low-frequency signal. Perform sliding frequency counting on the high-frequency signal and the low-frequency signal to obtain a high-frequency accumulated value and a low-frequency count value respectively; wherein the high-frequency signal is a system clock frequency signal; The BLDC motor speed is calculated based on the high-frequency accumulated value and the low-frequency count value; The specific method of performing sliding frequency counting on high-frequency signals and low-frequency signals to obtain high-frequency accumulated values ​​and low-frequency count values ​​respectively is as follows: Monitor the rotation state of the BLDC motor; when the rotation state of the BLDC motor changes, generate a state change signal; when the state change signal is valid, stop the high-low frequency conversion, clear the high-frequency accumulated value and the low-frequency count value; collect the rising edge of a low-frequency signal, and start the high-low frequency conversion when the rising edge appears; set the sliding order to M; initialize the low-frequency count value to 0, when the rising edge of the low-frequency signal is valid, the low-frequency count value increases from 0 to M in sequence, and when the low-frequency count value is M, keep the low-frequency count value at M; initialize the high-frequency accumulated value to 1, when the rising edge of the low-frequency signal is valid, start counting the high-frequency accumulated value, and one counting cycle is the frequency cycle of the low-frequency signal; accumulate the high-frequency count values ​​of M counting cycles to obtain the high-frequency accumulated value; The specific method for calculating the BLDC motor speed based on the high-frequency accumulated value and the low-frequency count value is: Get the low-frequency fixed-point number. The calculation expression is: low-frequency fixed-point number = low-frequency count value * clock frequency (Hz) * 60s / 3; Get the high-frequency fixed-point number, the calculation expression is: high-frequency fixed-point number = high-frequency accumulated value * pole pair number; Convert low-frequency fixed-point numbers and high-frequency fixed-point numbers to low-frequency floating-point numbers and high-frequency floating-point numbers through the fixed-point to floating-point IP core; The floating-point division IP core calculates the ratio of the low-frequency floating-point number to the high-frequency floating-point number to obtain the BLDC motor speed. The expression is: BLDC motor speed (rpm) = low-frequency floating-point number / high-frequency floating-point number.

2. The BLDC motor speed calculation method based on FPGA according to claim 1, characterized in that: The pretreatment includes: The three collected Hall signals are clocked twice in the clock domain; The three Hall signals after tapping are shifted and filtered, and the three filtered Hall signals and one Hall valid signal are output.

3. The BLDC motor speed calculation method based on FPGA according to claim 2, characterized in that: The specific method for judging whether the three Hall signals after preprocessing have static faults and line sequence faults is as follows: The states of the three Hall signals are determined on the rising edge of each Hall valid signal; the three Hall signals have 8 states: 000, 001, 010, 011, 100, 101, 110, and 111, with 000 and 111 being invalid states. When the invalid state of the three Hall signals appears continuously for a number of times reaching a preset value, the Hall signals are judged to be static faults; The commutation sequence of the three filtered Hall signals is obtained. When the commutation sequence is inconsistent with the fixed commutation sequence of the BLDC motor, it is determined to be a line sequence fault. When the result of the determination is a line sequence fault for a preset number of consecutive times, the Hall signal is determined to be a line sequence fault.

4. The BLDC motor speed calculation method based on FPGA according to claim 1, characterized in that: The specific method for judging the rotation state of the BLDC motor is: Set the state machine jump sequence number. The jump sequence numbers in the forward state are: 001-011-010-110-100-101-001; the jump sequence numbers in the reverse state are: 001-101-100-110-010-011-001; During the stop time, the state machine jump sequence number is determined based on the signal values ​​of the three filtered Hall signals, and the rotation state of the BLDC motor is obtained based on the state machine jump sequence number. When no change is detected in the three Hall signals within the stop judgment time, it is determined that the motor is in a stopped state.

5. The BLDC motor speed calculation method based on FPGA according to claim 4, characterized in that: The calculation expression of the stop time is: =(rotational speed*clock frequency (Hz)) / (number of pole pairs*6) in, For the judgment stop time.

6. The BLDC motor speed calculation method based on FPGA according to claim 1, characterized in that: The specific method of fusing the three pre-processed Hall signals to obtain a low-frequency signal is as follows: The three pre-processed Hall signals are merged into a three-bit register, and the signals in the three-bit register are clocked to obtain a set of register signals. The register signal is compared with the three pre-processed Hall signals. When any one of the three pre-processed Hall signals changes, a trigger is used to flip the changed signal under the control of the clock to generate a low-frequency signal.

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