Time-interleaved adc sampling method and system

Abstract

The application provides a time-interleaved ADC sampling method and system. The method is applied to a time-interleaved ADC sampling system. The system comprises a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer and a plurality of analog-to-digital converter sub-ADCs. The pseudo-random sequence generator is connected with the analog multiplexer and also connected with the digital multiplexer through the decoder. The analog multiplexer is connected with the digital multiplexer through the plurality of sub-ADCs. The number of channels of the digital multiplexer is M, and the number of channels of the analog multiplexer and the number of sub-ADCs are both M+1. When sampling a signal in each cycle, the pseudo-random sequence generator, the analog multiplexer, the plurality of sub-ADCs, the decoder and the digital multiplexer are used to realize multi-channel random interleaved output. The application realizes random sampling through the plurality of sub-ADCs, disrupts the spur period, changes the spur into noise floor and disperses in the entire Nyquist band, so as to correct the residual spur.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a time-interleaved ADC sampling method and system. Background Technology

[0002] The main function of a time-interleaved ADC (analog-to-digital converter) is to increase the overall sampling rate (Fs) of the ADC by using multiple sub-ADCs to sample in parallel. However, this process introduces interleaving spurious signals, which are mainly caused by three types of simulation imperfections: 1) offset, 2) gain, and 3) timing skew. For multi-interleaved ADCs, although existing technologies have corrected for these spurious signals, residual interleaving spurious signals still exist. This is because the limitations of correction accuracy prevent perfect calibration of mismatches in the analog domain. Furthermore, interleaving spurs are highly sensitive to mismatches, so even after correction, residual spurious signals still remain. Summary of the Invention

[0003] The purpose of this application is to provide a time-interleaved ADC sampling method and system. By randomizing the sampling process, the sub-ADC samples randomly instead of sequentially, which can disrupt the spurious period and transform the spurious into a noise floor, dispersing it throughout the Nyquist band, thereby correcting residual spurious. Furthermore, it can also achieve timing skew correction at specific input frequencies.

[0004] In a first aspect, this application provides a time-interleaved ADC sampling method, which is applied to a time-interleaved ADC sampling system. The system includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter (ADC) sub-ADCs. The pseudo-random sequence generator is connected to the analog multiplexer and also connected to the digital multiplexer through the decoder. The analog multiplexer is connected to the digital multiplexer through multiple ADC sub-ADCs. The digital multiplexer has M channels, and the analog multiplexer and the number of ADC sub-ADCs are both M+1. During each signal sampling, the following steps are performed: the pseudo-random sequence generator outputs a first pseudo-random signal to the analog multiplexer; the analog multiplexer selects the corresponding target ADC to output the currently accessed analog signal based on the first pseudo-random signal; the target ADC converts the analog signal into a digital signal and sends it to the digital multiplexer; the decoder decodes the first pseudo-random signal to obtain a second pseudo-random signal and sends it to the digital multiplexer; the digital multiplexer selects the corresponding output channel based on the second pseudo-random signal and outputs the digital signal of the target ADC.

[0005] Furthermore, the aforementioned pseudo-random sequence generator includes: a pseudo-random binary sequence module, a RAM memory, and a FIFO queue; the FIFO queue pre-stores sub-ADC identifiers corresponding to M sub-ADCs; the addresses in the RAM memory correspond to binary sequences, and each address stores a preset sub-ADC identifier; the preset sub-ADC identifier is the sub-ADC identifier corresponding to the (M+1)th sub-ADC; the step of the pseudo-random sequence generator outputting the first pseudo-random signal to the analog multiplexer includes: if the current number of beats is less than or equal to M, determining the sub-ADC identifier at the front of the current array as the first pseudo-random signal to be output to the analog multiplexer according to the order of the sub-ADC identifiers in the FIFO queue; if the current number of beats is greater than M, the pseudo-random binary sequence module inputs a random binary number to the RAM memory; the RAM memory selects the sub-ADC identifier in the corresponding target address according to the random binary number and adds it to the FIFO queue, and outputs the sub-ADC identifier in the target address as the first pseudo-random signal to the analog multiplexer, and stores the first sub-ADC identifier in the FIFO queue in the target address of the RAM memory.

[0006] Furthermore, in the above M+1 sub-ADCs, M is the number of regular sub-ADCs, or M+1 is the number of regular sub-ADCs; the number of regular sub-ADCs includes: 2, 4, 8 or 16.

[0007] Furthermore, the determination of M in the number of sub-ADCs is as follows: obtain the total ADC sampling rate and the highest sampling rate that the current sub-ADC can achieve; divide the total ADC sampling rate by the highest sampling rate of the current sub-ADC, and the quotient is M.

[0008] Furthermore, the decoder described above is used to decode a sequence of 1 to M+1 into a sequence of 1 to M.

[0009] Furthermore, the above method also includes: aligning the timing deviation of the third designated sub-ADC with reference to the sampling signals of the first and second designated sub-ADCs; for the case of M+1=4, the timing deviation alignment is performed three times according to the above steps: First, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the (k+1)-th sampling signal of the first sub-ADC; the third designated sub-ADC is the third sub-ADC; Second, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the k-th sampling signal of the third sub-ADC; the third designated sub-ADC is the second sub-ADC; Third, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the third sub-ADC; the sampling signal of the second designated sub-ADC is the (k+1)-th sampling signal of the first sub-ADC; the third designated sub-ADC is the fourth sub-ADC.

[0010] Furthermore, the step of aligning the timing deviation of the third designated sub-ADC with reference to the sampling signals of the first and second designated sub-ADCs includes: finding, from the random interleaved sampling spectrum, all first sampling cases immediately following the third designated sub-ADC; and all third designated sub-ADCs immediately following the first designated sub-ADCs; calculating a first correlation value based on the sampling signals of the first and third designated sub-ADCs in the first sampling case; calculating a second correlation value based on the sampling signals of the third and first designated sub-ADCs in the second sampling case; and aligning the timing deviation of the third designated sub-ADC based on the first and second correlation values.

[0011] Furthermore, the step of calculating the first correlation value based on the sampled signals of the first designated sub-ADC and the third designated sub-ADC in the first sampling case includes: performing a multiplication-accumulation operation using the following formula to obtain the first correlation value vxcorr1:

[0012]

[0013] Where y1(k) represents the sampling signal of the first specified sub-ADC; y3(k) represents the k-th sampling signal of the third specified sub-ADC; N represents the preset accumulation length;

[0014] The step of calculating the second correlation value based on the sampled signals of the third and first specified sub-ADCs in the second sampling case includes: performing a multiplication and accumulation operation using the following formula to obtain the second correlation value vxcorr2:

[0015]

[0016] Furthermore, the above-mentioned step of aligning the timing deviation of the third designated sub-ADC based on the first correlation value and the second correlation value includes: if the first correlation value is greater than the second correlation value, adjusting the delay of the third designated sub-ADC by increasing one step; if the first correlation value is less than the second correlation value, adjusting the delay of the third designated sub-ADC by decreasing one step; if the first correlation value is equal to the second correlation value, keeping the delay of the third designated sub-ADC unchanged.

[0017] Secondly, this application also provides a time-interleaved ADC sampling system, the system comprising: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter (ADC) sub-ADCs; the pseudo-random sequence generator is connected to the analog multiplexer and also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through multiple ADC sub-ADCs; the number of channels in the digital multiplexer is M, the number of channels in the analog multiplexer and the number of ADC sub-ADCs are both M+1; the time-interleaved ADC sampling system is used to perform the method described in any one of claims 1-9.

[0018] The time-interleaved ADC sampling method and system provided in this application are applied to a time-interleaved ADC sampling system. The system includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter (ADC) sub-ADCs. The pseudo-random sequence generator is connected to the analog multiplexer and also connected to the digital multiplexer through the decoder. The analog multiplexer is connected to the digital multiplexer through multiple ADC sub-ADCs. The digital multiplexer has M channels, and the number of channels in the analog multiplexer and the number of ADC sub-ADCs are both M+1. During each signal sampling, the following steps are performed: the pseudo-random sequence generator outputs a first pseudo-random signal to the analog multiplexer; the analog multiplexer selects the corresponding target ADC to output the currently accessed analog signal based on the first pseudo-random signal; the target ADC converts the analog signal into a digital signal and sends it to the digital multiplexer; the decoder decodes the first pseudo-random signal to obtain a second pseudo-random signal and sends it to the digital multiplexer; the digital multiplexer selects the corresponding output channel based on the second pseudo-random signal and outputs the digital signal of the target ADC. This application uses a randomization method to make the sub-ADC sample randomly instead of sequentially. This can disrupt the spurious period, turning the spurious into a noise floor and dispersing it throughout the Nyquist band, thereby correcting residual spurious. On this basis, timing skew correction can also be achieved for input at specific frequency points. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 A flowchart of a time-interleaved ADC sampling method provided in this application embodiment;

[0021] Figure 2A schematic diagram of a time-interleaved ADC sampling system provided in an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the structure of a pseudo-random sequence generator provided in an embodiment of this application;

[0023] Figure 4 This application provides a schematic diagram of a single-sided spectrum with and without random interleaving, as shown in the embodiments of this application.

[0024] Figure 5 This is a schematic diagram of the total ADC output and the output waveforms of the four sub-ADCs when the analog input is a special single-tone point (Fs / 4) and the sub-ADCs have timing skew, provided as an embodiment of this application.

[0025] Figure 6 This is a schematic diagram of a random interleaved sampling pattern provided in an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of the total ADC output and the waveforms of the four sub-ADCs when the analog input is a special single-tone point (Fs / 4) and the sub-ADCs have timing skew, provided as an embodiment of this application.

[0027] Figure 8 A schematic diagram of another time-interleaved ADC sampling system provided in this application embodiment;

[0028] Figure 9 This is a schematic diagram of another pseudo-random sequence generator provided in an embodiment of this application. Detailed Implementation

[0029] The technical solutions of this application will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] To address the issue of residual interleaved spurious signals in existing multi-interleaved ADCs despite correction, this application provides a time-interleaved ADC sampling method and system. By randomizing the sampling process, the sub-ADCs sample randomly instead of sequentially, thus disrupting the spurious signal period and converting the spurious signals into noise floor, dispersing them throughout the Nyquist band, thereby correcting the residual spurious signals.

[0031] To facilitate understanding of this embodiment, a time-interleaved ADC sampling method disclosed in this application embodiment will first be described in detail.

[0032] Figure 1 A flowchart of a time-interleaved ADC sampling method provided in this application embodiment is shown. This method is applied to a time-interleaved ADC sampling system; see also Figure 2 As shown, the system includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter (ADC) sub-modules; the pseudo-random sequence generator is connected to the analog multiplexer and also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through multiple ADC sub-modules; the digital multiplexer has M channels, and the analog multiplexer and the number of ADC sub-modules are both M+1; the following steps are performed during each signal sampling:

[0033] Step S102: The pseudo-random sequence generator outputs the first pseudo-random signal to the analog multiplexer;

[0034] See Figure 3 As shown, the pseudo-random sequence generator includes: a pseudo-random binary sequence module (as shown in prbs in the figure), a RAM memory (as shown in ram in the figure), and a FIFO queue (as shown in fifo in the figure); the FIFO queue pre-stores the sub-ADC identifiers corresponding to M sub-ADCs (identifiers 1, 2...M shown in the figure); the addresses in the RAM memory correspond to binary sequences (0, 1 shown in the figure, and in some other embodiments, they can also be 00, 01, 10, 11 to further improve randomness), and each address stores a preset sub-ADC identifier; the preset sub-ADC identifier is the sub-ADC identifier corresponding to the (M+1)th sub-ADC (identifier M+1 shown in the figure);

[0035] Based on the specific structure of the pseudo-random sequence generator described above, the step of the pseudo-random sequence generator outputting a first pseudo-random signal to the analog multiplexer includes:

[0036] (1) If the current number of beats is less than or equal to M, determine the first pseudo-random signal of the sub-ADC at the front of the current array as the first sub-ADC identifier according to the sub-ADC identifier order in the FIFO queue and output it to the analog multiplexer.

[0037] For example, the sub-ADC identifiers in the FIFO queue are numbered 1, 2, 3...M. When the current time step is 1, the first pseudo-random signal output to the analog multiplexer is 1; when the current time step is 2, the first pseudo-random signal output to the analog multiplexer is 2; when the current time step is 3, the first pseudo-random signal output to the analog multiplexer is 3... and when the current time step is M, the first pseudo-random signal output to the analog multiplexer is M.

[0038] (2) If the current number of beats is greater than M, the pseudo-random binary sequence module inputs a random binary number into the RAM memory; the RAM memory selects the sub-ADC identifier in the corresponding target address according to the random binary number and adds it to the FIFO queue, and outputs the sub-ADC identifier in the target address as the first pseudo-random signal to the analog multiplexer, and stores the first sub-ADC identifier in the FIFO queue in the target address of the RAM memory.

[0039] Taking the binary sequence corresponding to the address in the RAM memory as 0 and 1 as an example, when the current clock cycle is M+1, the sub-ADC identifiers corresponding to the binary sequences 0 and 1 are M+1 and 1, respectively. When the pseudo-random binary sequence module inputs a random binary number 0 into the RAM memory, it outputs the sub-ADC identifier M+1 corresponding to 0 as the first pseudo-random signal to the analog multiplexer, and stores the first sub-ADC identifier 2 in the FIFO queue in the target address 0 of the RAM memory. If the pseudo-random binary sequence module inputs a random binary number 1 into the RAM memory, it outputs the sub-ADC identifier 1 corresponding to 1 as the first pseudo-random signal to the analog multiplexer, and stores the first sub-ADC identifier 2 in the FIFO queue in the target address 1 of the RAM memory.

[0040] In this embodiment, the aforementioned prbs module generates a pseudo-random sequence of 0 / 1. This sequence selects a RAM address, and the sub-ADC number within that address is the sub-ADC to be activated in the current cycle. After activation, the sub-ADC number enters the FIFO queue, and simultaneously, the FIFO queue outputs a sub-ADC number, which enters the RAM (Random Access Memory). This process is repeated to generate a pseudo-random sequence between 1 and M+1.

[0041] Step S104: The analog multiplexer selects the corresponding target sub-ADC to output the currently connected analog signal according to the first pseudo-random signal;

[0042] For example, if the pseudo-random sequence generator outputs a first pseudo-random signal of 1 to the analog multiplexer, the analog multiplexer will select the sub-ADC1 corresponding to identifier 1 to output the currently accessed analog signal.

[0043] Step S106: The target sub-ADC converts the analog signal into a digital signal and sends it to the digital multiplexer;

[0044] Taking the above example again, sub-ADC1 converts the analog signal into a digital signal and sends it to the digital multiplexer.

[0045] In step S108, the decoder performs decoding processing on the first pseudo-random signal to obtain a second pseudo-random signal, which is then sent to the digital multiplexer.

[0046] The decoder described above is used to decode the sequence from 1 to M+1 into a sequence from 1 to M. By decoding the first pseudo-random signal, the identifier 1 of the first pseudo-random signal is transformed into a value in the sequence from 1 to M in chronological order. For example, if it is still 1, then the identifier 1 is sent to the digital multiplexer.

[0047] In step S110, the digital multiplexer selects the corresponding number of output channels according to the second pseudo-random signal and outputs the digital signal of the target sub-ADC.

[0048] The digital multiplexer outputs the digital signal converted by sub-ADC1 by the number of output channels corresponding to identifier 1.

[0049] For example, in 4-way interleaving, there are 4 sub-ADCs, but the digital multiplexer can only output 3 digital signals. The decoder's function is to map the randomized outputs of the 4 sub-ADCs onto the 3 outputs of the digital multiplexer in time sequence.

[0050] 1) During the Kth beat, the digital decoder connects the output of sub-ADC4 to the first output of the digital multiplexer so that the digital signal of sub-ADC4 can be output through the first output pin;

[0051] 2) At the K+1th beat, the analog side selects sub-ADC1 between sub-ADC1 and sub-ADC2; on the digital side, the output of sub-ADC1 is connected to the second output of the digital multiplexer.

[0052] 3) At the K+2th beat, the analog side selects the sub-ADCx, and the digital side will connect the output of the selected sub-ADCx to the third output of the digital multiplexer.

[0053] The above steps describe the output process of a single-shot sampling signal. After multiple-shot signal outputs, a randomly interleaved sampling signal, i.e., a digital signal, can be obtained.

[0054] In this embodiment, there are two operating methods:

[0055] In the first case, among the above M+1 sub-ADCs, M is the regular number of sub-ADCs, i.e., M = 2, 4, 8 or 16; which is equivalent to M+1 = 3, 5, 9 or 17.

[0056] The second type is where M+1 is the number of sub-ADCs; that is, M+1 = 2, 4, 8 or 16.

[0057] In practical applications, the specific number of sub-ADCs to use can be determined by calculating the value of M in the number of sub-ADCs using the following method:

[0058] Obtain the total ADC sampling rate and the highest sampling rate achievable by the current sub-ADC; divide the total ADC sampling rate by the highest sampling rate of the current sub-ADC to obtain the quotient M.

[0059] For example, obtain the total ADC sampling rate Fs, and based on the current sub-ADC design scheme and chip process level, give the highest achievable sampling rate Fs_sub of the sub-ADC; use Fs / Fs_sub to obtain the number of sub-ADCs for traditional time-interleaved sampling, and add 1 sub-ADC for random interleaving;

[0060] For example: Fs = 1000MHz,

[0061] 1) If the highest sampling rate Fs_sub achieved by the sub-ADC is 250MHz, then 4+1=5 sub-ADCs are needed to achieve random interleaving;

[0062] 2) If the highest sampling rate achieved by the sub-ADC is Fs_sub = 333.33MHz, then 3+1=4 sub-ADCs are needed to achieve random interleaving.

[0063] The time-interleaved ADC sampling method provided in this application changes the sampling order of the time-interleaved ADC, realizing pseudo-random selection and sampling of each sub-ADC, such as... Figure 2 As shown. Compared to the traditional time-interleaved ADC scheme, this scheme adds an extra sub-ADC to enable random interleaving of multiple sub-ADCs. For each fs clock cycle, a pseudo-random sequence between 1 and M+1 is generated by a pseudo-random sequence generator for multi-channel interleaving on the analog side and multi-channel deinterleaving on the digital side.

[0064] The above Figure 2 and Figure 3 The first implementation structure is shown; Figure 8 and Figure 9 The second implementation structure is shown. For the case of random interleaving of 4 sub-ADCs, the first implementation structure has 3 digital channels with a clock speed of fs / 3. The second implementation structure has 4 digital channels with a clock speed of fs / 4. From a circuit design perspective, the second structure is easier to implement. In practical applications, the first implementation structure can be used when using 4+1 sub-ADCs for random interleaving; the second implementation structure can be used when using 4 sub-ADCs for random interleaving.

[0065] The following examples, using an 8-channel ADC with time interleaving as an example, provide two application scenarios. For instance, if the ADC module sampling rate is 10GHz, there are two implementation methods:

[0066] Method 1 uses 8+1 sub-ADCs, each with a sampling rate of 10GHz / 8 = 1.25GHz. The preset interleaving sequence for the sub-ADCs is: 1-2-3-4-5-6-7-8. Therefore:

[0067] On the 9th beat, the sub-ADC will randomly choose between 1 and 9, determined by the prbs output on the 9th beat. Let's assume it chooses 1.

[0068] At the 10th beat, the sub-ADC will randomly select between 2 and 9, determined by the prbs output at the 10th beat. Let's assume it's selected as 9.

[0069] On the 11th beat, the sub-ADC will randomly select between 2 and 3, determined by the prbs output on the 11th beat.

[0070] The 12th beat, and so on.

[0071] Method two uses 7+1 sub-ADCs, with each sub-ADC having a sampling rate of 10GHz / 7 ≈ 1.43GHz. Compared to method one, this saves one sub-ADC; however, the sampling rate of each ADC increases from 1.25GHz to 1.43GHz. A trade-off can be struck in practice.

[0072] The default interleaving sequence for the sub-ADC initialization is: 1-2-3-4-5-6-7, then:

[0073] On the 8th beat, the sub-ADC will randomly select between 1 and 8, determined by the prbs output on the 8th beat. Let's assume it's selected as 8.

[0074] On the 9th beat, the sub-ADC will randomly select between 1 and 9, determined by the prbs output on the 9th beat. Let's assume the selected value is 1.

[0075] On the 10th beat, the sub-ADC will randomly select between 2 and 9, determined by the prbs output on the 10th beat. Let's assume it's selected as 9.

[0076] The 11th beat, and so on.

[0077] Without interleaving, the sampling points of the 8 sub-ADCs are fixed in timing, resulting in a fixed timing deviation between each sub-ADC and the others. With randomization, the timing deviation of each sub-ADC varies randomly, thus randomizing the spurious signals introduced by the timing deviations, effectively converting them into noise floor. Enabling random interleaving disperses residual interleaving spurious signals into the noise floor, providing a slight increase in noise floor and resolving the issue of correcting residual spur signals.

[0078] In addition, based on the digital signals sampled during the multi-shot signal sampling, a single-sided spectrum image is plotted; the horizontal axis of the single-sided spectrum image is frequency, and the vertical axis is normalized digital power; then, the spurious-free dynamic range (SFDR) can be determined based on the single-sided spectrum image.

[0079] Compared with the prior art, the multi-interleaving sampling method provided in this application can solve the residual interleaving spurious after multi-interleaving mismatch correction and improve SFDR. Figure 4 The left figure shows the SFDR after interleaving mismatch correction for the 8-channel sub-ADC, with an SFDR of -71.5 dBFs; Figure 4 The right figure shows the SFDR after enabling random interleaving in the 8-channel sub-ADC, which improves the SFDR to -85.9 dBFs.

[0080] Furthermore, existing timing skew correction methods cannot correct single-tone inputs at specific frequencies, such as... Figure 5 The diagram shows the total output waveform of the ADC and the output waveforms of the four sub-ADCs without random interleaving. Since the output waveforms of the four sub-ADCs are essentially straight lines, it is impossible to obtain correlation values ​​or perform timing deviation correction. In this embodiment, based on the aforementioned random interleaving method, the problem of being unable to correct timing skew at input frequencies with specific frequencies can be solved.

[0081] The above methods also include:

[0082] The timing deviation of the third designated sub-ADC is aligned with the sampling signals of the first and second designated sub-ADCs.

[0083] For the case where M+1=4, perform three timing offset alignments following the steps described above:

[0084] In the first instance, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the (k+1)-th sampling signal of the first sub-ADC; and the sampling signal of the third designated sub-ADC is the third sub-ADC.

[0085] The second time, the sampling signal of the first sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second sub-ADC is the k-th sampling signal of the third sub-ADC; the third sub-ADC is the second sub-ADC;

[0086] The third time, the sampling signal of the first sub-ADC is the k-th sampling signal of the third sub-ADC; the sampling signal of the second sub-ADC is the (k+1)-th sampling signal of the first sub-ADC; and the sampling signal of the third sub-ADC is the fourth sub-ADC.

[0087] Taking 4-way random interleaving as an example:

[0088] Step 1: Using sub-ADC1(k) and sub-ADC1(k+1) as references, align the timing skew of ADC3;

[0089] Step 2: Using sub-ADC1(k) and sub-ADC3(k) as references, align the timing skew of sub-ADC2;

[0090] Step 3: Using sub-ADC3(k) and sub-ADC1(k+1) as references, align the timing skew of sub-ADC4.

[0091] Furthermore, the step of aligning the timing deviation of the third designated sub-ADC with reference to the sampling signals of the first and second designated sub-ADCs includes:

[0092] (1) From the random interleaved sampling pattern, find the first sampling cases of all first designated sub-ADCs immediately followed by third designated sub-ADCs; and the second sampling cases of all third designated sub-ADCs immediately followed by first designated sub-ADCs; the 4-channel random interleaved sampling pattern is as follows: Figure 6 As shown.

[0093] (2) Calculate the first correlation value based on the sampled signals of the first designated sub-ADC and the third designated sub-ADC in the first sampling case; calculate the second correlation value based on the sampled signals of the third designated sub-ADC and the first designated sub-ADC in the second sampling case;

[0094] The steps for calculating the first correlation value based on the sampled signals of the first and third designated sub-ADCs in the first sampling case include: performing a multiplication-accumulation operation using the following formula to obtain the first correlation value vxcorr1:

[0095]

[0096] Where y1(k) represents the sampling signal of the first specified sub-ADC; y3(k) represents the k-th sampling signal of the third specified sub-ADC; N represents the preset accumulation length;

[0097] The step of calculating the second correlation value based on the sampled signals of the third and first specified sub-ADCs in the second sampling case includes: performing a multiplication and accumulation operation using the following formula to obtain the second correlation value vxcorr2:

[0098]

[0099] (3) Based on the first correlation value and the second correlation value, align the timing deviation of the third specified sub-ADC.

[0100] In practice, if the first correlation value is greater than the second correlation value, the delay of the third designated sub-ADC is adjusted by increasing the step size; if the first correlation value is less than the second correlation value, the delay of the third designated sub-ADC is adjusted by decreasing the step size; if the first correlation value is equal to the second correlation value, the delay of the third designated sub-ADC remains unchanged.

[0101] Taking the first step above as an example:

[0102] In the random interleaved spectrum, find the sampling status of all sub-ADC1 followed immediately by sub-ADC3, multiply the outputs of sub-ADC1 and sub-ADC3 at these two time points, and sum them for a fixed length N (this length is configurable), denoted as vxcorr1:

[0103]

[0104] Where y1 represents the output of sub-ADC1 and y3 represents the output of sub-ADC3.

[0105] In the random interleaved graph, find all points where sub-ADC3 is immediately followed by sub-ADC1, multiply the outputs of sub-ADC3 and sub-ADC1 at these two moments and sum them by the same length N, and denote it as vxcorr2; the calculation method of vxcorr2 is similar and will not be described here.

[0106] The calculation process for the second and third steps is similar. For example, when calculating the second step, in the random interleaved spectrum, find the sampling situation of sub-ADC1 immediately following sub-ADC2 and calculate vx1; find the sampling situation of sub-ADC2 immediately following sub-ADC3 and calculate vx2.

[0107] Figure 7 The diagram shows the total output waveform of the ADC and the output waveforms of the four sub-ADCs when there is a timing deviation. After adding random input at a special frequency point (such as FS / 4 = 250MHz), the random interleaving is constrained, the timing deviation value is adjusted, and the corresponding correlation value is calculated. The correlation value can reflect the timing deviation. The difference between vxcorr1 and vxcorr2 is calculated and compared with 0, which can be used as the calibration basis for the timing deviation.

[0108] In this embodiment, for single-tone correction scenarios at special frequencies, randomization breaks the fixed sampling of the same data by each sub-ADC, allowing timing skew to be corrected using correlation methods. Taking two-way interleaving as an example, the outputs of the two ADCs are y1(k) and y2(k); by calculating the correlation value between y1(k) and y2(k), and comparing the correlation value between y1(k+1) and y2(k), the simulation delay is adjusted so that the two correlation values ​​are the same, thus completing the timing skew correction.

[0109] Compared with existing technologies, the time-interleaved ADC sampling method provided in this application can solve the problem of residual interleaving spurious signals after multi-channel interleaving mismatch correction and improve SFDR. For single-tone inputs at specific frequencies, it can accurately correct timing skew deviations.

[0110] Based on the above method embodiments, this application also provides a time-interleaved ADC sampling system, see [link to relevant documentation]. Figure 2 As shown, the system includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter (ADC) sub-ADCs; the pseudo-random sequence generator is connected to the analog multiplexer and also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through multiple ADC sub-ADCs; the digital multiplexer has M channels, and the analog multiplexer and the number of ADC sub-ADCs are both M+1; the time-interleaved ADC sampling system is used to perform the method described in the foregoing embodiments.

[0111] The system provided in this application embodiment has the same implementation principle and technical effects as the aforementioned method embodiment. For the sake of brevity, any parts not mentioned in the system embodiment can be referred to the corresponding content in the aforementioned method embodiment.

[0112] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0113] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the technical scope disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A time-interleaved ADC sampling method, characterized in that, The method is applied to a time-interleaved ADC sampling system; the system includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter (ADC) sub-ADCs; the pseudo-random sequence generator is connected to the analog multiplexer and also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through multiple ADC sub-ADCs; the digital multiplexer has M channels, and the analog multiplexer and the number of ADC sub-ADCs are both M+1; The following steps are performed during each signal sampling: The pseudo-random sequence generator outputs a first pseudo-random signal to the analog multiplexer; The analog multiplexer selects the corresponding target sub-ADC to output the currently connected analog signal based on the first pseudo-random signal; The target sub-ADC converts the analog signal into a digital signal and sends it to the digital multiplexer; The decoder performs decoding processing on the first pseudo-random signal to obtain a second pseudo-random signal, which is then sent to the digital multiplexer. The digital multiplexer selects the corresponding number of output channels according to the second pseudo-random signal and outputs the digital signal of the target sub-ADC.

2. The method according to claim 1, characterized in that, The pseudo-random sequence generator includes: a pseudo-random binary sequence module, a RAM memory, and a FIFO queue; the FIFO queue pre-stores the sub-ADC identifiers corresponding to M sub-ADCs; the addresses in the RAM memory correspond to binary sequences, and each address stores a preset sub-ADC identifier; the preset sub-ADC identifier is the sub-ADC identifier corresponding to the (M+1)th sub-ADC. The step of the pseudo-random sequence generator outputting a first pseudo-random signal to the analog multiplexer includes: If the current number of beats is less than or equal to M, the sub-ADC identifier at the front of the current array is determined according to the sub-ADC identifier order in the FIFO queue and output as the first pseudo-random signal to the analog multiplexer; If the current number of beats is greater than M, the pseudo-random binary sequence module inputs a random binary number into the RAM memory; the RAM memory selects the sub-ADC identifier in the corresponding target address according to the random binary number and adds it to the FIFO queue, outputs the sub-ADC identifier in the target address as the first pseudo-random signal to the analog multiplexer, and stores the first sub-ADC identifier in the FIFO queue in the target address of the RAM memory.

3. The method according to claim 1, characterized in that, In the M+1 sub-ADCs, M is the regular number of sub-ADCs, or M+1 is the regular number of sub-ADCs; the regular number includes: 2, 4, 8 or 16.

4. The method according to claim 1, characterized in that, The method for determining M in the number of sub-ADCs is as follows: Obtain the total ADC sampling rate and the highest sampling rate that the current sub-ADC can achieve; The quotient M is obtained by dividing the total ADC sampling rate by the highest sampling rate of the current sub-ADC.

5. The method according to claim 1, characterized in that, The decoder is used to decode a sequence of 1 to M+1 into a sequence of 1 to M.

6. The method according to claim 1, characterized in that, The method further includes: The timing deviation of the third designated sub-ADC is aligned with the sampling signals of the first and second designated sub-ADCs. For the case where M+1=4, perform three timing offset alignments following the steps described above: In the first instance, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the (k+1)-th sampling signal of the first sub-ADC; the third designated sub-ADC is the third sub-ADC. The second time, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the first sub-ADC; the sampling signal of the second designated sub-ADC is the k-th sampling signal of the third sub-ADC; the third designated sub-ADC is the second sub-ADC; The third time, the sampling signal of the first designated sub-ADC is the k-th sampling signal of the third sub-ADC; the sampling signal of the second designated sub-ADC is the (k+1)-th sampling signal of the first sub-ADC; and the third designated sub-ADC is the fourth sub-ADC.

7. The method according to claim 6, characterized in that, The step of aligning the timing deviation of the third designated sub-ADC with reference to the sampling signals of the first and second designated sub-ADCs includes: From the random interleaved sampling pattern, find the first sampling cases of all first designated sub-ADCs followed by third designated sub-ADCs; and the second sampling cases of all third designated sub-ADCs followed by first designated sub-ADCs. Based on the sampled signals of the first and third specified sub-ADCs in the first sampling case, calculate the first correlation value; based on the sampled signals of the third and first specified sub-ADCs in the second sampling case, calculate the second correlation value. Based on the first correlation value and the second correlation value, the timing deviation of the third designated sub-ADC is aligned.

8. The method according to claim 7, characterized in that, The step of calculating the first correlation value based on the sampled signals of the first and third specified sub-ADCs in the first sampling case includes: performing a multiplication and accumulation operation using the following formula to obtain the first correlation value vxcorrl: Where y1(k) represents the sampling signal of the first specified sub-ADC; y3(k) represents the k-th sampling signal of the third specified sub-ADC; N represents the preset accumulation length; The step of calculating the second correlation value based on the sampled signals of the third and first specified sub-ADCs in the second sampling case includes: performing a multiplication and accumulation operation using the following formula to obtain the second correlation value vxcorr2:

9. The method according to claim 7, characterized in that, The step of aligning the timing deviation of the third designated sub-ADC based on the first correlation value and the second correlation value includes: If the first correlation value is greater than the second correlation value, adjust the delay of the third designated sub-ADC by one step. If the first correlation value is less than the second correlation value, adjust the delay of the third designated sub-ADC by one step. If the first correlation value is equal to the second correlation value, the delay of the third specified sub-ADC remains unchanged.

10. A time-interleaved ADC sampling system, characterized in that, The system includes: a pseudo-random sequence generator, a decoder, an analog multiplexer, a digital multiplexer, and multiple analog-to-digital converter (ADC) sub-ADCs; the pseudo-random sequence generator is connected to the analog multiplexer and also connected to the digital multiplexer through the decoder; the analog multiplexer is connected to the digital multiplexer through multiple ADC sub-ADCs; the digital multiplexer has M channels, and the analog multiplexer and the number of ADC sub-ADCs are both M+1; the time-interleaved ADC sampling system is used to perform the method as described in any one of claims 1-9.

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