Communication implementation method and electronic terminal

Abstract

The invention discloses a communication implementation method and an electronic terminal, the electronic terminal comprises a Bluetooth system on chip, and the method comprises the following steps: processing a received radio frequency signal to obtain a binary wake-up code; the radio frequency signal is sent by another electronic terminal; comparing the binary wake-up code with a pre-stored password; and if the binary wake-up code is the same as the pre-stored password, generating a wake-up signal to switch the Bluetooth system on chip from a dormant state to a working state. According to the invention, the power consumption is reduced, the service life of the battery is greatly prolonged, false wakeup is prevented, the Bluetooth SoC is quickly started as required, and the response speed and the user experience are optimized.

Description

Technical Field

[0001] The present application relates to the field of data communication technology, and further to a communication implementation method and an electronic terminal. Background Art

[0002] Bluetooth communication is a short-range wireless communication technology, mainly used for low-power data exchange and connection between electronic terminals.

[0003] Therefore, how to effectively reduce power consumption while ensuring normal Bluetooth communication has become one of the key issues that need to be urgently addressed in the current field of Bluetooth communication technology. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a communication implementation method and an electronic terminal, which can effectively reduce power consumption while ensuring normal Bluetooth communication.

[0005] In a first aspect, to achieve the above-mentioned objectives, an embodiment of the present application provides a communication implementation method, which is applied to an electronic terminal, wherein the electronic terminal includes a Bluetooth system-on-chip, and the method includes:

[0006] Processing a received radio frequency signal to obtain a binary wake-up code; the radio frequency signal is sent by another electronic terminal;

[0007] Comparing the binary wake-up code with a pre-stored password;

[0008] If the binary wake-up code is the same as the pre-stored password, a wake-up signal is generated to switch the Bluetooth system-on-chip from a dormant state to an active state.

[0009] In some embodiments, decoding to obtain a binary wake-up code includes:

[0010] Decoding the radio frequency signal to obtain a target analog signal;

[0011] Comparing each voltage value in the target analog signal with a voltage threshold; when the voltage value is higher than the voltage threshold, the comparison result is 1, and when the voltage value is lower than the voltage threshold, the comparison result is 0;

[0012] According to the arrangement order of all the voltage values in the target analog signal, a serial digital signal is output according to the comparison result corresponding to each voltage value, and the binary wake-up code is obtained according to the serial digital signal.

[0013] In some embodiments, obtaining the binary wake-up code according to the serial digital signal includes:

[0014] generating a start pulse signal when a starting edge of the serial digital signal is detected;

[0015] The pre-connected main clock signal is frequency-divided according to the start pulse signal to obtain a sub-clock signal; the frequency of the sub-clock signal is equal to the preset data rate;

[0016] Under the control of the sub-clock signal and the start pulse control signal, the binary wake-up code is compared with the pre-stored password to determine whether they are the same.

[0017] In some embodiments, the comparing the binary wake-up code with the pre-stored password under the control of the sub-clock signal and the start pulse control signal to see whether they are the same includes:

[0018] At a transition edge of the sub-clock signal, control a shift register group to sample a data bit according to the arrangement order of the binary wake-up code, the shift register group including N shift registers, the number of data storage bits of the N shift registers being equal to the number of bits of the binary wake-up code, and N being a positive integer;

[0019] When the number of the sub-clock signals reaches the number of bits of the binary wake-up code, the shift register group is controlled to stop sampling, and the binary wake-up code stored in the shift register group is compared with the pre-stored password stored in the latch to see whether they are the same.

[0020] In some embodiments, further comprising:

[0021] If the binary wake-up code is different from the pre-stored password, the dormant state of the Bluetooth system-on-chip is maintained.

[0022] In a second aspect, the present application further provides an electronic terminal, the electronic terminal including a Bluetooth system-on-chip, a hardware decoding circuit, and an antenna for receiving radio frequency signals, wherein the hardware decoding circuit includes:

[0023] a decoding module connected to the antenna, configured to decode the received radio frequency signal to obtain a binary wake-up code; the radio frequency signal is sent by another electronic terminal;

[0024] A processing module is connected to the decoding module and is used to compare the binary wake-up code with a pre-stored password. If the binary wake-up code is the same as the pre-stored password, a wake-up signal is generated to switch the Bluetooth system-on-chip from a dormant state to an active state.

[0025] In some embodiments, the decoding module includes:

[0026] an envelope detector, decoding the radio frequency signal to obtain a target analog signal;

[0027] a first comparator, connected to the envelope detector, configured to compare each voltage value in the target analog signal with a voltage threshold; and output a serial digital signal according to a comparison result corresponding to each voltage value in an arrangement order of all the voltage values in the target analog signal;

[0028] A processing unit is connected to the first comparator and is used to obtain the binary wake-up code according to the serial digital signal; when the voltage value is higher than the voltage threshold, the comparison result is 1, and when the voltage value is lower than the voltage threshold, the comparison result is 0.

[0029] In some embodiments, the processing unit includes:

[0030] a signal source, connected to the first comparator, and configured to generate a start pulse signal when a starting edge of the serial digital signal is detected;

[0031] a frequency divider connected to the signal source and the first comparator, configured to divide the pre-connected main clock signal according to the start pulse signal to obtain a sub-clock signal; the frequency of the sub-clock signal is equal to the preset data rate;

[0032] The comparison subunit is connected to the signal source and the first comparator, and is used to compare whether the binary wake-up code is the same as the pre-stored password under the control of the sub-clock signal and the start pulse control signal.

[0033] In some embodiments, the comparison subunit includes:

[0034] a counter connected to the signal source and the first comparator, and configured to count the number of the sub-clock signals when receiving the start pulse control signal;

[0035] a shift register group, connected to the signal source and the first comparator, and configured to sample a data bit at a transition edge of the sub-clock signal according to the arrangement order of the binary wake-up code, wherein the shift register group includes N shift registers, the number of data storage bits of the N shift registers being equal to the number of bits of the binary wake-up code, and N being a positive integer;

[0036] The shift register group is further configured to control the shift register group to stop sampling when the number of the sub-clock signals reaches the number of bits of the binary wake-up code;

[0037] A latch for storing a pre-stored password;

[0038] The second comparator is connected to the latch and the shift register group, and is used to compare whether the binary wake-up code stored in the shift register group is the same as the pre-stored password stored in the latch in advance.

[0039] In some embodiments, the processing module is further configured to maintain the Bluetooth system-on-chip in a dormant state if the binary wake-up code is different from the pre-stored password.

[0040] An embodiment of the present application provides a communication implementation method and electronic terminal, the electronic terminal including a Bluetooth system-on-chip. The method comprises: processing a received radio frequency signal to obtain a binary wake-up code; the radio frequency signal is transmitted by another electronic terminal; comparing the binary wake-up code with a pre-stored password; and if the binary wake-up code and the pre-stored password are the same, generating a wake-up signal to switch the Bluetooth system-on-chip from a dormant state to an active state. This application reduces power consumption, significantly extends battery life, prevents false wake-ups, enables fast, on-demand startup of the Bluetooth SoC, and optimizes response speed and user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present application.

[0042] Figure 1 This is a flow chart of the communication implementation method provided in the embodiment of the present application.

[0043] Figure 2 This is a structural diagram of an electronic terminal provided in an embodiment of the present application.

[0044] Figure 3 This is a structural diagram of a hardware decoding circuit of an electronic terminal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0046] In the description of the embodiments of the present application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0047] In order to enable any person skilled in the art to implement and use the present application, the following description is provided. In the following description, details are listed for the purpose of explanation. It should be understood that one of ordinary skill in the art will recognize that the present application can be implemented without using these specific details. In other examples, well-known processes will not be elaborated in detail to avoid obscuring the description of the embodiments of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in accordance with the embodiments of the present application.

[0048] At a time when Bluetooth communication technology is widely used in various electronic terminals, its operating mechanism in the connected state has certain limitations. At present, during the Bluetooth communication process, when Bluetooth is in the connected state, it will maintain periodic connection operation even if there is no data interaction to ensure that the master / slave devices can communicate normally and no data is lost. However, the Bluetooth system-on-chip (especially when it remains in a connectable state) is one of the relatively power-consuming modules in the device. Therefore, the problems brought about by this continuous periodic connection operation are becoming increasingly prominent, that is, when there is no data interaction, the master / slave devices still maintain unnecessary Bluetooth communication connection activities, resulting in additional power loss. This limits the battery life of the master / slave devices to a certain extent, especially in electronic terminals that are sensitive to power consumption, where this power loss problem is more obvious.

[0049] The following describes the communication implementation method and electronic terminal of the present application in conjunction with the accompanying drawings to solve the above problems.

[0050] Reference Figure 1 and Figure 2 , Figure 1 This is a flow chart of a communication implementation method provided in an embodiment of the present application. Figure 2 This is a schematic diagram of the structure of the electronic terminal 1 provided in the embodiment of the present application. Figure 1 Although a logical sequence may be shown in the flowcharts shown in the drawings or other figures, in some cases the steps shown or described may be performed in an order different from that shown. Figure 1 The communication implementation method shown is applied to Figure 2The electronic terminal 1 shown includes a Bluetooth system-on-chip. The communication implementation method includes steps S100 to S300, which are specifically as follows:

[0051] S100, processing a received radio frequency signal to obtain a binary wake-up code; the radio frequency signal is sent by another electronic terminal;

[0052] S200, comparing the binary wake-up code with a pre-stored password;

[0053] S300: If the binary wake-up code is the same as the pre-stored password, generate a wake-up signal to switch the Bluetooth system-on-chip from a sleep state to an active state.

[0054] Specifically, such as Figure 2 As shown, the Bluetooth SOC 20 (System on Chip) highly integrates a Bluetooth RF transceiver, baseband controller, processor (such as the ARM Cortex-M series), memory (RAM / ROM), power management module, and various peripheral interfaces (ADC, PWM, I2C, etc.) into a single chip. For ease of explanation, the electronic terminal 1 that applies and executes the communication implementation method is referred to as the first electronic terminal, and the other electronic terminal is referred to as the second electronic terminal. The first electronic terminal and the second electronic terminal both include the Bluetooth SOC 20, the antenna 20 described in the following embodiments, and the hardware decoding circuit 30. The Bluetooth SoCs of the first electronic terminal and the second resistor device are in a fully dormant or off state when a Bluetooth communication connection is not required. When the second electronic terminal, acting as a master device, needs to interact with the first electronic terminal, acting as a slave device, through Bluetooth communication, the second electronic terminal generates and transmits a radio frequency signal with a binary wake-up code to the antenna 20 of the first electronic terminal via the antenna 20. After the antenna 20 of the first electronic terminal receives the radio frequency signal, the hardware decoding circuit 30 of the first electronic terminal decodes the radio frequency signal and extracts the binary wake-up code. In this way, the first electronic terminal compares the binary wake-up code obtained by decoding the radio frequency signal received from the second electronic terminal with a pre-set and stored password to see if they are the same. If the first electronic terminal determines that the binary wake-up code is the same as the pre-stored password, the first electronic terminal generates a wake-up signal to wake up its own Bluetooth system-on-chip. It should be noted that the first electronic terminal and the second electronic terminal can both act as master devices or slave devices, that is, when the first electronic terminal acts as a master device, the second electronic terminal acts as a slave device, and when the first electronic terminal acts as a slave device, the second electronic terminal acts as a master device.

[0055] In the present application, when there is no communication demand, the Bluetooth system-on-chip of the electronic terminal 1 is completely in a deep sleep state (even completely powered off), with only the simple front-end hardware decoding circuit 30 composed of discrete analog / digital devices working to monitor specific RF signals. The static power consumption of the hardware decoding circuit 30 is much lower than that of the Bluetooth SOC 20 (even in the lowest power listening mode). In the present application, the Bluetooth SOC 20 of the electronic terminal 1 (i.e., the first electronic terminal) acting as a slave device will only be awakened when another electronic terminal acting as a master device (i.e., the second electronic terminal described above) actively sends an RF signal containing a binary wake-up code and the signal is successfully decoded and matches the pre-stored password. At other times, the Bluetooth SOC 20 is powered off or in a deep sleep state. In this way, it is only necessary to briefly and simply transmit a predefined, simple-structured RF signal with a binary wake-up code and match it to wake up the Bluetooth SOC 20 at the same time. This method replaces the continuously turned-on Bluetooth SOC 20 monitoring with extremely low-power RF monitoring. There is no need to establish a complex Bluetooth connection or send a standard Bluetooth broadcast packet to wake up the Bluetooth SOC 20 first, which saves a lot of unnecessary wake-up-monitoring-and-sleep cycle energy consumption, greatly extends battery life, and achieves ultra-low standby power consumption. At the same time, through the password comparison mechanism, it can also prevent the device from being mistakenly awakened by arbitrary or malicious RF signals, causing unnecessary power consumption and security risks, ensuring the security and reliability of the wake-up, preventing false wake-up, providing fast, on-demand startup of the Bluetooth SOC 20, and optimizing the response speed and user experience.

[0056] In some embodiments, as Figure 3 As shown, Figure 3 : is a structural diagram of the hardware decoding circuit 30 of the electronic terminal 1 provided in an embodiment of the present application. The decoding to obtain the binary wake-up code includes:

[0057] Decoding the radio frequency signal to obtain a target analog signal;

[0058] Comparing each voltage value in the target analog signal with a voltage threshold; when the voltage value is higher than the voltage threshold, the comparison result is 1, and when the voltage value is lower than the voltage threshold, the comparison result is 0;

[0059] According to the arrangement order of all the voltage values in the target analog signal, a serial digital signal is output according to the comparison result corresponding to each voltage value, and the binary wake-up code is obtained according to the serial digital signal.

[0060] Specifically, the radio frequency signal includes a high-frequency carrier signal and a low-frequency target analog signal, and decoding the radio frequency signal to obtain the target analog signal includes performing envelope detection on the radio frequency signal and then performing RC filtering to obtain the target analog signal. Figure 3As shown, the hardware decoding circuit 30 includes an envelope detector and a first comparator. The envelope detector includes a Schottky diode and an RC filter. The input end of the Schottky diode is connected to the output end of the antenna 20 to receive the RF signal transmitted by the antenna 20. The output end of the Schottky diode is connected to the input end of the RC filter, and the output end of the RC filter is connected to one input end of the first comparator. The RF signal is input to a Schottky diode (e.g., 1N5711). The Schottky diode is used for envelope detection (Envelope Detection), filtering out the high-frequency carrier signal (e.g., 2.4GHz / 5GHz) and outputting a low-frequency envelope signal including a binary wake-up code. The RC filter filters out high-frequency noise in the envelope signal to obtain a target analog signal including a binary wake-up code. The first comparator (e.g., TLV3501) converts the filtered target analog signal into a digital signal, namely, a binary wake-up code. That is, the target analog signal is input to one input end of the first comparator (e.g., the non-inverting input end +), and the other input end of the first comparator (e.g., the inverting input end -) is connected to a reference voltage (i.e., a voltage threshold). The first comparator compares each voltage value with the voltage threshold in the order in which all voltage values in the target analog signal are arranged. If the voltage value is higher than the voltage threshold, the first comparator outputs a comparison result of 1 (i.e., a high level); if the voltage value is lower than the voltage threshold, the first comparator outputs a comparison result of 0 (a low level). The comparison results corresponding to each voltage value are combined in the order in which all voltage values in the target analog signal are arranged to generate a serial digital signal. The high and low level changes in the serial digital signal represent the original binary wake-up code in the RF signal sent by the master device. The binary wake-up code is then derived from the serial digital signal.

[0061] This application only requires a simple envelope detector (usually including a Schottky diode and an RC filter) and a first comparator (which compares the voltage to a voltage threshold and outputs a serial digital signal of 0 / 1). It is completed in very low-power digital logic (it can even be a pure hardware state machine) without the need for complex processors or high-power operations, effectively supporting the low-power on-demand wake-up requirements of Bluetooth SOC 20.

[0062] In some implementations, obtaining the binary wake-up code according to the serial digital signal includes:

[0063] generating a start pulse signal when a starting edge of the serial digital signal is detected;

[0064] The pre-connected main clock signal is frequency-divided according to the start pulse signal to obtain a sub-clock signal; the frequency of the sub-clock signal is equal to the preset data rate;

[0065] Under the control of the sub-clock signal and the start pulse control signal, the binary wake-up code is compared with the pre-stored password to determine whether they are the same.

[0066] Specifically, such as Figure 3 As shown, the hardware decoding circuit 30 also includes an edge detector (e.g., 74HC123), a clock source (e.g., a crystal oscillator that generates a master clock signal such as 8 MHz, 16 MHz, or 32 MHz), and a frequency divider. The input of the edge detector is connected to the output of the first comparator, the output of the edge detector is connected to the enable input of the frequency divider, and the output of the clock source is connected to the clock input of the frequency divider.

[0067] The serial digital signal output by the first comparator is input to an edge detector, which detects the starting edge of the serial digital signal (e.g., the first rising edge or the first falling edge; for ease of explanation, the first rising edge is used as an example below). When the serial digital signal output by the first comparator changes from a low level to a high level (i.e., the first rising edge of the serial digital signal is detected), the edge detector is triggered and generates a start pulse signal. The start pulse signal marks the beginning of a valid data packet. The signal source generates and outputs a stable master clock signal with a preset frequency (e.g., 16 MHz) to the frequency divider. After receiving the start pulse signal generated by the edge detector, the frequency divider divides the master clock signal obtained from the signal source to obtain a sub-clock signal. The frequency of this sub-clock signal (e.g., 1 MHz) is the same as the baud rate of the binary wake-up code sent by the master device, i.e., the preset data rate. Then, under the control of the sub-clock signal, the hardware decoding circuit 30 compares the binary wake-up code with the pre-stored password to determine whether they are the same.

[0068] In some embodiments, the comparing, under the control of the sub-clock signal and the start pulse control signal, whether the binary wake-up code is the same as the pre-stored password includes:

[0069] At a transition edge of the sub-clock signal, control a shift register group to sample a data bit according to the arrangement order of the binary wake-up code, the shift register group including N shift registers, the number of data storage bits of the N shift registers being equal to the number of bits of the binary wake-up code, and N being a positive integer;

[0070] When the number of the sub-clock signals reaches the number of bits of the binary wake-up code, the shift register group is controlled to stop sampling, and the binary wake-up code stored in the shift register group is compared with the pre-stored password stored in the latch to see whether they are the same.

[0071] Specifically, such as Figure 3As shown, the hardware decoding circuit 30 also includes a counter (e.g., 74HC161), a shift register group, a DIP (Dual In-line Package) switch, a latch (e.g., 74HC573), a second comparator (e.g., TLV3501), and a transistor (e.g., 2N3904). The shift register group includes N shift registers, where N is a positive integer. When N ≥ 2, the N shift registers are connected in cascade. When N = 2, two shift registers with 8 bits of data storage, such as 74HC164 or 74HC595, can be connected in cascade. The output of the edge detector is connected to the enable input of the counter and the enable input of the shift register group. The output of the frequency divider is connected to the clock input of the counter and the clock input of the shift register group, respectively. The output of the counter is connected to the enable control terminal of the shift register. The output of the shift register group is connected to the first input of the second comparator, the output of the DIP switch is connected to the input of the latch, the output of the latch is connected to the second input of the second comparator, and the output of the second comparator is connected to the control terminal of the transistor.

[0072] After receiving a start pulse signal from the edge detector at its enable input, the counter begins counting the sub-clock signals output by the frequency divider. After receiving a start pulse signal from the edge detector at its enable input, the shift register group samples data on the transition edge (either rising or falling, depending on the circuit design) of each sub-clock signal output by the frequency divider. For ease of explanation, the following uses rising edges as an example. For example, on each rising edge of a sub-clock signal, the counter counts, and the shift register group samples the serial digital signal output by the first comparator, shifting the internally stored data one bit to the right. The newly sampled data bits are sequentially shifted in and stored. When the counter reaches the number of bits in the binary wake-up code, it generates an overflow signal. When the enable control terminal of the shift register group receives the overflow signal, it controls the shift register group to stop sampling new input data, preventing oversampling and subsequent noise or invalid data from being shifted in. Consequently, the shift register group latches the latest received binary wake-up code. A unique, fixed binary pre-stored password is pre-set via a DIP switch. The latch locks and stores this pre-stored password to prevent voltage fluctuations during the comparison process, and stably outputs a preset value to the second input of the second comparator, thereby ensuring comparison reliability and accuracy. The binary wake-up code just sampled from the shift register group and the pre-stored password previously stored in the latch are simultaneously input into the first and second inputs of the second comparator. When each bit of data received at the first input is identical to each bit of data received at the second input, the second comparator outputs a valid signal (usually active low or active high, depending on the transistor model and configuration). If the binary wake-up code is equal to the pre-stored password, the comparator's output valid signal drives the transistor (2N3904) to conduct, thereby generating a wake-up signal to the interrupt input pin of the Bluetooth SOC 20 to start waking up the Bluetooth SOC 20, switching the Bluetooth SOC 20, which is the first electronic terminal as a slave device, from a dormant state to an active state. After waking up, the Bluetooth SOC 20 can activate the Bluetooth communication function, establish a formal connection with the second electronic terminal as a master device, and exchange data. The Bluetooth SOC 20 is usually configured in sleep mode, but its interrupt input pin remains active listening (with very low power consumption).

[0073] This application sets the binary wake-up code equal to the pre-stored password as the sole credential for waking up the slave device's Bluetooth SOC 20. By receiving a simulated RF signal and integrating a hardware decoding circuit 30, this application enables the slave device to listen for RF signals in a near-zero-power sleep state. Only when the binary wake-up code in the received RF signal completely matches the pre-stored password will a hardware interrupt be generated to wake up the Bluetooth SOC 20. This wake-up process is completed by this ultra-low-power, dedicated hardware decoding circuit 30, implementing its reception, decoding, verification, and interrupt triggering functions. This eliminates any periodic wake-up and protocol stack overhead when there is no data interaction between the master and slave devices, achieving the lowest standby power consumption.

[0074] In some embodiments, further comprising:

[0075] If the binary wake-up code is different from the pre-stored password, the dormant state of the Bluetooth system-on-chip is maintained.

[0076] The present application further provides an electronic terminal 1, which includes a Bluetooth system-on-chip, a hardware decoding circuit 30, and an antenna 20 for receiving radio frequency signals. The hardware decoding circuit 30 includes:

[0077] a decoding module connected to the antenna 20 and configured to decode the received radio frequency signal to obtain a binary wake-up code; the radio frequency signal is sent by another electronic terminal;

[0078] A processing module is connected to the decoding module and is used to compare the binary wake-up code with a pre-stored password. If the binary wake-up code is the same as the pre-stored password, a wake-up signal is generated to switch the Bluetooth system-on-chip from a dormant state to an active state.

[0079] In some embodiments, the decoding module includes:

[0080] an envelope detector, decoding the radio frequency signal to obtain a target analog signal;

[0081] a first comparator, connected to the envelope detector, configured to compare each voltage value in the target analog signal with a voltage threshold; and output a serial digital signal according to a comparison result corresponding to each voltage value in an arrangement order of all the voltage values in the target analog signal;

[0082] A processing unit is connected to the first comparator and is used to obtain the binary wake-up code according to the serial digital signal; when the voltage value is higher than the voltage threshold, the comparison result is 1, and when the voltage value is lower than the voltage threshold, the comparison result is 0.

[0083] In some embodiments, the processing unit includes:

[0084] a signal source, connected to the first comparator, and configured to generate a start pulse signal when a starting edge of the serial digital signal is detected;

[0085] a frequency divider connected to the signal source and the first comparator, configured to divide the pre-connected main clock signal according to the start pulse signal to obtain a sub-clock signal; the frequency of the sub-clock signal is equal to the preset data rate;

[0086] The comparison subunit is connected to the signal source and the first comparator, and is used to compare whether the binary wake-up code is the same as the pre-stored password under the control of the sub-clock signal and the start pulse control signal.

[0087] In some embodiments, the comparison subunit includes:

[0088] a counter connected to the signal source and the first comparator, and configured to count the number of the sub-clock signals when receiving the start pulse control signal;

[0089] a shift register group, connected to the signal source and the first comparator, and configured to sample a data bit at a transition edge of the sub-clock signal according to the arrangement order of the binary wake-up code, wherein the shift register group includes N shift registers, the number of data storage bits of the N shift registers being equal to the number of bits of the binary wake-up code, and N being a positive integer;

[0090] The shift register group is further configured to control the shift register group to stop sampling when the number of the sub-clock signals reaches the number of bits of the binary wake-up code;

[0091] A latch for storing a pre-stored password;

[0092] The second comparator is connected to the latch and the shift register group, and is used to compare whether the binary wake-up code stored in the shift register group is the same as the pre-stored password stored in the latch in advance.

[0093] In some embodiments, the processing module is further configured to maintain the Bluetooth system-on-chip in a dormant state if the binary wake-up code is different from the pre-stored password.

[0094] During specific implementation, the above modules can be implemented as independent entities, or can be arbitrarily combined and implemented as the same or several entities. The specific implementation of the above modules can be found in the previous method embodiments and will not be repeated here.

[0095] The electronic terminal 1 may be a terminal, which may be a smart phone, a tablet computer, a laptop computer, a touch screen, a wireless mouse / keyboard, a smart sensor, a wearable device, a personal computer (PC), a personal digital assistant (PDA), certain Internet of Things terminals and other terminal devices. The electronic terminal 1 includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. The memory is coupled to the processor, and when the processor executes the computer program, the steps in the communication implementation method are implemented. It will be understood by those skilled in the art that the structure of the electronic terminal 1 mentioned above does not constitute a limitation on the electronic terminal 1, and may include more or fewer components than those mentioned above, or a combination of certain components, or a different arrangement of components.

[0096] The processor is the control center of the electronic terminal 1. It uses various interfaces and lines to connect the various parts of the entire electronic terminal 1. By running or loading software programs and / or modules stored in the memory and calling data stored in the memory, it executes various functions of the electronic terminal 1 and processes data, thereby monitoring the electronic terminal 1 as a whole.

[0097] The specific implementation of the above operations can be found in the previous embodiments and will not be repeated here.

[0098] Optionally, the electronic terminal 1 further includes: a touch screen display, a radio frequency circuit, an audio circuit, an input unit, and a power supply. The processor is electrically connected to the touch screen display, the radio frequency circuit, the audio circuit, the input unit, and the power supply, respectively. Those skilled in the art will appreciate that the structure of the electronic terminal 1 mentioned above does not limit the electronic terminal 1 and may include more or fewer components than those mentioned above, or combine certain components, or arrange the components differently.

[0099] The touch screen can be used to display a graphical user interface and receive operation instructions generated by the user acting on the graphical user interface. The touch screen can include a display panel and a touch panel. Among them, the display panel can be used to display information input by the user or information provided to the user and various graphical user interfaces of the electronic terminal 1. These graphical user interfaces can be composed of graphics, text, icons, videos, and any combination thereof. Optionally, the display panel can be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), etc. The touch panel can be used to collect user touch operations on or near it (for example, the user uses a finger, a stylus, or any other suitable object or accessory to operate on or near the touch panel), generate corresponding operation instructions, and execute the operation instructions. Optionally, the touch panel can include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch direction and detects the signal generated by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into touch point coordinates, and then sends it to the processor, and can receive commands sent by the processor and execute them. The touch panel can cover the display panel. When the touch panel detects a touch operation on or near it, it transmits it to the processor to determine the type of touch event. The processor then provides a corresponding visual output on the display panel based on the type of touch event. In an embodiment of the present application, the touch panel and the display panel can be integrated into a touch display screen to realize input and output functions. However, in some embodiments, the touch panel and the touch panel can be used as two independent components to realize input and output functions. That is, the touch display screen can also be used as part of the input unit to realize input functions.

[0100] The radio frequency circuit can be used to send and receive radio frequency signals, so as to establish wireless communication with a network device or other electronic terminal 1 through wireless communication, and to send and receive signals between the network device or other electronic terminal 1.

[0101] The audio circuit can be used to provide an audio interface between the user and the electronic terminal 1 via a speaker and microphone. The audio circuit can convert received audio data into electrical signals and transmit them to the speaker, which then converts them into sound signals for output. The microphone, on the other hand, converts collected sound signals into electrical signals, which are then received by the audio circuit and converted into audio data. The audio data is then processed by an output processor and then transmitted via a radio frequency circuit to, for example, another electronic terminal, or the audio data is output to a memory for further processing. The audio circuit may also include an earphone jack to provide communication between an external headset and the electronic terminal 1.

[0102] The input unit can be used to receive input numbers, character information or user feature information (such as fingerprint, iris, facial information, etc.), and generate keyboard, mouse, joystick, optical or trackball signal input related to user settings and function control.

[0103] The power supply is used to power the various components of the electronic terminal 1. Optionally, the power supply can be logically connected to the processor via a power management system, thereby enabling the power management system to manage charging, discharging, and power consumption. The power supply can also include one or more DC or AC power supplies, a recharging system, a power fault detection circuit, a power converter or inverter, a power status indicator, and other components. The electronic terminal 1 may also include a camera, sensors, a Wi-Fi module, a Bluetooth module, and other components, which are not detailed here.

[0104] Those skilled in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be accomplished by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0105] To this end, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the steps in any one of the communication implementation methods provided in the embodiments of the present application.

[0106] The computer-readable storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0107] In the above embodiments, the description of each embodiment has its own focus. For parts not described in detail in one embodiment, please refer to the relevant description of other embodiments. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working process and beneficial effects of the electronic terminal 1, computer-readable storage medium, electronic terminal 1 and its corresponding units described above can refer to the description of the communication implementation method in the above embodiment, and the details will not be repeated here.

[0108] The above is a detailed introduction to a communication implementation method and an electronic terminal 1 provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A communication implementation method, characterized in that: Applied to an electronic terminal including a Bluetooth system-on-chip, the method includes: Processing a received radio frequency signal to obtain a binary wake-up code; the radio frequency signal is sent by another electronic terminal; Comparing the binary wake-up code with a pre-stored password; If the binary wake-up code is the same as the pre-stored password, a wake-up signal is generated to switch the Bluetooth system-on-chip from a dormant state to an active state.

2. The communication implementation method according to claim 1, characterized in that: The decoding to obtain the binary wake-up code includes: Decoding the radio frequency signal to obtain a target analog signal; Comparing each voltage value in the target analog signal with a voltage threshold; when the voltage value is higher than the voltage threshold, the comparison result is 1, and when the voltage value is lower than the voltage threshold, the comparison result is 0; According to the arrangement order of all the voltage values in the target analog signal, a serial digital signal is output according to the comparison result corresponding to each voltage value, and the binary wake-up code is obtained according to the serial digital signal.

3. The communication implementation method according to claim 2, characterized in that: Obtaining the binary wake-up code according to the serial digital signal includes: generating a start pulse signal when a starting edge of the serial digital signal is detected; The pre-connected main clock signal is frequency-divided according to the start pulse signal to obtain a sub-clock signal; the frequency of the sub-clock signal is equal to the preset data rate; Under the control of the sub-clock signal and the start pulse control signal, the binary wake-up code is compared with the pre-stored password to determine whether they are the same.

4. The communication implementation method according to claim 3, characterized in that: The comparing, under the control of the sub-clock signal and the start pulse control signal, whether the binary wake-up code is the same as the pre-stored password comprises: At a transition edge of the sub-clock signal, control a shift register group to sample a data bit according to the arrangement order of the binary wake-up code, the shift register group including N shift registers, the number of data storage bits of the N shift registers being equal to the number of bits of the binary wake-up code, and N being a positive integer; When the number of the sub-clock signals reaches the number of bits of the binary wake-up code, the shift register group is controlled to stop sampling, and the binary wake-up code stored in the shift register group is compared with the pre-stored password stored in the latch to see whether they are the same.

5. The communication implementation method according to any one of claims 1 to 4, characterized in that: Also includes: If the binary wake-up code is different from the pre-stored password, the dormant state of the Bluetooth system-on-chip is maintained.

6. An electronic terminal, characterized in that: The electronic terminal includes a Bluetooth system-on-chip, a hardware decoding circuit, and an antenna for receiving radio frequency signals. The hardware decoding circuit includes: a decoding module connected to the antenna, configured to decode the received radio frequency signal to obtain a binary wake-up code; the radio frequency signal is sent by another electronic terminal; A processing module is connected to the decoding module and is used to compare the binary wake-up code with a pre-stored password. If the binary wake-up code is the same as the pre-stored password, a wake-up signal is generated to switch the Bluetooth system-on-chip from a dormant state to an active state.

7. The electronic terminal according to claim 6, characterized in that: The decoding module includes: an envelope detector, decoding the radio frequency signal to obtain a target analog signal; a first comparator, connected to the envelope detector, configured to compare each voltage value in the target analog signal with a voltage threshold; and output a serial digital signal according to a comparison result corresponding to each voltage value in an arrangement order of all the voltage values in the target analog signal; A processing unit is connected to the first comparator and is used to obtain the binary wake-up code according to the serial digital signal; when the voltage value is higher than the voltage threshold, the comparison result is 1, and when the voltage value is lower than the voltage threshold, the comparison result is 0.

8. The electronic terminal according to claim 7, characterized in that: The processing unit includes: a signal source, connected to the first comparator, and configured to generate a start pulse signal when a starting edge of the serial digital signal is detected; a frequency divider connected to the signal source and the first comparator, configured to divide the pre-connected main clock signal according to the start pulse signal to obtain a sub-clock signal; the frequency of the sub-clock signal is equal to the preset data rate; The comparison subunit is connected to the signal source and the first comparator, and is used to compare whether the binary wake-up code is the same as the pre-stored password under the control of the sub-clock signal and the start pulse control signal.

9. The electronic terminal according to claim 8, characterized in that: The comparison subunit includes: a counter connected to the signal source and the first comparator, and configured to count the number of the sub-clock signals when receiving the start pulse control signal; a shift register group, connected to the signal source and the first comparator, and configured to sample a data bit at a transition edge of the sub-clock signal according to the arrangement order of the binary wake-up code, wherein the shift register group includes N shift registers, the number of data storage bits of the N shift registers being equal to the number of bits of the binary wake-up code, and N being a positive integer; The shift register group is further configured to control the shift register group to stop sampling when the number of the sub-clock signals reaches the number of bits of the binary wake-up code; A latch for storing a pre-stored password; The second comparator is connected to the latch and the shift register group, and is used to compare whether the binary wake-up code stored in the shift register group is the same as the pre-stored password stored in the latch in advance.

10. The electronic terminal according to any one of claims 6 to 9, characterized in that: The processing module is further configured to maintain the Bluetooth system-on-chip in a dormant state if the binary wake-up code is different from the pre-stored password.

Images