Semiconductor device structure and forming method thereof

Abstract

A method of forming a semiconductor device structure includes forming first and second semiconductor fins on a front side of a substrate; removing a portion of the first and second semiconductor fins to expose the first and second substrate portions, respectively; forming a first source / drain region on the first substrate part, wherein the first source / drain region comprises an N-type epitaxial material; forming a second source / drain region on the second substrate part, wherein the second source / drain region comprises a P-type epitaxial material; depositing a dielectric material on the first and second source / drain regions; forming an opening in the dielectric material to expose a portion of the first and second source / drain regions; forming a mask on the exposed portion of the first source / drain region; performing an implantation process to implant a dopant in the second source / drain region; removing the mask; and depositing a conductive contact electrically connected to the first and second source / drain regions.

Description

Technical Field

[0001] The present invention relates to a semiconductor device structure and a method for forming the same, and more particularly to a dopant implantation process. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (e.g., the number of interconnected elements per chip area) has generally increased, while geometry size (e.g., the smallest component (or trace) that can be created using a process) has decreased. This downsizing process generally provides benefits by increasing production efficiency and reducing associated costs. However, this downsizing also increases the complexity of fabricating ICs.

[0003] Therefore, there is a need to improve the fabrication of integrated circuits. Summary of the Invention

[0004] A method for forming a semiconductor device structure includes: forming a first semiconductor fin and a second semiconductor fin on the front side of a substrate; removing portions of the first semiconductor fin and the second semiconductor fin to expose a first base portion and a second base portion, respectively; forming a first source / drain region on the first base portion, wherein the first source / drain region includes an N-type epitaxial material; forming a second source / drain region on the second base portion, wherein the second source / drain region includes a P-type epitaxial material; depositing a dielectric material on the first source / drain region and the second source / drain region; forming an opening in the dielectric material to expose a portion of the first source / drain region and a portion of the second source / drain region; forming a mask on the exposed portion of the first source / drain region; performing an implantation process to implant dopants in the second source / drain region; removing the mask; and depositing a conductive contact electrically connected to the first source / drain region and the second source / drain region.

[0005] A method for forming a semiconductor device structure includes: forming a first semiconductor fin and a second semiconductor fin on the front side of a substrate; removing portions of the first semiconductor fin and the second semiconductor fin to expose a first base portion and a second base portion, respectively; forming a first source / drain region on the first base portion, wherein the first source / drain region includes an N-type epitaxial material; forming a second source / drain region on the second base portion, wherein the second source / drain region includes a P-type epitaxial material; depositing a dielectric material on the first source / drain region and the second source / drain region; forming an opening in the dielectric material to expose the first source / drain region and the second source / drain region; performing a first implantation process to form a first doped region in the second source / drain region; depositing a conductive contact electrically connected to the first source / drain region and the second source / drain region; flipping the substrate; forming an opening in the substrate to expose the second source / drain region; and performing a second implantation process to form a second doped region in the second source / drain region.

[0006] A semiconductor device structure includes: a first source / drain region, disposed on a substrate, wherein the first source / drain region includes a P-type semiconductor material and a P-type dopant; a second source / drain region, adjacent to the first source / drain region, wherein the second source / drain region includes an N-type semiconductor material and a P-type dopant; and a gate electrode layer, disposed adjacent to the first source / drain region and the second source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following will be used in conjunction with the accompanying drawings to describe aspects of the disclosed embodiments in detail. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the sizes of various components may be arbitrarily enlarged or reduced to clearly illustrate the features of the disclosed embodiments.

[0008] Figure 1 is a circuit diagram of a 6-transistor static random access memory cell according to some embodiments.

[0009] Figures 2 to 6 is a perspective view of various stages in the fabrication of a semiconductor device structure according to some embodiments.

[0010] Figures 7 to 18 According to some embodiments, various stages of fabricating a semiconductor device structure are along Figure 6 Schematic cross-section diagram captured by line segment AA.

[0011] Figures 19 to 25 According to some embodiments, various stages of fabricating a semiconductor device structure are along Figure 6 Schematic cross-sectional view captured by line segment BB.

[0012] Figures 26 to 30 According to other embodiments, various alternative stages of fabricating a semiconductor device structure are described along the Figure 6 Schematic cross-sectional view captured by line segment BB.

[0013] Figures 31 to 35 According to other embodiments, various alternative stages of fabricating a semiconductor device structure are described along the Figure 6 Schematic cross-sectional view captured by line segment BB.

[0014] Figures 36 to 40 According to other embodiments, various alternative stages of fabricating a semiconductor device structure are described along the Figure 6 Schematic cross-sectional view captured by line segment BB.

[0015] Figure 41 and Figure 42 According to some embodiments, the semiconductor device structure is formed after the conductive contact is formed (refer to Figure 24 ) Along Figure 6 Schematic cross-sectional view and top view taken along line segment AA.

[0016] Figure 43 and Figure 44 According to some embodiments, Figure 42 A top view of an alternative high-density and high-current cell of a semiconductor device structure.

[0017] Figures 45 to 47 According to some embodiments, Figure 42 A top view of an alternative implant boundary of a semiconductor device structure.

[0018] Figures 48 to 50 According to some embodiments, various stages of the back-end process for manufacturing a semiconductor device structure are along Figure 6 Schematic cross-section diagram captured by line segment AA.

[0019] Figure 51 According to some embodiments, another stage of semiconductor device construction is along Figure 6 Schematic cross-section diagram captured by line segment AA.

[0020] Figure 52 FIG. 1 shows test results of channel resistance and drain induced barrier loading at different implantation depths according to some embodiments.

[0021] The description of the accompanying drawings is as follows:

[0022] 10: Static random access memory cell

[0023] 20: First inverter

[0024] 30: Storage node

[0025] 40: Second inverter

[0026] 50: Storage node

[0027] 100: Semiconductor device structure

[0028] 101: Base

[0029] 104: Semiconductor layer stacking

[0030] 106: First semiconductor layer

[0031] 106a: first semiconductor layer

[0032] 106b: second semiconductor layer

[0033] 106c: third semiconductor layer

[0034] 108: Second semiconductor layer

[0035] 112: Fin structure

[0036] 114: Groove

[0037] 116: Ibe

[0038] 116a: First Well

[0039] 116b: Second Well

[0040] 118: Insulation material

[0041] 120: Quarantine

[0042] 130: Sacrificial gate structure

[0043] 132: Sacrificial gate dielectric layer

[0044] 134: Sacrificial gate electrode layer

[0045] 136: Mask layer

[0046] 138: First gate spacer

[0047] 139: Second gate spacer

[0048] 144: Dielectric spacer

[0049] 150: First semiconductor material

[0050] 152: Dielectric layer

[0051] 154: Second semiconductor material

[0052] 156: Third semiconductor material

[0053] 162: Contact Etch Stop Layer

[0054] 164: Interlayer dielectric layer

[0055] 166: Etch stop layer

[0056] 167: Interface layer

[0057] 168: Second interlayer dielectric layer

[0058] 169: Work function layer

[0059] 170: Gate dielectric layer

[0060] 172: Gate electrode layer

[0061] 174: Gate structure

[0062] 180: Opening

[0063] 182: Source / drain region

[0064] 182a: first source / drain region

[0065] 182b: Second source / drain region

[0066] 184: Lining

[0067] 186: Mask

[0068] 188: Doping area

[0069] 188a: first doped region

[0070] 188b: Second doped region

[0071] 190: Planting Boundary

[0072] 190a: Planting boundary

[0073] 190b: Planting boundary

[0074] 190c: Planting boundary

[0075] 192: Silicide layer

[0076] 194: Conductive contact

[0077] 196: Dielectric lining

[0078] 198: Dielectric Materials

[0079] 202: Dorsal

[0080] 204: Opening

[0081] 206: Lining

[0082] 208: Doping area

[0083] 210: Conductive contact

[0084] 212: Top

[0085] 214: bottom

[0086] 216: bottom

[0087] 218: Top

[0088] A: Line segment

[0089] AA: Line segment

[0090] B: Line segment

[0091] BB: Line segment

[0092] BL: Bit Line

[0093] BLx: bit line

[0094] C: Line segment

[0095] CC: Line Segment

[0096] d1: depth

[0097] d2: depth

[0098] dn1: width

[0099] dn2: width

[0100] dn3: width

[0101] dp1: width

[0102] dp2: width

[0103] dp3: width

[0104] N1: first node

[0105] N2: Second node

[0106] PD: Pull-down transistor

[0107] PDx: Pull-down transistor

[0108] PG: Pass-gate transistor

[0109] PGx: Pass-gate transistor

[0110] PU: pull-up transistor

[0111] PUx: pull-up transistor

[0112] s1: interval

[0113] Vdd: voltage bus

[0114] Vss: ground potential

[0115] WL: character line

[0116] wp1:width

[0117] wp2:width

[0118] wp3:width DETAILED DESCRIPTION

[0119] The following disclosure provides many different embodiments or examples for implementing different components of the provided services. Specific examples of components and configurations are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, the description of a first component formed on a second component may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the present disclosure may repeat reference symbols and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not, in itself, dominate the relationship between the various embodiments and / or configurations discussed.

[0120] Furthermore, spatially relative terms, such as "below," "below," "below," "above," "above," "top," "over," and the like, may be used herein to describe the relationship of one element or component to other elements or components as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the elements in addition to the orientation depicted in the drawings. When the device is otherwise oriented (rotated 90 degrees or at other orientations), the spatially relative descriptors used herein should be interpreted in accordance with the rotated orientation.

[0121] Various embodiments described below generally relate to implanting dopants (e.g., P-type dopants such as boron (B)) in the source / drain regions of a p-type metal oxide semiconductor (PMOS) in a static random access memory (SRAM) to achieve lower contact resistance during source / drain formation (e.g., through higher boron concentrations in the epitaxial layer), improve pull-up (PU) transistor performance, and increase per-standard deviation (e.g., minimum DC read / write failure variance), SRAM read margin, and maximum voltage. Conversely, poor pull-up transistor performance can reduce maximum voltage (e.g., lower maximum voltage pass rate), and higher resistance can result in poor epitaxial coverage, which can negatively impact device performance.

[0122] Although embodiments of the present disclosure are discussed with respect to nanostructured channel field-effect transistors (e.g., gate all around field effect transistors (GAA FETs), such as horizontal gate all around (HGAA) FETs or vertical gate all around (VGAA) FETs), some aspects of the present disclosure may be implemented in other processes and / or other devices, such as planar FETs, fin field effect transistors (finFETs), or other suitable devices. Those skilled in the art will readily appreciate that other modifications may be made within the scope of the present disclosure. Where a gate all around (GAA) transistor structure is applicable, the gate all around transistor structure may be patterned using any suitable method. For example, one or more photolithography processes, including double patterning or multiple patterning processes, may be used to pattern the structure. Generally, double or multi-patterning processes combine photolithography with self-aligned processes to create patterns with finer pitches than can be achieved using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using photolithography. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used as a mask to pattern the wraparound gate structure.

[0123] Figure 1 1 is a circuit diagram of a 6-transistor static random access memory cell 10 according to some embodiments. The static random access memory cell 10 includes a first inverter 20 formed by a pull-up transistor PUx and a pull-down transistor PDx. The static random access memory cell 10 further includes a second inverter 40 formed by a pull-up transistor PU and a pull-down transistor PD. In addition, the first inverter 20 and the second inverter 40 are both coupled between a voltage bus Vdd and a ground potential Vss. In some embodiments, the pull-up transistor PUx and the pull-up transistor PU may be P-type metal oxide semiconductor transistors, and the pull-down transistor PDx and the pull-down transistor PD may be N-type metal oxide semiconductor (NMOS) transistors, and the scope of the patent application of the present disclosure is not limited thereto.

[0124] exist Figure 1In FIG. 1 , first inverter 20 and second inverter 40 are cross-coupled. That is, the input source of first inverter 20 is connected to the output source of second inverter 40. Similarly, the input source of second inverter 40 is connected to the output source of first inverter 20. The output source of first inverter 20 is referred to as storage node 30. Similarly, the output source of second inverter 40 is referred to as storage node 50. In normal operation mode, storage node 30 is in the opposite logic state of storage node 50. By using two cross-coupled inverters, SRAM cell 10 can latch data using a latch structure. As long as power is supplied via voltage bus Vdd, the stored data will not be lost in the absence of a refresh cycle.

[0125] In an SRAM device using 6-transistor SRAM cells, the cells are arranged into multiple columns and multiple rows. The columns of the SRAM array are formed by bit line pairs (i.e., bit line BLx and bit line BL). The cells of the SRAM device are arranged between the individual bit line pairs. Figure 1 As shown, the SRAM cell 10 is placed between the bit line BLx and the bit line BL.

[0126] exist Figure 1 In the embodiment, the SRAM cell 10 further includes a pass-gate transistor PGx connected between the bit line BLx and the storage node 30 of the first inverter 20. The SRAM cell 10 further includes a pass-gate transistor PG connected between the bit line BL and the storage node 50 of the second inverter 40. The gates of the pass-gate transistor PGx and the pass-gate transistor PG are connected to a word line WL, which connects the SRAM cells in a column of the SRAM array.

[0127] In operation, if pass-gate transistors PGx and PG are inactive, SRAM cell 10 will maintain complementary values at storage nodes 30 and 50 indefinitely as long as power is supplied via voltage bus Vdd. This is because each of the cross-coupled inverter pairs drives the other's input source, thereby maintaining the voltage at the storage nodes. This condition remains stable until power is removed from the SRAM or a write cycle is performed to change the stored data at the storage nodes.

[0128] exist Figure 1In the circuit diagram, pull-up transistors PU and PUx are P-type transistors. Pull-down transistors PDx, PD, pass-gate transistor PGx, and pass-gate transistor PG are N-type transistors. According to various embodiments, pull-up transistors PUx, PU, PDx, PD, pass-gate transistor PGx, and pass-gate transistor PG can be implemented using nanostructured channel field-effect transistors.

[0129] Figure 1 The structure of the SRAM cell 10 is described in the context of a 6-transistor SRAM. However, it should be understood by those skilled in the art that the components of the various embodiments described herein can be used to form other types of devices, such as an 8-transistor SRAM device, or other memory devices other than SRAM. In addition, the embodiments of the present disclosure can be used as stand-alone memory devices, memory devices integrated into other integrated circuits, or other similar devices. Therefore, the embodiments described herein are illustrative ways to form and use the present disclosure and are not intended to limit the scope of the present disclosure.

[0130] Figures 2 to 51 FIG. 1 is a diagram illustrating an exemplary process for manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. Figures 2 to 51 Additional steps are provided before, during, and after the illustrated process, and some of the steps described below may be replaced or eliminated for additional embodiments of the process. The order of the steps / processes is not intended to be limiting and may be interchanged. The semiconductor device structure 100 may include Figure 1 One or more components of the static random access memory unit 10.

[0131] Figures 2 to 62 are perspective views of various stages in the fabrication of a semiconductor device structure 100, according to some embodiments. As shown in FIG2 , the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on a front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a single crystal semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaSbAs), or indium phosphide (InP). In one embodiment, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement purposes. On one side, the insulating layer is an oxygen-containing layer.

[0132] The substrate 101 may include various regions doped with impurities (e.g., dopants having P-type conductivity or N-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for N-type field effect transistors and boron for P-type field effect transistors.

[0133] The semiconductor layer stack 104 includes semiconductor layers formed of different materials and arranged in an alternating pattern to facilitate the formation of nanostructured channels in multi-gate devices, such as nanostructured channel field-effect transistors. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes the alternating arrangement of the first and second semiconductor layers 106, 108. The first and second semiconductor layers 106, 108 are formed of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be formed of silicon, while the second semiconductor layer 108 may be formed of silicon germanium. In some examples, the first semiconductor layer 106 may be formed of silicon germanium, while the second semiconductor layer 108 may be formed of silicon. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials, such as germanium, silicon carbide (SiC), gallium arsenide, gallium phosphide, indium phosphide, indium arsenide (InAs), indium antimonide, gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide, gallium indium phosphide (GaInP), gallium indium arsenic phosphide (GaInAsP), or any combination thereof.

[0134] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the semiconductor layer stack 104 may be epitaxially grown by molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0135] The first semiconductor layer 106 or a portion thereof may form a nanostructured channel of the semiconductor device structure 100 in a later manufacturing stage. As used herein, the term "nanostructured" is intended to refer to any material portion having nanometer-scale (or even micrometer-scale) dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to circular and substantially circular elongated material portions, as well as beam-shaped or bar-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sectional shapes. The nanostructured channel of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructured transistor. A nanostructured transistor may be referred to as a nanosheet transistor, a nanowire transistor, a fully wrapped gate transistor, a multi-bridge channel (MBC) transistor, or any transistor having a gate electrode surrounding a channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 will be discussed further below.

[0136] Each first semiconductor layer 106 may have a thickness ranging between about 5 nm and 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging between about 2 nm and 50 nm. As shown in FIG. 2 , three first semiconductor layers 106 and three second semiconductor layers 108 are staggered for illustrative purposes and are not intended to limit the scope of the patent application to the portions specifically described. It should be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of film layers depends on the number of channels predetermined by the semiconductor device structure 100. In some embodiments, the semiconductor layer stack 104 includes two first semiconductor layers 106. In some embodiments, the semiconductor layer stack 104 includes three first semiconductor layers 106. In some embodiments, the semiconductor layer stack 104 includes four first semiconductor layers 106.

[0137] like Figure 3As shown, a fin structure 112 is formed by a semiconductor layer stack 104. The fin structure 112 may be a semiconductor fin. Each fin structure 112 has an upper portion including a first semiconductor layer 106 and a second semiconductor layer 108, and a well portion 116 formed by the substrate 101. The fin structure 112 may be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104, wherein the patterning uses multiple patterning steps including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process may include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask component including the photoresist layer. In some embodiments, an electron beam (e-beam) lithography process may be used to pattern the photoresist layer to form the mask component. The etching process forms trenches 114 in the unprotected areas through the hard mask layer, the semiconductor layer stack 104, and into the substrate 101, thereby forming a plurality of extended fin structures 112. The trenches 114 extend along the X-direction. The trenches 114 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or a combination thereof.

[0138] like Figure 4As shown, after forming the fin structures 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are buried in the insulating material 118. Then, a planarization step (e.g., chemical mechanical polishing (CMP) and / or etch-back) is performed to expose the tops of the fin structures 112. The insulating material 118 can be formed of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), fluorine-doped silicate glass (FSG), a low-k dielectric material, or any other suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0139] like Figure 5 As shown, the insulating material 118 is etched back to form an isolation region 120. The etching back of the insulating material 118 exposes a portion of the fin structure 112, such as the semiconductor layer stack 104. The etching back of the insulating material 118 exposes the trenches 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process (e.g., a dry etching process, a wet etching process, or a combination thereof). The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108 in contact with the well 116 formed by the substrate 101. In some embodiments, the isolation region 120 is a shallow trench isolation (STI) region.

[0140] like Figure 6As shown, one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structures 130 are formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate structures 130 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers. In some embodiments, although only one sacrificial gate structure 130 is shown, two or more sacrificial gate structures 130 may be arranged along the X direction.

[0141] The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a material primarily composed of silicon oxide. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 may serve as a channel region of the semiconductor device structure 100.

[0142] Figures 7 to 18 According to some embodiments, various stages of manufacturing the semiconductor device structure 100 are along Figure 6 The cross-sectional view is captured by the line segment AA. Figure 7 As shown, a first gate spacer 138 is deposited on the exposed surface of the semiconductor device structure 100. For example, the first gate spacer 138 is deposited on the fin structure 112, the isolation region 120, and the sacrificial gate structure 130. The first gate spacer 138 can be formed of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbide (SiOC), silicon oxycarbonitride, and / or combinations thereof. The first gate spacer 138 can be formed by any suitable process. In some embodiments, the first gate spacer 138 is a compliant film layer formed by a compliant process, such as an atomic layer deposition (ALD) process.

[0143] like Figure 8As shown, a second gate spacer 139 is deposited over the first gate spacer 138. The second gate spacer 139 may include any suitable dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbonitride, or silicon oxycarbide. The second gate spacer 139 may have a thickness in a range of approximately 0.5 nm to 5 nm. The second gate spacer 139 may be formed by any suitable process. In some embodiments, the second gate spacer 139 may be deposited by chemical vapor deposition (CVD), plasma-assisted chemical vapor deposition (PAGE), or electron cyclotron resonance chemical vapor deposition (ECR-CVD).

[0144] like Figure 9 As shown, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed. In some embodiments, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed by an anisotropic etching process. The anisotropic etching process can be a selective etching process that does not substantially affect the mask layer 136, the semiconductor layer stack 104, and the isolation region 120.

[0145] like Figure 10 As shown, the portion of the fin structure 112 not covered by the sacrificial gate structure 130, the first gate spacer 138, and the second gate spacer 139 is etched back to the level of the top surface of the isolation region 120, above its top surface, or below its top surface. The etch back of the portion of the fin structure 112 can be completed by an etching process. The etching process can be dry etching (such as reactive ion etching, neutral beam etching (NBE), or other similar methods) or wet etching (such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant). The well portion 116 is exposed on opposite sides of the sacrificial gate structure 130, as shown in FIG. Figure 10 shown.

[0146] like Figure 11As shown, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed along the X-direction. Removing the edge portions of the second semiconductor layer 108 forms a cavity. In some embodiments, portions of the second semiconductor layer 108 are removed using a selective wet etching process. When the second semiconductor layer 108 is formed of silicon germanium and the first semiconductor layer 106 is formed of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant such as, but not limited to, a solution of ammonium hydroxide, tetramethylammonium hydroxide, ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH).

[0147] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the recess to form dielectric spacers 144. Dielectric spacers 144 can be formed of a low-k dielectric material, such as silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. Dielectric spacers 144 can be formed by first forming a compliant dielectric layer using a compliant deposition process (e.g., atomic layer deposition), followed by an anisotropic etching process to remove portions of the compliant dielectric layer outside of dielectric spacers 144. During the anisotropic etching process, dielectric spacers 144 are protected by first semiconductor layer 106. The remaining second semiconductor layer 108 is covered between dielectric spacers 144 along the X-direction.

[0148] like Figure 12 As shown, a first semiconductor material 150 is formed on the exposed well portion 116. In some embodiments, the first semiconductor material 150 includes undoped silicon or undoped silicon germanium. The first semiconductor material 150 can first be formed on a semiconductor surface (such as on the exposed well portion 116 and on the first semiconductor layer 106) by epitaxial growth. A subsequent etching process is performed to remove the portion of the first semiconductor material 150 formed on the first semiconductor layer 106. As a result of the etching process, the portion of the first semiconductor material 150 formed on the exposed well portion 116 can form a recessed top surface. In some embodiments, the first semiconductor material 150 has a thickness in the Z direction ranging from approximately 5 nm to 50 nm.

[0149] Then, if Figure 13As shown, a dielectric layer 152 is formed on the first semiconductor material 150. The dielectric layer 152 can be formed by first forming a dielectric layer on the exposed surface of the semiconductor device structure 100, and then performing one or more etching processes to remove portions of the dielectric layer other than the dielectric layer 152. A mask layer (not shown) (such as a bottom antireflective coating (BARC) layer) can be used to assist in removing portions of the dielectric layer. The dielectric layer 152 may include any suitable dielectric material. In some embodiments, the dielectric layer 152 includes silicon nitride. The dielectric layer 152 may be formed by any suitable process. In some embodiments, the dielectric layer 152 is formed by chemical vapor deposition. Next, the second semiconductor material 154 is formed from the first semiconductor layer 106. The second semiconductor material 154 may be formed from one or more layers of silicon, silicon phosphide (SiP), silicon carbide, silicon arsenide (SiAs), silicon antimonide (SiSb), or silicon phosphocarbide (SiCP) for an N-type channel field effect transistor, or from one or more layers of silicon, silicon germanium, or germanium for a P-type channel field effect transistor. For a P-type channel field effect transistor, a P-type dopant (e.g., boron) may be included in the second semiconductor material 154. For an N-type channel field effect transistor, an N-type dopant (e.g., phosphorus (P) or arsenic (As)) may be included in the second semiconductor material 154. In some embodiments, the dopant concentration of the second semiconductor material 154 may be approximately 1×10 19 cm -3 to 2×10 21 cm -3 The second semiconductor material 154 may be formed by epitaxial growth using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. In some embodiments, as Figure 13 As shown, the second semiconductor material 154 is a continuous film layer above the first semiconductor layer 106 and the dielectric spacer 144. In some embodiments, the second semiconductor material 154 is selectively formed on semiconductor materials (such as the first semiconductor layer 106) and not formed on dielectric materials (such as the dielectric layer 152 and the dielectric spacer 144). In some embodiments, the second semiconductor material 154 includes facets that correspond to the crystal planes of the material used in the first semiconductor layer 106.

[0150] Then, if Figure 13As shown, a third semiconductor material 156 is formed from the second semiconductor material 154. The third semiconductor material 156 can be formed by an epitaxial growth method using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy. The third semiconductor material 156 can be formed with one or more film layers of silicon, silicon phosphide, silicon carbide, or silicon carbon phosphide for an N-type channel field effect transistor, or with one or more film layers of silicon, silicon germanium, or germanium for a P-type channel field effect transistor. For a P-type channel field effect transistor, a P-type dopant (such as boron) can be included in the third semiconductor material 156. For an N-type channel field effect transistor, an N-type dopant (such as phosphorus or arsenic) can be included in the third semiconductor material 156. In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 can include the same semiconductor material but have different dopant concentrations. The dopant concentration of the third semiconductor material 156 can be substantially greater than the dopant concentration of the second semiconductor material 154. In some embodiments, the dopant concentration of the third semiconductor material 156 can be approximately 5×10 19 cm -3 to 4×10 21 cm -3 The third semiconductor material 156 may be epitaxially grown from the second semiconductor material 154. The faceting of the second semiconductor material 154 may improve the quality of the third semiconductor material 156. In some embodiments, the dielectric layer 152 is not present, and the third semiconductor material 156 is grown from the first semiconductor material 150 and the second semiconductor material 154.

[0151] In some embodiments, a capping layer (not shown) may be formed on the third semiconductor material 156. The capping layer may include a semiconductor material. In some embodiments, the material of the capping layer is the same as that of the third semiconductor material 156. The capping layer may be epitaxially grown from the third semiconductor material 156.

[0152] In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 may be doped in situ during growth. If the dopant concentration of the second semiconductor material 154 and the third semiconductor material 156 is greater than the respective ranges mentioned above, the quality of the second semiconductor material 154 and the third semiconductor material 156 may be negatively affected. Therefore, subsequent processes may be performed to increase the dopant concentration to reduce electrical contact resistance. In other words, during the formation of the second semiconductor material 154 and the third semiconductor material 156 (e.g., epitaxial deposition with in-situ doping), if the dopant concentration is greater than the respective ranges mentioned above, the quality of the second semiconductor material 154 and the third semiconductor material 156 may be negatively affected. After the second semiconductor material 154 and the third semiconductor material 156 are formed, the dopant concentration of the second semiconductor material 154 and the third semiconductor material 156 may be increased to a level above the respective ranges mentioned above to reduce the electrical contact resistance without negatively affecting the quality of the second semiconductor material 154 and the third semiconductor material 156.

[0153] The second semiconductor material 154 and the third semiconductor material 156 may together form a source / drain (S / D) region 182. In the present disclosure, source region and drain region may be used interchangeably, and their structures are substantially the same. In addition, source / drain regions may refer to sources or drains individually or collectively, depending on the context. In some embodiments, one or more mask layers may be used to form P-type source / drain regions and N-type source / drain regions, respectively. In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 are crystalline semiconductor materials. For example, as shown in FIG. Figure 19 Specifically, a first source / drain region 182a is formed from a first base portion (e.g., above the first semiconductor material 150 and dielectric layer 152 on the first recessed portion of the fin structure 112). The first source / drain region 182a may be an N-type epitaxial material. Continuing this example, a second source / drain region 182b is formed from a second base portion (e.g., above the second recessed portion of the fin structure 112, separated from the first recessed portion by the isolation region 120). The second source / drain region 182b may be a P-type epitaxial material.

[0154] Then, if Figure 13As shown, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the second gate spacer 139, the isolation region 120, and the third semiconductor material 156 (or the capping layer, if present). The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride (CN), silicon oxide, silicon oxycarbide, other similar materials, or a combination thereof, and may be formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, atomic layer deposition, or any suitable deposition technique. In some embodiments, the CESL 162 is a single film layer, such as Figure 13 As shown. In some embodiments, the contact etch stop layer 162 includes two or more film layers. Next, an interlayer dielectric (ILD) layer 164 is formed on the contact etch stop layer 162. The material of the interlayer dielectric layer 164 may include a compound containing silicon, oxygen, carbon, and / or hydrogen (such as silicon oxide, silicon carbooxyhidride (SiCOH), or silicon oxycarbide). Organic materials such as polymers may also be used for the interlayer dielectric layer 164. The interlayer dielectric layer 164 may be deposited by a plasma-assisted chemical vapor deposition process or other suitable deposition techniques. In some embodiments, after forming the interlayer dielectric layer 164, the semiconductor device structure 100 may be subjected to a thermal process to anneal the interlayer dielectric layer 164.

[0155] After forming the interlayer dielectric layer 164, the semiconductor device structure 100 is planarized (eg, chemical mechanical polishing) until the sacrificial gate electrode layer 134 is exposed. Figure 13 shown.

[0156] Then, if Figure 14As shown, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. The removal of the sacrificial gate structure 130 and the second semiconductor layer 108 forms an opening between the first gate spacers 138 and between the first semiconductor layer 106. During the removal process, the interlayer dielectric layer 164 protects the third semiconductor material 156. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process (e.g., dry etching, wet etching, or a combination thereof), followed by the removal of the sacrificial gate dielectric layer 132 by any suitable process (e.g., dry etching, wet etching, or a combination thereof). In some embodiments, a wet etchant such as a tetramethylammonium hydroxide solution can be used to selectively remove the sacrificial gate electrode layer 134 without removing the first gate spacers 138, the interlayer dielectric layer 164, and the contact etch stop layer 162.

[0157] The second semiconductor layer 108 may be removed using a selective wet etching process. When the second semiconductor layer 108 is formed of silicon germanium and the first semiconductor layer 106 is formed of silicon, the chemistry used in the selective wet etching process removes the silicon germanium without substantially affecting the silicon and the dielectric material of the first gate spacer 138 and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 may be removed using a wet etchant such as, but not limited to, hydrogen fluoride (HF), nitric acid (HNO3), hydrochloric acid (HCl), or phosphoric acid (H3PO4).

[0158] like Figure 15 As shown, after forming the nanostructured channel (e.g., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed around the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed portion of the first semiconductor layer 106, and one or more work function layers (not shown) are formed between the gate dielectric layer 170 and the gate electrode layer 172. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or a high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include hafnium oxide (HfO2), hafnium silicate (HfSiO xThe gate dielectric layer 170 may be formed by chemical vapor deposition, atomic layer deposition, or other suitable deposition techniques. The work function layer may include polysilicon, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), molybdenum (Mo), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, and other suitable materials. The gate electrode layer 172 may include one or more layers of a conductive material, such as platinum (Pt), palladium (Pd), tantalum, ytterbium (Yb), aluminum, silver (Ag), titanium, ruthenium (Ru), molybdenum, chromium (Cr), tungsten, copper, similar materials, and / or combinations thereof. The gate electrode layer 172 may be formed by chemical vapor deposition, atomic layer deposition, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited on the upper surface of the interlayer dielectric layer 164. The gate dielectric layer 170 and the gate electrode layer 172 formed on the interlayer dielectric layer 164 are then removed by, for example, chemical mechanical polishing until the top surface of the interlayer dielectric layer 164 is exposed.

[0159] It should be understood that the semiconductor device structure 100 may undergo further processes, such as a cut metal gate (CMG) process and / or a continuous poly on diffusion edge (CPODE) process. The cut metal gate process separates the gate electrode layer 172 into multiple segments that can be independently controlled. The CPODE process forms isolation between devices.

[0160] like Figure 16 As shown, an etch stop layer (ESL) 166 and a second interlayer dielectric layer 168 are formed on the interlayer dielectric layer 164 and the gate electrode layer 172. The material of the etch stop layer 166 can be the same as that of the contact etch stop layer 162 and can be formed by the same process as that of the contact etch stop layer 162. The material of the second interlayer dielectric layer 168 can be the same as that of the interlayer dielectric layer 164 and can be formed by the same process as that of the interlayer dielectric layer 164.

[0161] Then, if Figure 17 As shown, an opening 180 is formed in the second interlayer dielectric layer 168, the etch stop layer 166, the interlayer dielectric layer 164, and the contact etch stop layer 162 to expose the third semiconductor material 156. In some embodiments, portions of the interlayer dielectric layer 164 and the contact etch stop layer 162 located above the third semiconductor material 156 may be removed. In some embodiments, a capping layer (not shown) and a portion of the third semiconductor material 156 may also be removed. The opening 180 may be formed by an etching process, such as a dry etching process, a wet etching process, or a combination thereof. A patterned mask (not shown) may be formed on the second interlayer dielectric layer 168, and the pattern of the patterned mask may be transferred to the second interlayer dielectric layer 168, the etch stop layer 166, the interlayer dielectric layer 164, and the contact etch stop layer 162.

[0162] like Figure 17 As shown, semiconductor device structure 100 includes an interfacial layer 167 formed on first semiconductor layer 106, and a work function layer 169 formed between gate dielectric layer 170 and gate electrode layer 172. Furthermore, semiconductor device structure 100 includes a dielectric liner 196 and a dielectric material 198. Dielectric liner 196 and dielectric material 198 may be isolation structures formed by a polymer edge process on a continuous diffusion region. In some embodiments, dielectric material 198 is formed from the same material as etch stop layer 166.

[0163] like Figure 18As shown, a liner 184 is formed on the vertical surfaces of the second interlayer dielectric layer 168, the etch stop layer 166, and the first gate spacer 138. The liner 184 can include any suitable material. In some embodiments, the liner 184 is a nitride layer, such as a silicon nitride layer. In some embodiments, the material of the liner 184 is the same as the material of the etch stop layer 166. The liner 184 can be formed by first forming a dielectric layer on the exposed surface of the semiconductor device structure 100, and then performing an anisotropic etching process to remove the portion of the dielectric layer formed on the horizontal surface of the semiconductor device structure 100. For example, the anisotropic etching process is used to remove the portion of the dielectric layer formed on the second interlayer dielectric layer 168 and the third semiconductor material 156. The liner 184 protects the second interlayer dielectric layer 168 during subsequent processing.

[0164] Figures 19 to 25 According to some embodiments, various stages of manufacturing the semiconductor device structure 100 are along Figure 6 Schematic cross-sectional view captured by line segment BB. Figure 19 The semiconductor device structure 100 is shown in FIG. Figure 18 The semiconductor device structure 100 is shown in the same manufacturing stage. In some embodiments, as Figure 19 As shown, the opening 180 exposes both the first source / drain region 182a (which may be an N-type epitaxial material) and the second source / drain region 182b (which may be a P-type epitaxial material). In some embodiments, the first source / drain region 182a is formed on the first well portion 116a. In some embodiments, the second source / drain region 182b is formed on the second well portion 116b.

[0165] like Figure 20 As shown, a mask 186 is formed on the exposed portion of the first source / drain region 182a. The mask 186 can be formed by any suitable process, such as a photolithography process. In some embodiments, the photolithography process can include forming a photoresist layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask including the photoresist layer. In some embodiments, an electron beam lithography process can be used to pattern the photoresist layer to form the mask.

[0166] In some embodiments, as Figure 20As shown, mask 186 covers the entire exposed portion of first source / drain region 182a, while mask 186 does not cover any exposed portion of second source / drain region 182b. The boundary of mask 186 is located between first source / drain region 182a and second source / drain region 182b. As shown, mask 186 extends from second interlayer dielectric layer 168 beyond first source / drain region 182a to the boundary between first source / drain region 182a and second source / drain region 182b. In other embodiments, mask 186 may extend past first source / drain region 182a. In some embodiments, mask 186 completely covers the exposed portion of first source / drain region 182a, thereby protecting first source / drain region 182a from subsequent implantation processes.

[0167] In some embodiments, in order to reduce the electrical contact resistance, one or more processes may be performed to increase the dopant concentration in the third semiconductor material 156 and / or the second semiconductor material 154. Figure 21 As shown, an implantation process is performed to implant dopants into the second source / drain region 182b to form a doped region 188 in the second source / drain region 182b. In some embodiments, the dopant is a P-type dopant, such as boron. In some embodiments, the boron isotope composition obtained by the implantation process includes 100% 11 B, is excellent for the boron isotope composition of the general P-type epitaxial source / drain region. 10 B: 11 The ratio of B is close to 20%:80%. The implantation process can have an implantation energy ranging from about 0.3keV to 60keV, greater than about 1×10 13 cm -2 The implantation process may include a doping dose of 100 nm and a process temperature ranging from approximately -150°C to 500°C. In some embodiments, the implantation process forms a doped region 188 in the second source / drain region 182b while leaving the first source / drain region 182a undoped. Mask 186 prevents doping in the protected area beneath mask 186 while doping the unprotected area outside the mask 186. In other words, doped region 188 may correspond to the pattern of mask 186. The depth and concentration of doped region 188 may be controlled, as described in detail below.

[0168] like Figure 22 As shown, the mask 186 is removed. The mask 186 can be removed by any suitable process. In some embodiments, the mask 186 can be removed by a wet stripping process or a plasma ashing process. The wet stripping process or the plasma ashing process can be used to selectively remove the mask 186 without substantially affecting the second interlayer dielectric layer 168, the first source / drain region 182a, the second source / drain region 182b, and the liner 184.

[0169] like Figure 23 As shown, a silicide layer 192 is formed on the exposed portions of the first source / drain region 182a and the second source / drain region 182b. The silicide layer 192 can be formed by any suitable process. In some embodiments, a metal layer (not shown) is first formed on the semiconductor device structure 100. The metal layer may include titanium, nickel, ruthenium, cobalt, tungsten, or other suitable metals. In some embodiments, the metal layer has a multilayer structure. The multilayer structure may include a metal layer and a metal nitride layer or a metal oxide layer. The metal layer can be deposited by any suitable process, such as atomic layer deposition, chemical vapor deposition, or physical vapor deposition (PVD). After the metal layer is deposited, an annealing process is performed to react the third semiconductor material 156 with the metal layer, thereby forming the silicide layer 192. The silicide layer 192 may include any suitable material, such as nickel silicide, titanium silicide (TiSi), cobalt silicide, ruthenium silicide (RuSi), or tungsten silicide (WSi).

[0170] like Figure 24 As shown, a conductive contact 194 is deposited in the opening 180. The conductive contact 194 is electrically connected to the first source / drain region 182a and the second source / drain region 182b. The conductive contact 194 can be electrically conductive and can include one or more materials including ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, or tantalum nitride. The conductive contact 194 can be formed by any suitable method, such as electrochemical plating (ECP) or physical vapor deposition. Figure 25 As shown, a planarization operation is performed, such as a chemical mechanical polishing method.

[0171] Figures 26 to 30 According to other embodiments, various alternative stages of fabricating a semiconductor device structure are described along the Figure 6 Schematic cross-sectional view captured by line segment BB. Figures 26 to 30 May include Figures 20 to 25 The aspects described are not limited. Figure 26 correspond Figure 20 However, as Figure 26 As shown, the exposed portion of the first source / drain region 182a remains exposed and unprotected during the subsequent implantation process, rather than forming a mask over the exposed portion of the first source / drain region 182a. Without the mask, either the exposed portion of the first source / drain region 182a or the second source / drain region 182b is not covered or protected from the implantation.

[0172] Figure 27 correspond Figure 21 However, as Figure 27 As shown, since the implantation process is performed without a mask on the first source / drain region 182a, dopants are implanted in both the exposed portion of the first source / drain region 182a and the exposed portion of the second source / drain region 182b to form a first doped region 188a and a second doped region 188b, respectively. In some embodiments, the first doped region 188a and the second doped region 188b may receive equivalent doping by the implantation process. In some embodiments, the first doped region 188a includes a P-type dopant in an N-type semiconductor material, and the second doped region 188b includes a P-type dopant in a P-type semiconductor material. As described above, the dopant is a P-type dopant, which can reduce the contact resistance of the P-type second doped region 188b and can negatively affect the N-type first source / drain region 182a. In some embodiments, the first source / drain region 182a is Figure 1 The SRAM cell 10 is shown as a portion of the pull-down transistor PDx, and the second source / drain region 182b is Figure 1 A portion of the pull-up transistor PUx of the SRAM cell 10 is shown. In some embodiments, the advantage of reduced contact resistance of the pull-up transistor PUx outweighs the disadvantage of negatively impacting the pull-down transistor PDx. In other words, in some embodiments, reducing the contact resistance of the pull-up transistor PUx is more important, while slightly increasing the contact resistance of the pull-down transistor PDx does not materially affect the operation of the SRAM cell 10. Therefore, in some embodiments, mask 186 is not formed, which has the advantage of reducing process time and cost.

[0173] Figures 28 to 30 Corresponding to Figures 23 to 25 , including forming a silicide layer 192, forming a conductive contact 194, and a planarization operation. Figure 30 The final structure shown differs from that shown in FIG. 1 by the presence of the first doped region 188a. Figure 25 .

[0174] Figures 31 to 35 According to other embodiments, various alternative stages of fabricating a semiconductor device structure are described along the Figure 6 Schematic cross-sectional view captured by line segment BB. Figures 31 to 35 May include Figures 20 to 25 The aspects described are not limited. Figure 31 correspond Figure 20 and Figure 21 However, as Figure 31As shown, in addition to covering the entire exposed portion of the first source / drain region 182a, a mask 186 is formed on a portion of the exposed portion of the second source / drain region 182b. Thus, only a portion of the exposed portion of the second source / drain region 182b is not covered by the mask 186 and becomes unprotected. In some embodiments, to ensure that the first source / drain region 182a is covered by the mask 186, a portion of the second source / drain region 182b is also covered by the mask 186. The boundary of the mask 186 is located on the second source / drain region 182b. In some embodiments, the position of the boundary is such that the mask 186 covers less than 90% of the total width (along the Y direction) of the exposed portion of the second source / drain region 182b, such as less than 70%, 50%, 30%, or 10% of the total width. As shown, the mask 186 extends from the second interlayer dielectric layer 168 beyond the first source / drain region 182a to the boundary on the second source / drain region 182b. In some embodiments, the mask 186 completely covers the exposed portion of the first source / drain region 182a and a portion of the second source / drain region 182b, thereby protecting the first source / drain region 182a and a portion of the second source / drain region 182b from being affected by the implantation. Figure 31 As shown, because mask 186 is expanded to cover a portion of the exposed portion of second source / drain region 182b, the width of doped region 188 is reduced. In this embodiment, the smaller doped region 188 reduces contact resistance, while the first source / drain region 182a is not doped by dopants during the implantation process. In other words, the risk of negatively impacting the first source / drain region 182a is reduced, while the advantage of reducing the contact resistance of the second source / drain region 182b is substantially maintained. The depth and concentration of doped region 188 can be controlled, as described in detail below.

[0175] Figures 32 to 35 Corresponding to Figures 22 to 25 , including removing the mask 186, forming a silicide layer 192, forming a conductive contact 194, and a planarization operation. Figure 35 The final structure shown differs from the Figure 25 .

[0176] Figures 36 to 40 According to other embodiments, various alternative stages of fabricating a semiconductor device structure are described along the Figure 6 Schematic cross-sectional view captured by line segment BB. Figures 36 to 40 May include Figures 20 to 25 The aspects described are not limited. Figure 36 correspond Figure 20 and Figure 21 However, as Figure 36As shown, mask 186 is formed only over a portion of the exposed portion of first source / drain region 182a. Thus, a portion of the exposed portion of first source / drain region 182a is not covered by mask 186 and remains unprotected. The boundary of mask 186 is located above first source / drain region 182a. In some embodiments, to ensure that second source / drain region 182b is not covered by mask 186, a portion of first source / drain region 182a is also exposed. In some embodiments, the boundary is positioned such that mask 186 covers greater than 10% of the total width of the exposed portion of first source / drain region 182a, such as greater than 30%, 50%, 70%, or 90% of the total width. As shown, mask 186 extends from second interlayer dielectric layer 168 to a boundary above first source / drain region 182a. The mask 186 partially covers the exposed portion of the first source / drain region 182a, thereby protecting only a portion of the first source / drain region 182a from being affected by the implantation. Figure 36 In comparison with Figure 27 Without the mask, the width of the first doped region 188a is relatively small because the mask 186 extends to cover a portion of the exposed portion of the first source / drain region 182a. In this embodiment, the smaller first doped region 188a does not substantially affect the operation of the SRAM cell 10 and can substantially reduce the contact resistance of the second source / drain region 182b (which is part of the pull-up transistor PUx). The depth and concentration of the first doped region 188a and the second doped region 188b can be controlled, as described in detail below.

[0177] Figures 37 to 40 Corresponding to Figures 22 to 25 , including removing the mask 186, forming a silicide layer 192, forming a conductive contact 194, and a planarization operation. Figure 40 The final structure shown is different from the Figure 25 .

[0178] Figure 41 and Figure 42 According to some embodiments, the semiconductor device structure 100 is formed after the conductive contact 194 is formed (eg, referring to Figure 25 ) Along Figure 6 The cross-sectional view and top view taken along line segment AA are shown. Figure 42 As shown, the gate electrode layer 172, the first source / drain region 182a, the second source / drain region 182b, the conductive contact 194, and the implantation boundary 190 (inner dashed line) are depicted. In some embodiments, the mask 186 (e.g., referring to FIG. Figure 21 ) defines the implant boundary 190 and corresponds to the unprotected and doped region outside the area of the mask 186, as previously described. Figure 42As shown, the implantation boundary 190 corresponds to the P-type active region (e.g., the two adjacent second source / drain regions 182b) and extends into the surrounding inactive region (e.g., the isolation region 120) in the direction of the N-type active region (e.g., the first source / drain region 182a) to approximately the midpoint between the P-type active region and the N-type active region. Thus, the implantation boundary 190 partially extends across the interval s1 between the first source / drain region 182a and the second source / drain region 182b. In some embodiments, the implantation boundary 190 in the X direction is not continuous, such as Figure 42 As shown. In addition, exemplary locations of the pull-up transistor PU and the pull-down transistor PD are identified. As previously mentioned, the first source / drain region 182a can be N-type, while the second source / drain region 182b can be P-type. Figure 42 As shown, in some embodiments, the width dn1 of the first source / drain region 182a is greater than the width dp1 of the second source / drain region 182b. In some embodiments, the ratio of the width dn1 to the width dp1 is in a range between about 1.5 and 2. Figure 42 As shown, a ratio of width wp1 to width dp1 of implant boundary 190 is in a range between approximately 6 and 15. In some embodiments, width wp1 is equal to the sum of twice the spacing s1 between first source / drain region 182a and second source / drain region 182b and twice the width dp1 of second source / drain region 182b.

[0179] Figure 43 and Figure 44 According to some embodiments, Figure 42 FIG. 1 is a top view of an alternative high density and high current cell of the semiconductor device structure 100. Figure 43 As shown, the width dn2 of the first source / drain region 182a is greater than the width dp2 of the second source / drain region 182b. For example, the width dn2 of the first source / drain region 182a is approximately equal to the width dp2 of the second source / drain region 182b. As used herein, the term "approximately" may mean ±5%. In addition, the width dp2 is approximately equal to the width dp1. Figure 43 As shown, a ratio of width wp2 to width dp2 of implant boundary 190 is in a range between approximately 6 and 15.

[0180] like Figure 44 As shown, the width dn3 of the first source / drain region 182a is greater than the width dp3 of the second source / drain region 182b. In some embodiments, the ratio of the width dn3 to the width dp3 is in the range of about 2 to 4. In addition, the width dp3 is approximately equal to the width dp1. Figure 44 As shown, a ratio of width wp3 to width dp3 of implant boundary 190 is in a range between approximately 6 and 15.

[0181] Figures 45 to 47 According to some embodiments, Figure 42 FIG. 1 is a top view of an alternative implant boundary of the semiconductor device structure 100. Figure 45 As shown, implant boundary 190a corresponds only to the P-type active region (e.g., the two adjacent second source / drain regions 182b) and does not extend into the surrounding inactive region (e.g., the isolation region 120) in the direction of the N-type active region (e.g., the first source / drain region 182a). For example, in the Y direction, implant boundary 190a is aligned with the opposite boundary of the second source / drain region 182b. In the X direction, implant boundary 190a is not continuous.

[0182] like Figure 46 As shown, implant boundary 190b corresponds to the P-type active region (e.g., the two adjacent second source / drain regions 182b) and extends into the surrounding inactive region (e.g., the isolation region 120) in the direction of the N-type active region (e.g., the first source / drain region 182a), beyond the midpoint toward the outer boundary of the N-type active region. For example, in the Y direction, implant boundary 190b is aligned with the outer boundary of the first source / drain region 182a. In the X direction, implant boundary 190b is not continuous.

[0183] like Figure 47 As shown, the implantation boundary 190c corresponds to the P-type active region (e.g., two adjacent second source / drain regions 182b) and the N-type active region (e.g., the first source / drain region 182a on either side of the P-type active region). For example, in the Y direction, the implantation boundary 190c extends completely over the first source / drain region 182a. In the X direction, the implantation boundary 190c is not continuous. This embodiment corresponds to Figures 26 to 30 The embodiment shown.

[0184] Figures 48 to 50 According to some embodiments, various stages of the back-end process for manufacturing the semiconductor device structure 100 are as follows Figure 6 The cross-sectional view is captured by the line segment AA. Figure 48 As shown, after forming the interconnect structure on the front side, the semiconductor device structure 100 is flipped and subjected to a back-end thinning process. Figure 48 and Figure 41 The semiconductor device structure 100 is similar, except that the semiconductor device structure 100 is inverted. In some embodiments, a carrier wafer (not shown) may be bonded to the front side of the semiconductor device structure 100, and the semiconductor device structure 100 may be flipped so that the back side 202 (or "backside surface") of the substrate 101 faces upward for back-end processing. Figure 49 As shown, a planarization or grinding operation (eg, a chemical mechanical polishing process) may be used to thin the back side 202 of the substrate 101. After thinning the substrate 101, the back side 202 includes the substrate 101 and the isolation region 120.

[0185] After thinning the substrate 101, one or more backside source / drain contact openings are formed. Figure 50 As shown, an opening 204 is formed in the substrate 101, the first semiconductor material 150, and the dielectric layer 152 to expose the second source / drain region 182b. The opening 204 can be formed by an etching process, such as a dry etching process, a wet etching process, or a combination thereof. A patterned mask (not shown) can be formed on the substrate 101, and the pattern of the patterned mask can be transferred to the first semiconductor material 150 and the dielectric layer 152.

[0186] Then, if Figure 50 As shown, a liner 206 is formed over the substrate 101, the first semiconductor material 150, the dielectric layer 152, and the second source / drain regions 182b. The liner 206 can comprise any suitable material. In some embodiments, the liner 206 is a nitride layer, such as a silicon nitride layer. In some embodiments, the material of the liner 206 is the same as the material of the etch stop layer 166. The liner 206 can be formed by first forming a dielectric layer on the exposed surface of the semiconductor device structure 100, and then performing an anisotropic etching process to remove the portion of the dielectric layer formed on the horizontal surface of the semiconductor device structure 100. For example, the anisotropic etching process is used to remove the portion of the dielectric layer formed on the second source / drain regions 182b.

[0187] Then, if Figure 50 As shown, a second implantation process is performed to implant dopants to form doped regions 208 in the second source / drain regions 182b. In some embodiments, the dopant is a P-type dopant, such as boron. Performing implantation processes in the second source / drain regions 182b from both the front side and the back side allows fine-tuning of the dopant concentration across a greater depth and improves pull-up device performance relative to a specific silicon channel and obtains SRAM read margin. The second implantation process may include Figure 21 The aspect of the implantation process is not limited. The depth and concentration of the doped region 208 can be controlled, as described in detail below. After the second implantation process, a silicide layer can be formed on the exposed portions of the second source / drain regions 182b. The silicide layer can be formed by any suitable process, including aspects of the other silicide processes described herein.

[0188] Then, if Figure 50As shown, a conductive contact 210 is formed in the opening 204. The conductive contact 210 is electrically connected to the second source / drain region 182b. The conductive contact 210 can be electrically conductive and may include one or more materials including ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, or tantalum nitride. The conductive contact 210 can be formed by any suitable method, such as electrochemical plating or physical vapor deposition. After forming the conductive contact 210, a planarization operation, such as a chemical mechanical polishing process, can be performed. After the planarization operation, a backside interconnect structure can be formed.

[0189] Figure 51 According to some embodiments, another stage of the semiconductor device structure 100 is along Figure 6 For example, Figure 51 The semiconductor device structure 100 may be depicted along Figure 42 The portion of line segment CC includes a first node N1, a Vdd node, and a second node N2. In some embodiments, the Vdd node may be Figure 1 In some embodiments, Figure 50 The backside implantation process may be performed at the Vdd node (power connection) instead of at the first node N1 and the second node N2 (signal connection). Figure 51 As shown, after the back-end process, the semiconductor device structure 100 is flipped back to illustrate the corresponding Figure 41 The direction of . Figure 51 As shown, a doped region 188 toward the front side and a doped region 208 closer to the back side are formed at different depths in the second source / drain region 182b. In some implementations, the doped region 188 and the doped region 208 overlap (e.g., at least portions of the doped regions merge with each other). In some embodiments, the depth d1 of the doped region 188 is in a range between approximately 5 nm and 25 nm (e.g., measured from the top 212 to the bottom 214 of the doped region 188). Figure 51 As shown, the top 212 of the doped region 188 can be aligned with the top surface of the first semiconductor layer 106a closest to the front side. However, in some embodiments, the top 212 of the doped region 188 can be above or below the top surface of the first semiconductor layer 106a. In some embodiments, the bottom 214 of the doped region 188 can be located at a level between the top surface and the bottom surface of the second semiconductor layer 106b below the first semiconductor layer 106a. In some embodiments, the doped region 188 covers at least two semiconductor slices, and the depth can be fine-tuned as the number of slices changes. In some embodiments, the depth d2 of the doped region 208 is in a range between approximately 5 nm and 25 nm (e.g., measured from the bottom 216 to the top 218 of the doped region 208). As Figure 51As shown, the bottom 216 of the doped region 208 can be aligned with the bottom surface of the third semiconductor layer 106 c closest to the back side 202. However, in some embodiments, the bottom 216 of the doped region 208 can be above or below the bottom surface of the third semiconductor layer 106 c. In some embodiments, the top 218 of the doped region 208 can be located at a level between the second semiconductor layer 106 b and the third semiconductor layer 106 c. In some embodiments, the dopant can have a concentration gradient from the third semiconductor material 156 to the second semiconductor material 154, which can achieve improved device performance. In some embodiments, implant dose separation can be used to fine-tune the pass gate / pull-up threshold voltage (Vt) balance to improve SRAM margin.

[0190] In some embodiments, it is advantageous to have a target concentration range for the dopant in the doped region 188, which is a measure of the change from the threshold voltage to the drain voltage, with respect to balancing the contact resistance against drain-induced barrier loading (DIBL). For example, if the doping concentration is greater than the target range, even if the contact resistance is improved, the drain-induced barrier loading is negatively affected. The implanted doping concentration depends on the depth (e.g., forming a gradient along the depth d1). Similarly, the implantation conditions (e.g., energy, dose, etc.) can be varied, depending on the depth range being treated. For example, in order to implant dopants in a shallow region starting at the top 212 of the doped region 188 (e.g., from line segment A to line segment B), the implantation energy can be in the range between about 0.6 keV and 1 keV, and the implantation dose can be in the range of about 1×10 15 cm -2 and 8×10 15 cm -2 Continuing with this example, to implant dopants in a deeper region adjacent to and below the shallow region (e.g., from line segment B to line segment C), a higher implantation energy, such as between approximately 1 keV and 1.3 keV, is required, while the implantation dose can remain the same as before. In some embodiments, it may be advantageous to have a target implantation depth, which can be represented by a projected range (Rp), which is the average depth of the implanted ions. Figure 52 The figure shows the test results of channel resistance (Rch) and drain induced barrier load at different implantation depths (extending to line segment A, line segment B, or line segment C), with the predicted range from higher to lower values being marked, according to some embodiments. Figure 52 In this case, lower channel resistance (meaning lower resistance) and lower drain-induced barrier loading values are desirable. Figure 52As shown, the implant depth near segment B represents the sweet spot for balancing channel resistance and drain-induced barrier loading. For example, at implant depths near segment B, there is a moderate reduction in channel resistance with a minimal impact on drain-induced barrier loading. In contrast, due to dopant diffusion effects between the source / drain regions and the channel, the impact of drain-induced barrier loading is negative at implant depths near segment A, while the improvement in channel resistance is minimal at implant depths near segment C. Results achievable through the implant process described herein include an increase in threshold voltage of 15% or more, a reduction in channel resistance of 13 ohm-μm or more, a reduction in prediction range of 8 ohm-μm or more, and a reduction in standard deviation of 2 mV or more.

[0191] In some embodiments, due to the improved pull-up performance of the P-type metal oxide semiconductor (PMOS) during the implantation process described herein, the maximum voltage at the wafer level can be improved by 50 mV to 150 mV. In some embodiments, the average increase in maximum voltage after implantation is approximately 50 mV. In some embodiments, the average increase in maximum voltage after implantation is approximately 150 mV.

[0192] Embodiments of the present disclosure provide a semiconductor device structure and method for forming the same. In some embodiments, an implantation process is performed to implant dopants in the source / drain regions to achieve lower contact resistance during source / drain formation, thereby improving pull-up transistor performance and increasing each of standard deviation, static random access memory read margin, and maximum voltage. The embodiments of the present disclosure achieve the aforementioned specific advantages.

[0193] A method for forming a semiconductor device structure includes: forming a first semiconductor fin and a second semiconductor fin on the front side of a substrate; removing portions of the first semiconductor fin and the second semiconductor fin to expose a first base portion and a second base portion, respectively; forming a first source / drain region on the first base portion, wherein the first source / drain region includes an N-type epitaxial material; forming a second source / drain region on the second base portion, wherein the second source / drain region includes a P-type epitaxial material; depositing a dielectric material on the first source / drain region and the second source / drain region; forming an opening in the dielectric material to expose a portion of the first source / drain region and a portion of the second source / drain region; forming a mask on the exposed portion of the first source / drain region; performing an implantation process to implant dopants in the second source / drain region; removing the mask; and depositing a conductive contact electrically connected to the first source / drain region and the second source / drain region.

[0194] In some embodiments, the dopant is a P-type dopant. In some embodiments, the dopant is boron. In some embodiments, a mask is formed on a portion of the exposed portion of the second source / drain region. In some embodiments, the method of forming a semiconductor device structure further includes forming a first silicide layer and a second silicide layer on the first source / drain region and the second source / drain region, respectively, before depositing the conductive contact. In some embodiments, the method of forming a semiconductor device structure further includes depositing a contact etch stop layer on the first source / drain region and the second source / drain region, and depositing a dielectric material on the contact etch stop layer. In some embodiments, each of the first semiconductor fin and the second semiconductor fin includes a plurality of semiconductor layers. In some embodiments, the method of forming a semiconductor device structure further includes forming a gate electrode layer around a portion of each of the semiconductor layers.

[0195] A method for forming a semiconductor device structure includes: forming a first semiconductor fin and a second semiconductor fin on the front side of a substrate; removing portions of the first semiconductor fin and the second semiconductor fin to expose a first base portion and a second base portion, respectively; forming a first source / drain region on the first base portion, wherein the first source / drain region includes an N-type epitaxial material; forming a second source / drain region on the second base portion, wherein the second source / drain region includes a P-type epitaxial material; depositing a dielectric material on the first source / drain region and the second source / drain region; forming an opening in the dielectric material to expose the first source / drain region and the second source / drain region; performing a first implantation process to form a first doped region in the second source / drain region; depositing a conductive contact electrically connected to the first source / drain region and the second source / drain region; flipping the substrate; forming an opening in the substrate to expose the second source / drain region; and performing a second implantation process to form a second doped region in the second source / drain region.

[0196] In some embodiments, each of the first semiconductor fin and the second semiconductor fin includes a plurality of semiconductor layers disposed adjacent to the second source / drain region. In some embodiments, the plurality of semiconductor layers includes a first semiconductor layer, a second semiconductor layer disposed on the first semiconductor layer, and a third semiconductor layer disposed on the second semiconductor layer. In some embodiments, the bottom of the first doped region is located at a level between a top surface and a bottom surface of the second semiconductor layer. In some embodiments, the top of the second doped region is located at a level between the second semiconductor layer and the third semiconductor layer. In some embodiments, the first doped region and the second doped region overlap in the second source / drain region. In some embodiments, the implantation energy of the first implantation process and the second implantation process is in a range between 0.6 keV and 1.3 keV.

[0197] A semiconductor device structure includes: a first source / drain region disposed on a substrate, wherein the first source / drain region includes a P-type semiconductor material and a P-type dopant; a second source / drain region adjacent to the first source / drain region, wherein the second source / drain region includes an N-type semiconductor material and a P-type dopant; and a gate electrode layer disposed adjacent to the first source / drain region and the second source / drain region.

[0198] In some embodiments, the P-type semiconductor material includes silicon germanium, the N-type semiconductor material includes silicon, and the P-type dopant includes boron. In some embodiments, the first source / drain region further includes a first doped region disposed on top of the first source / drain region, a second doped region disposed on the bottom of the first source / drain region, and a third doped region disposed between the first doped region and the second doped region, wherein the dopant concentration of the third doped region is substantially less than the dopant concentration of the first doped region and the second doped region. In some embodiments, the semiconductor device structure further includes a first conductive contact electrically connected to the first source / drain region, and a second conductive contact electrically connected to the first source / drain region. In some embodiments, the first conductive contact is disposed adjacent to the first doped region, and the second conductive contact is disposed adjacent to the second doped region.

[0199] The features of several embodiments are summarized above so that those with ordinary knowledge in the art can better understand the viewpoints of the embodiments of the present disclosure. Those with ordinary knowledge in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present disclosure to achieve the same purposes and / or advantages as the embodiments introduced herein. Those with ordinary knowledge in the art should also understand that such or other similar structures do not deviate from the spirit and scope of the present disclosure, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device structure, comprising: forming a first semiconductor fin and a second semiconductor fin on a front side of a substrate; removing a portion of the first semiconductor fin and the second semiconductor fin to expose a first base portion and a second base portion respectively; forming a first source / drain region on the first base, wherein the first source / drain region comprises an N-type epitaxial material; forming a second source / drain region on the second base, wherein the second source / drain region comprises a P-type epitaxial material; depositing a dielectric material on the first source / drain region and the second source / drain region; forming an opening in the dielectric material to expose a portion of the first source / drain region and a portion of the second source / drain region; forming a mask on the exposed portion of the first source / drain region; performing an implantation process to implant a dopant in the second source / drain region; Remove the mask; as well as A conductive contact is deposited to electrically connect the first source / drain region and the second source / drain region. 2 . The method for forming a semiconductor device structure as claimed in claim 1 , wherein the mask is formed on a portion of the exposed portion of the second source / drain region.

3. The method for forming a semiconductor device structure according to claim 1 , further comprising: Before depositing the conductive contact, a first silicide layer and a second silicide layer are formed on the first source / drain region and the second source / drain region respectively. 4 . The method for forming a semiconductor device structure according to claim 1 , wherein each of the first semiconductor fin and the second semiconductor fin comprises a plurality of semiconductor layers.

5. A method for forming a semiconductor device structure, comprising: forming a first semiconductor fin and a second semiconductor fin on a front side of a substrate; removing a portion of the first semiconductor fin and the second semiconductor fin to expose a first base portion and a second base portion respectively; forming a first source / drain region on the first base, wherein the first source / drain region comprises an N-type epitaxial material; forming a second source / drain region on the second base, wherein the second source / drain region comprises a P-type epitaxial material; depositing a dielectric material on the first source / drain region and the second source / drain region; forming an opening in the dielectric material to expose the first source / drain region and the second source / drain region; Performing a first implantation process to form a first doped region in the second source / drain region; Depositing a conductive contact electrically connected to the first source / drain region and the second source / drain region; placing the substrate in an inverted manner; forming an opening in the substrate to expose the second source / drain region; and A second implantation process is performed to form a second doped region in the second source / drain region. 6 . The method for forming a semiconductor device structure according to claim 5 , wherein each of the first semiconductor fin and the second semiconductor fin comprises a plurality of semiconductor layers disposed adjacent to the second source / drain region. 7 . The method for forming a semiconductor device structure as claimed in claim 6 , wherein a bottom of the first doped region is located at a level between a top surface and a bottom surface of the second semiconductor layer.

8. A semiconductor device structure comprising: a first source / drain region disposed on a substrate, wherein the first source / drain region comprises a P-type semiconductor material and a P-type dopant; a second source / drain region adjacent to the first source / drain region, wherein the second source / drain region comprises an N-type semiconductor material and a P-type dopant; and A gate electrode layer is disposed adjacent to the first source / drain region and the second source / drain region.

9. The semiconductor device structure of claim 8 , wherein the first source / drain region further comprises a first doped region disposed on a top portion of the first source / drain region, a second doped region disposed on a bottom portion of the first source / drain region, and a third doped region located between the first doped region and the second doped region, wherein the dopant concentration of the third doped region is substantially lower than the dopant concentrations of the first doped region and the second doped region. 10 . The semiconductor device structure of claim 9 , further comprising a first conductive contact electrically connected to the first source / drain region, and a second conductive contact electrically connected to the first source / drain region.

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