Audio subsystem interface module, audio SOC chip and electronic equipment

Abstract

The present disclosure relates to an audio subsystem interface module, an audio SOC chip, and an electronic device. The audio subsystem interface module includes: an audio subsystem interface module connected between a peripheral bus interface module and a peripheral device; the peripheral bus interface module is respectively connected to an application processor chip and a digital signal processing chip; the audio subsystem interface module includes multiple downstream path units, multiple loopback path units, and an audio data transmission interface module; the multiple downstream path units and the multiple loopback path units each include at least one synchronous first-in-first-out data buffer (SFIFO); the multiple synchronous first-in-first-out data buffers are used to implement backpressure logic for the audio subsystem interface module. The present disclosure reduces the power consumption of the SOC chip by introducing multiple downstream path units and multiple loopback path units, and avoids data overflow by applying backpressure to the previous node based on the multiple synchronous first-in-first-out data buffers in the path units.

Description

Technical Field

[0001] The present disclosure relates to the field of audio processing technology, and in particular to an audio subsystem interface module, an audio SOC chip, and an electronic device. Background Art

[0002] With the advancement of audio SoCs (System on Chips), the requirements for interaction between electronic devices equipped with audio SoCs and various peripherals are constantly increasing, supporting features such as high-definition audio playback, voice assistant response, and noise cancellation. This increase in functionality leads to a continuous increase in internal audio SoC resource consumption and time overhead. Specifically, the increasing resource consumption of the built-in AP (Application Processor) and DSP (Digital Signal Processing) leads to increasing power consumption and time overhead for audio SoCs. Therefore, how to better reduce the power consumption of SoC chips is a pressing technical issue. Summary of the Invention

[0003] To overcome the problems existing in the related art, the present disclosure provides an audio subsystem interface module, an audio SOC chip and an electronic device.

[0004] According to a first aspect of an embodiment of the present disclosure, an audio subsystem interface module is provided. The audio subsystem interface module is connected between a peripheral bus interface module and a peripheral device. The peripheral bus interface module is connected to an application processor chip and a digital signal processing chip, respectively. The audio subsystem interface module includes multiple downlink path units, multiple loopback path units, and an audio data transmission interface module.

[0005] The multiple downlink path units are used to perform downlink processing on at least one channel of digital audio data obtained from the application processor chip and / or the digital signal processing chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module;

[0006] The plurality of loop path units are used to aggregate at least one channel of digital audio data input through the audio data transmission interface module and digital audio data obtained after downlink processing by any downlink path unit of the plurality of downlink path units, and output the digital audio data obtained after the aggregation processing through the audio data transmission interface module;

[0007] The multiple downlink path units and the multiple loopback path units respectively include at least one synchronous first-in-first-out data buffer SFIFO, and the multiple synchronous first-in-first-out data buffers are used to implement the back pressure logic of the audio subsystem interface module.

[0008] Through the above technical solution, complex sound processing, sampling rate control, routing, and other large-scale computing logic can be implemented in hardware within the audio subsystem interface module, thereby improving the peripheral audio processing speed while reducing the power consumption of the audio SoC chip. Furthermore, by introducing multiple synchronous first-in-first-out (SFIFO) data buffers within the SoC chip's audio subsystem interface module, backpressure logic can be implemented more simply and effectively, reducing the risk of data overflow.

[0009] In some possible implementations, the multiple downlink path units include:

[0010] a first downlink path, configured to perform downlink processing on the first channel of digital audio data acquired from the application processor chip via the peripheral bus interface module, and output the digital audio data obtained after the downlink processing via the audio data transmission interface module;

[0011] a second downlink path for performing downlink processing on the second channel of digital audio data acquired from the digital signal processing chip via the peripheral bus interface module, and outputting the digital audio data obtained after the downlink processing via the audio data transmission interface module;

[0012] The third downlink path is used to perform downlink processing on the third channel of digital audio data obtained from the digital signal processing chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module.

[0013] In this way, different downlink paths can be used to process and transmit audio data according to different usage scenarios.

[0014] In some possible implementations, the first downlink path includes a first data buffer AP-FIFO, a first sample rate conversion module AP-SRC (Sample Rate Conversion), a first synchronous first-in-first-out data buffer SFIFO_AP, a first convergence point, a first audio effect processing module DA0-SE0, a second synchronous first-in-first-out data buffer SFIFO_DA0_SE0, a second audio effect processing module DA-SE1, a third synchronous first-in-first-out data buffer SFIFO_DA0_SE1, and a second convergence point, which are connected in sequence. The input end of the first data buffer AP-FIFO is connected to the first output end of the peripheral bus interface module, and the output end of the second convergence point is connected to the first input end of the audio data transmission interface module.

[0015] The second downlink path includes a second data buffer DA0-FIFO, a second sampling rate conversion module DA0-SRC, a fourth synchronous first-in-first-out data buffer SFIFO_DA0_SRC, a first convergence point, a first sound effect processing module DA0-SE0, a second synchronous first-in-first-out data buffer SFIFO_DA0_SE0, a second sound effect processing module DA-SE1, a third synchronous first-in-first-out data buffer SFIFO_DA0_SE1, and a second convergence point, wherein an input end of the second data buffer DA0-FIFO is connected to a second output end of the peripheral bus interface module;

[0016] The third downlink path includes a third data buffer DA1-FIFO, a third sampling rate conversion module DA1-SRC0, a fifth synchronous first-in-first-out data buffer SFIFO_DA1_SRC0, a third sound effect processing module DA1-SE0, a sixth synchronous first-in-first-out data buffer SFIFO_DA1_SE0, the second sound effect processing module DA-SE1, a seventh synchronous first-in-first-out data buffer SFIFO_DA1_SE1, a third convergence point, a fourth sampling rate conversion module DA1-SRC1 and an eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1, which are connected in sequence. The input end of the third data buffer DA1-FIFO is connected to the third output end of the peripheral bus interface module, and the output end of the eighth synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 is connected to the second input end of the audio data transmission interface module.

[0017] In this way, different downlink paths include different processing modules and first-in-first-out data buffers. This configuration can more simply and effectively implement back pressure on the previous node.

[0018] In some possible implementations, for the first downlink path, the backpressure logic includes the following steps:

[0019] When the audio data transmission interface module generates a first initial back pressure signal, back pressure is applied to the third synchronous first-in-first-out data buffer SFIFO_DA0_SE1 based on the first initial back pressure signal;

[0020] When the third synchronous FIFO_DA0_SE1 generates a nearly full backpressure signal, backpressure is applied to the second synchronous FIFO_DA0_SE0 by combining the nearly full backpressure signal and the busy backpressure signal generated by the second sound effect processing module DA-SE1;

[0021] When the second synchronous FIFO data buffer SFIFO_DA0_SE0 generates a nearly full backpressure signal, backpressure is applied to the first synchronous FIFO data buffer SFIFO_AP by combining the nearly full backpressure signal and the busy backpressure signal generated by the first sound effect processing module DA0-SE0;

[0022] When the first synchronous first-in-first-out data buffer SFIFO_AP generates a nearly full backpressure signal, backpressure is applied to the first data buffer AP-FIFO by combining the nearly full backpressure signal and a busy backpressure signal generated by the first sampling rate conversion module AP-SRC.

[0023] In this way, back pressure on the preceding node can be simply and effectively achieved in the AP downlink path.

[0024] In some possible implementations, for the second downlink path, the backpressure logic includes the following steps:

[0025] When the audio data transmission interface module generates a first initial back pressure signal, back pressure is applied to the third synchronous first-in-first-out data buffer SFIFO_DA0_SE1 based on the first initial back pressure signal;

[0026] When the third synchronous FIFO_DA0_SE1 generates a nearly full backpressure signal, backpressure is applied to the second synchronous FIFO_DA0_SE0 by combining the nearly full backpressure signal and the busy backpressure signal generated by the second sound effect processing module DA-SE1;

[0027] When the second synchronous FIFO data buffer SFIFO_DA0_SE0 generates a nearly full backpressure signal, backpressure is applied to the fourth synchronous FIFO data buffer SFIFO_DA0_SRC by combining the nearly full backpressure signal and the busy backpressure signal generated by the first sound effect processing module DA0-SE0;

[0028] When the fourth synchronous FIFO data buffer SFIFO_DA0_SRC generates a nearly full backpressure signal, the nearly full backpressure signal and the busy backpressure signal generated by the second sampling rate conversion module DA0-SRC are combined to perform backpressure on the second data buffer DA0-FIFO.

[0029] In this way, back pressure on the previous node can be simply and effectively achieved in the DA0 downlink path.

[0030] In some possible implementations, for the third downstream path, the backpressure logic includes the following steps:

[0031] When the audio data transmission interface module generates a second initial back pressure signal, back pressure is applied to the eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1 based on the second initial back pressure signal;

[0032] When the eighth synchronous FIFO data buffer SFIFO_DA1_SRC1 generates a nearly full backpressure signal, backpressure is applied to the seventh synchronous FIFO data buffer SFIFO_DA1_SE1 by combining the nearly full backpressure signal and the busy backpressure signal generated by the fourth sampling rate conversion module DA1-SRC1;

[0033] When the seventh synchronous FIFO data buffer SFIFO_DA1_SE1 generates a nearly full backpressure signal, backpressure is applied to the sixth synchronous FIFO data buffer SFIFO_DA1_SE0 by combining the nearly full backpressure signal and the busy backpressure signal generated by the second sound effect processing module DA-SE1;

[0034] When the sixth synchronous FIFO data buffer SFIFO_DA1_SE0 generates a nearly full backpressure signal, backpressure is applied to the fifth synchronous FIFO data buffer SFIFO_DA1_SRC0 by combining the nearly full backpressure signal and the busy backpressure signal generated by the third sound effect processing module DA1-SE0;

[0035] When the fifth synchronous FIFO data buffer SFIFO_DA1_SRC0 generates a nearly full backpressure signal, the third data buffer DA1-FIFO is backpressured by combining the nearly full backpressure signal and the busy backpressure signal generated by the third sampling rate conversion module DA1-SRC0.

[0036] In this way, back pressure on the previous node can be simply and effectively achieved in the DA1 downlink path.

[0037] In some possible implementations, the plurality of loop path units include:

[0038] a first loopback path for aggregating the fourth channel digital audio data and the fifth channel digital audio data inputted through the audio data transmission interface module with the digital audio data obtained after downlink processing by the second downlink path unit, and outputting the digital audio data obtained after the aggregating processing through the audio data transmission interface module;

[0039] The second loopback path is used to aggregate the fourth channel digital audio data and the fifth channel digital audio data input through the audio data transmission interface module with the digital audio data obtained after downlink processing by the third downlink path unit, and output the digital audio data obtained after the aggregation processing through the audio data transmission interface module.

[0040] In this way, different loopback paths can be used to process and transmit audio data for different usage scenarios.

[0041] In some possible implementations, the first loop path includes a fifth sampling rate conversion module AD1-SRC0, a side tone loop path module ST, a ninth synchronous first-in-first-out data buffer SFIFO_ST0, and the second downstream path; wherein a first input end of the loop path module ST is connected to a first output end of the audio data transmission interface module via the fifth sampling rate conversion module AD1-SRC0, a second input end of the loop path module ST is connected to a second output end of the audio data transmission interface module, and a first output end of the loop path module ST is connected to a second sink point via the ninth synchronous first-in-first-out data buffer SFIFO_ST0;

[0042] The second loop path includes the fifth sampling rate conversion module AD1-SRC0, the loop path module ST, a tenth synchronous first-in-first-out data buffer SFIFO_ST1 and the third downstream path; wherein the second output end of the loop path module ST is connected to the third sink point through the tenth synchronous first-in-first-out data buffer SFIFO_ST1.

[0043] In this way, different loop paths include different processing modules and first-in-first-out data buffers. This configuration can more simply and effectively implement back pressure on the previous node.

[0044] In some possible implementations, for the first loop path, the backpressure logic includes the following steps:

[0045] When the audio data transmission interface module generates a first initial back pressure signal, back pressure is applied to the ninth synchronous first-in-first-out data buffer SFIFO_ST0 based on the first initial back pressure signal;

[0046] When the ninth synchronous FIFO data buffer SFIFO_ST0 generates a nearly full backpressure signal, backpressure is applied to the first loop path based on the nearly full backpressure signal.

[0047] In this way, back pressure on the previous node can be simply and effectively achieved in the ST-DA0 path.

[0048] In some possible implementations, for the second loop path, the backpressure logic includes the following steps:

[0049] When the audio data transmission interface module generates a second initial back pressure signal, back pressure is applied to the eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1 based on the second initial back pressure signal;

[0050] When the eighth synchronous FIFO data buffer SFIFO_DA1_SRC1 generates a nearly full backpressure signal, backpressure is applied to the tenth synchronous FIFO data buffer SFIFO_ST1 in combination with the nearly full backpressure signal and the busy backpressure signal generated by the fourth sampling rate conversion module DA1-SRC1;

[0051] When the tenth synchronous FIFO data buffer SFIFO_ST1 generates a nearly full backpressure signal, backpressure is applied to the second loop path based on the nearly full backpressure signal.

[0052] In this way, back pressure on the previous node can be simply and effectively achieved in the ST-DA1 path.

[0053] In some possible implementations, the audio subsystem interface module further includes:

[0054] Multiple uplink path units are used to perform uplink processing on at least one channel of digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing to the application processor chip and / or the digital signal processing chip through the peripheral bus interface module.

[0055] In this way, by introducing multiple uplink path units, different uplink scenarios can be handled, thereby reducing power consumption for uplink scenarios.

[0056] In some possible implementations, the multiple uplink path units include:

[0057] a first uplink path, configured to perform uplink processing on the fourth channel digital audio data and the fifth channel digital audio data inputted through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing to the application processor chip through the peripheral bus interface module;

[0058] a second uplink path for performing uplink processing on the fourth channel of digital audio data inputted through the audio data transmission interface module, and outputting the digital audio data obtained after the uplink processing to the digital signal processing chip through the peripheral bus interface module;

[0059] The third uplink path is used to perform uplink processing on the fifth channel of digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing to the digital signal processing chip through the peripheral bus interface module.

[0060] In this way, different uplink paths can be used to process and transmit audio data according to different usage scenarios.

[0061] In some possible implementations, the first uplink path includes a fifth sampling rate conversion module AD1-SRC0, a fourth sound effect processing module AD1-SE, a fifth sound effect processing module AD0-SE, a multiplexer AP-MUX (Multiplexer), a first sampling rate conversion module AP-SRC connected in sequence to an output end of the multiplexer AP-MUX, and a first data buffer AP-FIFO. The fifth sampling rate conversion module AD1-SRC0 and the fourth sound effect processing module AD1-SE are connected in series and then connected to a first input end of the multiplexer AP-MUX. The fifth sound effect processing module AD0-SE is connected to a second input end of the multiplexer AP-MUX. The input end of the fifth sampling rate conversion module AD1-SRC0 is connected to a first output end of the audio data transmission interface module, and the input end of the fifth sound effect processing module AD0-SE is connected to a second output end of the audio data transmission interface module.

[0062] The second uplink path includes a fifth sound effect processing module AD0-SE, a sixth sampling rate conversion module AD0-SRC and a fourth data buffer AD0-FIFO connected in sequence;

[0063] The third uplink path includes the fifth sampling rate conversion module AD1-SRC0, the fourth sound effect processing module AD1-SE, the seventh sampling rate conversion module AD1-SRC1 and the fifth data buffer AD1-FIFO connected in sequence.

[0064] In this way, uplink data processing and transmission can be achieved more accurately and effectively through different uplink paths.

[0065] In some possible implementations, the audio subsystem interface module includes three levels of clock gating, and the three levels of clock gating include first-level clock gating, second-level clock gating, and third-level clock gating, wherein the second-level clock gating is generated based on the first-level clock gating, and the third-level clock gating is generated based on the second-level clock gating.

[0066] In this way, the power consumption of the SOC chip can be further reduced by setting different clock gating in the audio subsystem interface module.

[0067] In some possible implementations, the second audio effect processing module DA-SE1 is provided with the first-level clock gating;

[0068] The first downlink path, the second downlink path, the third downlink path, the first loop path, the second loop path, the second uplink path and the third uplink path are provided with the second-level clock gating;

[0069] The first sampling rate conversion module AP-SRC, the second sampling rate conversion module DA0-SRC, the third sampling rate conversion module DA1-SRC0, the first sound effect processing module DA0-SE0, the third sound effect processing module DA1-SE0, the fourth sampling rate conversion module DA1-SRC1, the fifth sampling rate conversion module AD1-SRC0, the sixth sampling rate conversion module AD0-SRC, the seventh sampling rate conversion module AD1-SRC1, the fourth sound effect processing module AD1-SE and the fifth sound effect processing module AD0-SE are provided with the third level clock gating.

[0070] In this way, different levels of clock gating have corresponding control logics that are different, which can further reduce chip power consumption while ensuring data transmission.

[0071] In some possible implementations, the audio data transmission interface module includes multiple audio data transmission interface sub-modules, each of the audio data transmission interface sub-modules includes an asynchronous first-in-first-out data buffer and a protocol processing module, and the APB bus clock domain pclk (APB_clk) of each audio data transmission interface sub-module is independently controlled.

[0072] In this way, each I2S in the audio data transmission interface module can be opened and closed completely independently without any invalid operations or dynamic power consumption caused by clock flips.

[0073] The second embodiment of the present disclosure provides an audio SOC chip, comprising: an application processor chip, a digital signal processing chip, a peripheral bus interface module, and the audio subsystem interface module described in the first aspect; wherein,

[0074] The application processor chip and the digital signal processing chip are respectively connected to the peripheral bus interface module, and the peripheral bus interface module is connected to the peripheral device through the audio subsystem interface module.

[0075] A third embodiment of the present disclosure provides an electronic device, which includes the audio SOC chip described in the second aspect.

[0076] The technical solutions provided by the embodiments of the present disclosure may have the following beneficial effects:

[0077] The disclosed embodiments incorporate an audio subsystem interface module into an audio SOC chip. Through the multiple downstream and loopback units within this module, complex computational logic, such as sound effects processing, sampling rate control, and routing, is implemented in hardware, thereby reducing the power consumption of the audio SOC chip. Furthermore, by incorporating multiple synchronous first-in-first-out (SFIFO) buffers within the downstream and loopback units, backpressure logic is implemented more simply and efficiently, reducing the risk of data overflow.

[0078] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0080] Figure 1 The figure shows an example of an audio subsystem interface module according to an exemplary embodiment.

[0081] Figure 2 The figure shows an example of a first downstream path in an audio subsystem interface module according to an exemplary embodiment.

[0082] Figure 3 The figure shows an example of a second downstream path in an audio subsystem interface module according to an exemplary embodiment.

[0083] Figure 4 The figure shows an example of a third downstream path in an audio subsystem interface module according to an exemplary embodiment.

[0084] Figure 5The figure is a diagram showing an example of a first loopback path in an audio subsystem interface module according to an exemplary embodiment.

[0085] Figure 6 The figure is a diagram showing an example of a second loopback path in an audio subsystem interface module according to an exemplary embodiment.

[0086] Figure 7 The figure shows an example of a first upstream path in an audio subsystem interface module according to an exemplary embodiment.

[0087] Figure 8 The figure shows an example of a second upstream path in an audio subsystem interface module according to an exemplary embodiment.

[0088] Figure 9 The figure shows an example of a third upstream path in an audio subsystem interface module according to an exemplary embodiment.

[0089] Figure 10 The figure is an example diagram showing three clocks involved in an audio SOC chip in an audio subsystem interface module according to an exemplary embodiment.

[0090] Figure 11 The figure is an example diagram showing back pressure logic involved in a downstream path and a loopback path in an audio subsystem interface module according to an exemplary embodiment.

[0091] Figure 12 The figure is an example diagram showing a data loss mechanism in an audio subsystem interface module according to an exemplary embodiment.

[0092] Figure 13 The figure is an example diagram showing a zero-padding mechanism in an audio subsystem interface module according to an exemplary embodiment.

[0093] Figure 14 The figure is an example diagram showing three-level clock gating in an audio subsystem interface module according to an exemplary embodiment.

[0094] Figure 15 The figure is an example diagram showing an encapsulation module in an audio subsystem interface module according to an exemplary embodiment.

[0095] Figure 16 The figure is an example diagram showing an encapsulation module in an audio subsystem interface module according to an exemplary embodiment.

[0096] Figure 17 This is an example diagram of a data flow diagram in a second application scenario of an audio subsystem interface module according to an exemplary embodiment.

[0097] Figure 18The figure is a schematic diagram of data flow in a third application scenario of an audio subsystem interface module according to an exemplary embodiment.

[0098] Figure 19 It is a block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0099] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0100] It should be noted that all actions of acquiring signals, information or data in the present disclosure are carried out in compliance with the corresponding data protection laws and policies of the country where they are located and with the authorization given by the owner of the corresponding device.

[0101] Figure 1 3 is a schematic diagram of an audio subsystem interface module AUDIF (AudioInterface) in an audio SOC chip according to an embodiment of the present disclosure.

[0102] based on Figure 1 As can be seen, the audio subsystem interface module 110 can be connected between the peripheral bus interface module 120 and the peripheral device 130 (peripheral). The peripheral bus interface module 120 can be connected to the application processor chip AP and the digital signal processing chip DSP, respectively. Here, the peripheral bus interface module 120 can be an Advanced Peripheral Bus (APB).

[0103] In the disclosed embodiment, the audio subsystem interface module 110 may include multiple downlink path units, multiple loopback path units, and an audio data transmission interface module 111. The audio data transmission interface module 111 may be an I2S (Inter-IC Sound) wrapper. The audio data transmission interface module can transmit analog audio signals to a peripheral device.

[0104] Specifically, multiple downlink path units can be used to perform downlink processing on at least one channel of digital audio data obtained from the application processor chip AP and / or the digital signal processing chip DSP through the peripheral bus interface module 120, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module 111.

[0105] Here, the plurality of downlink path units may include a first downlink path, a second downlink path, and a third downlink path, wherein the first downlink path may also be referred to as an AP downlink path, the second downlink path may also be referred to as a DA0 downlink path, and the third downlink path may also be referred to as a DA1 downlink path.

[0106] The first downlink path can be used to perform downlink processing on the first channel of digital audio data obtained from the application processor chip AP through the peripheral bus interface module APB, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module 111 (I2S encapsulation module).

[0107] like Figure 2 As shown, the first downlink path may include a first data buffer AP-FIFO (First in first out, first in first out data buffer), a first sampling rate conversion module AP-SRC (Sample Rate Conversion, sampling rate conversion module), a first synchronous first in first out data buffer SFIFO (Synchronize FIFO, synchronization FIFO)_AP (1), a first convergence point 112, a first sound effect processing module DA0-SE0, a second synchronous first in first out data buffer SFIFO_DA0_SE0 (4), a second sound effect processing module DA (Digital to Analog)-SE1, a third synchronous first in first out data buffer SFIFO_DA0_SE1 (6) and a second convergence point 113. Based on Figure 2 It can be seen that the input end of the first data buffer AP-FIFO can be connected to the first output end of the peripheral bus interface module APB, and the output end of the second convergence point 113 can be connected to the first input end of the audio data transmission interface module 111 (I2S encapsulation module).

[0108] Optionally, the second downstream path can be used to perform downstream processing on the second channel of digital audio data obtained from the digital signal processing chip DSP through the peripheral bus interface module APB, and output the digital audio data obtained after the downstream processing through the audio data transmission interface module (I2S encapsulation module).

[0109] like Figure 3As shown, the second downlink path may include a second data buffer DA0-FIFO, a second sampling rate conversion module DA0-SRC, a fourth synchronous first-in-first-out data buffer SFIFO_DA0_SRC (2), a first convergence point 112, a first sound effect processing module DA0-SE0, a second synchronous first-in-first-out data buffer SFIFO_DA0_SE0 (4), a second sound effect processing module DA-SE1, a third synchronous first-in-first-out data buffer SFIFO_DA0_SE1 (6) and a second convergence point 113 connected in sequence. Figure 3 It can be seen that the input end of the second data buffer DA0-FIFO can be connected to the second output end of the peripheral bus interface module APB.

[0110] Optionally, the third downstream path can be used to perform downstream processing on the third channel of digital audio data obtained from the digital signal processing chip DSP through the peripheral bus interface module APB, and output the digital audio data obtained after the downstream processing through the audio data transmission interface module (I2S encapsulation module).

[0111] like Figure 4 As shown, the third downlink path may include a third data buffer DA1-FIFO, a third sampling rate conversion module DA1-SRC0, a fifth synchronous first-in-first-out data buffer SFIFO_DA1_SRC0 (3), a third sound effect processing module DA1-SE0, a sixth synchronous first-in-first-out data buffer SFIFO_DA1_SE0 (5), a second sound effect processing module DA-SE1, a seventh synchronous first-in-first-out data buffer SFIFO_DA1_SE1 (7), a third convergence point 114, a fourth sampling rate conversion module DA1-SRC1 and an eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1 (8) connected in sequence. Based on Figure 4 It can be seen that the input end of the third data buffer DA1-FIFO can be connected to the third output end of the peripheral bus interface module APB, and the output end of the eighth synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 (8) can be connected to the second input end of the audio data transmission interface module (I2S encapsulation module).

[0112] In summary, the downlink path can refer to taking data from the AP / DSP, sending it to the audif module (audio subsystem interface module) through the APB interface for processing, and finally sending it to the peripheral device through I2S.

[0113] In other embodiments, multiple loopback path units can be used to aggregate at least one channel of digital audio data input through the audio data transmission interface module (I2S encapsulation module) and digital audio data obtained after downlink processing through any one of the multiple downlink path units, and output the digital audio data obtained after the aggregation processing through the audio data transmission interface module (I2S encapsulation module).

[0114] Here, the plurality of loop path units may include a first loop path and a second loop path, wherein the first loop path may be referred to as an ST-DA0 path, and the second loop path may be referred to as an ST-DA1 path.

[0115] The first loopback path can be used to aggregate the fourth-channel digital audio data and the fifth-channel digital audio data input through the audio data transmission interface module (I2S encapsulation module) with the digital audio data obtained after downlink processing through the second downlink path unit, and output the digital audio data obtained after the aggregation processing through the audio data transmission interface module (I2S encapsulation module).

[0116] like Figure 5 As shown, the first loop path may include a fifth sampling rate conversion module AD1-SRC0, a loop path module ST, a ninth synchronous first-in-first-out data buffer SFIFO_ST0 (9) and a second downlink path. Figure 5 It can be seen that the first input end of the loop path module ST can be connected to the first output end of the audio data transmission interface module (I2S encapsulation module) through the fifth sampling rate conversion module AD1-SRC0, the second input end of the loop path module ST can be connected to the second output end of the audio data transmission interface module (I2S), and the first output end of the loop path module ST can be connected to the second convergence point 113 through the ninth synchronous first-in-first-out data buffer SFIFO_ST0 (9).

[0117] It is understandable that the first loop path can select either AD0 or AD1 data, be processed by the ST path, and then be aggregated with the DA0 branch data.

[0118] Optionally, the second loopback path may be used to aggregate the fourth-channel digital audio data and the fifth-channel digital audio data input through the audio data transmission interface module (I2S encapsulation module) with the digital audio data obtained after downlink processing through the third downlink path unit, and output the digital audio data obtained after the aggregate processing through the audio data transmission interface module (I2S encapsulation module).

[0119] like Figure 6As shown, the second loop path may include a fifth sampling rate conversion module AD1-SRC0, a loop path module ST, a tenth synchronous first-in-first-out data buffer SFIFO_ST1 (10) and a third downlink path. Figure 6 It can be seen that the second output terminal of the loop path module ST is connected to the third sink 114 through the tenth synchronous first-in-first-out data buffer SFIFO_ST1 (10).

[0120] It can be understood that the second loop path is similar to the first loop path, and it can select either AD0 or AD1 data, be processed by the ST path, and then converge with the DA1 branch data.

[0121] In summary, peripheral data passes through the I2S wrapper interface and can be transmitted to the audif module-ST path through AD0 and AD1. After data selection and processing, it is aggregated with the downstream path data and can be sent to the peripheral through the I2S interface (I2S encapsulation module).

[0122] In other embodiments, the audio subsystem interface module 110 may further include multiple upstream path units, wherein the multiple upstream path units may be used to perform upstream processing on at least one channel of digital audio data input through the audio data transmission interface module (I2S encapsulation module), and output the digital audio data obtained after the upstream processing to the application processor chip AP and / or the digital signal processing chip DSP through the peripheral bus interface module APB.

[0123] Specifically, the plurality of uplink path units may include a first uplink path, a second uplink path, and a third uplink path, wherein the first uplink path may be referred to as an AP uplink path, the second uplink path may be referred to as an AD0 uplink path, and the third uplink path may be referred to as an AD1 uplink path.

[0124] The first uplink path can be used to perform uplink processing on the fourth channel digital audio data and the fifth channel digital audio data input through the audio data transmission interface module (I2S encapsulation module), and output the digital audio data obtained after the uplink processing to the application processor chip AP through the peripheral bus interface module APB.

[0125] like Figure 7 As shown, the first uplink path may include a fifth sampling rate conversion module AD1-SRC0, a fourth sound effect processing module AD1-SE (Sound Effect, sound effect processing module), a fifth sound effect processing module AD0-SE, a multiplexer AP-MUX, and a first sampling rate conversion module AP-SRC and a first data buffer AP-FIFO connected in sequence to the output end of the multiplexer AP-MUX.

[0126] based on Figure 7 It can be seen that the fifth sampling rate conversion module AD1-SRC0 and the fourth sound effect processing module AD1-SE can be connected in series to the first input end of the multiplexer AP-MUX, the fifth sound effect processing module AD0-SE can be connected to the second input end of the multiplexer AP-MUX, the input end of the fifth sampling rate conversion module AD1-SRC0 can be connected to the first output end of the audio data transmission interface module (I2S encapsulation module), and the input end of the fifth sound effect processing module AD0-SE can be connected to the second output end of the audio data transmission interface module (I2S encapsulation module).

[0127] Optionally, the second uplink path can be used to perform uplink processing on the fourth channel of digital audio data input through the audio data transmission interface module (I2S encapsulation module), and output the digital audio data obtained after the uplink processing to the digital signal processing chip DSP through the peripheral bus interface module APB.

[0128] like Figure 8 As shown, the second uplink path may include a fifth sound effect processing module AD0-SE, a sixth sampling rate conversion module AD0-SRC and a fourth data buffer AD0-FIFO connected in sequence.

[0129] Optionally, the third uplink path can be used to perform uplink processing on the fifth channel of digital audio data input through the audio data transmission interface module (I2S encapsulation module), and output the digital audio data obtained after the uplink processing to the digital signal processing chip DSP through the peripheral bus interface module APB.

[0130] like Figure 9 As shown, the third upstream path may include a fifth sampling rate conversion module AD1-SRC0, a fourth sound effect processing module AD1-SE, a seventh sampling rate conversion module AD1-SRC1 and a fifth data buffer AD1-FIFO connected in sequence.

[0131] In summary, the upstream path can refer to taking data from the peripheral device, sending it to the audif module (audio subsystem interface module) through the I2S interface (I2S wrapper) for processing, and finally transmitting it to the AP / DSP through the APB interface.

[0132] As an optional method, the audio SOC chip can involve three clock domain conversions, namely from AP / DSP to audio subsystem interface module (audif) and then to peripherals, which mainly involves the following: Figure 10 The three clock domain conversions are shown. Figure 10It can be seen that the three clock domains can be pclk / audif_core_clk / I2S clk respectively, among which I2S clk (clock) can include three clocks: i2s clk, pclk_i2s_X and audif core clk.

[0133] In addition, the process from AP / DSP to audio subsystem interface module (audif) and then to peripherals can also include sampling rate conversion and various data path routing aggregation. Among them, the SRC module in sampling rate conversion can support conversion between multiple frequency sampling rates, such as 44.1K to 48K.

[0134] The three clock frequencies (pclk, audif_core_clk, and I2S clk) described above can decrease in sequence, resulting in a progressively slower computation speed in the downstream path. To prevent overflows caused by premature data transfer from the previous stage to the next stage, the disclosed embodiment incorporates multiple synchronous first-in-first-out data buffers to implement backpressure logic. The upstream path, in contrast, achieves progressively faster computation speeds, eliminating the risk of overflow and eliminating the need for a backpressure path.

[0135] As can be seen from the above description, each of the multiple downstream path units and the multiple loopback path units may include at least one synchronous first-in-first-out data buffer SFIFO, wherein the multiple synchronous first-in-first-out data buffers are used to implement the backpressure logic of the audio subsystem interface module. In other words, the backpressure logic corresponding to different downstream paths or loopback paths is different, as detailed in FIG. Figure 11 shown.

[0136] pass Figure 11It can be seen that for the first downlink path, the back pressure logic includes the following steps: when the audio data transmission interface module (I2S encapsulation module) generates a first initial back pressure signal (af_da0), the embodiment of the present disclosure can perform back pressure on the third synchronous first-in-first-out data buffer SFIFO_DA0_SE1 (6) based on the first initial back pressure signal; when the third synchronous first-in-first-out data buffer SFIFO_DA0_SE1 (6) generates a nearly full back pressure signal (af signal), the second synchronous first-in-first-out data buffer SFIFO_DA0_SE0 (6) can be back pressured in combination with the nearly full back pressure signal (af signal) and the busy back pressure signal (busy signal) generated by the second sound effect processing module DA-SE1. 4) back pressure is performed; when the second synchronous first-in-first-out data buffer SFIFO_DA0_SE0 (4) generates a back pressure signal (af signal) indicating that it is about to be full, the first synchronous first-in-first-out data buffer SFIFO_AP (1) is back pressured by combining the back pressure signal (af signal) indicating that it is about to be full and the busy back pressure signal (busy signal) generated by the first sound effect processing module DA0-SE0; when the first synchronous first-in-first-out data buffer SFIFO_AP (1) generates a back pressure signal (af signal) indicating that it is about to be full, the first data buffer AP-FIFO is back pressured by combining the back pressure signal (af signal) indicating that it is about to be full and the busy back pressure signal (busy signal) generated by the first sampling rate conversion module AP-SRC.

[0137] Optionally, for the second downlink path, the back pressure logic may include the following steps: when the audio data transmission interface module (I2S) generates a first initial back pressure signal (af_da0), the embodiment of the present disclosure may perform back pressure on the third synchronous first-in-first-out data buffer SFIFO_DA0_SE1 (6) based on the first initial back pressure signal; when the third synchronous first-in-first-out data buffer SFIFO_DA0_SE1 (6) generates a nearly full back pressure signal (af signal), the second synchronous first-in-first-out data buffer SFIFO_DA0_SE0 (4) may be back pressured in combination with the nearly full back pressure signal (af signal) and the busy back pressure signal (busy signal) generated by the second sound effect processing module DA-SE1 (4). Back pressure; when the second synchronous first-in-first-out data buffer SFIFO_DA0_SE0 generates a nearly full back pressure signal (af signal), the nearly full back pressure signal (af signal) and the busy back pressure signal (busy signal) generated by the first sound effect processing module DA0-SE0 are combined to perform back pressure on the fourth synchronous first-in-first-out data buffer SFIFO_DA0_SRC (2); when the fourth synchronous first-in-first-out data buffer SFIFO_DA0_SRC (2) generates a nearly full back pressure signal (af signal), the nearly full back pressure signal (af signal) and the busy back pressure signal (busy signal) generated by the second sampling rate conversion module DA0-SRC are combined to perform back pressure on the second data buffer DA0-FIFO.

[0138] Optionally, for the third downlink path, the backpressure logic may include the following steps: when the audio data transmission interface module (I2S) generates a second initial backpressure signal (af_da1), backpressure is applied to the eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1 (8) based on the second initial backpressure signal; when the eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1 (8) generates a nearly full backpressure signal (af signal), backpressure is applied to the seventh synchronous first-in-first-out data buffer SFIFO_DA1_SE1 (7) in combination with the nearly full backpressure signal (af signal) and the busy backpressure signal (busy signal) generated by the fourth sampling rate conversion module DA1-SRC1; when the seventh synchronous first-in-first-out data buffer SFIFO_DA1_SE1 (7) generates a nearly full backpressure signal (af signal), backpressure is applied to the seventh synchronous first-in-first-out data buffer SFIFO_DA1_SE1 (7) in combination with the nearly full backpressure signal (af signal) and the second sound effect processing The busy backpressure signal (busy signal) generated by the module DA-SE1 is used to backpressure the sixth synchronous first-in-first-out data buffer SFIFO_DA1_SE0 (5); when the sixth synchronous first-in-first-out data buffer SFIFO_DA1_SE0 (5) generates a nearly full backpressure signal (af signal), the nearly full backpressure signal (af signal) and the busy backpressure signal (busy signal) generated by the third sound effect processing module DA1-SE0 are combined to backpressure the fifth synchronous first-in-first-out data buffer SFIFO_DA1_SRC0 (3); when the fifth synchronous first-in-first-out data buffer SFIFO_DA1_SRC0 (3) generates a nearly full backpressure signal (af signal), the nearly full backpressure signal (af signal) and the busy backpressure signal (busy signal) generated by the third sampling rate conversion module DA1-SRC0 are combined to backpressure the third data buffer DA1-FIFO.

[0139] In the embodiment of the present disclosure, the first initial back pressure signal may be the back pressure signal af_da0 generated internally by the I2S wrapper (I2S encapsulation module) for the DA0 branch; the second initial back pressure signal may be the back pressure signal af_da1 generated internally by the I2S wrapper (I2S encapsulation module) for the DA1 branch.

[0140] The almost-full backpressure signal may be an af signal (almost-full), which is triggered when the FIFO is about to be filled. Specifically, when af=1, the backpressure upstream node cannot transmit data or perform operations.

[0141] The busy backpressure signal can be a busy signal. When the computing unit is in a computing state / busy state, busy = 1. At this time, the backpressure is applied to the upstream node, preventing it from transmitting data or performing calculations. Here, the computing unit can be the aforementioned AP-SRC, DA0-SE0, and DA-SE1.

[0142] In summary, if the current node receives an af=1 backpressure signal from the subsequent stage, or receives a busy=1 backpressure signal from the subsequent stage, it will not be able to transmit data to the subsequent stage or perform operations.

[0143] The above is for the back pressure logic of different downlink paths. In addition, different loopback paths have different corresponding back pressure logics.

[0144] Specifically, for the first loop path, the back pressure logic may include the following steps: when the audio data transmission interface module (I2S) generates a first initial back pressure signal, the embodiment of the present disclosure may perform back pressure on the ninth synchronous first-in-first-out data buffer SFIFO_ST0 (9) based on the first initial back pressure signal; when the ninth synchronous first-in-first-out data buffer SFIFO_ST0 (9) generates a nearly full back pressure signal (af signal), the first loop path may be back pressured based on the nearly full back pressure signal (af signal).

[0145] Optionally, for the second loop path, the back pressure logic may include the following steps: when the audio data transmission interface module (I2S) generates a second initial back pressure signal, the eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1 (8) is back pressured based on the second initial back pressure signal; when the eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1 (8) generates a nearly full back pressure signal (af signal), the embodiment of the present disclosure may combine the nearly full back pressure signal (af signal) and the busy back pressure signal (busy signal) generated by the fourth sampling rate conversion module DA1-SRC1 to back pressure the tenth synchronous first-in-first-out data buffer SFIFO_ST1 (10); when the tenth synchronous first-in-first-out data buffer SFIFO_ST1 (10) generates a nearly full back pressure signal (af signal), the second loop path is back pressured based on the nearly full back pressure signal (af signal).

[0146] As a specific implementation method, Figure 11 As shown in the figure, the I2S wrapper (I2S encapsulation module) can generate a back pressure signal af_da0 for the DA0 branch and a back pressure signal af_da1 for the DA1 branch. Among them, af_da0 can back pressure SFIFO_DA0_SE1 (6) and SFIFO_ST0 (9); af_da1 can back pressure SFIFO_DA1_SRC1 (8).

[0147] On this basis, SFIFO_DA0_SE1 (6) generates an af backpressure signal, which, together with the busy backpressure signal generated by DA-SE1, can jointly backpressure SFIFO_DA0_SE0 (4); SFIFO_ST0 (9) generates an af backpressure signal, which can backpressure the ST-DA0 loop path (the first loop path).

[0148] Optionally, SFIFO_DA1_SRC1 (8) generates an af backpressure signal, which, together with the busy backpressure signal generated by DA1-SRC1, can jointly backpressure SFIFO_DA1_SE1 (7) and SFIFO_ST1 (10).

[0149] Optionally, SFIFO_DA1_SE1 (7) generates an af backpressure signal, which, combined with the busy backpressure signal generated by DA-SE1, can jointly backpressure SFIFO_DA1_SE0 (5); SFIFO_ST1 (10) generates an af backpressure signal that can backpressure the ST-DA1 loop path (second loop path).

[0150] Optionally, SFIFO_DA0_SE0 (4) generates an af backpressure signal, which, together with the busy backpressure signal generated by DA0-SE0, can jointly backpressure SFIFO_AP (1) and SFIFO_DA0_SRC (2).

[0151] Optionally, SFIFO_DA1_SE0 (5) generates an af backpressure signal, which, in combination with the busy backpressure signal generated by DA1-SE0, can jointly backpressure SFIFO_DA1_SRC0 (3).

[0152] Optionally, SFIFO_AP (1) generates an af backpressure signal, which, together with the busy backpressure signal generated by AP-SRC, can jointly backpressure AP_FIFO, ultimately controlling the interaction between the audif-AP downlink path (the first downlink path) and the AP.

[0153] Optionally, SFIFO_DA0_SRC (2) generates an af backpressure signal, which, combined with the busy backpressure signal generated by DA0-SRC, can jointly backpressure DA0_FIFO, ultimately controlling the interaction between the audif-DA0 downstream path (second downstream path) and the DSP.

[0154] Optionally, SFIFO_DA1_SRC0 (3) generates an af backpressure signal, which, combined with the busy backpressure signal generated by DA1-SRC, can jointly backpressure DA1_FIFO, ultimately controlling the interaction between the audif-DA1 downstream path (the third downstream path) and the DSP.

[0155] By relying on the nearly full signal of the convergence point FIFO and whether the algorithm module / pipe is busy to complete data flow regulation, the software configuration workload and debugging difficulty can be minimized, and the link performance can be improved. In other words, the link back pressure can be optimized simply and clearly to reduce the control logic complexity of the audio subsystem interface module.

[0156] The audio subsystem interface module (Audif module) in the disclosed embodiments can significantly reduce power consumption in typical scenarios (e.g., when all functions, such as sound effect processing, sampling rate control, and routing processing, are fully operational). For example, the disclosed embodiments can be applied to mobile phone voice calls, music playback, video viewing, and gaming.

[0157] As another optional method, the multi-channel audio convergence point has a unique "data loss" requirement. For two C-channels / D-channels from different clock domains, if after the C-channel receives data, if the D-channel (main channel) does not receive data, the data received by the C-channel will be "discarded", that is, the data loss processing operation will be performed. After the D-channel receives data, the convergence processing with the C-channel will be started again.

[0158] The above-mentioned data loss handling operation may belong to the data loss mechanism, which is aimed at the loop path. For example, Figure 12 As shown, DA0 is the master and ST-DA0 is the slave. Because ST-DA0 has fewer modules, data from the master arrives at the convergence point quickly, while data from DA0 takes a relatively long time to arrive. At this point, the valid signal from the master DA0 has not yet arrived, but the valid signal from the slave ST-DA0 has already arrived multiple times, resulting in a large buffer. This data will be discarded when the master's valid signal arrives. It will not converge with the latest slave data until the master's data and valid signal arrive.

[0159] It should be noted that based on the "data loss" requirement at the aggregation point, the DA-SE1 module can aggregate the data from the AP / DA0 / DA1 three channels for mixing processing. At this time, there must be no over-complement, under-complement or interval error, so the requirements for data flow control of the entire link are relatively high.

[0160] like Figure 13 As shown, most links on the master DA0 / DA1 are independent. When converging with the slave AP / ST_DA0 / ST_DA1, data loss processing must function properly. Furthermore, the DA-SE1 module must converge synchronously with the two master DA0 / DA1 links, using DA0 / DA1 data for shared logic to avoid mismatches.

[0161] In addition, the second sound effect processing module DA-SE1 module can be provided with a "0" filling mechanism. For example, if there is data and a valid signal on the DA0 path, but there is no data and a valid signal on the DA1 path, if the DA-SE1 module is in working state and detects a valid signal on the DA0 path, and confirms that there is no valid signal on DA1, the embodiment of the present disclosure can fill the DA1 data with "0" and treat the DA0 valid signal as a valid signal of DA1.

[0162] like Figure 13 As shown, there is a "0-filling" mechanism at the first convergence point, the second convergence point and the third convergence point.

[0163] Alternatively, the audio subsystem interface module may include three levels of clock gating, where the three levels of clock gating may include a first level of clock gating (a primary clock), a second level of clock gating (a secondary clock), and a third level of clock gating (a tertiary clock). The second level of clock gating may be generated based on the first level of clock gating, and the third level of clock gating may be generated based on the second level of clock gating.

[0164] Specifically, such as Figure 14 The second audio effect processing module DA-SE1 shown can be provided with a first level of clock gating; the first downstream path, the second downstream path, the third downstream path, the first loop path, the second loop path, the second upstream path and the third upstream path are provided with the second level of clock gating; the first sampling rate conversion module AP-SRC, the second sampling rate conversion module DA0-SRC, the third sampling rate conversion module DA1-SRC0, the first audio effect processing module DA0-SE0, the third audio effect processing module DA1-SE0, the fourth sampling rate conversion module DA1-SRC1, the fifth sampling rate conversion module AD1-SRC0, the sixth sampling rate conversion module AD0-SRC, the seventh sampling rate conversion module AD1-SRC1, the fourth audio effect processing module AD1-SE and the fifth audio effect processing module AD0-SE can be provided with a third level of clock gating.

[0165] It is understandable that the primary clock may include the audif module main clock audif_core_clk. Since the DA-SE1 module needs to process DA0 / DA1 two-way data at the same time, it may also use the primary clock.

[0166] Secondary clocks can include the AP path, DA0 / DA1 downlink path, AD0 / AD1 uplink path, and ST_DA0 / DA1 loopback path. Each branch can be controlled by a corresponding enable register, which controls whether the branch clock is enabled. For example, the corresponding secondary clock can be generated by the clk_gate module. When the corresponding branch is not in use, the secondary clock of that branch can be turned off to reduce power consumption. The relationship between the secondary gated clock, branches, and enable registers can be shown in Table 1.

[0167] Table 1

[0168]

[0169] The tertiary clock can be a module in the downstream path that can generate a busy backpressure signal. Based on the secondary clock, the disclosed embodiment can use the busy signal as the enable signal of the clk_gate module to generate the tertiary clock of this module. When busy = 1, the tertiary clock of this module is turned on. After the calculation is completed, busy = 0, the tertiary clock of this module is turned off to further reduce power consumption.

[0170] In addition, the five calculation units of the upstream path AD0_SRC / AD1_SRC0 / AD0_SE / AD1_SE / AD1_SRC1 may also be provided with corresponding busy logic, that is, busy=1 during calculation and busy=0 after calculation is completed.

[0171] The specific information of the three-level clock can be shown in Table 2.

[0172] Table 2

[0173]

[0174] In the process of setting up three-level clock gating, the embodiment of the present disclosure can add a clk_gate module to the clock to generate the corresponding gated clock. The clk_gate module can have an enable signal en. When en=1, the corresponding gated clock is generated; when en=0, the corresponding gated clock is disabled.

[0175] The disclosed embodiment divides the entire link into different pipes by setting a three-level clock in the audio subsystem interface module. After each pipe calculates the current data point, it can independently shut down the clock and wait for the next calculation. This can reduce the dynamic power consumption of the link, that is, it can significantly reduce the dynamic power consumption caused by clock flips.

[0176] Alternatively, the audio data transmission interface module (I2S encapsulation module) can include multiple audio data transmission interface submodules. Each audio data transmission interface submodule can include an asynchronous first-in-first-out data buffer (I2S_afifo) and a protocol processing module (I2S_logic). The APB bus clock domain (pclk) of each audio data transmission interface submodule is independently controlled.

[0177] In other words, an I2S wrapper (encapsulation module) can contain multiple I2S ports, each of which is internally divided into an I2S_afifo (asynchronous first-in-first-out data buffer) and an I2S_logic (protocol processing module). This means that an I2S wrapper can contain multiple groups of I2S ports and corresponding mapping logic.

[0178] I2S_afifo is used to transfer data across clock domains, and I2S_logic is used to process data according to the I2S protocol. Each I2S can also contain three clock domains: pclk, audif_core_clk, and I2S clk.

[0179] As an example, Figure 15 As shown, the configuration domain clock for each I2S can be pclk. This means that the clock used for interaction with audif_core is audif_core_clk, while the clock output to the peripherals is the respective I2S_clk. Furthermore, by using afifo to separate the interaction between I2S_logic and audif_core, each I2S can maintain its own I2S_clk output to the peripherals. This clock relationship is simple to design and meets practical requirements.

[0180] As another example, Figure 16 As shown, the embodiment of the present disclosure can subdivide the pclk clock into multiple independent clocks of the same origin, such as pclk_i2s_0, pclk_i2s_1 and pclk_i2s_2, within the audif module through the top-level CRG (Clock and Reset Generation) module, so that the pclk clock corresponding to each group of I2S can be independently shut down.

[0181] For example, when I2S_2 is not used, the embodiment of the present disclosure may turn off pclk_i2s_2 and clk_i2s_2, so that I2S_2 does not have any invalid operations and dynamic power consumption caused by clock flips.

[0182] The embodiment of the present disclosure can avoid the problem of a large number of invalid operations in I2S by independently controlling the APB bus clock domain pclk of each audio data transmission interface submodule, and at the same time reduce the dynamic power consumption caused by clock flipping.

[0183] In summary, the I2S package module contains multiple I2Ss, each of which can contain three clock domains. Using the top-level CRG, the clock signals required by each I2S are all independently isolated, allowing each I2S to be independently turned on and off. Since in most scenarios, not every I2S needs to be active, this optimization can significantly reduce I2S power consumption.

[0184] To facilitate understanding, the following three common application scenarios are used as examples to describe the data flow.

[0185] The first application scenario: playing music.

[0186] The audio source data is sent to the digital signal processing chip (DSP). After preliminary processing by the DSP, it is then sent by the peripheral bus interface module (APB) to the downstream path of the audio subsystem interface module (audif module), such as the second downstream path. It should be noted that the downstream path may also be the third downstream path. The selection of the downstream path can be configured by software and is not explicitly limited in this disclosure.

[0187] On this basis, the second downstream path performs sampling rate conversion and sound effect module processing, and converts the processed results into digital-to-analog signals through the audio data transmission interface module I2S, that is, converting digital signals into analog signals so that they can be heard by the user.

[0188] The second application scenario: receiving a text message during music playback.

[0189] like Figure 17 As shown in the music playback process described above, when a text message is received, the application processor chip AP generates a digital audio signal corresponding to the text message alert tone. This digital audio signal is then sent to the first downstream path via the peripheral bus interface module APB. After simple processing on this first downstream path, it is sent to the second downstream path to merge with the digital audio signal corresponding to the music playback. The digital audio signal corresponding to the music playback and the digital audio signal corresponding to the text message alert tone are then mixed. Finally, the audio data transmission interface module I2S performs digital-to-analog conversion, converting the digital signal into an analog signal for the user to hear.

[0190] The third application scenario: making phone calls.

[0191] like Figure 18As shown, the other party's voice is received by the mobile phone modem module, and the corresponding digital audio signal is sent to the digital signal processing chip DSP. The digital signal is initially processed by the digital signal processing chip DSP, and then sent to the downstream path of the audio subsystem interface module AUDIF through the peripheral bus interface module APB, such as the third downstream path. It should be noted that the signal can also be sent to the second downstream path, and the selection of the downstream path can be configured by software.

[0192] On this basis, the audio is processed by each sound effect module on the third downlink path and finally sent to the audio data transmission interface module I2S. The audio data transmission interface module I2S performs digital-to-analog conversion, that is, converts the digital signal into an analog signal so that it can be heard by the user.

[0193] The user's voice, corresponding to an analog signal, is converted to a digital signal by the I2S audio data transmission interface module and then fed into the third upstream path. The signal is then processed by the various audio modules on the third upstream path. The data is then sent by the APB interface module to the digital signal processing chip DSP for further processing before being transmitted via the mobile modem module to the other party's phone. The converted digital signal can also be fed into the second upstream path and processed by the various audio modules on the second upstream path. The choice of upstream path is software-configurable.

[0194] It should be noted that when a user holds the phone against their right ear while making a call, their left ear may hear their voice clearly, but their right ear may not. In this case, the data corresponding to their own voice is received by the third uplink path, selected and processed by the second loopback path, and then combined with the other party's voice on the third downlink path for mixing. Finally, it is sent to the audio data transmission interface module I2S, where it performs digital-to-analog conversion to generate an analog mixed signal for the user to hear, thus improving their listening experience.

[0195] The software constraint logic principle of the audio SOC chip in the disclosed embodiment is to ensure that when the audio data transmission interface module I2S inputs or outputs data, the audio subsystem interface module AUDIF is already in normal working state, that is, when each I2S is reset independently, it cannot affect the interaction between audif_core and other I2S. Therefore:

[0196] Reset sequence: The audio data transmission interface module I2S is reset first, and the audio subsystem interface module AUDIF is reset later.

[0197] Reset sequence: The audio subsystem interface module AUDIF is reset first, and the audio data transmission interface module I2S is reset later.

[0198] In addition, when the audio data transmission interface module I2S is reset, it is necessary to ensure that the corresponding branch connecting the audio subsystem interface module audif_core and the audio data transmission interface module I2S is in an invalid state.

[0199] It should be noted that resetting any of the multiple FIFOs on the APB side (AP_FIFO, DA0_FIFO, DA1_FIFO, AD0_FIFO, and AD1_FIFO) requires resetting the audio subsystem interface module audif_core as well. Furthermore, when all AFIFOs are asynchronously processed, the reset signals in both clock domains can be from the same source to ensure simultaneous reset.

[0200] To ensure that the back pressure of the downlink path can be established normally, the minimum amount of data that the AP / DSP can write to the three FIFOs, AP_FIFO, DA0_FIFO, and DA1_FIFO, for the first time through APB must be greater than the corresponding ae (almost-empty) value of each FIFO.

[0201] In some implementations, if the loopback path is enabled, data from I2SA may pass through the loopback path, converge with downstream data, and then be sent to I2SB. In this case, I2SA / B must have the same clock source to prevent frequency differences from accumulating and causing convergence errors. If the loopback path is enabled, downstream data must reach the convergence point to avoid the ST path being in a "data loss" state.

[0202] Optionally, when the second audio effect processing module DA-SE1 is in the on state, if the data of the second downstream path and the third downstream path are ultimately sent to different I2Ss, all corresponding I2Ss need to have the same clock source to prevent synchronization failure caused by frequency difference accumulation.

[0203] When the second audio effect processing module DA-SE1 is enabled, it is necessary to ensure that data from both the second and third downstream channels can be sent out normally through the I2S. Otherwise, any abnormal data transmission in either channel, resulting in abnormal back pressure, will affect the data flow of the other channel, thereby causing synchronization errors in the second audio effect processing module DA-SE1.

[0204] The embodiment of the present disclosure completes data flow regulation through the nearly full signal of the convergence point fifo and whether the algorithm module / pipe is busy, which can greatly reduce the workload of software configuration and the difficulty of debugging, and can improve the performance of the link. In addition, by setting a three-level clock to divide the entire link into different pipes, each pipe will independently turn off the clock after calculating the current data point and wait for the next calculation, which can reduce the dynamic power consumption of the link. In addition, the I2S encapsulation module contains multiple I2Ss, and each I2S can contain three clock domains. The embodiment of the present disclosure uses the top-level CRG to independently open all the clock signals required by each I2S, so that each I2S can be switched on and off independently. Since not every I2S needs to work in most scenarios, the present disclosure can greatly reduce the power consumption of the I2S.

[0205] Based on the above embodiments, the present disclosure further proposes an audio SOC chip, which includes: an application processor chip, a digital signal processing chip, a peripheral bus interface module and the above audio subsystem interface module.

[0206] The application processor chip and the digital signal processing chip can be connected to the peripheral bus interface module respectively, and the peripheral bus interface module can be connected to the peripheral device through the audio subsystem interface module.

[0207] Figure 19 FIG1 is a block diagram of an electronic device 800 according to an exemplary embodiment. For example, the electronic device 800 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc. The electronic device 800 may include the aforementioned audio SOC chip.

[0208] Reference Figure 19 , the electronic device 800 may include one or more of the following components: a processing component 802 , a memory 804 , a power component 806 , a multimedia component 808 , an audio component 810 , an input / output interface 812 , a sensor component 814 , and a communication component 816 .

[0209] The processing component 802 generally controls the overall operation of the electronic device 800, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 802 may include one or more processors 820 to execute instructions. In addition, the processing component 802 may include one or more modules to facilitate interaction between the processing component 802 and other components. For example, the processing component 802 may include a multimedia module to facilitate interaction between the multimedia component 808 and the processing component 802.

[0210] The memory 804 is configured to store various types of data to support operations on the electronic device 800. Examples of such data include instructions for any application or method operating on the electronic device 800, contact data, phone book data, messages, pictures, videos, etc. The memory 804 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0211] The power supply component 806 provides power to the various components of the electronic device 800. The power supply component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 800.

[0212] The multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, it may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensors can not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide action. In some embodiments, the multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the electronic device 800 is in an operating mode, such as a capture mode or a video mode, the front-facing camera and / or the rear-facing camera can receive external multimedia data. Each front-facing camera and the rear-facing camera can have a fixed optical lens system or have focal length and optical zoom capabilities.

[0213] The audio component 810 is configured to output and / or input audio signals. For example, the audio component 810 includes a microphone (MIC) that is configured to receive external audio signals when the electronic device 800 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 804 or transmitted via the communication component 816. In some embodiments, the audio component 810 also includes a speaker for outputting audio signals.

[0214] The input / output interface 812 provides an interface between the processing component 802 and peripheral interface modules, such as a keyboard, a click wheel, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0215] The sensor assembly 814 includes one or more sensors for providing various aspects of status assessment for the electronic device 800. For example, the sensor assembly 814 can detect the open / closed state of the electronic device 800, the relative positioning of components, such as the display and keypad of the electronic device 800. The sensor assembly 814 can also detect changes in the position of the electronic device 800 or a component of the electronic device 800, the presence or absence of user contact with the electronic device 800, the orientation or acceleration / deceleration of the electronic device 800, and temperature changes of the electronic device 800. The sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 814 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0216] The communication component 816 is configured to facilitate wired or wireless communication between the electronic device 800 and other devices. The electronic device 800 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0217] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0218] Those skilled in the art will also understand that the various illustrative logical blocks and steps listed in the embodiments of this application can be implemented through electronic hardware, computer software, or a combination of both. Whether such functions are implemented through hardware or software depends on the specific application and the design requirements of the entire system. Those skilled in the art may use various methods to implement the described functions for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of this application.

[0219] It should be understood that, unless otherwise specifically noted, the features of the various embodiments of the present disclosure described herein may be combined with each other. As used herein, the term "and / or" includes any one of the relevant listed items and any combination of any two or more thereof; similarly, "at least one of" includes any one of the relevant listed items and any combination of any two or more thereof.

[0220] It should be understood that, unless otherwise expressly specified or limited, the terms "join," "attach," "install," "connect," "connect," "fix," etc. used in the embodiments of the present disclosure should be understood in a broad sense. For example, they can be fixedly connected, detachably connected, or integrated; they can be mechanically connected, electrically connected, or communicable with each other; they can be directly connected, or indirectly connected through an intermediate medium, and they can be internally connected between two elements or an interactive relationship between two elements, unless otherwise expressly limited. For those skilled in the art, the specific meanings of the above terms in this article can be understood according to specific circumstances.

[0221] Although terms such as "first", "second" and "third" may be used herein to describe various components, parts, regions, layers or sections, these components, parts, regions, layers or sections are not limited to these terms. On the contrary, these terms are only used to distinguish one component, part, region, layer or section from another component, part, region, layer or section. Therefore, without departing from the teachings of each example, the first component, part, region, layer or section mentioned in the examples described herein may also be referred to as the second component, part, region, layer or section. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include at least one such feature. In the description herein, the meaning of "multiple" is at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0222] Furthermore, the word "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as advantageous over other aspects or designs. Rather, the use of the word exemplary is intended to present concepts in a concrete manner. As used herein, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X applies to A or B" is intended to mean any of the natural inclusive permutations. That is, if X applies to A; X applies to B; or X applies to both A and B, then "X applies to A or B" satisfies any of the aforementioned instances. Furthermore, the articles "a" and "an," as used in this application and the appended claims, are generally understood to mean "one or more," unless otherwise specified or clear from the context to refer to the singular form.

[0223] Likewise, although the present disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding this specification and the accompanying drawings. The present disclosure includes all such modifications and variations and is limited only by the scope of the claims. With particular regard to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, terms used to describe such components are intended to correspond to any component (functionally equivalent) that performs the specific function of the described component, even if not structurally equivalent to the disclosed structure. In addition, although particular features of the present disclosure may have been disclosed with respect to only one of several implementations, such features may be combined with one or more other features of other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms "include," "have," "have," "have," or variations thereof are used in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term "comprising."

[0224] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

[0225] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. An audio subsystem interface module, characterized in that: The audio subsystem interface module is connected between the peripheral bus interface module and the peripherals. The peripheral bus interface module is connected to the application processor chip and the digital signal processing chip respectively. The audio subsystem interface module includes multiple downlink path units, multiple loopback path units and an audio data transmission interface module. The multiple downstream path units are configured to perform downstream processing on at least one channel of digital audio data obtained from the application processor chip and / or the digital signal processing chip via the peripheral bus interface module, and output the digital audio data obtained after the downstream processing via the audio data transmission interface module. The multiple downstream path units include a first downstream path, a second downstream path, and a third downstream path. The first downstream path includes a first data buffer AP-FIFO, a first sampling rate conversion module AP-SRC, a first synchronous first-in-first-out data buffer SFIFO_AP, a first sink point, a first sound effect processing module DA0-SE0, a second synchronous first-in-first-out data buffer SFIFO_DA0_SE0, a second sound effect processing module DA-SE1, a third synchronous first-in-first-out data buffer SFIFO_DA0_SE1, and a second sink point, which are connected in sequence. The input end of the first data buffer AP-FIFO is connected to the first output end of the peripheral bus interface module, and the output end of the second sink point is connected to the first input end of the audio data transmission interface module. The plurality of loop path units are used to aggregate at least one channel of digital audio data input through the audio data transmission interface module and digital audio data obtained after downlink processing by any downlink path unit of the plurality of downlink path units, and output the digital audio data obtained after the aggregation processing through the audio data transmission interface module; The multiple downlink path units and the multiple loopback path units each include at least one synchronous first-in-first-out data buffer SFIFO, and the multiple synchronous first-in-first-out data buffers are used to implement the back pressure logic of the audio subsystem interface module; For the first downlink path, the backpressure logic includes the following steps: When the audio data transmission interface module generates a first initial back pressure signal, back pressure is applied to the third synchronous first-in-first-out data buffer SFIFO_DA0_SE1 based on the first initial back pressure signal; When the third synchronous FIFO_DA0_SE1 generates a nearly full backpressure signal, backpressure is applied to the second synchronous FIFO_DA0_SE0 by combining the nearly full backpressure signal and the busy backpressure signal generated by the second sound effect processing module DA-SE1; When the second synchronous FIFO data buffer SFIFO_DA0_SE0 generates a nearly full backpressure signal, backpressure is applied to the first synchronous FIFO data buffer SFIFO_AP by combining the nearly full backpressure signal and the busy backpressure signal generated by the first sound effect processing module DA0-SE0; When the first synchronous first-in-first-out data buffer SFIFO_AP generates a nearly full backpressure signal, backpressure is applied to the first data buffer AP-FIFO by combining the nearly full backpressure signal and a busy backpressure signal generated by the first sampling rate conversion module AP-SRC.

2. The audio subsystem interface module according to claim 1, wherein: The first downlink path is used to perform downlink processing on the first channel of digital audio data obtained from the application processor chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module; The second downlink path is used to perform downlink processing on the second channel of digital audio data obtained from the digital signal processing chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module; The third downlink path is used to perform downlink processing on the third channel of digital audio data obtained from the digital signal processing chip through the peripheral bus interface module, and output the digital audio data obtained after the downlink processing through the audio data transmission interface module.

3. The audio subsystem interface module according to claim 1, wherein: The second downlink path includes a second data buffer DA0-FIFO, a second sampling rate conversion module DA0-SRC, a fourth synchronous first-in-first-out data buffer SFIFO_DA0_SRC, a first convergence point, a first sound effect processing module DA0-SE0, a second synchronous first-in-first-out data buffer SFIFO_DA0_SE0, a second sound effect processing module DA-SE1, a third synchronous first-in-first-out data buffer SFIFO_DA0_SE1, and a second convergence point, wherein an input end of the second data buffer DA0-FIFO is connected to a second output end of the peripheral bus interface module; The third downlink path includes a third data buffer DA1-FIFO, a third sampling rate conversion module DA1-SRC0, a fifth synchronous first-in-first-out data buffer SFIFO_DA1_SRC0, a third sound effect processing module DA1-SE0, a sixth synchronous first-in-first-out data buffer SFIFO_DA1_SE0, the second sound effect processing module DA-SE1, a seventh synchronous first-in-first-out data buffer SFIFO_DA1_SE1, a third convergence point, a fourth sampling rate conversion module DA1-SRC1 and an eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1, which are connected in sequence. The input end of the third data buffer DA1-FIFO is connected to the third output end of the peripheral bus interface module, and the output end of the eighth synchronous first-in-first-out data buffer SFIFO-DA1-SRC1 is connected to the second input end of the audio data transmission interface module.

4. The audio subsystem interface module according to claim 3, characterized in that: For the second downlink path, the backpressure logic includes the following steps: When the audio data transmission interface module generates a first initial back pressure signal, back pressure is applied to the third synchronous first-in-first-out data buffer SFIFO_DA0_SE1 based on the first initial back pressure signal; When the third synchronous FIFO_DA0_SE1 generates a nearly full backpressure signal, backpressure is applied to the second synchronous FIFO_DA0_SE0 by combining the nearly full backpressure signal and the busy backpressure signal generated by the second sound effect processing module DA-SE1; When the second synchronous FIFO data buffer SFIFO_DA0_SE0 generates a nearly full backpressure signal, backpressure is applied to the fourth synchronous FIFO data buffer SFIFO_DA0_SRC by combining the nearly full backpressure signal and the busy backpressure signal generated by the first sound effect processing module DA0-SE0; When the fourth synchronous FIFO data buffer SFIFO_DA0_SRC generates a nearly full backpressure signal, the nearly full backpressure signal and the busy backpressure signal generated by the second sampling rate conversion module DA0-SRC are combined to perform backpressure on the second data buffer DA0-FIFO.

5. The audio subsystem interface module according to claim 3, wherein: For the third downlink path, the backpressure logic includes the following steps: When the audio data transmission interface module generates a second initial back pressure signal, back pressure is applied to the eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1 based on the second initial back pressure signal; When the eighth synchronous FIFO data buffer SFIFO_DA1_SRC1 generates a nearly full backpressure signal, backpressure is applied to the seventh synchronous FIFO data buffer SFIFO_DA1_SE1 by combining the nearly full backpressure signal and the busy backpressure signal generated by the fourth sampling rate conversion module DA1-SRC1; When the seventh synchronous FIFO data buffer SFIFO_DA1_SE1 generates a nearly full backpressure signal, backpressure is applied to the sixth synchronous FIFO data buffer SFIFO_DA1_SE0 by combining the nearly full backpressure signal and the busy backpressure signal generated by the second sound effect processing module DA-SE1; When the sixth synchronous FIFO data buffer SFIFO_DA1_SE0 generates a nearly full backpressure signal, backpressure is applied to the fifth synchronous FIFO data buffer SFIFO_DA1_SRC0 by combining the nearly full backpressure signal and the busy backpressure signal generated by the third sound effect processing module DA1-SE0; When the fifth synchronous FIFO data buffer SFIFO_DA1_SRC0 generates a nearly full backpressure signal, the third data buffer DA1-FIFO is backpressured by combining the nearly full backpressure signal and the busy backpressure signal generated by the third sampling rate conversion module DA1-SRC0.

6. The audio subsystem interface module according to claim 1, wherein: The plurality of loop path units include: a first loopback path for aggregating the fourth channel digital audio data and the fifth channel digital audio data inputted through the audio data transmission interface module with the digital audio data obtained after downlink processing by the second downlink path unit, and outputting the digital audio data obtained after the aggregating processing through the audio data transmission interface module; The second loopback path is used to aggregate the fourth channel digital audio data and the fifth channel digital audio data input through the audio data transmission interface module with the digital audio data obtained after downlink processing by the third downlink path unit, and output the digital audio data obtained after the aggregation processing through the audio data transmission interface module.

7. The audio subsystem interface module according to claim 6, characterized in that: The first loop path includes a fifth sampling rate conversion module AD1-SRC0, a loop path module ST, a ninth synchronous first-in-first-out data buffer SFIFO_ST0, and the second downlink path; wherein a first input end of the loop path module ST is connected to a first output end of the audio data transmission interface module via the fifth sampling rate conversion module AD1-SRC0, a second input end of the loop path module ST is connected to a second output end of the audio data transmission interface module, and a first output end of the loop path module ST is connected to a second sink point via the ninth synchronous first-in-first-out data buffer SFIFO_ST0; The second loop path includes the fifth sampling rate conversion module AD1-SRC0, the loop path module ST, a tenth synchronous first-in-first-out data buffer SFIFO_ST1 and the third downstream path; wherein the second output end of the loop path module ST is connected to the third sink point through the tenth synchronous first-in-first-out data buffer SFIFO_ST1.

8. The audio subsystem interface module according to claim 7, characterized in that: For the first loop path, the backpressure logic includes the following steps: When the audio data transmission interface module generates a first initial back pressure signal, back pressure is applied to the ninth synchronous first-in-first-out data buffer SFIFO_ST0 based on the first initial back pressure signal; When the ninth synchronous FIFO data buffer SFIFO_ST0 generates a nearly full backpressure signal, backpressure is applied to the first loop path based on the nearly full backpressure signal.

9. The audio subsystem interface module according to claim 7, wherein: For the second loop path, the backpressure logic includes the following steps: When the audio data transmission interface module generates a second initial back pressure signal, back pressure is applied to the eighth synchronous first-in-first-out data buffer SFIFO_DA1_SRC1 based on the second initial back pressure signal; When the eighth synchronous FIFO data buffer SFIFO_DA1_SRC1 generates a nearly full backpressure signal, backpressure is applied to the tenth synchronous FIFO data buffer SFIFO_ST1 in combination with the nearly full backpressure signal and the busy backpressure signal generated by the fourth sampling rate conversion module DA1-SRC1; When the tenth synchronous FIFO data buffer SFIFO_ST1 generates a nearly full backpressure signal, backpressure is applied to the second loop path based on the nearly full backpressure signal.

10. The audio subsystem interface module according to claim 1, wherein: The audio subsystem interface module also includes: Multiple uplink path units are used to perform uplink processing on at least one channel of digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing to the application processor chip and / or the digital signal processing chip through the peripheral bus interface module.

11. The audio subsystem interface module according to claim 10, characterized in that: The multiple uplink path units include: a first uplink path, configured to perform uplink processing on the fourth channel digital audio data and the fifth channel digital audio data inputted through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing to the application processor chip through the peripheral bus interface module; a second uplink path for performing uplink processing on the fourth channel of digital audio data inputted through the audio data transmission interface module, and outputting the digital audio data obtained after the uplink processing to the digital signal processing chip through the peripheral bus interface module; The third uplink path is used to perform uplink processing on the fifth channel of digital audio data input through the audio data transmission interface module, and output the digital audio data obtained after the uplink processing to the digital signal processing chip through the peripheral bus interface module.

12. The audio subsystem interface module according to claim 11, characterized in that: The first uplink path includes a fifth sampling rate conversion module AD1-SRCO, a fourth sound effect processing module AD1-SE, a fifth sound effect processing module AD0-SE, a multiplexer AP-MUX, a first sampling rate conversion module AP-SRC connected in sequence to an output end of the multiplexer AP-MUX, and a first data buffer AP-FIFO. The fifth sampling rate conversion module AD1-SRCO and the fourth sound effect processing module AD1-SE are connected in series and then connected to a first input end of the multiplexer AP-MUX. The fifth sound effect processing module AD0-SE is connected to a second input end of the multiplexer AP-MUX. The input end of the fifth sampling rate conversion module AD1-SRCO is connected to a first output end of the audio data transmission interface module, and the input end of the fifth sound effect processing module AD0-SE is connected to a second output end of the audio data transmission interface module. The second uplink path includes a fifth sound effect processing module AD0-SE, a sixth sampling rate conversion module AD0-SRC and a fourth data buffer AD0-FIFO connected in sequence; The third uplink path includes the fifth sampling rate conversion module AD1-SRC0, the fourth sound effect processing module AD1-SE, the seventh sampling rate conversion module AD1-SRC1 and the fifth data buffer AD1-FIFO connected in sequence.

13. The audio subsystem interface module according to any one of claims 1 to 12, characterized in that: The audio subsystem interface module includes three levels of clock gating, which includes first-level clock gating, second-level clock gating and third-level clock gating. The second-level clock gating is generated based on the first-level clock gating, and the third-level clock gating is generated based on the second-level clock gating.

14. The audio subsystem interface module according to claim 13, wherein: The second audio effect processing module DA-SE1 is provided with the first level clock gating; The first downlink path, the second downlink path, the third downlink path, the first loop path, the second loop path, the second uplink path and the third uplink path are provided with the second-level clock gating; The first sampling rate conversion module AP-SRC, the second sampling rate conversion module DA0-SRC, the third sampling rate conversion module DA1-SRC0, the first sound effect processing module DA0-SE0, the third sound effect processing module DA1-SE0, the fourth sampling rate conversion module DA1-SRC1, the fifth sampling rate conversion module AD1-SRC0, the sixth sampling rate conversion module AD0-SRC, the seventh sampling rate conversion module AD1-SRC1, the fourth sound effect processing module AD1-SE and the fifth sound effect processing module AD0-SE are provided with the third level clock gating.

15. The audio subsystem interface module according to any one of claims 1 to 12, characterized in that: The audio data transmission interface module includes multiple audio data transmission interface sub-modules, each of which includes an asynchronous first-in-first-out data buffer and a protocol processing module, and the APB bus clock domain pclk of each audio data transmission interface sub-module is independently controlled.

16. An audio SOC chip, characterized in that: include: An application processor chip, a digital signal processing chip, a peripheral bus interface module, and an audio subsystem interface module according to any one of claims 1 to 15; wherein, The application processor chip and the digital signal processing chip are respectively connected to the peripheral bus interface module, and the peripheral bus interface module is connected to the peripheral device through the audio subsystem interface module.

17. An electronic device, characterized in that: include: The audio SOC chip as claimed in claim 16.

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