Data writing method, storage device and computer readable storage medium

Abstract

The invention discloses a data writing method, a storage device and a computer readable storage medium. The method comprises the following steps: starting a timing operation in response to starting writing in a current storage area; in response to the fact that timing time generated by the timing operation is larger than preset time, invalid data are written into the current storage area to fully store the current storage area, and therefore corresponding reading voltage is set for the current storage area; wherein in response to the fact that the current storage area is full, the timing time of the timing operation is reset so as to be used for timing operation of the next storage area. By means of the mode, the influence of data write amplification can be reduced while the reading performance of the storage device is guaranteed.

Description

Technical Field

[0001] The present application relates to the field of storage, and in particular to a data writing method, a storage device, and a computer-readable storage medium. Background Art

[0002] In the field of NAND Flash storage, with the continuous evolution of 3D technology, the number of NAND stacking layers is increasing, resulting in higher storage density and larger capacity per memory block. However, larger memory blocks are more prone to QoS and write amplification issues in practical applications. In practice, the speed at which a host writes data to a storage device is not uniform; more data may be written during certain time periods and less during other time periods. This can lead to significant differences in storage voltage distributions between data written earlier and later within the same memory block due to different retention times. This can lead to more data errors when reading the memory block using the same read voltage standard, impacting QoS. However, if open blocks are closed too quickly, invalid data is written to fill the memory block, leaving more areas within the memory block without valid data, wasting storage space and causing write amplification. Therefore, when writing data to large-capacity memory blocks, QoS and write amplification issues conflict with each other. Summary of the Invention

[0003] The main purpose of this application is to provide a data writing method, a storage device and a computer-readable storage medium, which can solve the technical problem of the contradiction between QoS and write amplification when storing data.

[0004] To address the aforementioned technical issues, the first technical solution employed in this application is to provide a data writing method. This method is applied to a storage device comprising multiple storage blocks, each of which comprises at least two storage areas. The method comprises initiating a timing operation in response to the start of writing to a current storage area; in response to a timing time generated by the timing operation being greater than a preset time, writing invalid data to the current storage area to fill the current storage area, thereby setting a corresponding read voltage for the current storage area; wherein, in response to the current storage area being full, the timing time of the timing operation is reset to zero to prepare for the timing operation of the next storage area.

[0005] To solve the above technical problem, the second technical solution adopted in this application is to provide a storage device. The storage device includes a memory and a processor, the memory is used to store program data, and the program data can be executed by the processor to implement the method described in the first technical solution.

[0006] To solve the above technical problems, the third technical solution adopted by this application is to provide a computer-readable storage medium that stores program data and can be executed by a processor to implement the method described in the first technical solution.

[0007] The beneficial effects of the present application are as follows: a storage block is divided into regions, each storage block is divided into at least two storage regions, and a timing is performed when writing to the current storage region, based on the storage region as a judgment standard. If the timing exceeds a preset time, the current storage region is filled with invalid data, and a corresponding read voltage is set for the current storage region. By dividing the storage block into storage regions, using the smaller storage region as the unit to be turned on and off when writing data, and setting a corresponding read voltage for each storage region, data space wasted during write amplification is reduced, thereby minimizing the impact of data write amplification while ensuring the read performance of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 This is a schematic diagram of the data storage threshold voltage when the storage block is not closed in time;

[0010] Figure 2 This is a flow chart of the first embodiment of the data writing method of the present application;

[0011] Figure 3 This is a schematic diagram of data state voltage distribution for invalid data;

[0012] Figure 4 It is a programming diagram of type C / third invalid data;

[0013] Figure 5 is a schematic diagram of a command from an external controller when a storage device control unit generates invalid data;

[0014] Figure 6 This is a flow chart of the second embodiment of the data writing method of the present application;

[0015] Figure 7 This is a flow chart of the third embodiment of the data writing method of the present application;

[0016] Figure 8 This is a schematic diagram of invalid data writing;

[0017] Figure 9 This is a schematic structural diagram of an embodiment of a storage device of the present application;

[0018] Figure 10 It is a structural diagram of an embodiment of a computer-readable storage medium of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] The terms "first," "second," and the like in this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements, but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0021] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0022] In the field of storage, if the capacity of a storage block is large and the frequency of writing data to the storage block is low and the speed is slow, then if the storage block is not closed in time, the data stored in the same storage block will have more read errors when read according to a set of read voltages, affecting the read performance of the storage device. If the storage block is closed after a certain period of time, too much invalid data may be written, wasting a lot of storage space. Specifically, if Figure 1 As shown, Figure 1This diagram illustrates the data storage threshold voltage distribution when a storage block is not closed in a timely manner. When data 1 is first written, its storage threshold voltage is Vt1 (solid line). For a long period after writing data 1, the host does not write new data to the storage block. Due to this, the threshold voltage of data 1 decreases, shifting to the right, due to retention. At some point, when the host writes new data, data 2, to the same storage block, the storage threshold voltage of data 1 shifts to Vt2 (dashed line), while the storage threshold voltage of data 2 remains at Vt1. At this point, the voltage distributions of Vt1 and Vt2 differ significantly. Whether using Vt1's read voltage (Vt1Vrd), Vt2's read voltage (Vt2Vrd), or any other set of read voltage standards, a high number of error bits will occur. Due to hardware limitations, storage systems cannot set a corresponding read voltage for every piece of data. Therefore, when a storage block contains a large number of data written at long intervals, reading data using the read voltage corresponding to that storage block can easily trigger a reread, impacting storage system read performance. If a storage block is closed immediately, Data 1 and Data 2, which were written at a longer interval, will be stored in different storage blocks. The remaining storage space in the storage block corresponding to Data 1 will be wasted, causing write amplification. Closing a storage block means that valid user data will no longer be written to it before an erase operation is performed on it. Closing a storage area, described later, is similar: valid user data will no longer be written to it before an erase operation is performed on that storage area.

[0023] Therefore, in order to balance the contradiction between data reading performance and write amplification, this application divides the storage block into multiple areas, uses each area in the storage block as the opening and closing unit for data writing, and sets corresponding read voltages for it. By setting multiple sets of read voltages for a storage block, the impact of storage block write amplification is reduced, thereby ensuring the data reading performance of the storage block.

[0024] Reference Figure 2 , Figure 2 This is a flow chart of the first embodiment of the data writing method of this application. The method is applied to a storage device, which includes multiple storage blocks, each storage block including at least two storage areas. The method includes the following steps:

[0025] S11: In response to the start of writing to the current storage area, a timing operation is started.

[0026] Each memory block includes multiple memory pages. The memory block is divided into memory pages. Each memory area includes at least one memory page. When data is written to a memory area, the timing operation corresponding to the memory area begins.

[0027] S12: In response to the timing time generated by the timing operation being greater than the preset time, writing invalid data into the current storage area to fill the current storage area, thereby setting a corresponding read voltage for the current storage area.

[0028] The preset time is the maximum time from the start of writing data to the storage area to the data written to the storage area without causing a storage threshold voltage shift. The size of the storage area must also be determined based on the preset time. The amount of data reached by continuously writing data within the preset time is the maximum capacity, and the capacity of the allocated storage area must not exceed this maximum capacity. This ensures that when data is continuously written to the storage area within the preset time, that is, when data is written at the maximum speed, the storage area will not be underfilled. In other words, even if data is written at the maximum speed, the storage threshold voltage of the initially written data in the storage area will not shift.

[0029] If the current storage area is full within the preset time, or becomes full after writing invalid data, the timer is reset and used again for the next storage area. It is conceivable that the timer can start from zero or start counting down from a preset time. If it starts from zero, it is reset and restarted when it is full. If it starts counting down from a preset time, it is reset and restarted when it is full. Both methods are equivalent and can be used as the technical operations of this application.

[0030] After a storage area is full, the storage area is closed and a read voltage is set for the storage area for subsequent reading of data within the storage area. Since the write voltages may differ when data is written, different read voltages can be set for different storage areas accordingly. The read voltage setting can be related to the write voltage. In the storage block of this embodiment, each storage area has a corresponding set of read voltage configurations, and the read voltage configurations corresponding to each area can be set to be the same or different. Each storage block has at least two storage areas, which correspond to at least two sets of read voltage configurations, and these two sets of read voltage configurations can be the same or different.

[0031] In this embodiment, the memory blocks are divided into regions, with each memory block being divided into at least two storage regions. Using the storage region as a criterion, a timer is started when writing begins in the current storage region. If the timer exceeds a preset time, the current storage region is filled with invalid data, and a corresponding read voltage is set for the current storage region. By dividing the memory blocks into storage regions, using the smaller storage region as the unit to be turned on and off during data writing, and setting a corresponding read voltage for each storage region, data space wasted during write amplification is reduced, minimizing the impact of data write amplification while maintaining the read performance of the storage device.

[0032] In one embodiment, the invalid data used to fill the storage area includes at least one of the following: first invalid data including at least two data states; second invalid data having only one data state, and the storage voltage of the data state is distributed within a first voltage range; third invalid data having only one data state, and the storage voltage of the data state is distributed within a second voltage range, and the second voltage range is greater than the first voltage range.

[0033] The first invalid data is data with a relatively even distribution of 0 and 1. For example, for SLC, it has two data states 0 and 1, and these two data states are evenly distributed in the data stored in the storage area. For MLC, it has four data states 00, 01, 10, and 11, and these four data states are evenly distributed in the data stored in the storage area. Or for TLC, it has eight data states 000, 001, 010, 011, 100, 101, 110, and 111, and these eight data states are evenly distributed in the data stored in the storage area.

[0034] The second invalid data has only one data state. For example, for SLC, one of the data states 0 or 1 is selected as the data state of the second invalid data. For MLC, one of the four data states 00, 01, 10, and 11 is selected as the data state of the second invalid data. For TLC, one of the eight data states is selected as the data state of the second invalid data. The data state of the second invalid data is one of the data states of the first invalid data.

[0035] The third invalid data has only one data state. The third invalid data is similar to the second invalid data, but the second voltage range corresponding thereto is greater than the first voltage range corresponding to the data state of the second invalid data.

[0036] like Figure 3 As shown, Figure 3 FIG. 1 is a schematic diagram of data state voltage distribution of invalid data. Figure 3 Type A is the storage voltage distribution of eight data states in TLC. When the first invalid data is written to the storage area, the eight data states are evenly distributed. Figure 3 TypeB is the second invalid data, which is a data state of the first invalid data. Figure 3 Type C is the third invalid data, which is similar to the second invalid data, except that the voltage distribution range of the data state of the third invalid data is greater than the voltage distribution range of the data state of the second invalid data.

[0037] The first and second invalid data are used to program one memory cell at a time, while the third invalid data is used to program at least two memory cells at a time. The first invalid data is similar to the user data, while the second invalid data has a narrower voltage distribution range. Therefore, the first and second invalid data can only program one memory cell at a time. However, the third invalid data, due to its wider voltage distribution range, can be programmed in parallel to program multiple memory cells at a time. A memory cell can be a single bit.

[0038] like Figure 4 As shown, Figure 4 This is a schematic diagram of programming type C / third invalid data.

[0039] exist Figure 4 In the example, the third invalid data of all memory cells between WLx TSG0 and the last TSG of WLy can be programmed in one programming operation, while only one TSG can be enabled at a time for programming the first invalid data and the second invalid data.

[0040] The voltage distribution range of a single data state of the first and second invalid data is relatively narrow, and their distribution requirements are relatively high. Therefore, each programming requires the participation of the TSG in controlling program verification. However, since the data state distribution range of the third invalid data is relatively wide, program verification is not required when writing the third invalid data to the current storage area.

[0041] The purpose of using only one data state for the second and third invalid data is to reduce invalid data filling time and improve storage device performance. Using the second invalid data filling method involves programming each corresponding memory cell to a single data state. Since the data state is the same, the starting voltage, verification voltage, and verification method can be adjusted to complete programming as quickly as possible. For the third invalid data, using the third invalid data filling method allows for simultaneous programming of multiple memory cells with a single programming pulse of an appropriate voltage, and can selectively eliminate the programming verification process, significantly reducing programming time.

[0042] In one embodiment, the storage device further includes a control unit, and the invalid data is generated by the control unit or by the storage block itself. If the invalid data is generated by the control unit of the storage device, the control unit of the storage device inputs the invalid data to the storage block; if the invalid data is not generated by the control unit of the storage device, the storage block needs to generate the invalid data itself.

[0043] like Figure 5 As shown, Figure 5Schematic diagram of the controller's commands when generating invalid data for a memory block of a storage device. The first type of fill, type A / B DMY, is used to fill the first or second invalid data. The storage device's control unit sends a CMD1 program command and ADDR1 to the memory array (memory block). ADDR1 is the address of the memory cell. The memory array of the storage device then programs the data into the corresponding memory cell according to ADDR1. The second type of fill, type C DMY, is used to fill the third invalid data. The storage device's control unit sends CMD1, ADDR1, and ADDR2 to the memory array (memory block). The memory array then programs all memory cells between ADDR1 and ADDR2 according to ADDR1 and ADDR2.

[0044] Reference Figure 6 , Figure 6 This is a flow chart of the second embodiment of the data writing method of this application. This method is a further extension of the above embodiment and includes the following steps:

[0045] S21: During the invalid data writing process, in response to receiving a data writing command, the writing of the invalid data is stopped, and data is written to the current storage area according to the data writing command.

[0046] When writing invalid data to the current storage area to fill the current storage area, if a data write command is received when the current storage area is not full during the invalid data writing process, the writing of the invalid data is stopped and the new data is written to the current storage area according to the data write command.

[0047] S22: In response to the current storage area not being full, continue writing invalid data into the current storage area.

[0048] After writing data into the current storage area according to the data write command, if the current storage area is still not full, invalid data continues to be written into the current storage area.

[0049] The manner of continuing to write invalid data is the same as the manner of starting to write invalid data to the storage area in response to the timing time being greater than the preset time, which can refer to the manner described in the following embodiment.

[0050] Reference Figure 7 , Figure 7 This is a flow chart of the third embodiment of the data writing method of this application. This method is a further extension of step S13 and includes the following steps:

[0051] S31: Writing first invalid data into a first storage page that has stored data but is not full.

[0052] In a storage device, each storage block includes multiple storage pages, and each storage area includes at least one storage page. When writing invalid data to a storage area, it is first determined whether the storage page where the data was last written is full. If it is determined that a first storage page that has stored data but is not full exists, indicating that the storage page where the data was last written is not full, the first invalid data is written to the page.

[0053] S32: After the writing is completed, in response to the current storage area not being full, writing second invalid data into a second storage page adjacent to the first storage page and not storing any data.

[0054] After the first storage page is filled, it is determined whether the current storage area corresponding to the first storage page is full. If not, second invalid data is written to a second storage page adjacent to the first storage page and not storing any data.

[0055] If the current storage area is full, there is no need to write invalid data, close the current storage area, and process the next storage area according to the command.

[0056] S33: After the writing is completed, in response to the current storage area not being full, third invalid data is written to a third storage page in the current storage area that does not store data.

[0057] If the current storage area is not full after the second invalid data is written, the third invalid data is written to a third storage page in the current storage area that has not stored any data to fill the current storage area.

[0058] like Figure 8 As shown, Figure 8 This diagram illustrates writing invalid data. In the block diagram, assume that data writing begins with data UD1 in WL0 of storage area zone 1. After the write is complete, in response to a timeout exceeding a preset time, the first invalid data is written, DMY1, to the first, partially filled storage page WL1. DMY1 protects the data below DMY1 and introduces a coupling effect, raising the voltage of the data below it (WL0 TSG3) to a level close to that of the other user data.

[0059] In response to zone 1 still not being full, the second invalid data DMY2 is written to the adjacent page WL2 where no data is stored in WL1. The function of DMY2 is similar to that of DMY1, which is to make the voltage of all user data on WL1 close to that on WL0.

[0060] In response to zone 1 not being full, the third invalid data DMY3 is written to the third storage page in zone 1 that does not store data, thereby filling zone 1. The function of DMY3 is to prevent a large number of erased states from existing between UD1 and UD2, which violates the write requirement and makes UD2 susceptible to program disturbance, affecting the data reliability of UD2.

[0061] The first, second, and third invalid data all improve data reliability. The first and second invalid data raise the voltage of the underlying user data, making the voltage of all user data consistent. The third data prevents a large number of erased memory cells within a storage area from affecting the reliability of user data in different areas.

[0062] After zone 1 is full, the corresponding read voltage is saved according to the write voltage, so that the data in the zone can be read according to the corresponding read voltage. The data writing process of zone 2 is similar and will not be repeated here.

[0063] The selection of the first invalid data, the second invalid data, and the third invalid data can be adjusted based on actual conditions. If experiments show that the second invalid data and the third invalid data can meet the voltage requirements of the memory cell where the first invalid data is located, the first memory page that has stored data but is not fully stored can also be written with the second invalid data or the third invalid data. If the third invalid data can meet the voltage requirements of the memory cell where the second invalid data is located, the second memory page can also be written with the third invalid data.

[0064] Regardless of whether a data write command is received at any stage of writing the first invalid data, the second invalid data, or the third invalid data, the writing of the invalid data is stopped, and writing is performed according to the data write command. After completing the writing of the data write command, the first invalid data, the second invalid data, and the third invalid data are written in sequence according to the steps.

[0065] like Figure 9 As shown, Figure 9 This is a structural diagram of an embodiment of a storage device of the present application.

[0066] The storage device includes a processor 110 and a memory 120 .

[0067] The processor 110 controls the operation of the electronic device and may also be referred to as a CPU (Central Processing Unit). The processor 110 may be an integrated circuit chip with the ability to process signal sequences. The processor 110 may also be a general-purpose processor, a digital signal sequence processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. The general-purpose processor may be a microprocessor or any conventional processor.

[0068] The memory 120 stores instructions and program data required for the processor 110 to operate.

[0069] The processor 110 is configured to execute instructions to implement the method provided by any one of the embodiments and possible combinations of the aforementioned data writing methods of the present application.

[0070] like Figure 10 As shown, Figure 10 This is a structural diagram of an embodiment of a computer-readable storage medium of the present application.

[0071] An embodiment of the readable storage medium of the present application includes a memory 210, and the memory 210 stores program data. When the program data is executed, the method provided by any embodiment and possible combination of the data writing method of the present application is implemented.

[0072] The memory 210 may include a medium that can store program instructions, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or it may be a server that stores the program instructions. The server may send the stored program instructions to other devices for execution, or it may execute the stored program instructions itself.

[0073] In summary, the present application divides storage blocks into regions, dividing each storage block into at least two storage regions. Using the storage region as a criterion, a timer is run when writing begins in the current storage region. If the timer exceeds a preset time, the current storage region is filled with invalid data, and a corresponding read voltage is set for the current storage region. By dividing the storage block into storage regions, using the smaller storage region as the unit to be turned on and off when writing data, and setting a corresponding read voltage for each storage region, data space wasted during write amplification is reduced, minimizing the impact of data write amplification while ensuring the read performance of the storage device.

[0074] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of modules or units is merely a logical functional division. In actual implementation, other division methods may be used. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented.

[0075] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0076] In addition, each functional unit in each embodiment of the present application may be integrated into a processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit. The above-mentioned integrated units may be implemented in the form of hardware or software functional units.

[0077] If the integrated units in the above other embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the various implementation methods of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0078] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A data writing method, characterized in that: Applied to a storage device, the storage device includes a plurality of storage blocks, each storage block includes at least two storage areas, the method includes: In response to starting writing to the current storage area, starting a timing operation; In response to a timing time generated by the timing operation being greater than a preset time, writing invalid data into the current storage area to fill the current storage area, thereby setting a corresponding read voltage for the current storage area; In response to the current storage area being full, the timing time of the timing operation is reset to zero for the timing operation of the next storage area.

2. The method according to claim 1, characterized in that The invalid data includes at least one of the following: first invalid data including at least two data states; second invalid data having only one data state, wherein storage voltages of the data state are distributed within a first voltage range; The third invalid data has only one data state, and a storage voltage of the data state is distributed within a second voltage range, and the second voltage range is greater than the first voltage range.

3. The method according to claim 2, characterized in that The first invalid data and the second invalid data are used to program one memory cell at a time, and the third invalid data is used to program at least two memory cells at a time.

4. The method according to claim 2, characterized in that The method further comprises: Program verification is not performed when the third invalid data is written to the current storage area.

5. The method according to claim 1, wherein The storage device further includes a control unit, and the invalid data is generated by the control unit or by the storage block itself.

6. The method according to claim 1, characterized in that Writing invalid data into the current storage area to fill up the current storage area includes: During the invalid data writing process, in response to receiving a data writing command, the writing of the invalid data is stopped, and data is written to the current storage area according to the data writing command.

7. The method according to claim 6, characterized in that After writing data to the current storage area according to the data write command, the method includes: In response to the current storage area being not full, the invalid data continues to be written into the current storage area.

8. The method according to claim 2, characterized in that Each of the storage blocks includes a plurality of storage pages, each of the storage areas includes at least one storage page, and writing invalid data to the current storage area includes: Writing the first invalid data into a first storage page that has stored data but is not full; After the writing is completed, in response to the current storage area not being full, writing the second invalid data into a second storage page adjacent to the first storage page and not storing any data; After the writing is completed, in response to the current storage area not being full, the third invalid data is written to a third storage page in the current storage area that does not store data.

9. A storage device, characterized in that: The system comprises a memory and a processor, wherein the memory is used to store program data, and the program data can be executed by the processor to implement the method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that Program data is stored and can be executed by a processor to implement the method according to any one of claims 1 to 8.

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