Element index collection execution method and system of vector register and storage medium

Abstract

The invention is suitable for the technical field of vector processors, and particularly relates to an element index collection execution method and system of a vector register and a storage medium. The element index collection and execution system comprises a vector register file, an instruction transmitting unit, an index collection and execution unit and an instruction write-back unit. The vector register file is used for storing multiple groups of source vector data and multiple groups of index vector data; the instruction transmitting unit is used for reading source vector data and index vector data in the vector register file; and the index collection execution unit is used for performing index search execution processing on the received source vector data and index vector data. Compared with the prior art, the method has the advantages that the source vector register data cache and the index vector register data cache are used for sequentially storing the source vector data and the index vector data which are possibly accessed in the vector register file, so that the reading request is prevented from being repeatedly sent by the vector register file; therefore, the index collection execution unit is decoupled from the access of the vector register file.

Description

Technical Field

[0001] The present invention is applicable to the technical field of vector processors, and in particular relates to a method, system and storage medium for collecting and executing element indexes of a vector register. Background Art

[0002] Vector processors are commonly used to accelerate data-parallel tasks. Vector processor instructions typically target a register group, which can contain multiple vector registers, each of which contains multiple parallel elements. For example, a vector instruction specifies a register group containing four vector registers with an 8-bit element width. When each vector register is 128 bits wide, each vector register contains 16 elements, for a total of 64 elements in a register group. In practical applications, data calculations processed by vector processors may require access to non-contiguous or irregularly distributed data. Therefore, vector processors include many instructions to handle such scenarios. Vector register index gather is one such instruction. By using the values of each element in the first register group as an index, it reads the source vector elements in the second register group and writes them back to the destination register group, thereby collecting irregular data. For example, suppose an index vector register group contains 64 elements, each of which points to any one of the 64 elements in the source vector register group. The source vector element pointed to by the element is written back to the corresponding position in the destination register according to the arrangement of the elements in the index vector register group, thus collecting non-contiguous and irregularly distributed data.

[0003] In the field of vector processing, existing technical solutions usually request to read part of the index vector register and the source vector register from the register file. After traversing the part of the index vector, it requests to read the next part until all the vector elements of the destination register are obtained. The following are two typical existing technologies: The first prior art uses vector elements as the minimum processing unit, reads a number of index vector elements and source vector elements each time, retrieves the valid indexed elements in the source vector elements and writes them back to the destination register. The specific process is as follows: 1. Based on the vector element value V of the current index, request to read W consecutive index vector elements after the vector index value from the register file and write them into the first operation buffer; 2. Using V as the address, request to read W consecutive source vector elements from the register file and write them into the second operation buffer; 3. Check whether each index vector in the first operation buffer points to the second operation buffer. Within one clock cycle, write the element in the second operation buffer indexed by the first operation buffer to the third operation buffer, and update the completion flag corresponding to each index vector element in the first operation buffer. 4. Repeatedly read new source vector elements until all the W index vector elements in the group are indexed, and then continue to read the next group of W index vector elements for processing until all the index vector elements are indexed. The second prior art uses a vector register as a processing unit (a vector register contains multiple vector elements). The specific process is as follows: 1. Request the register file to return an index vector register; 2. Request the register file to return a source vector register that holds the indexed element; 3. Find the element in the source vector register that corresponds to the element in the index vector register, write it to the corresponding position in the destination register buffer, and mark the element in the index vector register that has been found; 4. Repeat steps 2-3 until all elements in the index vector register are indexed. At this point, the elements of one destination vector register are generated and written back to the register file. 5. Repeat steps 1-4 until all destination registers in the register bank are written back to the register file.

[0004] The above-mentioned existing technologies all repeatedly request the register stack to read part of the operation data, and then send a read request to read the next piece of data after the execution of part of the data is completed. Although this method can make the execution path occupy less area resources, it has obvious defects: each time a read request is sent to the register, it depends on the data returned last time to complete the execution within the unit, and there is a certain delay in reading the vector register value returned by the register stack; when the target register group to be executed contains multiple vector registers, read requests will be frequently sent to the register stack, and when the register read request is busy, the execution delay will be further increased. In addition, when there are multiple index values with similar values in the index vector register group, these index values usually point to the same piece of vector registers, but because these index values are distributed far apart in space, it will cause a single instruction execution to require multiple requests to the register stack for the same piece of vector registers, resulting in low instruction execution efficiency.

[0005] Therefore, there is an urgent need for a new vector register element index collection execution method, system and storage medium to solve the above technical problems. Summary of the Invention

[0006] The present invention provides a method, system and storage medium for executing element index collection of vector registers, aiming to avoid repeatedly sending read requests to the register stack, reduce the execution delay of vector register index collection instructions, and reduce hardware overhead by multiplexing the same execution path through the bit width of each element.

[0007] In a first aspect, the present invention provides an element index collection execution system for a vector register, the element index collection execution system comprising a vector register stack, an instruction issue unit, an index collection execution unit, and an instruction write-back unit; The vector register file is used to store multiple groups of source vector data and multiple groups of index vector data; The instruction issuing unit is configured to read the source vector data and the index vector data in the vector register file, and to transmit the source vector data and the index vector data to the index gathering and executing unit; The index collection execution unit is used to perform index lookup execution processing on the received source vector data and the index vector data to obtain a result to be written back; and send the result to be written back to the instruction write back unit; The instruction write-back unit is configured to write the received result to be written back into a destination register in the vector register file.

[0008] The index collection execution unit includes a source vector register data cache, an index vector register data cache, a source vector interleaving unit, an index interleaving unit, an element search execution path and a destination register data cache; The source vector register data cache is used to store the source vector data; The index vector register data cache is used to store the index vector data; The source vector interleaving unit is configured to read the source vector data in the source vector register data cache and perform interleaving processing on the source vector data, and send the interleaved source vector data to the element search execution path; The index interleaving unit is configured to read the index vector data in the index vector register data cache and perform interleaving processing on the index vector data, and send the interleaved index vector data to the element search execution path; The element search execution path is used to search in parallel for elements of the source vector data corresponding to index elements of the index vector data to obtain the results to be written back; and send the results to be written back to the destination register data cache; The destination register data cache is used to store the received result to be written back and send the result to be written back to the instruction write back unit.

[0009] Preferably, when the number of vector registers read by the instruction issuing unit in the vector register file is one, the instruction issuing unit transmits the source vector data and the index vector data to the source vector interleaving unit and the index interleaving unit respectively; When the number of vector registers in the vector register file read by the instruction issuing unit is greater than one, the instruction issuing unit sends the source vector data and the index vector data to the source vector register data cache and the index vector register data cache, respectively.

[0010] Preferably, when the number of vector registers in the vector register stack read by the instruction emission unit is greater than one, after the instruction emission unit transmits the first group of the source vector data and the index vector data to the source vector register data cache and the index vector register data cache, the source vector interleaving unit and the index interleaving unit directly read the source vector data and the index vector data respectively for interleaving processing.

[0011] Preferably, the element search execution path is further used to add an index completion flag to the index element in the index vector data whose indexing is completed.

[0012] In a second aspect, the present invention further provides a method for collecting and executing element indexes of a vector register. The method is based on the system for collecting and executing element indexes of a vector register as described in the above embodiment, and comprises the following steps: S1, the instruction issuing unit issues a read request to the vector register file to read the source vector data and index vector data in the vector register file; S2, when the number of vector registers read by the instruction issuing unit in the vector register file is greater than one; the instruction issuing unit transmits the source vector data and the index vector data to the source vector register data cache and the index vector register data cache respectively for storage; the source vector interleaving unit reads the source vector data from the source vector register data cache, and the index interleaving unit reads the index vector data from the index vector register data cache; When the number of vector registers in the vector register file read by the instruction issuing unit is equal to one, the instruction issuing unit transmits the source vector data and the index vector data to the source vector interleaving unit and the index interleaving unit respectively; S3, interleaving the source vector data and the index vector data respectively through the source vector interleaving unit and the index interleaving unit, and sending the interleaved source vector data and the index vector data to the element search execution path; S4. Searching in parallel through the element search execution path for elements of the source vector data corresponding to the index elements of the interleaved index vector data to obtain a result to be written back; and sending the result to be written back to the destination register data cache; S5. Sending the result to be written back to the instruction write-back unit through the destination register data cache; S6. Write the result to be written back into a destination register in the vector register file through the instruction write back unit.

[0013] In the third aspect, the present invention also provides a computer device, comprising: a memory, a processor, and an element index collection execution program for a vector register stored on the memory and runnable on the processor, wherein the processor implements the steps in the element index collection execution method for a vector register as described in any one of the above embodiments when executing the element index collection execution program for the vector register.

[0014] In a fourth aspect, the present invention also provides a computer-readable storage medium, on which a vector register element index collection execution program is stored. When the vector register element index collection execution program is executed by a processor, the steps in the vector register element index collection execution method as described in any one of the above embodiments are implemented.

[0015] Compared with the prior art, the present invention stores source vector data and index vector data that may be accessed in the vector register stack in sequence through the source vector register data cache and the index vector register data cache, thereby avoiding repeated sending of read requests to the vector register stack, thereby decoupling the index collection execution unit from the access of the vector register stack, being more conducive to pipeline execution and reducing execution delay; when no more than one vector register is read in the vector register stack, the present invention can fully perform pipeline operation, further improving efficiency; and through the source vector interleaving unit and the index interleaving unit, the source vector data and the index vector data are interleaved respectively, which can enable different vector element bit widths to reuse an element search execution path, thereby reducing hardware overhead. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings: Figure 1 1 is a schematic diagram of the structure of a vector register element index collection and execution system provided by an embodiment of the present invention; Figure 2 This is a flowchart of a method for collecting and executing element indexes of a vector register provided by an embodiment of the present invention; Figure 3 It is a structural diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0018] Example 1 The embodiment of the present invention provides an element index collection execution system for a vector register, please refer to Figure 1 , Figure 1 It is a structural diagram of an element index collection and execution system 100 of a vector register provided by an embodiment of the present invention, wherein the element index collection and execution system includes a vector register stack 1, an instruction emission unit 2, an index collection and execution unit 3, and an instruction write-back unit 4.

[0019] The vector register file 1 is used to store multiple groups of source vector data and multiple groups of index vector data.

[0020] Indexing Vector Elements refers to the process of locating, accessing, or manipulating one or more elements in a vector (which can be understood as an ordered sequence of elements, such as an array or list) by using an index, that is, the position of the element in the vector.

[0021] Source Vector Elements are elements contained in a vector that serves as the source of data. Their core function is to provide raw data or input information for an operation.

[0022] The instruction issuing unit 2 is used to read the source vector data and the index vector data in the vector register file 1, and transmit the source vector data and the index vector data to the index collection and execution unit 3. Specifically, when the instruction issuing unit 2 issues, it generally transmits one source vector data and one index vector data at the same time. Before issuing a vector register index instruction, the instruction issuing unit 2 will sequentially send all vector register read requests in the register group specified by the instruction to the vector register file 1.

[0023] The index collection and execution unit 3 is configured to perform index lookup and execution processing on the received source vector data and the index vector data to obtain a result to be written back, and send the result to be written back to the instruction write-back unit 4. The result to be written back is the corresponding destination register value obtained after finding that each index element in the index vector data corresponds to a source vector element of the source vector data.

[0024] The instruction write-back unit 4 is configured to write the received result to be written back into a destination register in the vector register file 1 .

[0025] In the embodiment of the present invention, the index collection execution unit 3 includes a source vector register data cache 31, an index vector register data cache 32, a source vector interleaving unit 33, an index interleaving unit 34, an element search execution path 35 and a destination register data cache 36.

[0026] The source vector register data cache 31 is used to store the source vector data; The index vector register data cache 32 is used to store the index vector data; The source vector interleaving unit 33 is configured to read the source vector data in the source vector register data cache 31 and perform interleaving processing, and send the interleaved source vector data to the element search execution path 35; The index interleaving unit 34 is configured to read the index vector data in the index vector register data cache 32 and perform interleaving processing on the index vector data, and send the interleaved index vector data to the element lookup execution path 35 .

[0027] Specifically, in order to enable different vector element bit widths to reuse the same element search execution path 35, it is necessary to interleave the source vector data and index vector data according to the current element bit width and then connect them to the element search execution path 35, so that different vector element bit widths can reuse one element search execution path 35, reducing hardware overhead.

[0028] The element search execution path 35 is used to search in parallel for the elements of the source vector data corresponding to the index elements of the index vector data, obtain the results to be written back, and send the results to be written back to the destination register data cache 36. Specifically, the element search execution path 35 searches in parallel for the source vector elements of the source vector data that are effectively pointed to by each index element of the index vector data, and writes them back to the destination register cache.

[0029] Since the element number range within the source vector register data emitted each time is known, for example: for the first vector register of the vector register stack 1 for instruction execution, assuming that each vector register contains 32 elements, its element index number range is 0-31, and the corresponding second vector register is 32-63; based on this, it can be calculated which elements in the index vector register data cache 32 can complete the indexing during each search execution process, and the elements that have completed the indexing can be marked. In subsequent searches, the search path of these elements can be closed, which saves power consumption; when all elements in an index vector register data cache 32 are marked, it means that all elements in a destination register have been obtained and can be written back.

[0030] The destination register data cache 36 is used to store the received result to be written back and send the result to be written back to the instruction write-back unit 4 .

[0031] In an embodiment of the present invention, when the number of vector registers read by the instruction emission unit 2 in the vector register stack 1 is one, the instruction emission unit 2 transmits the source vector data and the index vector data to the source vector interleaving unit 33 and the index interleaving unit 34 respectively; the source vector data and the index vector data directly enter the source vector interleaving unit 33 and the index interleaving unit 34 after passing through a 2-to-1 path selector.

[0032] When the number of vector registers read by the instruction issuing unit 2 in the vector register stack 1 is greater than one, the instruction issuing unit 2 sends the source vector data and the index vector data to the source vector register data cache 31 and the index vector register data cache 32 respectively.

[0033] In an embodiment of the present invention, when the number of vector registers read by the instruction emission unit 2 in the vector register stack 1 is greater than one, after the instruction emission unit 2 transmits the first group of the source vector data and the index vector data to the source vector register data cache 31 and the index vector register data cache 32, the source vector interleaving unit 33 and the index interleaving unit 34 directly read and interleave the source vector data and the index vector data respectively.

[0034] Through the above method, there is no need to wait for all the source vector data and the index vector data to be transmitted, which is more conducive to pipeline execution. By continuously sending read requests, all vector register data in the vector register stack 1 are written into the source vector register data cache 31 and the index vector register data cache 32 for access, and the vector register stack 1 is avoided from repeatedly requesting the same vector register. It can better decouple the index collection execution unit 3 from the access of the vector register stack 1, thereby improving execution efficiency.

[0035] In an embodiment of the present invention, the element search execution path 35 is further configured to add an index completion flag to the index element in the index vector data for which indexing is completed.

[0036] Specifically, take the example that the number of vector registers in the vector register file 1 read by the instruction emission unit 2 is greater than one. During execution, the instruction emission unit 2 first emits a set of source vector data and a set of index vector data to the index collection execution unit 3 into the source vector register data cache 31 and the index vector register data cache 32. The source vector data and the index vector data will be continuously emitted to the index collection execution unit 3 until all the vectors in the vector register file 1 specified by the instruction are received by the index collection execution unit 3 and written into the source vector register data cache 31 and the index vector register data cache 32.

[0037] After the first set of source vector data and index vector data is written, it can be read and the next process can be executed without waiting until all vectors in the vector register stack 1 are written to the data cache. When the first set of source vector data and index vector data is read out, the corresponding index completion flag is updated according to the value of each index element, and the index search is performed after interleaving to obtain the result value of the element that has completed the index at that time and write it into the destination register data cache 36. If there are still index elements that have not been marked as completed at this time, continue to read the next source vector in the source vector data to search and update the completion flag until all index elements in the current index vector data are marked as completed, and write the current destination register value back; then continue to read the next source vector and index vector, repeat the above search and execution process until all destination registers are written back and the instruction execution is completed.

[0038] Compared with the prior art, the present invention stores source vector data and index vector data that may be accessed in the vector register stack in sequence through the source vector register data cache and the index vector register data cache, thereby avoiding repeated sending of read requests to the vector register stack, thereby decoupling the index collection execution unit from the access of the vector register stack, being more conducive to pipeline execution and reducing execution delay; when no more than one vector register is read in the vector register stack, the present invention can fully perform pipeline operation, further improving efficiency; and through the source vector interleaving unit and the index interleaving unit, the source vector data and the index vector data are interleaved respectively, which can enable different vector element bit widths to reuse an element search execution path, thereby reducing hardware overhead.

[0039] Example 2 Please refer to Figure 2 The present invention further provides a method for collecting and executing element indexes of a vector register. The method is based on the system for collecting and executing element indexes of a vector register as described in the above embodiment. The method comprises the following steps: S1, the instruction issuing unit 2 issues a read request to the vector register file 1 to read the source vector data and index vector data in the vector register file 1; S2, when the number of vector registers read by the instruction issuing unit 2 in the vector register file 1 is greater than one; the instruction issuing unit 2 sends the source vector data and the index vector data to the source vector register data cache 31 and the index vector register data cache 32 for storage respectively; the source vector interleaving unit 33 reads the source vector data from the source vector register data cache 31, and the index interleaving unit 34 reads the index vector data from the index vector register data cache 32; When the number of vector registers read by the instruction issuing unit 2 in the vector register file 1 is equal to one, the instruction issuing unit 2 transmits the source vector data and the index vector data to the source vector interleaving unit 33 and the index interleaving unit 34 respectively; S3, interleaving the source vector data and the index vector data respectively through the source vector interleaving unit 33 and the index interleaving unit 34, and sending the interleaved source vector data and the index vector data to the element search execution path 35; S4. Searching in parallel through the element search execution path 35 for the element of the source vector data corresponding to the index element of the interleaved index vector data, obtaining a result to be written back; and sending the result to be written back to the destination register data cache 36; S5, sending the result to be written back to the instruction write-back unit 4 through the destination register data cache 36; S6. Write the result to be written back into the destination register in the vector register file 1 through the instruction write-back unit 4.

[0040] The element index collection and execution method of the vector register can realize the element index collection and execution system 100 of the vector register in the above embodiment, and can achieve the same technical effect. Please refer to the description in the above embodiment and will not be repeated here.

[0041] Example 3 The embodiment of the present invention also provides a computer device, please refer to Figure 3 , Figure 3 2 is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 200 includes: a memory 202, a processor 201, and an element index collection execution program of a vector register stored in the memory 202 and capable of running on the processor 201.

[0042] The processor 201 calls the vector register element index collection execution program stored in the memory 202 to execute the steps of the vector register element index collection execution method provided by the embodiment of the present invention. Figure 1 , specifically including the following steps: S1, the instruction issuing unit 2 issues a read request to the vector register file 1 to read the source vector data and index vector data in the vector register file 1; S2, when the number of vector registers read by the instruction issuing unit 2 in the vector register file 1 is greater than one; the instruction issuing unit 2 sends the source vector data and the index vector data to the source vector register data cache 31 and the index vector register data cache 32 for storage respectively; the source vector interleaving unit 33 reads the source vector data from the source vector register data cache 31, and the index interleaving unit 34 reads the index vector data from the index vector register data cache 32; When the number of vector registers read by the instruction issuing unit 2 in the vector register file 1 is equal to one, the instruction issuing unit 2 transmits the source vector data and the index vector data to the source vector interleaving unit 33 and the index interleaving unit 34 respectively; S3, interleaving the source vector data and the index vector data respectively through the source vector interleaving unit 33 and the index interleaving unit 34, and sending the interleaved source vector data and the index vector data to the element search execution path 35; S4. Searching in parallel through the element search execution path 35 for the element of the source vector data corresponding to the index element of the interleaved index vector data, obtaining a result to be written back; and sending the result to be written back to the destination register data cache 36; S5, sending the result to be written back to the instruction write-back unit 4 through the destination register data cache 36; S6. Write the result to be written back into the destination register in the vector register file 1 through the instruction write-back unit 4.

[0043] The computer device 200 provided in the embodiment of the present invention can implement the steps in the element index collection and execution method of the vector register in the above embodiment, and can achieve the same technical effects. Please refer to the description in the above embodiment and will not be repeated here.

[0044] Example 4 An embodiment of the present invention also provides a computer-readable storage medium, which stores an element index collection execution program for a vector register. When the element index collection execution program for a vector register is executed by a processor, the various processes and steps in the element index collection execution method for a vector register provided by an embodiment of the present invention are implemented, and the same technical effects can be achieved. To avoid repetition, they will not be repeated here.

[0045] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented using a computer program or hardware associated with instructions. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0046] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0047] Through the above description of the embodiments, those skilled in the art will clearly understand that the methods of the above embodiments can be implemented using software plus the necessary general-purpose hardware platform. Of course, hardware can also be used, but in many cases the former is the more preferred implementation method. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, or optical disk) and includes a number of instructions for enabling a terminal (such as a mobile phone, computer, server, air conditioner, or network device) to execute the methods described in the various embodiments of the present invention.

[0048] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A vector register element index gather execution system, characterized in that: The element index collection execution system includes a vector register stack, an instruction issuance unit, an index collection execution unit and an instruction write-back unit; The vector register file is used to store multiple groups of source vector data and multiple groups of index vector data; The instruction issuing unit is configured to read the source vector data and the index vector data in the vector register file, and to send the source vector data and the index vector data to the index gathering and executing unit; The index collection execution unit is used to perform index lookup execution processing on the received source vector data and the index vector data to obtain a result to be written back; and sending the result to be written back to the instruction write-back unit; The instruction write-back unit is used to write the received result to be written back into a destination register in the vector register file; The index collection execution unit includes a source vector register data cache, an index vector register data cache, a source vector interleaving unit, an index interleaving unit, an element search execution path and a destination register data cache; The source vector register data cache is used to store the source vector data; The index vector register data cache is used to store the index vector data; The source vector interleaving unit is configured to read the source vector data in the source vector register data cache and perform interleaving processing on the source vector data, and send the interleaved source vector data to the element search execution path; The index interleaving unit is configured to read the index vector data in the index vector register data cache and perform interleaving processing on the index vector data, and send the interleaved index vector data to the element search execution path; The element search execution path is used to search in parallel for elements of the source vector data corresponding to index elements of the index vector data to obtain the result to be written back; and sending the result to be written back to the destination register data cache; The destination register data cache is used to store the received result to be written back and send the result to be written back to the instruction write back unit.

2. The vector register element index collection execution system according to claim 1, wherein: When the number of vector registers read by the instruction issuing unit in the vector register file is one, the instruction issuing unit transmits the source vector data and the index vector data to the source vector interleaving unit and the index interleaving unit respectively; When the number of vector registers in the vector register file read by the instruction issuing unit is greater than one, the instruction issuing unit sends the source vector data and the index vector data to the source vector register data cache and the index vector register data cache respectively.

3. The vector register element index collection execution system according to claim 2, wherein: When the number of vector registers in the vector register stack read by the instruction emission unit is greater than one, after the instruction emission unit transmits the first group of the source vector data and the index vector data to the source vector register data cache and the index vector register data cache, the source vector interleaving unit and the index interleaving unit directly read the source vector data and the index vector data respectively for interleaving processing.

4. The vector register element index collection execution system according to claim 1, wherein: The element search execution path is further used to add an index completion flag to the index element in the index vector data whose indexing is completed.

5. A method for collecting and executing element indexes of a vector register, characterized in that: The element index collection and execution method of the vector register is based on the element index collection and execution system of the vector register according to any one of claims 1 to 4, and the element index collection and execution method comprises the following steps: S1, the instruction issuing unit issues a read request to the vector register file to read the source vector data and index vector data in the vector register file; S2, when the number of vector registers read by the instruction issuing unit in the vector register file is greater than one; the instruction issuing unit transmits the source vector data and the index vector data to the source vector register data cache and the index vector register data cache respectively for storage; the source vector interleaving unit reads the source vector data from the source vector register data cache, and the index interleaving unit reads the index vector data from the index vector register data cache; When the number of vector registers in the vector register file read by the instruction issuing unit is equal to one, the instruction issuing unit transmits the source vector data and the index vector data to the source vector interleaving unit and the index interleaving unit respectively; S3, interleaving the source vector data and the index vector data respectively through the source vector interleaving unit and the index interleaving unit, and sending the interleaved source vector data and the index vector data to the element search execution path; S4. Searching in parallel through the element search execution path for elements of the source vector data corresponding to the index elements of the interleaved index vector data to obtain a result to be written back; and sending the result to be written back to the destination register data cache; S5. Sending the result to be written back to the instruction write-back unit through the destination register data cache; S6. Write the result to be written back into a destination register in the vector register file through the instruction write back unit.

6. A computer device, characterized in that: include: A memory, a processor, and a vector register element index collection execution program stored in the memory and executable on the processor, wherein the processor implements the steps of the vector register element index collection execution method as described in claim 5 when executing the vector register element index collection execution program.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a vector register element index collection execution program, which, when executed by a processor, implements the steps in the vector register element index collection execution method as claimed in claim 5.

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