Element indexing of vector registers

Abstract

The application belongs to the technical field of vector processor, and particularly relates to an element index collection execution method and system of a vector register and a storage medium. The element index collection execution system comprises a vector register stack, an instruction emission unit, an index collection execution unit and an instruction write-back unit; the vector register stack is used for storing multiple groups of source vector data and multiple groups of index vector data; the instruction emission unit is used for reading the source vector data and the index vector data in the vector register stack; and the index collection execution unit is used for performing index lookup and execution processing on the received source vector data and index vector data. Compared with the prior art, the source vector register data cache and the index vector register data cache are used to sequentially store the source vector data and the index vector data that can be accessed in the vector register stack, so that the repeated sending of read requests to the vector register stack is avoided, and the access of the index collection execution unit and the vector register stack is decoupled.

Description

TECHNICAL FIELD

[0001] The present application is suitable for the field of vector processor technology, and particularly relates to a method and system for collecting element indexes of a vector register, and a storage medium. BACKGROUND

[0002] A vector processor is usually used to accelerate data parallel tasks, and instructions of the vector processor can usually be directed to a register group, which can contain multiple vector registers, each of which contains multiple parallel elements. For example, a vector instruction specifies that a register group contains 4 vector registers, and the element bit width is 8 bits. When the bit width of each vector register is 128 bits, each vector register contains 16 elements, and a register group contains 64 elements. In actual applications, data computation processed by the vector processor can need to access non-continuous and irregularly distributed data. Therefore, the vector processor can contain instructions for processing such scenarios, and vector register index collection is one of such instructions. By taking the values of elements in a first register group as indexes, source vector elements in a second register group are read, and then written back to a destination register group, so as to achieve the collection of irregularly distributed data. For example, assuming that a register group containing 64 elements of an index vector contains 64 elements of a source vector, each element points to any one of the 64 elements of the source vector. The source vector elements pointed to by the index vector register group are written back to the corresponding positions of the destination register group according to the positions of the elements in the index vector register group, so as to achieve the collection of non-continuous and irregularly distributed data.

[0003] In the field of vector processing, the prior art usually requests the register stack to read part of the index vector registers and source vector registers, and then requests to read the next part after the part of the index vector is traversed, until all vector elements of the destination register are obtained. The following are two typical prior arts:

[0004] The first prior art takes a vector element as the minimum processing unit, reads a number of index vector elements and source vector elements each time, retrieves the elements of the source vector elements that are effectively indexed, and writes them back to the destination register. The specific process is as follows:

[0005] 1. According to the value V of the current index vector element, request the register stack to read W consecutive index vector elements after the value V of the vector index, and write them into the first operation buffer;

[0006] 2. Take V as the address, request the register stack to read W consecutive source vector elements, and write them into the second operation buffer;

[0007] 3. Check if each index vector in the first operation buffer points to the second operation buffer, and in one clock cycle, write the element in the second operation buffer indexed by the first operation buffer into the third operation buffer, while updating the completion flag corresponding to each index vector element in the first operation buffer;

[0008] 4. Repeat reading new source vector elements until all W index vector elements are completed, and then continue reading the next group of W index vector elements for processing until all index vector elements are completed.

[0009] Prior art two takes a vector register as a processing unit (a vector register contains multiple vector elements), and the specific process is as follows:

[0010] 1. Request the register bank to return 1 index vector register;

[0011] 2. Request the register bank to return 1 source vector register containing indexed elements;

[0012] 3. Find the element in the source vector register corresponding to the element in the index vector register, write it into the corresponding position of the destination register buffer, and mark the element in the index vector register that has completed the search;

[0013] 4. Repeat steps 2-3 until all elements in the index vector register are completed, at which time the element generation of 1 destination vector register is completed, and it is written back to the register bank;

[0014] 5. Repeat steps 1-4 until all destination registers in the register group are written back to the register bank.

[0015] The above prior art repeatedly requests the register bank to read part of the operation data, and after the part of the data is executed, the next piece of data is read by sending a read request. Although this method can make the execution path occupy less area resources, it has obvious defects: each time the read request is sent to the register, it depends on the data returned by the last time to complete the execution in the unit, and there is a certain delay in reading the register bank to return the vector register value; when the target register group for execution contains multiple vector registers, the read request will be frequently sent to the register bank, and when the register read request is busy, the execution delay will be further increased. In addition, when there are multiple index values close to each other in the index vector register group, these index values usually point to the same piece of vector register, but due to the far spatial distribution of these index values, the same piece of vector register needs to be requested from the register bank multiple times for one instruction execution, resulting in low instruction execution efficiency.

[0016] Therefore, there is an urgent need for a new vector register element index collection execution method, system and storage medium to solve the above technical problems. SUMMARY

[0017] The application provides a vector register element index collection execution method, system and storage medium, aiming to avoid repeatedly sending read requests to a register stack, reduce the execution delay of a vector register index collection instruction, and reduce hardware costs by multiplexing the same execution path through each element bit width.

[0018] In a first aspect, the application provides a vector register element index collection execution system, which comprises a vector register stack, an instruction emission unit, an index collection execution unit and an instruction write-back unit.

[0019] The vector register stack is used to store multiple groups of source vector data and multiple groups of index vector data.

[0020] The instruction emission unit is used to read the source vector data and the index vector data in the vector register stack, and emit the source vector data and the index vector data to the index collection execution unit.

[0021] The index collection execution unit is used to perform index lookup execution processing on the received source vector data and index vector data to obtain a to-be-written-back result, and send the to-be-written-back result to the instruction write-back unit.

[0022] The instruction write-back unit is used to write the received to-be-written-back result into a destination register in the vector register stack.

[0023] The index collection execution unit comprises a source vector register data cache, an index vector register data cache, a source vector interleaving unit, an index interleaving unit, an element lookup execution path and a destination register data cache.

[0024] The source vector register data cache is used to store the source vector data.

[0025] The index vector register data cache is used to store the index vector data.

[0026] The source vector interleaving unit is used to read the source vector data in the source vector register data cache and perform interleaving processing, and send the interleaving-processed source vector data to the element lookup execution path.

[0027] The index interleaving unit is used to read the index vector data in the index vector register data cache and perform interleaving processing, and send the interleaving-processed index vector data to the element lookup execution path.

[0028] The element lookup execution path is configured to find elements of the source vector data corresponding to index elements of the index vector data in parallel, to obtain the to-be-written-back result, and to send the to-be-written-back result to the destination register data cache.

[0029] The destination register data cache is configured to store the to-be-written-back result received and to send the to-be-written-back result to the instruction write-back unit.

[0030] Preferably, when the number of vector registers in the vector register file read by the instruction issue unit is one, the instruction issue unit issues the source vector data and the index vector data to the source vector interleaving unit and the index interleaving unit respectively.

[0031] When the number of vector registers in the vector register file read by the instruction issue unit is more than one, the instruction issue unit issues the source vector data and the index vector data to the source vector register data cache and the index vector register data cache respectively.

[0032] Preferably, when the number of vector registers in the vector register file read by the instruction issue unit is more than one, after the instruction issue unit issues a first group of the source vector data and the index vector data to the source vector register data cache and the index vector register data cache, the source vector interleaving unit and the index interleaving unit directly read the source vector data and the index vector data respectively for interleaving processing.

[0033] Preferably, the element lookup execution path is further configured to add an index completion flag to an index element in the index vector data for which the index is completed.

[0034] In a second aspect, the present application provides a vector register element index collection execution method, which is based on the vector register element index collection execution system as described in the above embodiments, and the vector register element index collection execution method comprises the following steps:

[0035] S1, the instruction issue unit sends a read request to the vector register file to read source vector data and index vector data in the vector register file;

[0036] S2, when the instruction issue unit reads that the number of vector registers in the vector register file is greater than one; the instruction issue unit issues the source vector data and the index vector data into the source vector register data cache and the index vector register data cache respectively for storage; the source vector interleaving unit reads the source vector data from the source vector register data cache, and the index interleaving unit reads the index vector data from the index vector register data cache;

[0037] When the instruction issue unit reads that the number of vector registers in the vector register file is equal to one, the instruction issue unit issues the source vector data and the index vector data to the source vector interleaving unit and the index interleaving unit respectively;

[0038] S3, the source vector interleaving unit and the index interleaving unit respectively perform interleaving processing on the source vector data and the index vector data, and send the interleaving-processed source vector data and index vector data to the element lookup execution channel;

[0039] S4, the element lookup execution channel parallelly looks up the elements of the source vector data corresponding to the index elements of the interleaving-processed index vector data to obtain a to-be-written-back result, and sends the to-be-written-back result to the destination register data cache;

[0040] S5, the destination register data cache sends the to-be-written-back result to the instruction write-back unit;

[0041] S6, the instruction write-back unit writes the to-be-written-back result into the destination register in the vector register file.

[0042] In a third aspect, the present application also provides a computer device, comprising a memory, a processor, and a vector register element index collection execution program stored in the memory and executable on the processor, wherein the processor implements the steps in the vector register element index collection execution method according to any one of the above embodiments when executing the vector register element index collection execution program.

[0043] In a fourth aspect, the present application also provides a computer readable storage medium, wherein the computer readable storage medium stores a vector register element index collection execution program, and the vector register element index collection execution program implements the steps in the vector register element index collection execution method according to any one of the above embodiments when executed by a processor.

[0044] Compared with the prior art, the application sequentially stores source vector data and index vector data possibly accessed in the vector register stack in the source vector register data cache and the index vector register data cache, avoids repeatedly sending a read request to the vector register stack, thereby decoupling the access of the index collection execution unit and the vector register stack, being more conducive to pipeline execution, reducing execution delay; when the vector register read in the vector register stack is not more than one, the application can completely perform pipeline operation, further improving efficiency; and the source vector interleaving unit and the index interleaving unit respectively perform interleaving processing on the source vector data and the index vector data, which can multiplex one element search execution path for different vector element bit widths, reducing hardware overhead. BRIEF DESCRIPTION OF DRAWINGS

[0045] The application will be described in detail below with reference to the accompanying drawings. The above or other aspects of the application will become more apparent and more readily appreciated from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0046] Figure 1 is a structural schematic diagram of an element index collection execution system of a vector register provided by an embodiment of the application;

[0047] Figure 2 is a flowchart of an element index collection execution method of a vector register provided by an embodiment of the application;

[0048] Figure 3 is a structural schematic diagram of a computer device provided by an embodiment of the application. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the application clearer, the application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and not to limit the application.

[0050] Embodiment one

[0051] An embodiment of the application provides an element index collection execution system of a vector register, which refers to Figure 1 , Figure 1 is a structural schematic diagram of an element index collection execution system 100 of a vector register provided by an embodiment of the application, and the element index collection execution system includes a vector register stack 1, an instruction emission unit 2, an index collection execution unit 3 and an instruction write-back unit 4.

[0052] The vector register stack 1 is used to store multiple groups of source vector data and multiple groups of index vector data.

[0053] Indexing Vector Elements refers to the process of locating, accessing or operating on certain element(s) in a vector (which can be understood as an ordered sequence of elements, such as an array, a list, etc.) through indexing, i.e. the position of the element in the vector.

[0054] Source Vector Element refers to an element contained in a vector that serves as a source of data. The core role is to provide original data or input information for operations.

[0055] The instruction emission unit 2 is configured to read the source vector data and the index vector data in the vector register heap 1 and emit the source vector data and the index vector data to the index collection execution unit 3. Specifically, when the instruction emission unit 2 emits, one source vector data and one index vector data will be emitted at the same time in general cases. Before the vector register indexing instruction is emitted, the instruction emission unit 2 will send a read request of all vector registers in the register group specified by the instruction to the vector register heap 1 in sequence.

[0056] The index collection execution unit 3 is configured to perform index lookup execution processing on the received source vector data and index vector data to obtain a to-be-written-back result, and send the to-be-written-back result to the instruction write-back unit 4. The to-be-written-back result is a corresponding destination register value obtained after each index element in the index vector data is found to correspond to a source vector element of the source vector data.

[0057] The instruction write-back unit 4 is configured to write the received to-be-written-back result to a destination register in the vector register heap 1.

[0058] In the embodiment of the present application, the index collection execution unit 3 comprises a source vector register data buffer 31, an index vector register data buffer 32, a source vector interleaving unit 33, an index interleaving unit 34, an element lookup execution channel 35 and a destination register data buffer 36.

[0059] The source vector register data buffer 31 is configured to store the source vector data.

[0060] The index vector register data buffer 32 is configured to store the index vector data.

[0061] The source vector interleaving unit 33 is configured to read the source vector data in the source vector register data buffer 31 and perform interleaving processing, and send the interleaving-processed source vector data to the element lookup execution channel 35.

[0062] The index interleaving unit 34 is configured to read the index vector data in the index vector register data cache 32 and perform interleaving processing, and send the interleaving-processed index vector data to the element lookup execution channel 35.

[0063] Specifically, in order to enable different vector element bit widths to share one element lookup execution channel 35, the source vector data and the index vector data need to be interleaved and reconnected to the element lookup execution channel 35 according to the current element bit width, so that different vector element bit widths can share one element lookup execution channel 35, and the hardware overhead is reduced.

[0064] The element lookup execution channel 35 is configured to find the elements of the source vector data corresponding to the index elements of the index vector data in parallel, obtain the to-be-written-back result, and send the to-be-written-back result to the destination register data cache 36.

[0065] Since the element number range in the source vector register data transmitted each time is known, for example, for the first vector register of the vector register heap 1 for instruction execution, assuming that each vector register contains 32 elements, the element index number range is 0-31, and the corresponding second vector register is 32-63; accordingly, it can be calculated which elements in the index vector register data cache 32 can complete indexing in each lookup execution process, and the elements that complete indexing are marked, and in subsequent lookup, the lookup channel of these elements can be closed to save power consumption; when all the elements in an index vector register data cache 32 are marked as complete, it means that all the elements in a piece of destination register are obtained, and writing back can be performed.

[0066] The destination register data cache 36 is configured to store the received to-be-written-back result, and send the to-be-written-back result to the instruction write-back unit 4.

[0067] In the embodiment of the application, when the instruction emission unit 2 reads one vector register in the vector register heap 1, the instruction emission unit 2 emits the source vector data and the index vector data to the source vector interleaving unit 33 and the index interleaving unit 34 respectively; the source vector data and the index vector data directly enter the source vector interleaving unit 33 and the index interleaving unit 34 through a 2-to-1 channel selector.

[0068] When the number of vector registers in the vector register file 1 read by the instruction issue unit 2 is greater than one, the instruction issue unit 2 issues the source vector data and the index vector data to the source vector register data cache 31 and the index vector register data cache 32 respectively.

[0069] In the embodiment of the present application, when the number of vector registers in the vector register file 1 read by the instruction issue unit 2 is greater than one, after the instruction issue unit 2 issues the source vector data and the index vector data of the first group to the source vector register data cache 31 and the index vector register data cache 32, the source vector interleaving unit 33 and the index interleaving unit 34 directly read the source vector data and the index vector data for interleaving processing respectively.

[0070] In the above manner, the source vector data and the index vector data do not need to be issued completely, which is beneficial for pipeline execution. By continuously sending read requests, all vector register data in the vector register file 1 is written into the source vector register data cache 31 and the index vector register data cache 32 for access, and the vector register file 1 is prevented from repeatedly requesting the same piece of vector register, which better decouples the access of the index gather execution unit 3 and the vector register file 1, thereby improving execution efficiency.

[0071] In the embodiment of the present application, the element lookup execution path 35 is further configured to add an index completion flag to an index element in the index vector data for which the index is completed.

[0072] Specifically, taking the case where the number of vector registers in the vector register file 1 read by the instruction issue unit 2 is greater than one. In execution, first, the instruction issue unit 2 issues a group of source vector data and a group of index vector data into the source vector register data cache 31 and the index vector register data cache 32 to the index gather execution unit 3, and the source vector data and the index vector data will be continuously issued to the index gather execution unit 3 until all vector registers in the vector register file 1 specified by the instruction are received by the index gather execution unit 3 and written into the source vector register data cache 31 and the index vector register data cache 32.

[0073] When the first set of source vector data and index vector data is written, the next process can be read and executed without waiting for all vectors in the vector register file 1 to be written to the data cache. When the first set of source vector data and index vector data is read, the corresponding index completion flag is updated according to the value of each index element, and the index lookup is performed after interleaving to obtain the element result value of the current completion index written to the destination register data cache 36. If there are still index elements that have not been marked as completed at this time, the next source vector lookup in the source vector data is read and the completion flag is updated. Until all index elements in the current index vector data are marked as completed, the current destination register value is written back. Then the next source vector and index vector are read and the above-mentioned lookup execution process is repeated until all destination registers are written back and the instruction execution is completed.

[0074] Compared with the prior art, the source vector register data cache and the index vector register data cache of the application store the source vector data and the index vector data that may be accessed in the vector register file in turn, avoiding repeated read requests to the vector register file, thereby decoupling the index collection execution unit and the access of the vector register file, being more conducive to pipeline execution, and reducing execution delay. When the vector register read in the vector register file does not exceed one, the application can completely perform pipeline operation, further improving efficiency. And the source vector interleaving unit and the index interleaving unit respectively perform interleaving processing on the source vector data and the index vector data, which can multiplex one element lookup execution path for different vector element bit widths, reducing hardware overhead.

[0075] Embodiment two

[0076] Please refer to Figure 2 The application further provides a vector register element index collection execution method based on the vector register element index collection execution system as described in the above embodiments, and the element index collection execution method comprises the following steps:

[0077] S1, the instruction emission unit 2 sends a read request to the vector register file 1 to read the source vector data and the index vector data in the vector register file 1;

[0078] S2, when the instruction emitting unit 2 reads the number of vector registers in the vector register heap 1 is greater than one;The instruction emitting unit 2 emits the source vector data and the index vector data into the source vector register data cache 31 and the index vector register data cache 32 respectively for storage;The source vector interleaving unit 33 reads the source vector data from the source vector register data cache 31, and the index interleaving unit 34 reads the index vector data from the index vector register data cache 32;

[0079] When the instruction emitting unit 2 reads the number of vector registers in the vector register heap 1 is equal to one, the instruction emitting unit 2 emits the source vector data and the index vector data into the source vector interleaving unit 33 and the index interleaving unit 34 respectively;

[0080] S3, the source vector data and the index vector data are interleaved by the source vector interleaving unit 33 and the index interleaving unit 34 respectively, and the interleaved source vector data and the index vector data are sent to the element lookup execution channel 35;

[0081] S4, the element lookup execution channel 35 looks up the elements of the source vector data corresponding to the index elements of the interleaved index vector data in parallel, and obtains a result to be written back;And the result to be written back is sent to the destination register data cache 36;

[0082] S5, the result to be written back is sent to the instruction write-back unit 4 by the destination register data cache 36;

[0083] S6, the result to be written back is written into the destination register in the vector register heap 1 by the instruction write-back unit 4.

[0084] The element index collection execution method can realize the vector register element index collection execution system 100 in the above embodiment, and can realize the same technical effect. Please refer to the description in the above embodiment, which will not be repeated here.

[0085] Embodiment three

[0086] The embodiment of the application also provides a computer device, please refer to Figure 3 , Figure 3 is a structural schematic diagram of the computer device provided by the embodiment of the application, the computer device 200 includes a memory 202, a processor 201 and a vector register element index collection execution program stored on the memory 202 and executable on the processor 201.

[0087] The processor 201 invokes the element index collection execution program of the vector register stored in the memory 202 to execute the steps in the element index collection execution method of the vector register provided by the embodiment of the application. Figure 1 , and specifically includes the following steps:

[0088] S1, the instruction emission unit 2 sends a read request to the vector register heap 1 to read the source vector data and the index vector data in the vector register heap 1;

[0089] S2, when the number of vector registers in the vector register heap 1 read by the instruction emission unit 2 is greater than one; the instruction emission unit 2 emits the source vector data and the index vector data into the source vector register data cache 31 and the index vector register data cache 32 respectively for storage; the source vector interleaving unit 33 reads the source vector data from the source vector register data cache 31, and the index interleaving unit 34 reads the index vector data from the index vector register data cache 32;

[0090] When the number of vector registers in the vector register heap 1 read by the instruction emission unit 2 is equal to one, the instruction emission unit 2 emits the source vector data and the index vector data to the source vector interleaving unit 33 and the index interleaving unit 34 respectively;

[0091] S3, the source vector data and the index vector data are interleaved by the source vector interleaving unit 33 and the index interleaving unit 34 respectively, and the interleaved source vector data and index vector data are sent to the element lookup execution channel 35;

[0092] S4, the element lookup execution channel 35 is used to find the elements of the source vector data corresponding to the index elements of the interleaved index vector data in parallel to obtain a to-be-written-back result; and the to-be-written-back result is sent to the destination register data cache 36;

[0093] S5, the to-be-written-back result is sent to the instruction write-back unit 4 by the destination register data cache 36;

[0094] S6, the instruction write-back unit 4 is used to write the to-be-written-back result into the destination register in the vector register heap 1.

[0095] The computer device 200 provided by the embodiment of the application can implement the steps in the element index collection execution method of the vector register in the above-described embodiment, and achieve the same technical effects. Please refer to the description in the above-described embodiment, which will not be repeated here.

[0096] Embodiment Four

[0097] The embodiment of the present application further provides a computer readable storage medium, which stores a vector register element index collection execution program, and the vector register element index collection execution program realizes each process and step in the vector register element index collection execution method provided by the embodiment of the present application when executed by a processor, and can realize the same technical effects. To avoid repetition, details are not described herein.

[0098] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program or instruction related hardware. The program can be stored in a computer readable storage medium, and when the program is executed, the program can include the processes of the above-mentioned embodiment methods. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM).

[0099] It should be noted that in this document, the term "comprising" or "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0100] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be realized by means of software and necessary general hardware platforms, and of course, they can also be realized by hardware, but in many cases, the former is a better embodiment. Based on this understanding, the technical solutions of the present application or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disc, optical disc) and includes a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, air conditioner or network device, etc.) execute the method described in each embodiment of the present application.

[0101] The embodiments of the present application are described above with reference to the accompanying drawings, and the disclosed are only the preferred embodiments of the present application, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, but not restrictive, and the ordinary skilled in the art can make many equivalent changes without departing from the spirit of the present application and the scope of protection of the claims, and all the equivalent changes are within the protection scope of the present application.

Claims

1. A vector register element index gather execution system, characterized in that: The element index collection execution system comprises a vector register stack, an instruction emission unit, an index collection execution unit and an instruction write-back unit; The vector register stack is configured to store a plurality of sets of source vector data and a plurality of sets of index vector data; The instruction emission unit is configured to read the source vector data and the index vector data in the vector register stack, and emit the source vector data and the index vector data to the index collection execution unit; The index collection execution unit is configured to perform index lookup execution processing on the received source vector data and index vector data to obtain a to-be-written-back result, and send the to-be-written-back result to the instruction write-back unit; The instruction write-back unit is configured to write the received to-be-written-back result into a destination register in the vector register stack. The index collection execution unit comprises a source vector register data buffer, an index vector register data buffer, a source vector interleaving unit, an index interleaving unit, an element lookup execution channel and a destination register data buffer; The source vector register data buffer is configured to store the source vector data; The index vector register data buffer is configured to store the index vector data; The source vector interleaving unit is configured to read the source vector data in the source vector register data buffer and perform interleaving processing, and send the interleaved source vector data to the element lookup execution channel; The index interleaving unit is configured to read the index vector data in the index vector register data buffer and perform interleaving processing, and send the interleaved index vector data to the element lookup execution channel; The element lookup execution channel is configured to find, in parallel, elements of the source vector data corresponding to index elements of the index vector data to obtain the to-be-written-back result, and send the to-be-written-back result to the destination register data buffer; The destination register data buffer is configured to store the received to-be-written-back result, and send the to-be-written-back result to the instruction write-back unit. When the number of vector registers in the vector register stack read by the instruction emission unit is one, the instruction emission unit emits the source vector data and the index vector data to the source vector interleaving unit and the index interleaving unit, respectively; When the number of vector registers in the vector register stack read by the instruction emission unit is more than one, the instruction emission unit emits the source vector data and the index vector data to the source vector register data buffer and the index vector register data buffer, respectively.

2. The vector register element index gather execution system of claim 1, wherein, When the number of vector registers in the vector register stack read by the instruction emission unit is more than one, after the instruction emission unit emits a first set of the source vector data and the index vector data to the source vector register data buffer and the index vector register data buffer, the source vector interleaving unit and the index interleaving unit directly read the source vector data and the index vector data, respectively, for interleaving processing. ​ 3. The vector register element index gather execution system of claim 2, wherein, ​ 4. The vector register element index gather execution system of claim 1, wherein, The element lookup execution channel is also used to add an index completion flag to an index completed index element in the index vector data.

5. A method of gather execution of elements of a vector register, the method comprising: The element index collection execution method based on the element index collection execution system of the vector register according to any one of claims 1-4 comprises the following steps: S1, the instruction emission unit sends a read request to the vector register stack to read source vector data and index vector data in the vector register stack; S2, when the number of vector registers in the vector register stack read by the instruction emission unit is greater than one; the instruction emission unit emits the source vector data and the index vector data into the source vector register data cache and the index vector register data cache respectively for storage; the source vector interleaving unit reads the source vector data from the source vector register data cache, and the index interleaving unit reads the index vector data from the index vector register data cache; When the number of vector registers in the vector register stack read by the instruction emission unit is equal to one, the instruction emission unit emits the source vector data and the index vector data to the source vector interleaving unit and the index interleaving unit respectively; S3, the source vector data and the index vector data are interleaved by the source vector interleaving unit and the index interleaving unit respectively, and the interleaved source vector data and index vector data are sent to the element lookup execution channel; S4, the element lookup execution channel is used to find the elements of the source vector data corresponding to the index elements of the interleaved index vector data in parallel, to obtain a to-be-written-back result; and the to-be-written-back result is sent to the destination register data cache; S5, the to-be-written-back result is sent to the instruction write-back unit by the destination register data cache; S6, the to-be-written-back result is written into the destination register in the vector register stack by the instruction write-back unit.

6. A computer device, comprising: Comprise: a memory, a processor, and a vector register element index collection execution program stored on the memory and executable on the processor, and the processor executes the vector register element index collection execution program to realize the steps in the vector register element index collection execution method in claim 5.

7. A computer readable storage medium characterized by The computer readable storage medium stores a vector register element index collection execution program, and the vector register element index collection execution program is executed by a processor to realize the steps in the vector register element index collection execution method in claim 5.

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