An instruction processing method

Abstract

The application discloses an instruction processing method, which is suitable for a CPU processing instructions in a pipeline mode, and comprises the following steps: performing instruction matching based on instruction information, determining whether the instruction needs bypass processing, stopping the pipeline where the instruction is located if it is determined that the instruction needs bypass processing, determining the instruction result of the instruction after the instruction is processed through bypass as the instruction result of the instruction, and resuming the pipeline at the target address indicated by the bypass. The above method can identify a specified instruction through instruction matching, and then process the instruction through bypass.

Description

Technical Field

[0001] This application relates to the field of computer instruction processing technology, and in particular to an instruction processing method. Background Technology

[0002] In modern computer systems, the instruction set of the Central Processing Unit (CPU) is the foundation for program execution. The CPU contains a decoder that parses instructions. When the decoder cannot parse an instruction, it considers that instruction to be illegal. In this case, the CPU switches to kernel mode to process the illegal instruction. The processing method may be to simulate the execution of the illegal instruction or to terminate the current program.

[0003] However, this approach involves software processing for handling illegal instructions, which is inefficient and cumbersome, severely impacting system performance. Therefore, further research is needed to improve the efficiency of handling illegal instructions.

[0004] Furthermore, some instructions do not cause the CPU to switch to kernel mode, but their execution may potentially impact system stability or security in some way, and therefore need to be identified and addressed promptly. Thus, how to identify specific instructions and how to process them after identification requires further research. Summary of the Invention

[0005] This application provides an instruction processing method for identifying a specified instruction through instruction matching, and then processing the instruction through a bypass.

[0006] In a first aspect, embodiments of this application provide an instruction processing method, which can be executed by a CPU that processes instructions in a pipelined mode. The method includes: performing instruction matching based on indication information representing the instruction to determine whether the instruction needs to be bypassed; if it is determined that the instruction needs to be bypassed, pausing the pipeline where the instruction is located; determining the instruction result after bypassing the instruction as the instruction result, and resuming the pipeline at the target address indicated by the bypass.

[0007] By employing the above method, the matched instructions are bypassed through instruction matching, thus bypassing the normal pipeline path. This allows for bypassing of the matched instructions. By determining the result of the bypassed instruction as the instruction's result, the instruction's processing logic can be altered. By restoring the pipeline at the target address indicated by the bypass, the bypass can specify the next instruction to be executed, thereby changing the program's execution flow.

[0008] In one possible implementation, the pipeline includes a fetch stage and an execution effect stage; the execution effect stage is a pipeline stage located after the fetch stage and required to be rolled back in case of an exception; instruction matching based on instruction representation information includes: performing instruction matching based on instruction representation information on the instructions obtained through the fetch stage of the pipeline, while the pipeline continues to be in the execution state; if the pipeline executes to any execution effect stage and has not yet obtained an instruction matching result, the pipeline is paused until the instruction matching result is obtained, and the instruction matching result indicates whether the instruction needs to be bypassed.

[0009] In one possible implementation, the pipeline includes a fetch stage and an execution effect stage; the execution effect stage is a pipeline stage located after the fetch stage and required to be rolled back in case of an exception; instruction matching based on instruction representation information includes: performing instruction matching based on instruction representation information on the instructions obtained through the fetch stage of the pipeline, while the pipeline continues to be in the execution state; if it is determined that the instruction needs to be bypassed, the pipeline containing the instruction is paused, including: if it is determined that the instruction needs to be bypassed, and the pipeline has reached any execution effect stage, then after rolling back the pipeline, the pipeline containing the instruction is paused.

[0010] In one possible implementation, the pipeline further includes a non-execution effect stage located after the instruction fetch stage and before the execution effect stage; the non-execution effect stage is a pipeline stage that does not require rollback in case of an exception; if it is determined that the instruction needs to be bypassed, the pipeline containing the instruction is paused, including: if it is determined that the instruction needs to be bypassed, and the pipeline executes to any non-execution effect stage, then the pipeline containing the instruction is paused.

[0011] In one possible implementation, the non-executive effect level includes the decoding level.

[0012] In one possible implementation, the pipeline includes an instruction fetch stage and a decoding stage; instruction matching based on instruction representation information to determine whether the instruction needs to be bypassed includes: after the pipeline completes the instruction fetch stage and before the decoding stage begins, instruction matching based on instruction representation information to determine whether the instruction needs to be bypassed.

[0013] In one possible implementation, the method further includes: if it is determined that the instruction does not require bypass processing, then continuing to execute the pipeline until the instruction result is obtained.

[0014] In one possible implementation, the pipeline sequentially includes an instruction fetch stage and an instruction adjustment stage; the instruction adjustment stage is located after the instruction fetch stage; instruction matching based on instruction representation information includes: during the processing of any instruction adjustment stage by the pipeline, performing instruction matching based on instruction representation information on a first instruction before adjustment by the instruction adjustment stage and a second instruction after adjustment by the instruction adjustment stage.

[0015] In one possible implementation, instruction matching is performed based on the indication information of the representation instruction to determine whether the instruction needs to be bypassed, including: for any matching item, determining whether the indication information of the representation instruction matches the mask and / or target value in the matching item; if they match, then determining that the instruction needs to be bypassed.

[0016] In one possible implementation, the target value of the matching item represents the opcode for obtaining the current clock; the mask of the matching item is the bit where the opcode is located; and the instruction result is clock information unrelated to the current clock or inaccurate clock information.

[0017] In one possible implementation, the instruction requiring bypass processing is a new instruction; the target value of the matching item is a reserved opcode, and / or the mask of the matching item is a reserved bit field, and the target value of the matching item is at least a level opcode.

[0018] In one possible implementation, the instruction requiring bypass processing has an error in the CPU's hardware implementation, which leads to an unexpected instruction result; the bypass result is either the expected instruction result, triggers an exception, or is empty.

[0019] In one possible implementation, the CPU includes an instruction matching unit and an instruction bypass unit; the instruction matching is performed based on indication information representing the instruction to determine whether the instruction needs to be bypassed, including: the instruction matching unit performs coarse matching on the instruction based on the mask and / or target value in the matching item, and takes the matched instruction as the coarse matching instruction; the instruction bypass unit performs fine matching on the coarse matching instruction to determine whether the instruction is an illegal instruction that needs to be bypassed.

[0020] In one possible implementation, the effective bits of the mask and / or target value in the matching item corresponding to the coarse match are less than the effective bits formed by summing the matching rules used in the fine match.

[0021] Secondly, embodiments of this application provide a central processing unit (CPU), the CPU including an instruction matching unit and an instruction bypass unit. The instruction matching unit is used to execute the method as in any possible implementation of the first aspect. The instruction bypass unit is a programmable logic device used to bypass instructions based on the instructions of the instruction matching unit and to feed back the instruction result of the bypassed processing to the instruction matching unit.

[0022] In one possible implementation, the instruction matching unit is specifically used to perform coarse matching on the instruction based on the mask and / or target value in the matching item, and take the matched instruction as the coarse matching instruction; the bypass processing unit is further used to perform fine matching based on the coarse matching instruction, and determine whether the instruction is an illegal instruction that needs to be bypassed.

[0023] Thirdly, embodiments of this application provide an instruction processing device, the instruction processing device comprising: a memory for storing computer programs or instructions; and a processor for calling the computer programs or instructions stored in the memory to execute the method as described in any possible implementation of the first aspect. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart illustrating an instruction processing method provided in an embodiment of this application.

[0026] Figure 2 A flowchart illustrating the first type of instruction matching timing provided in this application embodiment;

[0027] Figure 3 A flowchart illustrating the second instruction matching timing provided in this application embodiment;

[0028] Figure 4 A flowchart illustrating the third instruction matching timing provided in this application embodiment;

[0029] Figure 5 A flowchart illustrating the fourth instruction matching timing provided in this application embodiment;

[0030] Figure 6 This is a schematic diagram of the structure of an instruction processing device 6000 provided in an embodiment of this application. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] This application provides an instruction processing method for identifying a specified instruction through instruction matching, and then processing the instruction through a bypass.

[0033] To facilitate understanding, some terms used in this application will be explained first.

[0034] Instruction is a shorthand term for machine code instruction, and it is the foundation of program execution. The core of a machine code instruction is its opcode. The decoder must first determine the instruction's opcode in order to determine the arrangement of operands and the meaning of each operand, and then further send the instruction to the subsequent pipeline stage for execution according to the behavior defined in the instruction set.

[0035] Pipelining is an essential part of modern computer processors. It refers to breaking down the computer instruction processing into multiple steps and executing them in parallel by multiple hardware processing units to accelerate instruction execution. Pipelining is a fixed hardware logic. Pipeline implementations vary, and different CPUs may have varying numbers of pipeline stages. The most classic pipeline design is a 5-stage pipeline. The 5-stage pipeline includes instruction fetch (IF), instruction decode (ID), execute (EX), memory access (MEM), and write back (WB). Specifically, IF fetches the instruction to be executed from memory; ID parses and interprets the fetched instruction; EX performs arithmetic, logical, and control transfer operations based on the decoded result, especially the operation type and operands; MEM handles memory-related operations, including reading data and storing results; and WB writes the execution result to the appropriate register for use by subsequent instructions.

[0036] Figure 1 This is a flowchart illustrating an instruction processing method provided in an embodiment of this application. This flowchart can be executed by a CPU that processes instructions in a pipelined manner. Figure 1 As shown, the process includes the following steps:

[0037] Step 101: The CPU performs instruction matching based on the instruction indication information to determine whether the instruction needs to be bypassed.

[0038] Instruction indication information can be the instruction's machine code, its memory address, or its internal number; no limitation is made here. The instruction can be identified based on this indication information. Instruction matching presupposes that the processor has completed instruction fetching. Under this premise, instruction matching is performed based on the indication information representing the instruction to determine whether the instruction requires bypass processing. A bypass is an alternative path to the usual path. In most cases, the instruction will not be matched, and the pipeline continues execution until the instruction's result is obtained (in other words, the pipeline is the usual path). When an instruction is matched, it bypasses the usual path; the bypass is the alternative path the instruction takes in this situation.

[0039] Step 102: If it is determined that the instruction needs to be bypassed, then pause the pipeline containing the instruction.

[0040] There are multiple opportunities to perform instruction matching based on the indication information of the characterization instruction. The embodiments of this application provide the following four opportunities.

[0041] (i) After the instruction fetch stage is completed in the pipeline and before the decoding stage begins

[0042] After the instruction fetch stage is completed in the pipeline and before the decoding stage begins, instruction matching is performed based on the indication information representing the instruction to determine whether the instruction needs to be bypassed. Figure 2 This is a flowchart illustrating the first instruction matching timing provided in an embodiment of this application. It is understood that the pipeline may include a fetch stage and a decode stage, from... Figure 2 As can be seen, inserting instruction matching before the decoding stage means that if a match is found, the pipeline pauses and the instruction is bypassed, preventing it from entering the decoding stage and subsequent pipeline stages. The pipeline resumes at a specified address after bypass processing. If no match is found, the instruction does not require bypass processing, enters the decoding stage, and then proceeds to the subsequent pipeline stages, continuing execution until the instruction's result is obtained. Thus, by determining the instruction matching result before the decoding stage begins, and if a match is successful, the decoding stage and subsequent pipeline stages can be avoided, minimizing unnecessary pipeline stage execution and reducing unnecessary power consumption or overhead.

[0043] The pipeline also includes other pipeline stages. The embodiments of this application are not limited to instruction matching only before the decoding stage, but may also perform instruction matching before other pipeline stages.

[0044] (ii) When the pipeline is executed concurrently with the instruction matching, and the instruction matching is completed, the pipeline execution proceeds to the non-execution effect level.

[0045] Understandably, besides the instruction fetch stage, a pipeline contains multiple pipeline stages. These stages can be categorized into non-executable stages and executable stages. Non-executable stages are located after the instruction fetch stage and before the executable stages. Non-executable stages do not require rollback in case of exceptions and include the decode stage. This is because in the processor pipeline, instructions only have an execution effect in a relatively late stage; if execution is interrupted before this point, the instructions will not have any effect. In the classic 5-stage pipeline, the decode stage belongs to the non-executable stage.

[0046] Optionally, the instructions obtained through the instruction fetch stage of the pipeline are subjected to instruction matching based on the instruction representation information, and the pipeline continues to be in the execution state. If it is determined that the instruction needs to be bypassed, the pipeline will pause the pipeline containing the instruction when it reaches any non-execution effect stage. Figure 3 This is a flowchart illustrating the second type of instruction matching timing provided in an embodiment of this application. From... Figure 3 As can be seen, after instruction fetching, instruction matching is performed. Simultaneously, the instruction is in the execution state within the pipeline. If a match is found, and the pipeline reaches any non-execution effect stage, the pipeline pauses and the instruction is bypassed. The result obtained at this non-execution effect stage is essentially discarded and does not enter subsequent pipeline stages. If no match is found, it is determined that the instruction does not require bypass processing, and pipeline execution continues until the instruction's execution result is obtained. In this way, instruction matching and pipeline execution run concurrently. If instruction matching fails, pipeline execution can continue until the instruction's execution result is obtained, preventing delays caused by instruction matching and improving pipeline execution efficiency.

[0047] (iii) It occurs concurrently with the pipeline, and the pipeline fails to obtain an instruction matching result at any execution effect level.

[0048] Optionally, the instructions obtained through the instruction fetch stage of the pipeline are subjected to instruction matching based on the instruction representation information, and the pipeline continues to be in the execution state. If the pipeline has not obtained an instruction matching result when it reaches any execution effect stage, the pipeline is paused until the instruction matching result is obtained. The instruction matching result indicates whether the instruction needs to be bypassed.

[0049] Specifically, in some cases, instruction matching may use overly complex matching methods, resulting in a slow matching process. Since instructions don't produce an execution effect until a relatively late stage in the processor pipeline, pausing pipeline execution before this point will prevent the instructions from having any effect. In other words, if the pipeline is blocked before the pipeline stage that produces the effect (i.e., the execution effect stage), the results of the completed pipeline stage can be discarded without additional rollback, making it seem as if a certain instruction was never executed. More simply, this is an efficient rollback that doesn't require any backup or recovery; it only discards the current state. This design is meaningful because once the pipeline enters a subsequent pipeline stage that might produce an effect, additional overhead and time are incurred for rollback, increasing the processor's design complexity and power consumption.

[0050] Figure 4 This is a flowchart illustrating the third instruction matching timing provided in this application embodiment. Instruction matching can be performed simultaneously with pipeline stages that will not yet have an effect on the instruction. Reaching any execution effect stage in pipeline execution indicates that the pipeline is about to enter a pipeline stage that will have an effect. The execution effect stage is the pipeline stage located after the instruction fetch stage and needs to be rolled back in case of an exception. Before the pipeline reaches any execution effect stage, it is confirmed whether instruction matching is complete. If not, it waits for instruction matching to complete before deciding whether to send the instruction to a bypass or allow it to enter subsequent pipeline stages. After instruction matching, if a match is found, the pipeline is paused and the instruction is sent to a bypass. At this time, the result obtained from the non-execution effect stage is essentially discarded and will not enter subsequent pipeline stages. If no match is found, it is determined that the instruction does not need bypass processing, and the pipeline continues to execute until the instruction result is obtained. If the instruction matching process is slow, and instruction matching is not completed before the pipeline enters the execution effect stage, the pipeline is paused until instruction matching is completed, thus saving CPU overhead. Because if the pipeline is not interrupted, when the instruction matching is completed, the pipeline will execute to the effect level. If the instruction matching is successful and the instruction is sent to the bypass for execution, the pipeline level will need to be rolled back.

[0051] (iv) When the instruction matching is completed, the pipeline executes to the execution effect level simultaneously with the pipeline.

[0052] Optionally, the instructions obtained through the instruction fetch stage of the pipeline are subjected to instruction matching based on the instruction representation information, and the pipeline continues to be in the execution state. If it is determined that the instruction needs to be bypassed, the pipeline will be executed to any execution effect stage, and then the pipeline where the instruction is located will be paused after the pipeline is rolled back.

[0053] Specifically, in some cases, instruction matching may be even slower, to the point that by the time instruction matching is complete, the pipeline has already reached the execution effect level. Figure 5 This is a flowchart illustrating the fourth instruction matching timing provided in the embodiments of this application. Figure 5 As can be seen, instruction matching can be performed simultaneously with the pipeline level. If a match is found, the instruction is sent to the bypass, and the pipeline is rolled back to cancel the effects of the pipeline. If no match is found, the execution state of the pipeline is not affected, and the pipeline continues to proceed normally.

[0054] The four timings (i), (ii), (iii), and (iv) mentioned above are merely illustrative examples. They are neither mutually exclusive nor do they cover all possible timings. In practical applications, various timings can be used in combination within the same product. For example, different timings can be dynamically selected based on the complexity of the matching item and / or the progress of instruction matching; another example is the dynamic selection of timings based on which pipeline level the pipeline has reached when instruction matching is completed.

[0055] It should be noted that pausing or rolling back the pipeline can be done simultaneously with sending instructions to the bypass, without any timing dependency. This simultaneous pausing or rolling back of the pipeline and sending instructions to the bypass can improve instruction processing efficiency. Alternatively, if the CPU cannot perform these simultaneous actions, the pipeline can be paused or rolled back first, followed by sending instructions to the bypass; this is because fewer pipeline stages result in fewer effects and less overhead from the rollback.

[0056] Furthermore, it should be noted that on the same pipeline, if instruction 1 needs to pause at pipeline level n because the instruction matching result has not yet been determined, the next instruction on the same pipeline after instruction 1, such as instruction 2, will be executed at most up to pipeline level n-1, the next instruction on the same pipeline after instruction 2, such as instruction 3, will be executed at most up to pipeline level n-2, and so on.

[0057] Of course, in some cases there may be multiple pipelines. In this case, if instruction 1 is on pipeline 1 and instruction 2 is on pipeline 2, then instruction 2 does not need to be queued after instruction 1. However, instruction 2 cannot enter the execution effect stage of pipeline 2. Otherwise, instruction 2 will produce an execution effect, thus violating the principle that instruction 2 must produce an execution effect after the instruction preceding instruction 2 (including instruction 1).

[0058] Step 103: The CPU determines the instruction result after processing the instruction through the bypass as the instruction result, and resumes the pipeline at the target address indicated by the bypass.

[0059] Specifically, after an instruction is sent to the bypass, the instruction bypass unit in the CPU processes the instruction and determines the result of the instruction as the instruction result. The pipeline is then resumed at the target address indicated by the bypass. The pipeline pauses until the instruction bypass simulation completes the execution of the instruction. After the target address is determined, the paused pipeline will resume operation at the target address.

[0060] Generally, the target address is the address of the instruction following the one that has already been simulated. This allows the pipeline to continue processing the next instruction, since the matched instruction has already been simulated by the instruction bypass unit and doesn't need to be executed a second time. Optionally, the target address can also be another address. For example, if the bypassed instruction is a jump or branch instruction, the target address should be the jump or branch target address. If the instruction bypass unit doesn't fully execute the bypassed instruction but only corrects some internal processor state, the target address can be set to the bypassed instruction itself, and the instruction can be temporarily skipped from the instruction match, allowing the pipeline to execute the instruction and obtain the correct internal processor state during this pipeline execution. If only an instruction needs to be completely skipped, the instruction bypass unit, after receiving the bypassed instruction and determining that it should be skipped, does nothing and directly specifies the address of the next instruction as the target address, thus skipping the instruction.

[0061] In a five-stage pipeline, the fetch stage is followed by the decode stage. Optionally, in more complex pipelines, there may be additional pipeline stages after the fetch stage to further process the fetched instructions. For example, the pipeline includes a fetch stage, an instruction adjustment stage, and a decode stage. Instruction matching is performed based on instruction representation information, including: during the pipeline processing of any instruction adjustment stage, performing instruction matching based on instruction representation information for both the first instruction before adjustment by the instruction adjustment stage and the second instruction after adjustment by the instruction adjustment stage.

[0062] Specifically, the instruction matcher can operate before or after any pipeline stage, or alongside any pipeline stage. Any pipeline stage can modify and transform instructions. The instruction matcher can match both the instructions before and after modification and transformation, configuring different sets of matching terms for these two matches. Furthermore, if multiple pipeline stages modify and transform the instructions fetched by the instruction fetch stage multiple times, the instruction matcher can perform multiple matches on each modified and transformed instruction. In this way, the instruction matcher can match instructions before and after modification and transformation, increasing the probability of instruction matching and expanding its application in practical business applications.

[0063] In one possible implementation, the pipeline includes a fetch stage, and the pipeline is resumed at the target address indicated by the bypass, including resuming the pipeline from the fetch stage, wherein the first instruction obtained by the fetch stage is an instruction existing at the target address indicated by the bypass.

[0064] The methods for instruction matching based on the indication information of the representation instruction in this application embodiment are varied, including tree matching and graph matching, and optionally, mask matching. Instruction matching based on the indication information of the representation instruction to determine whether the instruction needs bypass processing includes: for any matching item, determining whether the indication information of the representation instruction matches the mask and / or target value in the matching item; if a match is found, then determining that the instruction needs bypass processing.

[0065] Specifically, each match includes a mask and a target value. The mask indicates the bits in each instruction that are involved in the matching; the target value is used to compare with the instruction to be matched. Table 1 shows an example of matching an 8-bit instruction with a match.

[0066] Table 1

[0067]

[0068] In this table, 1 represents a 1, 0 represents a 0, and x represents any value for the 1. As shown in Table 1, bits with a mask value of 1 participate in the matching process, while bits with a mask value of 0 do not. Since the instruction and target value have the same binary representation under the 1-bit mask in this example, the instruction successfully matches the target, or in other words, the instruction and the target are matched.

[0069] Optionally, the instruction set can be a fixed-length instruction set or a variable-length instruction set, where the instruction length is not unique. For variable-length instruction sets, both the mask and the target value have the maximum length. Bits set to 0 in the mask allow non-existent bits to be matched, but bits set to 1 require the corresponding bit in the instruction to be present. Instructions shorter than the maximum length have two matching methods: matching with high-order bits aligned or matching with low-order bits aligned. If the instruction length in the variable-length instruction set could be 8 bits or 12 bits, then both the mask and the target value are 12 bits long. Assuming that instructions shorter than the maximum length are matched with high-order bits aligned, if at least four consecutive bits of the least significant bit of the mask are 0, then this match can match both 8-bit and 12-bit instructions; conversely, if any one of the four least significant bits of the mask is 1, then this match can only match 12-bit instructions.

[0070] Assuming that instructions shorter than the maximum length are matched by aligning the low bits, then if the highest bit of the mask has at least four consecutive 0 bits, the match can match both 8-bit and 12-bit instructions. Conversely, if any of the last four bits of the mask is 1, the match can only match 12-bit instructions.

[0071] Therefore, for variable-length instruction sets, the same match term can seem ambiguous because it can match instructions of two different lengths. However, this problem can be completely avoided by writing the match term appropriately.

[0072] For example, the instruction length of some variable-length instruction sets is directly determined by the opcode. Therefore, as long as the matching item contains a match for the opcode, it is actually equivalent to limiting the instruction length, so there is no ambiguity in the instruction length.

[0073] Therefore, to ensure that the matching terms do not cause ambiguity regarding instruction length for variable-length instruction sets, it is essential to ensure that the matching bits encompass the bits containing the opcode. If matching the first-level opcode is sufficient to determine the instruction length, then only the bits containing the first-level opcode should be included. Otherwise, if matching opcodes from level 1 to n is sufficient to determine the instruction length, then the bits containing opcodes from level 1 to n should be included.

[0074] Alternatively, some variable-length instruction sets may be too complex. In that case, we can add a new parameter to the match: the instruction length. This parameter specifies the expected instruction length for the match. If the instruction length is not equal to this parameter, the match is considered to have failed.

[0075] According to an instruction processing method proposed in an embodiment of this application, this application also provides a method for correcting logic defects in an Application-Specific Integrated Circuit (ASIC). An ASIC is an integrated circuit specifically designed to meet the needs of a particular electronic system. Its circuit structure and function are customized for a specific application. Once an ASIC is manufactured, its internal logic is fixed and cannot be changed. A typical CPU is an ASIC.

[0076] For side-channel attacks, since side-channel attacks always require measuring the side effects of hardware, the following instruction sequence is often repeatedly executed during the measurement phase of a side-channel attack: Step 1: Obtain and record the current clock; Step 2: Execute instructions that may be affected by the aforementioned side effects; Step 3: Obtain and record the current clock.

[0077] Steps 1 and 3 can be used to determine the time required to execute step 2. After this sequence of instructions is executed repeatedly, attackers can use statistical analysis to determine the time required for step 2 execution under different conditions. The resulting statistical characteristics can be used to leak sensitive information from the side channel. Taking the cached side channel used by both Meltdown and Spectre as an example, the aforementioned side effects affect the access latency of each element in the array. Therefore, it is always necessary to measure the access latency of each element in the array (corresponding to step 2 above), resulting in the following cyclical execution pattern: obtain and record the current clock; access a certain array element; obtain and record the current clock.

[0078] Therefore, this application proposes an instruction matching method, wherein the target value of the matching item represents the opcode for obtaining the current clock, the mask of the matching item is the bit where the opcode is located, and the instruction result is clock information unrelated to the current clock or inaccurate clock information.

[0079] Specifically, this application proposes a bypass for instructions used to obtain the current clock, preventing the instructions from obtaining an accurate clock or clock information unrelated to the current clock. This disrupts the statistical differences caused by the side channel and avoids the leakage of sensitive data from the side channel. Furthermore, if the instruction matching method is mask matching, the mask of the matching item should select the bit containing the opcode of the instruction used to obtain the current clock, and the corresponding target value is the opcode of the instruction used to obtain the current clock. Of course, if there are multiple opcodes, all multiple opcodes are included in the mask and target value. Thus, when an instruction is matched, the instruction bypass unit gains complete control over the instruction and can directly cause it to return an incorrect or inaccurate clock.

[0080] This application also provides a method for correcting errors in the CPU hardware implementation that lead to unexpected instruction results. Such instructions are set as instructions requiring bypass processing, so that the bypass result is either the expected instruction result, triggers an exception, or is empty. Since the bypass result is determined to be the instruction result of the given instruction, making the bypass result the expected instruction result corrects the hardware implementation error, ensuring the instruction produces the expected result. Some logical defects can be corrected simply by preventing the instruction from being executed. There are two ways to prevent instruction execution: one is to trigger an exception, and the other is to ignore such instructions. Each method has its advantages: triggering an exception is more in line with the instruction set specifications; since handling exceptions has higher overhead, directly ignoring such instructions without triggering an exception is beneficial to performance. Ignoring instructions means that after receiving such instructions, the instruction bypass unit directly sets the target address to the address of the next instruction, or directly outputs the bypass result as an empty result.

[0081] The CPU includes an instruction matching unit and an instruction bypass unit. Instruction matching is achieved by setting matching terms, with two possible methods: the first is fine-grained instruction matching; the second is to first match a class of instructions (coarse matching), and then further identify whether an instruction needs bypass processing in the instruction bypass unit (fine matching). Each method has its advantages and disadvantages: the first method avoids the overhead of fine matching, but consumes more matching terms when many instructions need bypass processing; the second method saves matching terms, but fine matching introduces additional overhead. In other words, different target instructions (i.e., instructions that need bypass processing) can share the same matching term, as long as their masks and target values ​​have common bits, these common bits can be configured as a shared matching term. For the first matching method, if the instruction matching method is mask matching, the mask and target value of the matching term should select the minimum number of bits sufficient to determine the target instruction and exclude non-target instructions; that is, to cover as wide a range of matching results as possible while ensuring matching accuracy. For the second matching method, the mask of the matching item and the selected bits of the target value may determine both the target instruction and the non-target instruction. In this case, the instruction matching unit performs a coarse match on the instruction based on the mask and / or target value in the matching item, and takes the matched instruction as the coarse match instruction. The instruction bypass unit performs a fine match on the coarse match instruction to determine whether the instruction is an instruction that needs to be bypassed.

[0082] The instruction matching unit's method of performing coarse and fine matching of instructions can also be applied to situations where an instruction has an error in its CPU hardware implementation, leading to unexpected instruction results. If the instruction does not have an error in its CPU hardware implementation, it is executed normally; otherwise, the bypass result is either the expected instruction result, an exception is triggered, or nothing is returned. Optionally, the effective bits of the mask and / or target value in the matching item corresponding to the coarse match are less than the effective bits formed by summing the matching rules used for the fine match. That is, the mask and target value of the matching item select several levels of opcodes, or certain bits of the opcode, thus sacrificing some matching precision and leaving it to the instruction bypass unit for fine matching of the instruction, thereby saving the use of matching items. In this case, in addition to implementing the aforementioned behavior of ignoring instructions or triggering exceptions, the instruction bypass unit also needs to allow the normal execution of legal instructions. That is, after determining that the instruction is legally executable, the target address is set to the address of the instruction, which causes the instruction to temporarily skip one instruction matching, thereby allowing the instruction to be executed normally, i.e., executed on the pipeline.

[0083] Taking the GhostWrite logical defect as an example, this illustrates how to use the two matching methods. Taking mask matching as an example, if you want to use the first matching method to cover all illegal mop field values ​​under STORE-FP, namely 001, 100, 101, and 110, you would set the following matching items as shown in Table 2.

[0084] Table 2

[0085]

[0086] At this point, the mask and target value of each match item do indeed cover the minimum number of bits sufficient to determine a class of instructions. Adding any bit to the match results in unnecessary narrowing of the matching range; removing any bit will result in matching potentially valid instructions. Notice that match item 2 does not match the 26th bit, which is the lowest bit of the mop field. This is because the mop field values ​​100 and 101 are both invalid, so matching only the two highest bits is sufficient to match both values ​​simultaneously; in other words, these two values ​​share the same match item. Generally, the number of matches is always limited and their use should be carefully planned. Therefore, merging these two values ​​into the same match item can save on match item consumption. Of course, in practical use, match item 2 can also be split into two matches, one matching mop=100 and the other matching mop=101, achieving the same effect, only using more matches.

[0087] If you want to use the second matching method to cover all illegal mop field values ​​(i.e., 001, 100, 101, 110) under STORE-FP, for example, you would set the following matching items.

[0088]

[0089] At this point, the MOP field is not involved in the matching, so valid MOP field values ​​will also be matched. The instruction bypass unit then needs to analyze the validity of the MOP field after obtaining the bypassed instruction, and then determine whether the instruction should be executed normally, or whether an exception should be raised, or whether the instruction result should be empty. It can be seen that this method greatly saves matching items.

[0090] This application also provides a method for adding new instructions using instruction bypass, wherein the instruction to be bypassed is a new instruction, the target value of the matching item is a reserved opcode, and / or the mask of the matching item is a reserved bit field, and the target value of the matching item is at least a level opcode.

[0091] Specifically, a typical instruction set contains many reserved opcodes and even the values ​​of certain bit fields in some instructions. Optionally, new instructions can be constructed using reserved opcodes or bit field fetching to achieve new functions. New instructions can be constructed by configuring instruction matching entries, and the logic involved in instruction bypass units can also be used to implement the functionality of new instructions. For example, if a new instruction is added using a reserved opcode, the matching entry will include the opcode in the matching, set the mask of the corresponding bit to 1, and set the target value to the target opcode. If the reserved opcode is an n-level opcode, then opcodes from level 1 to level n should all be included in the matching.

[0092] If a certain type of instruction defines the values ​​of some of its reserved bit fields, it is necessary not only to include the opcodes at all levels that can determine the type of instruction in the matching, but also to include the new bit field values ​​in the matching, that is, to set the mask of the corresponding bit to 1 and set the target value to the new bit field value.

[0093] This application also provides a CPU, including an instruction matching unit and an instruction bypass unit. The instruction bypass unit can be a Programmable Logic Device (PLD). The PLD can implement specified logic to read or modify the processor's internal state, thereby simulating the effects of instruction execution at certain pipeline stages. Specifically, the bypassed instructions are processed by logic programmed (burned, or flashed) into the PLD. The logic programmed into the PLD should be compatible with each matching item. In other words, the logic in the PLD should be capable of executing all machine code matched by the matching items. This does not mean that all machine code matched by the matching items will be considered valid by the logic in the programmable logic device. Determining the machine code of some bypassed instructions as abnormal and triggering an exception is also a possible execution method. Optionally, multiple instruction bypass units can be implemented to process multiple bypassed instructions simultaneously. This can be achieved by setting up multiple PLDs or by programming multiple instruction bypass logics within a single PLD. The instruction matching unit in this application can be a PLD or an ASIC.

[0094] The instruction matching unit is used to execute any of the instruction processing methods described above. The instruction bypass unit is used to bypass the instruction based on the instruction matching unit's instructions and feed back the bypassed instruction result to the instruction matching unit. Specifically, the instruction matching unit is used to perform coarse matching on the instruction based on the mask and / or target value in the matching item, and to take the matched instruction as the coarse matching instruction. The bypass processing unit is also used to perform fine matching based on the coarse matching instruction to determine whether the instruction is an illegal instruction that needs to be bypassed.

[0095] Figure 6This is a schematic diagram of the structure of an instruction processing device 6000 provided in an embodiment of this application. Figure 6 As shown, it includes at least one processor 601 and a memory 602 connected to at least one processor 601. In this embodiment, the specific connection medium between the processor 601 and the memory 602 is not limited. Figure 6 Taking the connection between the processor 601 and the memory 602 via a bus as an example, the bus can be divided into address bus, data bus, control bus, etc.

[0096] In this embodiment of the application, the memory 602 stores instructions that can be executed by at least one processor 601. By executing the instructions stored in the memory 602, the at least one processor 601 can implement the steps of the above-described instruction processing method.

[0097] The processor 601 is the control center of the computer device, capable of connecting various parts of the computer device via various interfaces and lines. It performs resource configuration by running or executing instructions stored in the memory 602 and accessing data stored in the memory 602. Optionally, the processor 601 may include one or more processing units. The processor 601 may integrate an application processor and a modem processor. The application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may not be integrated into the processor 601. In some embodiments, the processor 601 and the memory 602 may be implemented on the same chip; in other embodiments, they may be implemented on separate chips.

[0098] Processor 601 can be a general-purpose processor, such as a central processing unit (CPU), digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0099] Memory 602, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 602 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Memory 602 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited thereto. In the embodiments of this application, memory 602 can also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0100] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0101] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0102] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0103] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0104] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An instruction processing method, characterized by, The method is suitable for a CPU using a pipeline mode to process instructions, and the method comprises: The pipeline comprises a fetch stage and an execution effect stage; the execution effect stage is a pipeline stage after the fetch stage and needs to be rolled back when an exception occurs; instruction matching is performed based on indication information representing the instruction and a mask and / or a target value in any matching item, to determine whether the instruction needs to be processed by bypassing; the indication information is at least one of a machine code of the instruction, an address of the instruction on a memory, and an internal number of the instruction; the mask is used to indicate binary bits participating in matching in the instruction; the target value is a binary value compared with the instruction; if it is determined that the instruction needs to be processed by bypassing, the pipeline in which the instruction is located is stalled; an instruction result obtained by processing the instruction by bypassing is determined as an instruction result of the instruction, and the pipeline is resumed at a target address indicated by the bypassing; wherein the instruction matching based on the indication information representing the instruction and the mask and / or the target value in any matching item comprises: the instruction obtained by the fetch stage of the pipeline is subjected to instruction matching based on the indication information representing the instruction, and the pipeline continues to be in an execution state; if the pipeline executes to any execution effect stage and has not obtained an instruction matching result, the pipeline is paused until the instruction matching result is obtained, the instruction matching result being whether the instruction needs to be processed by bypassing.

2. The method of claim 1, wherein, The instruction matching based on the indication information representing the instruction and the mask and / or the target value in any matching item further comprises: the instruction obtained by the fetch stage of the pipeline is subjected to instruction matching based on the indication information representing the instruction, and the pipeline continues to be in an execution state; if it is determined that the instruction needs to be processed by bypassing, the pipeline in which the instruction is located is stalled, comprising: if it is determined that the instruction needs to be processed by bypassing, the pipeline executes to any execution effect stage, and then the pipeline is stalled after being rolled back.

3. The method according to claim 1 or 2, characterized in that, The pipeline further comprises a non-execution effect stage after the fetch stage and before the execution effect stage; the non-execution effect stage is a pipeline stage that does not need to be rolled back when an exception occurs; if it is determined that the instruction needs to be processed by bypassing, the pipeline in which the instruction is located is stalled, comprising: if it is determined that the instruction needs to be processed by bypassing, the pipeline executes to any non-execution effect stage, and then the pipeline in which the instruction is located is stalled.

4. The method of claim 1, wherein, The pipeline comprises a fetch stage and a decode stage; the decode stage is before the execution effect stage; The instruction matching based on the indication information representing the instruction and the mask and / or the target value in any matching item to determine whether the instruction needs to be processed by bypassing comprises: instruction matching is performed based on the indication information representing the instruction after the fetch stage of the pipeline is completed and before the decode stage of the pipeline starts, to determine whether the instruction needs to be processed by bypassing.

5. The method of claim 1, wherein, The pipeline comprises a fetch stage and an instruction adjustment stage; the instruction adjustment stage is after the fetch stage; the instruction adjustment stage is before the execution effect stage; The instruction matching is performed based on the indication information of the representative instruction and a mask and / or a target value in any matching item, and includes: During processing of any instruction adjustment stage of the pipeline, instruction matching based on indication information of a representative instruction is performed on a first instruction before adjustment by the instruction adjustment stage and a second instruction after adjustment by the instruction adjustment stage.

6. The method of any one of claims 1, 2, or 4, wherein, The instruction matching is performed based on the indication information of the representative instruction and a mask and / or a target value in any matching item, and includes: If the matching is successful, it is determined that the instruction needs to be processed by bypassing.

7. The method of claim 6, wherein, The target value of the matching item represents an operation code of a current clock; the mask of the matching item is a bit where the operation code is located; and the instruction result is clock information irrelevant to the current clock or inaccurate clock information.

8. The method of claim 6, wherein, The instruction needing to be processed by bypassing is a newly added instruction. The target value of the matching item is a reserved operation code, and / or the mask of the matching item is a reserved bit field, and the target value of the matching item is at least one level of operation code.

9. The method of claim 6, wherein, The instruction needing to be processed by bypassing has an error in hardware implementation of a CPU, and the error causes an unexpected instruction result; and the bypass result is an expected instruction result, an exception, or null.

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