Memory device and computing system including the same

Abstract

A memory device and a computing system including the memory device are disclosed. The computing system includes a first memory device that stores a first data set, and a compute quick link (CXL) switch that arbitrates communications of a first host device and a second host device with the first memory device based on a CXL interface. A first memory device receives a first data request and a second data request from a first host device and a second host device through a CXL switch, respectively, and obtains first directory information and second directory information from the first host device and the second host device through the CXL switch, first encoded data is generated based on the first directory information and the second directory information, and the first encoded data is output to each of the first host device and the second host device through the CXL switch in response to the first data request and the second data request.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0023782 filed on February 19, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present disclosure described herein relate to a semiconductor memory, and more particularly, to a computing system including a memory device. Background Art

[0004] Semiconductor memories are classified as volatile memory devices that lose stored data when power is cut off, such as dynamic random access memory (DRAM) or static RAM (SRAM), or non-volatile memory devices that retain stored data even when power is cut off, such as flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), or resistive RAM (RRAM).

[0005] In a computing system in which multiple host devices share a memory device, when each of the multiple host devices requests data from the memory device, the memory device sequentially transmits the data corresponding to the request to the multiple host devices. A problem with this data transmission method is that the efficiency of data transmission decreases as the number of host devices sharing the memory device increases. Therefore, in a computing system in which multiple host devices share a memory device, a method for improving data transmission efficiency may be needed. Summary of the Invention

[0006] Embodiments of the present disclosure provide a memory device that uses a data transmission method to improve data transmission efficiency and a computing system including the memory device.

[0007] According to some embodiments, a system includes a first memory device storing a first data set, and a Compute Express Link (CXL) switch arbitrating communications between a first host device and a second host device and the first memory device over a CXL interface. The first memory device is configured to receive a first data request from the first host device via the CXL switch, receive a second data request from the second host device via the CXL switch, obtain first directory information associated with at least one data stored in the first host device from the first host device via the CXL switch, obtain second directory information associated with at least one data stored in the second host device from the second host device via the CXL switch, generate first encoded data based on the first directory information and the second directory information, and output the first encoded data to the first host device and the second host device via the CXL switch in response to the first data request and the second data request.

[0008] According to some embodiments, a system includes a first memory device storing a plurality of data, and a fabric manager that arbitrates communications between a first host device and a second host device and the first memory device based on a Compute Express Link (CXL) interface. The fabric manager receives a first data request from the first host device, receives a second data request from the second host device, obtains first directory information associated with at least one data stored in the first host device from the first host device, obtains second directory information associated with at least one data stored in the second host device from the second host device, generates a third data request based on the first directory information and the second directory information, and sends the third data request to the first memory device. The first memory device generates first encoded data in response to the third data request and sends the first encoded data to the fabric manager. The fabric manager also outputs the first encoded data received from the first memory device to the first host device and the second host device in response to the first data request and the second data request, respectively.

[0009] According to some embodiments, a system includes a first host device and a second host device, a first memory device storing a plurality of data, and a Compute Express Link (CXL) switch, wherein the CXL switch arbitrates communication between the first and second host devices and the first memory device based on a CXL interface. The first host device sends a first data request to the first memory device via the CXL switch, and the second host device sends a second data request to the first memory device via the CXL switch. After receiving the first and second data requests, the first memory device obtains first directory information associated with at least one data stored in the first host device from the first host device via the CXL switch, obtains second directory information associated with at least one data stored in the second host device from the second host device via the CXL switch, generates first encoded data based on the first and second directory information, and outputs the first encoded data to each of the first and second host devices via the CXL switch in response to the first and second data requests. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0011] Figure 1 is a block diagram illustrating a computing system including a storage device.

[0012] Figure 2 is a block diagram illustrating a computing system to which a storage system is applied, according to some embodiments of the present disclosure.

[0013] Figure 3 is shown in more detail Figure 2 A block diagram of the components of a computing system.

[0014] Figure 4 is a block diagram illustrating a computing system according to some embodiments of the present disclosure.

[0015] Figure 5 It shows Figure 4 A flow chart of a data transfer operation of a computing system.

[0016] Figure 6A 、 Figure 6B and Figure 6C It is an explanation Figure 4 An illustration of the operation of a computing system.

[0017] Figure 7A 、 Figure 7B and Figure 7C It shows Figure 4 An illustration of the operation of a computing system.

[0018] Figure 8 It is shown that the memory module is used to implement Figure 4 A block diagram of a memory device.

[0019] Figure 9 It shows that the memory module is used to implement Figure 4 A block diagram of a memory device.

[0020] Figure 10 is a block diagram illustrating a computing system according to some embodiments of the present disclosure.

[0021] Figure 11 is a block diagram illustrating a computing system according to some embodiments of the present disclosure.

[0022] Figure 12 It shows Figure 11 A flow chart of a data transfer operation of a computing system.

[0023] Figure 13A 、 Figure 13B and Figure 13C It shows Figure 11 An illustration of the operation of a computing system. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described clearly and in detail so that those skilled in the technical field of the present disclosure can easily practice the embodiments of the present disclosure.

[0025] The components described with reference to terms such as "part or unit," "module," "block," and "or / or" used in the detailed description and the functional blocks shown in the drawings may be implemented in the form of software, hardware, or a combination thereof. Illustratively, the software may be machine code, firmware, embedded code, and application software. For example, the hardware may include an electrical circuit, an electronic circuit, a processor, a computer, an integrated circuit, an integrated circuit core, a pressure sensor, an inertial sensor, a micro-electromechanical system (MEMS), passive components, or a combination thereof.

[0026] Figure 1 is a block diagram illustrating a computing system 10 including a storage device 13. Figure 1 , the computing system 10 may include a host 11, a plurality of memory devices 12a and 12b, and a storage device 13. The host 11 may be external to the storage device 13 and may control the overall operation of the computing system 10. The plurality of memory devices 12a and 12b may be used as an operating memory or a system memory of the host 11.

[0027] The storage device 13 may include a storage controller 13a, a buffer memory 13b, and a nonvolatile memory 13c. The storage controller 13a may store data in the nonvolatile memory 13c or transmit data stored in the nonvolatile memory 13c to the host 11 under the control of the host 11.

[0028] The buffer memory 13b can store various information required for the operation of the storage device 13. For example, the storage controller 13a can manage the data stored in the non-volatile memory 13c by using map data. The map data may include information about the relationship between the logical block addresses managed by the host 11 and the physical block addresses of the non-volatile memory 13c.

[0029] In some embodiments, the buffer memory 13b may be a high-speed memory, such as DRAM.

[0030] Figure 2 1 is a block diagram illustrating a computing system 100 to which a storage system according to some embodiments of the present disclosure is applied. Figure 2 The computing system 100 may include a host 101, a plurality of memory devices 102a and 102b, a Compute Express Link (CXL) storage device 110, and a CXL memory 120. In some embodiments, the computing system 100 may be included in a user device such as a personal computer, a laptop computer, a server, a media player, a digital camera, or an automotive device (such as a navigation device, a black box, or an automotive electrical device). In some embodiments, the computing system 100 may be a mobile system such as a portable communication terminal (mobile phone), a smartphone, a tablet personal computer, a wearable device, a healthcare device, or the Internet of Things (IoT).

[0031] Host 101 can control the overall operation of computing system 100. In some embodiments, host 101 can be one of various processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a data processing unit (DPU). In some embodiments, host 101 can include a single-core processor or a multi-core processor.

[0032] The plurality of memory devices 102a and 102b may be used as main memory or system memory for the computing system 100. In some embodiments, each of the plurality of memory devices 102a and 102b may be a DRAM device and may include a form factor of a dual in-line memory module (DIMM). However, the scope of the present disclosure is not limited in this regard, and the plurality of memory devices 102a and 102b may include non-volatile memory devices, such as flash memory devices, phase change RAM (PRAM), resistive RAM (RRAM), or magnetic RAM (MRAM).

[0033] The plurality of memory devices 102a and 102b may communicate directly with the host 101 via a double data rate (DDR) interface. In some embodiments, the host 101 may include a memory controller configured to control the plurality of memory devices 102a and 102b. However, the scope of the present disclosure is not limited thereto, and the plurality of memory devices 102a and 102b may communicate with the host 101 via various interfaces.

[0034] The CXL memory device 110 may include a CXL memory controller 111 and a non-volatile memory NVM. The CXL memory controller 111 may store data in the non-volatile memory NVM or transmit data stored in the non-volatile memory NVM to the host 101 under the control of the host 101. In some embodiments, the non-volatile memory NVM may be a NAND flash memory, but the scope of the present disclosure is not limited thereto.

[0035] The CXL memory 120 may include a CXL memory controller 121 and a buffer memory BFM. The CXL memory controller 121 may store data in the buffer memory BFM or transmit data stored in the buffer memory BFM to the host 101. In some embodiments, the buffer memory BFM may be a DRAM, but the scope of the present disclosure is not limited thereto.

[0036] In some embodiments, the host 101, CXL storage device 110, and CXL memory 120 can be configured to share the same interface. For example, the host 101, CXL storage device 110, and CXL memory 120 can communicate with each other via a CXL interface IF_CXL. In some embodiments, the CXL interface IF_CXL can represent a low-latency, high-bandwidth link that enables various connections between accelerators, memory devices, or various electronic devices by supporting dynamic protocol multiplexing for coherency, memory access, and input / output protocols (I / O protocols).

[0037] In some embodiments, the CXL memory device 110 may access the CXL memory 120 through the CXL interface IF_CXL. The CXL memory 120 may store data in the buffer memory BFM or transmit data stored in the buffer memory BFM to the CXL memory device 110 under the control of the CXL memory device 110.

[0038] In some embodiments, the storage controller 13a of the conventional storage device 13 can communicate with the host 11 through a host interface (such as Peripheral Component Interconnect Express (PCIe) or Non-Volatile Memory Express (NVMe)), and can communicate with the buffer memory 13b through a memory interface (such as DDR or Low Power Double Data Rate (LPDDR) interface). In other words, the storage controller 13a of the conventional storage device 13 can communicate with the external host 11 and the internal buffer memory 13b of the storage device through different interfaces (i.e., heterogeneous interfaces).

[0039] On the other hand, according to some embodiments of the present disclosure, the CXL storage controller 111 of the CXL storage device 110 can communicate with the host 101 and the CXL memory 120 (i.e., the buffer memory) via the CXL interface IF_CXL. In other words, the CXL storage controller 111 of the CXL storage device 110 can communicate with the host 101 and the CXL memory 120 via a homogeneous interface or a common interface.

[0040] Hereinafter, for ease of description, it is assumed that the host 101, the CXL storage device 110, and the CXL memory 120 can communicate with each other via the CXL interface IF_CXL. However, the scope of the present disclosure is not limited thereto, and the host 101, the CXL storage device 110, and the CXL memory 120 can communicate with each other based on various computing interfaces (such as the GEN-Z protocol, the NVLink protocol, the CCIX protocol, and the open CAPI (Coherent Accelerator Processor Interface) protocol).

[0041] Figure 3 is shown in more detail Figure 2 A block diagram of the components of a computing system. Figure 2 and Figure 3 The computing system 100 may include a CXL switch SW_CXL, a host 101 , a CXL storage device 110 , and a CXL memory 120 .

[0042] The CXL switch SW_CXL may be a component included in the CXL interface IF_CXL. The CXL switch SW_CXL may be configured to arbitrate communications between the host 101, the CXL storage device 110, and the CXL memory 120. For example, when the host 101 and the CXL storage device 110 communicate with each other, the CXL switch SW_CXL may be configured to provide information, such as requests, data, responses, and / or signals sent from the host 101 or the CXL storage device 110, to the CXL memory device 110 or the host 101. When the host 101 and the CXL memory 120 communicate with each other, the CXL switch SW_CXL may be configured to provide information, such as requests, data, responses, and / or signals sent from the host 101 or the CXL memory 120, to the host 101 or the CXL memory 120. When the CXL storage device 110 and the CXL memory 120 communicate with each other, the CXL switch SW_CXL may be configured to provide information, such as requests, data, responses, and / or signals sent from the CXL storage device 110 or the CXL memory 120 , to the CXL storage device 110 or the CXL memory 120 .

[0043] The host 101 may include a CXL host interface (CXL_H I / F) circuit 101 a that can communicate with the CXL storage device 110 or the CXL memory 120 through a CXL switch SW_CXL.

[0044] The CXL memory device 110 may include a CXL memory controller 111 and a non-volatile memory NVM. The CXL memory controller 111 may include a CXL memory interface (CXL_S I / F) circuit 111 a, a processor 111 b, a RAM 111 c, a flash translation layer (FTL) 111 d, an error correction code (ECC) engine 111 e, and a NAND interface circuit 111 f.

[0045] The CXL memory interface circuit 111 a may be connected to the CXL switch SW_CXL and may communicate with the host 101 or the CXL memory 120 .

[0046] Processor 111b may be configured to control overall operations of CXL memory controller 111. RAM 111c may be used as an operating memory or buffer memory for CXL memory controller 111. In some embodiments, RAM 111c may be an SRAM and may be used as a read buffer, a write buffer, or the like.

[0047] The FTL 111d can perform various management operations for efficiently using the non-volatile memory NVM. For example, the FTL 111d can perform address conversion between logical block addresses managed by the host 101 and physical block addresses used in the non-volatile memory NVM based on mapping data (or a mapping table). The FTL 111d can perform bad block management operations associated with the non-volatile memory NVM. The FTL 111d can perform wear leveling operations associated with the non-volatile memory NVM. The FTL 111d can also perform garbage collection operations associated with the non-volatile memory NVM.

[0048] In some embodiments, FTL 111d may be implemented in software, hardware, firmware, or a combination thereof. When FTL 111d is implemented in software or firmware, program code associated with FTL 111d may be stored in RAM 111c and driven by processor 111b. When FTL 111d is implemented in hardware, hardware components configured to perform the various management operations described above may be implemented in CXL storage controller 111.

[0049] The ECC engine 111e can perform error detection and correction on data stored in the non-volatile memory NVM. For example, the ECC engine 111e can generate parity bits associated with the data to be stored in the non-volatile memory NVM, and the generated parity bits can be stored in the non-volatile memory NVM together with the data. When reading data from the non-volatile memory NVM, the ECC engine 111e can detect and correct errors in the data by using the parity bits read from the non-volatile memory NVM together with the data.

[0050] The NAND interface circuit 111f can control the non-volatile memory NVM so that data is stored in or read from the non-volatile memory NVM. In some embodiments, the NAND interface circuit 111f can be implemented to comply with a standard protocol, such as a toggle interface or an open NAND flash memory interface (ONFI). For example, the non-volatile memory NVM may include multiple NAND flash memory devices, and when the NAND interface circuit 111f is implemented based on a toggle interface, the NAND interface circuit 111f communicates with the multiple NAND flash memory devices through multiple channels. Multiple NAND flash memory devices can be connected to multiple channels through a multi-channel multiplexing configuration.

[0051] The NAND interface circuit 111f can transmit a chip enable signal / CE, a command latch enable signal CLE, an address latch enable signal ALE, a read enable signal / RE, and a write enable signal / WE to each of the plurality of NAND flash memory devices through each of the plurality of channels. The NAND interface circuit 111f and each of the plurality of NAND flash memory devices can exchange a data signal DQx and a data strobe signal DQS through each of the plurality of channels.

[0052] Table 1.

[0053] / CE CLE ALE / WE / RE DQS DQ model L H L ↑ H X CMD Command Input L L H ↑ H X ADDR Address Input L L L H H ↑↓ DATA_in Data Input L L L H ↑↓ ↑↓ DATA_out Data Output

[0054] Table 1 shows the operating modes of the NAND flash memory device according to the state of each signal. Referring to Table 1, when the NAND flash memory device receives a command CMD, an address ADDR, a data input Data_in, or a data output DATA_out, the chip enable signal / CE maintains a low level L state. During the command input mode (Command Input), the NAND interface circuit 111f can control the signal lines so that the command latch enable signal CLE is at a high level H, the address latch enable signal ALE is at a low level L, the write enable signal / WE switches between a high level H and a low level L, and the read enable signal / RE is at a high level H. During the command input mode (Command Input), the NAND interface circuit 111f can transmit the command CMD to the NAND flash device via the data signal DQx in synchronization with the rising edge ↑ of the write enable signal / WE. The NAND flash memory device can recognize the command CMD from the data signal DQx in response to the rising edge ↑ of the write enable signal / WE.

[0055] During the address input mode (Address Input), the NAND interface circuit 111f can control the signal lines so that the command latch enable signal CLE is at a low level L, the address latch enable signal ALE is at a high level H, the write enable signal / WE switches between a high level H and a low level L, and the read enable signal / RE is at a high level H. During the address input mode (Address Input), the NAND interface circuit 111f can send the address ADDR to the NAND flash memory device via the data signal DQx in synchronization with the rising edge ↑ of the write enable signal / WE. The NAND flash memory device can identify the address ADDR from the data signal DQx in response to the rising edge ↑ of the write enable signal / WE. In some embodiments, the address ADDR can be a value corresponding to the physical block address of the NAND flash memory device.

[0056] During the data input mode (Data Input), the NAND interface circuit 111f may control the signal lines so that the command latch enable signal CLE is at a low level L, the address latch enable signal ALE is at a low level L, the write enable signal / WE is at a high level H, the read enable signal / RE is at a high level H, and the data strobe signal DQS switches between a high level H and a low level L. During the data input mode (Data Input), the NAND interface circuit 111f may transmit data DATA to the NAND flash memory device through the data signal DQx in synchronization with the rising edge ↑ and the falling edge ↓ of the data strobe signal DQS. The NAND flash memory device may identify the data DATA from the data signal DQx in response to the rising edge ↑ and the falling edge ↓ of the data strobe signal DQS.

[0057] During the data output mode (Data Output), the NAND interface circuit 111f may control the signal lines so that the command latch enable signal CLE is at a low level L, the address latch enable signal ALE is at a low level L, the write enable signal / WE is at a high level H, and the read enable signal / RE switches between a high level H and a low level L. During the data output mode (Data Output), the NAND flash memory device may generate a data strobe signal DQS that switches between a high level H and a low level L in response to the read enable signal / RE. The NAND flash memory device may transmit data DATA to the NAND interface circuit 111f via a data signal DQx synchronized with the rising edge ↑ and the falling edge ↓ of the data strobe signal DQS. The NAND interface circuit 111f may identify the data DATA from the data signal DQx in response to the rising edge ↑ and the falling edge ↓ of the data strobe signal DQS.

[0058] The above-described switching interfaces are illustrative, and the scope of the present disclosure is not limited thereto.

[0059] The nonvolatile memory NVM may store or output data under the control of the CXL memory controller 111 .

[0060] The CXL memory 120 may include a CXL memory controller 121 and a buffer memory BFM. The CXL memory controller 121 may include a CXL memory interface (CXL_MI / F) circuit 121a, a processor 121b, a memory manager 121c, and a buffer memory interface circuit 121d.

[0061] The CXL memory interface circuit 121 a may be connected to a CXL switch SW_CXL and may communicate with the host 101 or the CXL memory device 110 through the CXL switch SW_CXL.

[0062] Processor 121b may be configured to control the overall operation of CXL memory controller 121. Memory manager 121c may be configured to manage buffer memory (BFM). For example, memory manager 121c may be configured to convert memory addresses (e.g., logical addresses or virtual addresses) accessed from host 101 or CXL memory device 110 into physical addresses of buffer memory (BFM). In some embodiments, the memory addresses may be addresses used to manage a storage area of CXL memory 120 and may be logical addresses or virtual addresses specified and managed by host 101.

[0063] The buffer memory interface circuit 121d may control the buffer memory BFM to store data in the buffer memory BFM or read data from the buffer memory BFM. In some embodiments, the buffer memory interface circuit 121d may be implemented to comply with standard protocols such as DDR interface and LPDDR.

[0064] The buffer memory BFM may store data or may output stored data under the control of the CXL memory controller 121 .

[0065] In some embodiments, the host 101 and the CXL storage device 110 may communicate with each other using CXL.10 as an input / output protocol. CXL.io may include a non-compliant input / output protocol based on PCIe. The host 101 and the CXL storage device 110 may exchange user data or various information with each other using CXL.10.

[0066] In some embodiments, the CXL memory device 110 and the CXL memory 120 may communicate with each other using CXL.mem as a memory access protocol. CXL.mem may be a memory access protocol that supports accessing memory. The CXL memory device 110 may access a portion of the CXL memory 120 (e.g., a region dedicated to CXL memory devices) using CXL.mem.

[0067] In some embodiments, the host 101 and the CXL memory 120 can communicate with each other using CXL.mem as a memory access protocol. The host 101 can access the remaining area of the CXL memory 120 (eg, the remaining area except for the dedicated area for CXL storage) using CXL.mem.

[0068] The above access types (eg, CXL.10, CXL.mem) are some example protocols, but the scope of the present disclosure is not limited in this respect.

[0069] In some embodiments, the CXL storage device 110 and the CXL memory 120 may be installed on a physical port (e.g., a PCIe physical port) based on a CXL interface. In some embodiments, the CXL storage device 110 and the CXL memory 120 may be implemented based on an E1.S, E1.1, E3.S, E3.1, or PCIe AIC (CEM) form factor. In some embodiments, the CXL storage device 110 and the CXL memory 120 may be implemented based on a U.2 form factor, an M.2 form factor, or various other PCIe-based form factors or various other small form factors. As described below, Figure 4 As described in , the CXL storage device 110 and the CXL memory 120 may be implemented in various form factors and may support a hot-swap function that allows installation in or removal from a physical port.

[0070] Figure 4 is a block diagram illustrating a computing system according to some embodiments of the present disclosure. Hereinafter, for ease of description, detailed descriptions of overlapping components will be omitted. Figure 4 , the computing system 200 may include a first host 201_1 and a second host 201_2 , a plurality of memory devices 202_1 and 202_2 , a CXL switch SW_CXL, and a CXL memory 210 .

[0071] The first host 201_1 and the second host 201_2 include cache memories 211_1 and 211_2, respectively, and can store frequently accessed data in the cache memories 211_1 and 211_2, respectively. For example, the first host 201_1 can include cache memory 211_1 and can store frequently accessed data in the cache memory 211_1. For example, the second host 201_2 can include cache memory 211_2 and can store frequently accessed data in the cache memory 211_2.

[0072] The first host 201_1 and the second host 201_2 may be directly connected to a plurality of memory devices 202_1 and 202_2, respectively. For example, the first host 201_1 may be directly connected to the memory device 202_1, and the second host 201_2 may be directly connected to the memory device 202_2.

[0073] The first host 201_1 and the second host 201_2 may store frequently accessed data in the memory devices 202_1 and 202_2, respectively. For example, the first host 201_1 may store frequently accessed data in the memory device 202_1, and the second host 201_2 may store frequently accessed data in the memory device 202_2.

[0074] In some embodiments, the first host 201_1 and the second host 201_2 may store data in the cache memories 211_1 and 211_2 or the memory devices 202_1 and 202_2 based on the frequency of accessing the data.

[0075] For example, when the frequency of accessing data is greater than or equal to a first threshold, the first host 201_1 may store the data in the cache memory 211_1. When the frequency of accessing data is less than or equal to the first threshold, the first host 201_1 may store the data in the memory device 202_1. In some embodiments, when the frequency of accessing data is less than or equal to the first threshold and greater than or equal to a second threshold, the first host 201_1 may store the data in the memory device 202_1.

[0076] For example, when the frequency of accessing data is greater than or equal to a first threshold, the second host 201_2 may store the data in the cache memory 211_2. When the frequency of accessing data is less than or equal to the first threshold and greater than or equal to a second threshold, the second host 201_2 may store the data in the memory device 202_2. In some embodiments, when the frequency of accessing data is less than or equal to the first threshold and greater than or equal to the second threshold, the second host 201_2 may store the data in the memory device 202_2.

[0077] In some embodiments, the threshold may be a value predetermined by the first host 201_1 and the second host 201_2 based on the frequency of accessing data.

[0078] The first host 201_1 and the second host 201_2 and the CXL memory 210 may be connected to the CXL switch SW_CXL and may communicate with each other through the CXL switch SW_CXL, respectively.

[0079] The first host 201_1 and the second host 201_2 may respectively send data requests to the CXL memory 210 through the CXL switch SW_CXL. For example, the first host 201_1 may send a first data request through the CXL switch SW_CXL, and the second host 201_2 may send a second data request through the CXL switch SW_CXL.

[0080] Each of the first host 201_1 and the second host 201_2 can receive data corresponding to the data request from the CXL memory 210 through the CXL switch SW_CXL. For example, the first host 201_1 can receive data corresponding to the first data request through the CXL switch SW_CXL, and the second host 201_2 can receive data corresponding to the first data request through the CXL switch SW_CXL.

[0081] The CXL memory controller 211 may receive data requests from the first host 201_1 and the second host 201_2 through the CXL switch SW_CXL. For example, the CXL memory controller 211 may receive a first data request from the first host 201_1 and a second data request from the second host 201_2 through the CXL switch SW_CXL.

[0082] The CXL memory controller 211 may acquire directory information about data stored in the cache memories 211_1 and 211_2 or the memory devices 202_1 and 202_2 through the CXL switch SW_CXL.

[0083] For example, after receiving the first data request, the CXL memory controller 211 may obtain first directory information about at least one data stored in the cache memory 211_1 or the memory device 202_1 from the first host 201_1 through the CXL switch SW_CXL.

[0084] For example, after receiving the second data request, the CXL memory controller 211 may obtain second directory information about at least one data stored in the cache memory 211_2 or the memory device 202_2 from the second host 201_2 through the CXL switch SW_CXL.

[0085] The CXL memory controller 211 may generate encoded data from at least some of the plurality of data stored in the buffer memory BFM based on the directory information and may transmit the encoded data to each of the first host 201_1 and the second host 201_2 through the CXL switch SW_CXL.

[0086] For example, the CXL memory controller 211 may identify, based on the first directory information, first data from the plurality of data associated with the first data request that is not stored in the cache memory 211_1 or the memory device 202_1. Based on the second directory information, the CXL memory controller 211 may identify, based on the second directory information, second data from the plurality of data associated with the second data request that is not stored in the cache memory 211_2 or the memory device 202_2. The CXL memory controller 211 may generate encoded data by encoding the first and second data from the plurality of data stored in the buffer memory BFM, where the encoding is based on a logical operation. In response to the first and second data requests, the CXL memory controller 211 may transmit the encoded data to each of the first host 201_1 and the second host 201_2 via the CXL switch SW_CXL.

[0087] In some embodiments, the CXL memory controller 211 may perform encoding based on an XOR operation to generate encoded data. However, the scope of the present disclosure is not limited thereto, and the CXL memory controller 211 may perform encoding based on various logical operations to generate encoded data.

[0088] In some embodiments, the computing system 200 may include a reference Figure 2 and Figure 3 The CXL memory device 110 is described instead of the CXL memory 210. In this case, the CXL memory controller 111 of the CXL memory device 110 may execute the same Figure 4 The CXL memory controller 211 performs the same operation.

[0089] As described above, in the computing system 200 in which the first host 201_1 and the second host 201_2 share the CXL memory 210, the CXL memory 210 can output encoded data to each of the first host 201_1 and the second host 201_2 in response to data requests from the first host 201_1 and the second host 201_2, thereby improving data transmission efficiency.

[0090] Figure 5 It shows Figure 4 Flowchart of data transfer operations of a computing system. Figure 4 and Figure 5 In operation S111 , the first host 201_1 may issue a first data request REQ_d1 . The first data request REQ_d1 may be sent to the CXL switch SW_CXL. The CXL switch SW_CXL may send the first data request REQ_d1 to the CXL memory 210 that is the target of the first data request REQ_d1 .

[0091] In operation S112 , the second host 201_2 may issue a second data request REQ_d2 . The second data request REQ_d2 may be sent to the CXL switch SW_CXL . The CXL switch SW_CXL may send the second data request REQ_d2 to the CXL memory 210 , which is the target of the second data request REQ_d2 .

[0092] In some embodiments, the operations of operation S111 and operation S112 may be performed simultaneously.

[0093] Through operations S121 to S124, the CXL memory 210 can obtain directory information about data stored in the cache memories 211_1 and 211_2 or the memory devices 202_1 and 202_2 from the first host 201_1 and the second host 201_2. For example, in operation S121, the CXL memory 210 may output a first directory information request REQ_dr1 to obtain first directory information about at least one data stored in the cache memory 211_1 or the memory device 202_1. The first directory information request REQ_dr1 may be sent to the CXL switch SW_CXL. The CXL switch SW_CXL may send the first directory information request REQ_dr1 to the first host 201_1, which is the target of the first directory information request REQ_dr1.

[0094] In operation S122, the first host 201_1 may output a first directory information response REP_dr1 in response to a first directory information request REQ_dr1 received from the CXL switch SW_CXL. The first directory information response REP_dr1 may include first directory information. The first directory information response REP_dr1 may be transmitted to the CXL switch SW_CXL. The CXL switch SW_CXL may deliver the first directory information response REP_dr1 to the CXL memory 210, which is the target of the first directory information response REP_dr1.

[0095] In operation S123, the CXL memory 210 may output a second directory information request REQ_dr2 to obtain second directory information about at least one data stored in the cache memory 211_2 or the memory device 202_2. The second directory information request REQ_dr2 may be sent to the CXL switch SW_CXL. The CXL switch SW_CXL may send the second directory information request REQ_dr2 to the second host 201_2, which is the target of the second directory information request REQ_dr2.

[0096] In operation S124, the second host 201_2 may output a second directory information response REP_dr2 in response to the second directory information request REQ_dr2 received from the CXL switch SW_CXL. The second directory information response REP_dr2 may include the second directory information. The second directory information response REP_dr2 may be transmitted to the CXL switch SW_CXL. The CXL switch SW_CXL may transmit the second directory information response REP_dr2 to the CXL memory 210, which is the target of the second directory information response REP_dr2.

[0097] In some embodiments, the operations of operation S121 and operation S123 may be performed simultaneously.

[0098] In operation S131, the CXL memory 210 may generate encoded data based on first directory information and second directory information. For example, the CXL memory 210 may identify, based on the first directory information, first data from a plurality of data associated with a first data request that is not stored in the first host 201_1 (e.g., cache memory 211_1 or memory device 202_1). The CXL memory 210 may identify, based on the second directory information, second data from a plurality of data associated with a second data request that is not stored in the second host 201_2 (e.g., cache memory 211_2 or memory device 202_2). The CXL memory 210 may generate the encoded data by encoding the first data and the second data from the plurality of data stored in the buffer memory BFM based on a first logical operation.

[0099] In some embodiments, the first logical operation may be an XOR operation, but the scope of the present disclosure is not limited thereto, and the first logical operation may be one of various logical operations.

[0100] The CXL memory 210 can transmit encoded data to each of the first host 201_1 and the second host 201_2 in response to the first and second data requests through operations S141 and S142. For example, in operation S141, the CXL memory 210 can output a first data response REP_d1 in response to the first data request REQ_d1. The first data response REP_d1 can include encoded data. The first data response REP_d1 can be transmitted to the CXL switch SW_CXL. The CXL switch SW_CXL can transmit the first data response REP_d1 to the CXL memory 210, which is the destination of the first data response REP_d1.

[0101] In operation S142, the CXL memory 210 may output a second data response REP_d2 in response to the second data request REQ_d2. The second data response REP_d2 may include encoded data. The second data response REP_d2 may be transmitted to the CXL switch SW_CXL. The CXL switch SW_CXL may transmit the second data response REP_d2 to the CXL memory 210 as the destination of the second data response REP_d2.

[0102] In some embodiments, the encoded data in operations S141 and S142 may be sent in the form of a message.

[0103] In some embodiments, the CXL memory 210 may not perform at least one of operations S141 and S142. For example, after sending the first data request REQ_d1, the first host 201_1 may perform operations unrelated to the first data request REQ_d1. In this case, the first host 201_1 may send a data interrupt request to the CXL memory 210 via the CXL switch SW_CXL. The CXL memory 210 may respond to the data interrupt request received from the CXL switch SW_CXL without performing operation S141. However, the scope of the present disclosure is not limited in this regard. If some of the first host 201_1 and the second host 201_2 do not receive a data response and the CXL memory 210 recognizes this, the CXL memory 210 may not perform some of operations S141 and S142.

[0104] In operation S151, the first host 201_1 and the second host 201_2 may perform decoding on the encoded data received from the CXL switch SW_CXL. As a result of performing the decoding, the first host 201_1 and the second host 201_2 may obtain necessary data.

[0105] For example, the first host 201_1 may perform decoding based on the second logical operation on the encoded data received from the CXL switch SW_CXL. As a result of the decoding, the first host 201_1 may obtain first data from the data associated with the first data request that is not stored in the first host 201_1 (e.g., the cache memory 211_1 or the memory device 202_1). For example, the second host 201_2 may perform decoding based on the second logical operation on the encoded data received from the CXL switch SW_CXL. As a result of the decoding, the second host 201_2 may obtain second data from the data associated with the second data request that is not stored in the second host 201_2 (e.g., the cache memory 211_2 or the memory device 202_2).

[0106] In some embodiments, the second logical operation may be the same as the first logical operation described above. For example, the second logical operation may be an XOR operation, but the scope of the present disclosure is not limited thereto, and the second logical operation may be one of various logical operations.

[0107] Figure 6A 、 Figure 6B and Figure 6C It is an explanation Figure 4 For ease of description and simplification of the drawings, components of the first and second hosts 201_1 and 201_2 and the CXL memory 210 are conceptually illustrated, and some unnecessary components are omitted.

[0108] exist Figure 6A 、 Figure 6B and Figure 6C , it is assumed that the first host 201_1 stores data w4, the second host 201_2 stores data w3, and the CXL memory 210 stores a plurality of data w1 to wn.

[0109] refer to Figure 4 、 Figure 5 and Figure 6A , the first host 201_1 can send a first data request REQ_d1 to the CXL memory 210 via the CXL switch SW_CXL, and the second host 201_2 can send a second data request REQ_d2 to the CXL memory 210 via the CXL switch SW_CXL. The first data request REQ_d1 and the second data request REQ_d2 can be requests for data w3 and data w4. In other words, the first data request REQ_d1 and the second data request REQ_d2 can both be related to data w3 and data w4.

[0110] refer to Figure 4 、 Figure 5 、 Figure 6A and Figure 6B , after receiving the first data request REQ_d1 and the second data request REQ_d2 from the CXL switch SW_CXL, the CXL memory 210 may obtain directory information about data stored in the first host 201_1 and the second host 201_2 .

[0111] For example, the CXL memory 210 may send a first directory information request REQ_dr1 to the first host 201_1 via the CXL switch SW_CXL to obtain first directory information associated with data w4 stored in the first host 201_1. In response to the first directory information request REQ_dr1 received from the CXL switch SW_CXL, the first host 201_1 may send a first directory information response REP_dr1 to the CXL memory 210 via the CXL switch SW_CXL. The first directory information response REP_dr1 may include the first directory information.

[0112] For example, the CXL memory 210 may send a second directory information request REQ_dr2 to the second host 201_2 via the CXL switch SW_CXL to obtain second directory information associated with the data w3 stored in the second host 201_2. In response to the second directory information request REQ_dr2 received from the CXL switch SW_CXL, the second host 201_2 may send a second directory information response REP_dr2 to the CXL memory 210 via the CXL switch SW_CXL. The second directory information response REP_dr2 may include the second directory information.

[0113] refer to Figure 4 、 Figure 5 、 Figure 6A 、 Figure 6B and Figure 6C , the CXL memory 210 may generate encoded data based on the first directory information and the second directory information, and transmit the generated encoded data to each of the first host 201_1 and the second host 201_2 .

[0114] For example, the CXL memory 210 may identify, based on the first directory information, first data w3 from the plurality of data w3 and w4 associated with the first data request REQ_d1 that is not stored in the first host 201_1. Furthermore, based on the second directory information, the CXL memory 210 may identify, based on the second directory information, second data w4 from the plurality of data w3 and w4 associated with the second data request REQ_d2 that is not stored in the second host 201_2. The CXL memory 210 may generate encoded data by encoding the identified first data w3 and second data w4 from the plurality of data w1 to wn stored in the buffer memory BFM using an XOR operation. In this case, the encoded data may be an XOR message having a message format such as [ ]. In response to the first data request REQ_d1 and the second data request REQ_d2, the CXL memory 210 may transmit the encoded data to each of the first host 201_1 and the second host 201_2 via the CXL switch SW_CXL.

[0115] The first host 201_1 may perform an XOR operation on the received encoded data and the data w4 stored in the first host 201_1 to decode the encoded data. As a result of the decoding, the first host 201_1 may obtain data w3.

[0116] The second host 201_2 may perform an XOR operation on the received coded data and the data w3 stored in the second host 201_2 to decode the coded data. As a result of the decoding, the second host 201_2 may obtain data w4.

[0117] exist Figure 6A 、 Figure 6B and Figure 6C , although the first data request REQ_d1 and the second data request REQ_d2 are illustrated as requests for the same data, the scope of the present disclosure is not limited thereto, and the first data request REQ_d1 and the second data request REQ_d2 may be requests for data different from each other.

[0118] Figure 7A 、 Figure 7B and Figure 7C Is used to show Figure 4For ease of description and simplification of the drawings, components of the first and second hosts 201_1 and 201_2 and the CXL memory 210 are conceptually illustrated, and some unnecessary components are omitted.

[0119] exist Figure 7A 、 Figure 7B and Figure 7C , a plurality of data w1 to wn are divided into first sub-data w1_1 to wn_1 and second sub-data w1_2 to wn_2, a first host 201_1 stores the first sub-data w1_1 to wn_1, a second host 201_2 stores the second sub-data w1_2 to wn_2, and it is assumed that the CXL memory 210 stores the plurality of data w1 to wn.

[0120] refer to Figure 4 、 Figure 5 and Figure 7A , the first host 201_1 may send a first data request REQ_d1 to the CXL memory 210 through the CXL switch SW_CXL, and the second host 201_2 may send a second data request REQ_d2 to the CXL memory 210 through the CXL switch SW_CXL. The first data request REQ_d1 may be a request for data w3 and w4, and the second data request REQ_d2 may be a request for data w1 and w2.

[0121] refer to Figure 4 、 Figure 5 、 Figure 7A and Figure 7B , after receiving the first data request REQ_d1 and the second data request REQ_d2 from the CXL switch SW_CXL, the CXL memory 210 may obtain directory information about data stored in the first host 201_1 and the second host 201_2 .

[0122] For example, the CXL memory 210 may send a first directory information request REQ_dr1 to the first host 201_1 via the CXL switch SW_CXL to obtain first directory information associated with the first sub-data w1_1 to wn_1 stored in the first host 201_1. In response to receiving the first directory information request REQ_dr1, the first host 201_1 may send a first directory information response REP_dr1 to the CXL memory 210 via the CXL switch SW_CXL. The first directory information response REP_dr1 may include the first directory information.

[0123] For example, the CXL memory 210 may send a second directory information request REQ_dr2 to the second host 201_2 via the CXL switch SW_CXL to obtain second directory information associated with the second sub-data w1_2 to wn_2 stored in the second host 201_2. In response to receiving the second directory information request REQ_dr2, the second host 201_2 may send a second directory information response REP_dr2 to the CXL memory 210 via the CXL switch SW_CXL. The second directory information response REP_dr2 may include the second directory information.

[0124] refer to Figure 4 、 Figure 5 、 Figure 7A 、 Figure 7B and Figure 7C , the CXL memory 210 may generate encoded data based on the first directory information and the second directory information, and may output the generated encoded data to each of the first host 201_1 and the second host 201_2 .

[0125] For example, the CXL memory 210 may identify data w3_2 and w4_2 that are not stored in the first host 201_1 from among the plurality of data w3 and w4 associated with the first data request REQ_d1 based on the first directory information. Furthermore, the CXL memory 210 may identify data w1_1 and w2_1 that are not stored in the second host 201_2 from among the plurality of data w1 and w2 associated with the second data request REQ_d2 based on the second directory information. The CXL memory 210 may generate encoded data by performing an XOR-based encoding on the identified data w1_1, w2_1, w3_2, and w4_2 from among the plurality of data w1 to wn. In this case, the encoded data may have a message form, such as In response to the first data request REQ_d1 and the second data request REQ_d2 , the CXL memory 210 may transmit the encoded data to each of the first host 201_1 and the second host 201_2 through the CXL switch SW_CXL.

[0126] The first host 201_1 may perform decoding on the coded data by performing an XOR operation on the received coded data and the first sub-data w1_1 to wn_1 stored in the first host 201_1. As a result of performing the decoding, the first host 201_1 may obtain data w3_2 and w4_2.

[0127] The second host 201_2 may perform decoding on the coded data by performing an XOR operation on the received coded data and the second sub-data w1_2 to wn_2 stored in the second host 201_2. As a result of performing the decoding, the second host 201_2 may obtain data w1_1 and w2_1.

[0128] In some embodiments, Figure 7B and Figure 7C Unlike the CXL memory 210, which can generate encoded data based on the first data request REQ_d1 and the second data request REQ_d2 without obtaining the first and second directory information. For example, according to a predetermined rule, the first host 201_1 can be configured to store the first sub-data w1_1 to wn_1, and the second host 201_2 can be configured to store the second sub-data w1_2 to wn_2. In this case, the CXL memory 210 can identify the data w3_2 and w4_2 required by the first host 201_1 based on the first data request REQ_d1, and identify the data w1_1 and w2_1 required by the second host 201_2 based on the second data request REQ_d2. The CXL memory 210 can generate the encoded data by performing an XOR-based encoding on the identified data w1_1, w2_1, w3_2, and w4_2 from the plurality of data w1 to wn.

[0129] Figure 8 This is achieved by using the memory module 300. Figure 4 A block diagram of the CXL memory 210 is shown. Figure 4 and Figure 8 , the memory module 300 may include a plurality of memory devices 310_1 to 310_16 , a power management integrated circuit (PMIC) 320 , and a register clock driver (RCD) 330 .

[0130] Each of the plurality of memory devices 310_1 to 310_16 may include a memory cell array MCA and an internal processor iP. That is, each of the plurality of memory devices 310_1 to 310_16 may be a processor-in-memory (PIM) type memory device.

[0131] The memory cell array MCA can store a plurality of data. The internal processor iP can perform an internal processing operation. For example, the internal processing operation may refer to a processing operation on the plurality of data stored in the memory cell array MCA, such as data search, data addition, data movement, data comparison, data exchange, and / or data processing / calculation.

[0132] The internal processor iP may generate coded data from at least some of the plurality of data stored in the memory cell array MCA. For example, the internal processor iP may generate coded data by performing coding on at least some of the plurality of data stored in the memory cell array MCA, and the coding may be based on a logical operation. That is, each of the plurality of memory devices 310_1 to 310_16 may perform coding based on a logical operation on some of the plurality of data stored therein.

[0133] Each of the plurality of memory devices 310_1 to 310_16 may output encoded data to the outside of the memory module 300 through a data line in response to a signal provided from the register clock driver 330 .

[0134] Figure 9 It shows that the memory module is used to implement Figure 4 Hereinafter, for the convenience of description, detailed description of overlapping components will be omitted.

[0135] refer to Figure 4 、 Figure 8 and Figure 9 , the memory module 400 may include a plurality of memory devices 410_1 to 410_16 , a PMIC 420 , a register clock driver RCD 430 , and an accelerator 440 .

[0136] Each of the plurality of memory devices 410_1 to 410_16 may store a plurality of data.

[0137] The accelerator 440 can be configured to handle a specific type of processing. The accelerator 440 can include at least one of various auxiliary processors, such as a graphics processing unit (GPU), a digital signal processor (DSP), an image signal processor (ISP), a neural processor, or a neuromorphic processor. In some embodiments, the accelerator 440 can perform high-speed data operations, such as artificial intelligence (AI) data operations.

[0138] The accelerator 440 may generate coded data by performing coding on at least some of the plurality of data stored in the plurality of memory devices 410_1 to 410_16, and the coding is based on a logical operation. In other words, Figure 8 In , each internal processor iP can perform encoding based on logical operations. Figure 9 In the embodiment of the present invention, the accelerator 440 may perform encoding based on the logical operation. The accelerator 440 may output the generated encoded data to the outside of the memory module 400.

[0139] Figure 105 is a block diagram of a computing system 500 according to some embodiments of the present disclosure. Detailed descriptions of overlapping components will be omitted hereinafter for ease of description.

[0140] refer to Figure 4 and Figure 10 , the computing system 500 may include first to third hosts 501_1 to 501_3 , a plurality of memory devices 502_1 to 502_3 , a CXL switch SW_CXL, a first CXL memory 510_1 , and a second CXL memory 510_2 .

[0141] The first CXL memory 510_1 and the second CXL memory 510_2 may respectively store a plurality of data. For example, the first CXL memory 510_1 may store a plurality of data w1 to wn, and the second CXL memory 510_2 may store a plurality of data y1 to yn.

[0142] The first CXL memory 510_1 and the second CXL memory 510_2 may operate independently.

[0143] For example, the first CXL memory 510_1 may receive first to third data requests from the first to third hosts 501_1 to 501_3 respectively through the CXL switch SW_CXL.

[0144] After receiving a first data request, the first CXL memory 510_1 may obtain, via the CXL switch SW_CXL, first directory information associated with at least one data stored in the cache memory 511_1 or the memory device 502_1. After receiving a second data request, the first CXL memory 510_1 may obtain, via the CXL switch SW_CXL, second directory information associated with at least one data stored in the cache memory 511_2 or the memory device 502_2. After receiving a third data request, the first CXL memory 510_1 may obtain, via the CXL switch SW_CXL, third directory information associated with at least one data stored in the cache memory 511_3 or the memory device 502_3.

[0145] The first CXL memory 510_1 may generate first coded data from at least some of the plurality of data w1 to wn stored in the buffer memory BFM based on the first to third directory information and may transmit the first coded data to each of the first to third hosts 501_1 to 501_3 in response to the first to third data requests.

[0146] For example, the second CXL memory 510_2 may receive the fourth to sixth data requests from the first to third hosts 501_1 , 501_3 , respectively, through the CXL switch SW_CXL.

[0147] After receiving the fourth data request, the first CXL memory 510_1 may obtain, via the CXL switch SW_CXL, fourth directory information associated with at least one data stored in the cache memory 511_1 or the memory device 502_1. After receiving the fifth data request, the second CXL memory 510_2 may obtain, via the CXL switch SW_CXL, fifth directory information associated with at least one data stored in the cache memory 511_2 or the memory device 502_2. After receiving the sixth data request, the second CXL memory 510_2 may obtain, via the CXL switch SW_CXL, sixth directory information associated with at least one data stored in the cache memory 511_3 or the memory device 502_3.

[0148] The second CXL memory 510_2 may generate second encoded data from at least some of the plurality of data y1 to yn stored in the buffer memory BFM based on the fourth to sixth directory information. In response to the fourth to sixth data requests, the second CXL memory 510_2 may transmit the second encoded data to each of the first to third hosts 501_1 to 501_3.

[0149] exist Figure 10 In the embodiment, although the computing system 500 includes first to third hosts 501_1 to 501_3 and first and second CXL memories 510_1 and 510_2 , the scope of the present disclosure is not limited thereto and may include a plurality of hosts and a plurality of CXL memories.

[0150] Figure 11 6 is a block diagram of a computing system 600 according to some embodiments of the present disclosure. Hereinafter, for ease of description, detailed descriptions of overlapping components will be omitted.

[0151] refer to Figure 11 , a computing system 600 may include a first host 601_1 and a second host 601_2 , a plurality of memory devices 602_1 and 602_2 , a CXL memory 610 , and a fabric manager 620 .

[0152] The fabric manager 620 may be configured to arbitrate communications between the first host 601_1 and the second host 601_2 and the CXL memory 610. In some embodiments, the fabric manager 620 may be a component included in the CXL switch SW_CXL.

[0153] The fabric manager 620 may receive a first data request and a second data request from a first host 601_1 and a second host 601_2, respectively. After receiving the first data request, the fabric manager 620 may obtain, from the first host 601_1, first directory information associated with at least one data stored in the cache memory 611_1 or the memory device 602_1. After receiving the second data request, the fabric manager 620 may obtain, from the second host 601_2, second directory information associated with at least one data stored in the cache memory 611_2 or the memory device 602_2.

[0154] Fabric manager 620 may generate a third data request based on the first directory information and the second directory information. For example, fabric manager 620 may identify, based on the first directory information, first data from the plurality of data associated with the first data request that is not stored in cache memory 611_1 or memory device 602_1. Fabric manager 620 may identify, based on the second directory information, second data from the plurality of data associated with the second data request that is not stored in cache memory 611_2 or memory device 602_2. Fabric manager 620 may modify the first and second data requests to generate a third data request for the first and second data. Fabric manager 620 may send the third data request to CXL memory 610.

[0155] In response to a third data request received from the fabric manager 620, the CXL memory controller 611 may generate encoded data by encoding first data and second data among the plurality of data, wherein the encoding is based on a logical operation. The CXL memory controller 611 may transmit the encoded data to the fabric manager 620 in response to the third data request. The fabric manager 620 may transmit the encoded data to each of the first host 601_1 and the second host 601_2 in response to the first data request and the second data request.

[0156] Figure 12 It shows Figure 11 Flowchart of data transmission operation of a computing system. Figure 11 and Figure 12 In operation S211 , the first host 601_1 may issue a first data request REQ_d1 . The first data request REQ_d1 may be transmitted to the fabric manager 620 .

[0157] In operation S212 , the second host 601_2 may issue a second data request REQ_d2 , which may be transmitted to the fabric manager 620 .

[0158] In some embodiments, the operations of operation S211 and operation S212 may be performed simultaneously.

[0159] The fabric manager 620 may obtain directory information associated with data stored in the cache memories 611_1 and 611_2 or the memory devices 602_1 and 602_2 from the first host 601_1 and the second host 601_2 through operations S221 to S224. For example, in operation S221, the fabric manager 620 may send a first directory information request REQ_dr1 to the first host 601_1 to obtain first directory information associated with at least one data stored in the cache memory 611_1 or the memory device 602_1.

[0160] In operation S222, the first host 601_1 may transmit a first directory information response REP_dr1 to the fabric manager 620 in response to the first directory information request REQ_dr1 received from the fabric manager 620. The first directory information response REP_dr1 may include first directory information.

[0161] In operation S223 , the fabric manager 620 may send a second directory information request REQ_dr2 to the second host 601_2 to acquire second directory information about at least one data stored in the cache memory 611_2 or the memory device 602_2 .

[0162] In operation S224, the second host 601_2 may transmit a second directory information response REP_dr2 to the fabric manager 620 in response to the second directory information request REQ_dr2 received from the fabric manager 620. The second directory information response REP_dr2 may include second directory information.

[0163] In some embodiments, the operations of operation S221 and operation S223 may be performed simultaneously.

[0164] In operation S231, the fabric manager 620 may generate a third data request REQ_d3 based on the first directory information and the second directory information. For example, the fabric manager 620 may identify, based on the first directory information, first data from the plurality of data associated with the first data request REQ_d1 that is not stored in the cache memory 611_1 or the memory device 602_1. The fabric manager 620 may identify, based on the second directory information, second data from the plurality of data associated with the second data request REQ_d2 that is not stored in the cache memory 611_2 or the memory device 602_2. The fabric manager 620 may modify the first and second data requests to generate the third data request REQ_d3 for the first and second data.

[0165] In operation S232 , the fabric manager 620 may send a third data request REQ_d3 to the CXL memory 610 .

[0166] In operation S241 , the CXL memory 610 may generate encoded data by performing encoding on first data and second data among a plurality of data stored in the buffer memory BFM based on a first logical operation in response to a third data request REQ_d3 .

[0167] In some embodiments, the first logical operation may be an XOR operation, but the scope of the present disclosure is not limited thereto, and the first logical operation may be one of various logical operations.

[0168] In operation S251, the CXL memory 610 may transmit a third data response REP_d3 to the fabric manager 620 in response to a third data request REQ_d3 received from the fabric manager 620. The third data response REP_d3 may include encoded data.

[0169] The fabric manager 620 may transmit the encoded data received from the CXL memory 610 to each of the first host 601_1 and the second host 601_2 through operations S261 and S262. For example, in operation S261, the fabric manager 620 may transmit the encoded data received from the CXL memory 610 to the first host 601_1 in response to a first data request REQ_d1. In operation S262, the fabric manager 620 may transmit the encoded data received from the CXL memory 610 to the second host 601_2 in response to a second data request REQ_d2.

[0170] In operation S271, the first host 601_1 and the second host 601_2 may perform decoding on the encoded data received from the fabric manager 620. As a result of performing the decoding, the first host 601_1 and the second host 601_2 may acquire necessary data.

[0171] For example, the first host 601_1 may perform decoding based on the second logical operation on the encoded data received from the fabric manager 620. As a result of the decoding, the first host 601_1 may obtain first data that is not stored in the first host 601_1 (e.g., cache memory 611_1 or memory device 602_1) from among the data associated with the first data request. For example, the second host 601_2 may perform decoding based on the second logical operation on the encoded data received from the fabric manager 620. As a result of the decoding, the second host 601_2 may obtain second data that is not stored in the second host 601_2 (e.g., cache memory 611_2 or memory device 602_2) from among the data associated with the second data request.

[0172] In some embodiments, the second logical operation may be the same as the first logical operation described above. For example, the second logical operation may be an XOR operation, but the scope of the present disclosure is not limited thereto, and the second logical operation may be one of various logical operations.

[0173] Figure 13A 、 Figure 13B and Figure 13C Is used to show Figure 11 For ease of description and simplification of the drawings, components of a first host 601_1 and a second host 601_2 and a CXL memory 610 are conceptually illustrated, and some unnecessary components are omitted.

[0174] exist Figure 13A 、 Figure 13B and Figure 13C , it is assumed that the first host 601_1 stores data w4, the second host 601_2 stores data w3, and the CXL memory 610 stores a plurality of data w1 to wn.

[0175] refer to Figure 11 、 Figure 12 and Figure 13A , the first host 601_1 and the second host 601_2 may respectively send a first data request REQ_d1 and a second data request REQ_d2 to the fabric manager 620. The first data request REQ_d1 and the second data request REQ_d2 may be requests for data w3 and w4. In other words, the first data request REQ_d1 and the second data request REQ_d2 may both be related to data w3 and w4.

[0176] refer to Figure 11 、 Figure 12 、 Figure 13A and Figure 13B , after receiving the first data request REQ_d1 and the second data request REQ_d2 from the first host 601_1 and the second host 601_2 , respectively, the fabric manager 620 may obtain directory information about data stored in the first host 201_1 and the second host 201_2 .

[0177] For example, the fabric manager 620 may send a first directory information request REQ_dr1 to the first host 601_1 to obtain first directory information about data w4 stored in the first host 601_1. The first host 601_1 may send a first directory information response REP_dr1 to the fabric manager 620 in response to the received first directory information request REQ_dr1. The first directory information response REP_dr1 may include the first directory information.

[0178] For example, the fabric manager 620 may send a second directory information request REQ_dr2 to the second host 601_2 to obtain second directory information associated with data w3 stored in the second host 601_2. The second host 601_2 may send a second directory information response REP_dr2 to the fabric manager 620 in response to the received second directory information request REQ_dr2. The second directory information response REP_dr2 may include the second directory information.

[0179] refer to Figure 11 、 Figure 12 、 Figure 13A 、 Figure 13B and Figure 13C Fabric manager 620 may generate a third data request REQ_d3 based on the first directory information and the second directory information. For example, fabric manager 620 may identify, based on the first directory information, first data w3 from among the plurality of data w3 and w4 associated with first data request REQ_d1 that is not stored in cache memory 611_1 or memory device 602_1. Fabric manager 620 may identify, based on the second directory information, second data w4 from among the plurality of data w3 and w4 associated with second data request REQ_d2 that is not stored in cache memory 611_2 or memory device 602_2. Fabric manager 620 may modify the first and second data requests to generate a third data request REQ_d3 for first data w3 and second data w4. Fabric manager 620 may send third data request REQ_d3 to CXL memory 610.

[0180] In response to the third data request REQ_d3, the CXL memory 610 may generate coded data by performing XOR-based coding on the first data w3 and the second data w4 among the plurality of data w1 to wn stored in the buffer memory BFM. In this case, the coded data may be an XOR message having a value such as CXL memory 610 may send a third data response REP_d3 to fabric manager 620 in response to a third data request REQ_d3 received from fabric manager 620. The third data response REP_d3 may include encoded data.

[0181] The fabric manager 620 may transmit the encoded data received from the CXL memory 610 to each of the first host 601_1 and the second host 601_2 in response to the first data request REQ_d1 and the second data request REQ_d2 .

[0182] The first host 601_1 may perform an XOR operation on the encoded data received from the fabric manager 620 and the data w4 stored in the first host 601_1 to perform decoding on the encoded data. As a result of performing the decoding, the first host 601_1 may obtain data w3.

[0183] The second host 601_2 may perform an XOR operation on the encoded data received from the fabric manager 620 and the data w3 stored in the second host 601_2 to decode the encoded data. As a result of the decoding, the second host 601_2 may obtain data w4.

[0184] In the above embodiments, the components according to the technical concept of the present disclosure are described using terms such as first, second, and third. However, terms such as first, second, third, etc. are used to distinguish components from each other and do not limit the present disclosure. For example, terms such as first, second, third, etc. do not imply a sequential order or any form of numerical meaning.

[0185] According to the present disclosure, in a system where multiple host devices share a memory device, the efficiency of data transmission between the multiple host devices and the memory device can be improved.

[0186] The above description is a specific example for implementing the present disclosure. The present disclosure will include not only the above-mentioned embodiments, but also embodiments that can be simply changed or easily changed. In addition, the present disclosure will also include technologies that can be easily modified and implemented in the future by using the above-mentioned embodiments.

Claims

1. A system comprising: a first memory device configured to store a first data set; as well as a Compute Express Link (CXL) switch configured to arbitrate communications between a first host device and a second host device and the first memory device based on a CXL interface; The first memory device is configured to perform an operation, the operation comprising: receiving a first data request from the first host device via the CXL switch; receiving a second data request from the second host device via the CXL switch; obtaining, from the first host device, through the CXL switch, first directory information associated with at least one data stored in the first host device; obtaining, from the second host device, through the CXL switch, second directory information associated with at least one data stored in the second host device; generating first encoded data based on the first directory information and the second directory information; and In response to the first data request and the second data request, the first encoded data is output to each of the first host device and the second host device through the CXL switch.

2. The system according to claim 1, wherein: The first memory device is configured to generate the first encoded data by performing encoding on at least some of the data associated with the first data request and the second data request among a plurality of data included in the first data set, and Wherein, the encoding is based on logical operations.

3. The system according to claim 2, wherein: The first memory device is configured to perform operations comprising: identifying, based on the first directory information, first data among a plurality of data associated with the first data request that is not stored in the first host device; identifying, based on the second directory information, second data from a plurality of data associated with the second data request that is not stored in the second host device; and The logical operation is performed based on the first data and the second data.

4. The system according to claim 3, wherein: The at least some of the plurality of data include the first data and the second data, wherein the logical operation is performed on the at least some of the data.

5. The system according to claim 2, wherein: The logical operation is an XOR operation.

6. The system according to claim 2, wherein: The first memory device comprises a memory module comprising a plurality of memory devices, and The memory module includes an accelerator configured to perform the logical operation on at least some of the plurality of data stored in the plurality of memory devices.

7. The system according to claim 2, wherein: The first memory device comprises a memory module comprising a plurality of memory devices, and Each of the plurality of memory devices includes an internal processor configured to perform the logical operation on at least some of the plurality of data stored in each of the plurality of memory devices.

8. The system according to claim 1, wherein: When receiving a data interruption request to stop outputting the first encoded data from the first host device, the first memory device suspends outputting the first encoded data to the first host device.

9. The system of claim 1 , further comprising: a second memory device configured to store a second data set, The second memory device operates independently of the first memory device.

10. The system according to claim 9, wherein: The second memory device is configured to perform operations comprising: receiving a third data request from the first host device via the CXL switch; receiving a fourth data request from the second host device via the CXL switch; obtaining, through the CXL switch, the first directory information and the second directory information; generating second encoded data based on the first directory information and the second directory information; and In response to the third data request and the fourth data request, the second encoded data is output to each of the first host device and the second host device through the CXL switch.

11. The system according to claim 1, wherein: The first memory device is configured to perform operations comprising: receiving the first data request, and outputting a first directory information request associated with the first directory information to the first host device through the CXL switch; and The second data request is received, and a second directory information request associated with the second directory information is output to the second host device through the CXL switch.

12. A system comprising: A first memory device configured to store a plurality of data; as well as a fabric manager configured to arbitrate communications between a first host device and a second host device and the first memory device based on a compute express link (CXL) interface; The structure manager is configured to perform operations, including: receiving a first data request from the first host device; receiving a second data request from the second host device; obtaining, from the first host device, first directory information associated with at least one data stored in the first host device; obtaining, from the second host device, second directory information associated with at least one data stored in the second host device; and generating a third data request based on the first directory information and the second directory information, and sending the third data request to the first memory device, wherein the first memory device is configured to generate first encoded data in response to the third data request and send the first encoded data to the fabric manager, and The fabric manager is further configured to output the first encoded data received from the first memory device to each of the first host device and the second host device in response to the first data request and the second data request.

13. The system according to claim 12, wherein: The first memory device generates the first encoded data by performing a logical operation on at least some of the plurality of data associated with the third data request.

14. The system according to claim 13, wherein: The fabric manager is further configured to perform operations including: identifying, based on the first directory information, first data among a plurality of data associated with the first data request that is not stored in the first host device; and identifying, based on the second directory information, second data from a plurality of data associated with the second data request that is not stored in the second host device, The third data request is associated with the first data and the second data.

15. The system according to claim 13, wherein: The logical operation is an XOR operation.

16. A system comprising: a first host device and a second host device; A first memory device configured to store a plurality of data; as well as a Compute Express Link (CXL) switch configured to arbitrate communications between the first host device and the second host device and the first memory device based on a CXL interface; wherein the first host device sends a first data request to the first memory device via the CXL switch, and the second host device sends a second data request to the first memory device via the CXL switch, and After receiving the first data request and the second data request, the first memory device is configured to perform an operation, the operation comprising: obtaining, from the first host device, through the CXL switch, first directory information associated with at least one data stored in the first host device; obtaining, from the second host device, through the CXL switch, second directory information associated with at least one data stored in the second host device; generating first encoded data based on the first directory information and the second directory information; and In response to the first data request and the second data request, the first encoded data is output to each of the first host device and the second host device through the CXL switch.

17. The system according to claim 16, wherein: The first memory device is configured to generate the first encoded data by performing a logical operation on at least some of the plurality of data associated with the first data request and the second data request.

18. The system according to claim 17, wherein: The first memory device is configured to perform operations comprising: identifying, based on the first directory information, first data among a plurality of data associated with the first data request that is not stored in the first host device; identifying, based on the second directory information, second data from a plurality of data associated with the second data request that is not stored in the second host device; and The logical operation is performed based on the first data and the second data.

19. The system according to claim 17, wherein: Each of the first host device and the second host device performs decoding based on the logical operation on the first encoded data.

20. The system of claim 16, wherein: Each of the plurality of data is divided into first sub-data and second sub-data, wherein the first host device is configured to store the first sub-data of each of the plurality of data, and The second host device is configured to store the second sub-data of each of the plurality of data.

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