Solid state disk rapid hard destruction method, device and system and storage medium

Abstract

The invention provides a solid state disk rapid hard destruction method, device and system and a storage medium, and belongs to the technical field of data processing. The fast hard destruction method for the solid state disk specifically comprises the following steps that a destruction voltage signal input from the outside is received, a periodic square wave control signal is generated through a single chip microcomputer, and the high-low level duty ratio of the square wave signal is determined by the charging and discharging time of a capacitor charging and discharging circuit; the MOS tube switching circuit is controlled to switch on and off of the normal power supply circuit and the destruction circuit; a pulse voltage is generated through a capacitor charging and discharging circuit, the pulse voltage is applied to a Flash chip power supply pin of the solid state disk so as to burn a storage chip, and the purpose of destroying data is achieved. According to the method, destruction is carried out in the mode that pulse voltage is formed through capacitor charging and discharging, the pressure of a power supply circuit is reduced, it is guaranteed that each Flash chip is fully burnt out, and the risk of data recovery does not exist.

Description

Technical Field

[0001] The present invention relates to the technical field of solid-state hard disk data processing, and in particular to a method, device, system and computer-readable storage medium for rapid hard destruction of a solid-state hard disk. Background Art

[0002] With the advancement of computer technology, higher requirements have been placed on the security and confidentiality of data stored on solid-state drives (SSDs). SSD hard destruction technology enables rapid data destruction, burning the Flash chip to permanently destroy the data. Currently, SSDs are widely used in both military and civilian applications. Large amounts of confidential data, such as electronic maps and guidance video information, must be destroyed under specific conditions to prevent information leakage. Therefore, SSDs with hard destruction technology have a wider range of applications.

[0003] Utility model patent No. CN204719761U (hereinafter referred to as "Prior Art 1") discloses a smart destruction solid-state hard drive, comprising a single-chip microcomputer and a Flash chip. The single-chip microcomputer is respectively connected to a key security device, a sensor, a power conversion chip, a password cracking detector, a signal transceiver, and a destruction circuit. The key security device is connected to the password cracking detector, the Flash chip is respectively connected to the key security device and the destruction circuit, the password cracking detector is connected to a data interface, and the power conversion chip is connected to a backup power supply. The beneficial effects of this utility model are: through the functions of the destruction circuit, the password cracking detector, and the sensor, the destruction speed of the solid-state hard drive is effectively improved, and the operation is convenient and intelligent, thereby giving this smart destruction solid-state hard drive a broader development space.

[0004] Patent publication number CN117037880A (hereinafter referred to as "Prior Art 2") discloses an optimized design for a hardware destruction circuit in a solid-state drive (SSD). The circuit includes a power selection circuit and an energy storage capacitor. The power selection circuit receives an external hardware destruction command and, in response to the command, switches the power supply from the Flash chip to the energy storage capacitor. The high voltage of the energy storage capacitor destroys the internal data in the Flash chip, thereby destroying the data. This solution utilizes the SSD's existing energy storage capacitor (high voltage) as the surge voltage for destroying the Flash chip, requiring only simple control and conversion circuitry. This simplifies the existing destruction power boost circuit and eliminates the high-voltage boost circuit, saving hardware costs and simplifying circuit board layout space.

[0005] Existing technology 1 relies on password cracking detectors and sensors to trigger destruction, which has the risk of false triggering and the destruction voltage cannot be adjusted, resulting in insufficient adaptability; Existing technology 2 mainly releases high voltage directly through a fixed 35V energy storage capacitor, which cannot adapt to different power supply environments, resulting in complex design; Existing technology 1 uses continuous high-voltage burning, which requires high-power front-end power supply, and is prone to incomplete destruction due to insufficient power supply.

[0006] In actual use, there are still the following deficiencies: First, the destruction voltage amplitude cannot be adjusted: the destruction voltage of the existing hard destruction technology is obtained by converting 3.3V to 8V, and the normal power supply circuit of Flash is used to output it to the Flash chip, and the destruction voltage cannot be adjusted.

[0007] Second, the requirements for the power supply circuit are too high: the original hard destruction technology is to burn the Flash chip by converting the voltage from 3.3V to 8V for a period of time, and all Flash chips are burned at the same time. The front end must have sufficient power supply capacity, otherwise it will lead to insufficient power supply during the destruction process and incomplete destruction.

[0008] Third, the secondary usability is poor: using the original normal power supply circuit to input the destruction voltage will burn other original devices and circuits, and even cause the entire solid-state drive and other equipment to burn, which poses a great safety risk. There is no special destruction of the Flash chip that stores data, making the hard-destroyed solid-state drive unable to be used again, and the cost is high. Summary of the Invention

[0009] The purpose of the present invention is to provide a method, device, system and storage medium for rapid hard destruction of solid-state hard drives, which uses capacitor charging and discharging to form a pulse voltage for destruction, reducing the pressure on the power supply circuit, ensuring that each Flash chip is fully burned, and there is no risk of data recovery.

[0010] In order to solve the above technical problems, the technical solution adopted by the present invention is: In a first aspect, the present invention provides a method for rapidly destroying a solid-state hard drive, comprising the following steps: Receive an external destruction voltage signal, where the amplitude range of the destruction voltage signal is 16V-32V; Generate a periodic square wave control signal through the single-chip microcomputer. The high and low level duty ratios of the square wave control signal are determined by the charge and discharge time of the capacitor charge and discharge circuit. The recommended low level duration is 0.8-1.5ms and the high level duration is 9-20ms. Based on the square wave control signal, the MOS tube switch circuit is controlled to switch the normal power supply circuit and the destruction circuit on and off; A pulse voltage is generated by a capacitor charge and discharge circuit, and the pulse voltage is applied to the power pin of the Flash chip of the solid-state drive to burn the storage chip and achieve the purpose of destroying data.

[0011] Furthermore, the amplitude of the destruction voltage signal is input externally, the input voltage range is 16V-32V, and the input is continuous for more than 1 second.

[0012] Furthermore, the duration of the pulse voltage does not exceed 0.8-1.5 ms, and the pulse interval is 10-30 ms, and the specific time is adjusted by the capacitor charging and discharging circuit.

[0013] Furthermore, after the destruction is completed, the following steps are also included: Detect the burn status of the Flash chip. If it is not completely burned, the re-destruction process will be automatically triggered.

[0014] In a second aspect, the present invention provides a solid state hard drive rapid hard destruction device, comprising: A signal receiving module, used for receiving an externally input destruction voltage signal; A single chip microcomputer control module, connected to the signal receiving module, for generating a periodic square wave control signal; A MOS tube switch module, connected to the single-chip microcomputer control module, for switching between a normal power supply circuit and a destruction circuit according to the square wave control signal; The capacitor charging and discharging module is connected to the MOS tube switch module and is used to generate a pulse voltage and output it to the Flash chip.

[0015] Furthermore, the capacitor charge and discharge module includes multiple energy storage capacitors connected in parallel, the capacity of a single capacitor is 0.1-10μF, the rated voltage is 63-100V, it is designed with a 50% derating, and the total capacitance is not less than 100μF.

[0016] Furthermore, the MOS transistor switch module includes a combination circuit composed of an NMOS transistor and a PMOS transistor, which is used to completely isolate the connection between the normal power supply circuit and the Flash chip in the destroyed state.

[0017] In a third aspect, the present invention provides a solid state hard drive rapid hard destruction system, comprising the solid state hard drive rapid hard destruction device described above; A power management unit, configured to provide an adjustable voltage input to the destruction device, wherein the voltage range is 16V to 32V; A monitoring module, used to detect voltage fluctuations and Flash chip status during the destruction process in real time, and to feed back abnormal signals to the single-chip control module; Communication interface, supports remote triggering of destruction instructions or receiving destruction status information.

[0018] Among them, the communication interface supports wireless communication protocols, including Wi-Fi, Bluetooth or 5G, for data interaction with cloud servers or mobile terminals.

[0019] In a fourth aspect, the present invention provides a computer-readable storage medium, wherein the computer program instructions are stored in the computer-readable storage medium, and when the program is executed by a processor, the method for rapid hard destruction of a solid-state hard drive described above is implemented.

[0020] Compared with the prior art, the present invention has the following beneficial effects: The present invention uses a single-chip microcomputer control circuit, a MOS transistor switching circuit, and a capacitor charging and discharging circuit to burn Flash chips. This method uses capacitor charging and discharging to generate a pulse voltage for destruction, reducing pressure on the power supply circuit and ensuring that each Flash chip is fully burned, eliminating the risk of data recovery. The voltage is adjustable to accommodate different power supply capacities, reducing design complexity. The pulsed destruction method reduces front-end power supply pressure and ensures thorough destruction. More importantly, the independent circuit design targets only the Flash chip, allowing for secondary use after replacement, reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is a block diagram of the logic composition of hard destruction technology.

[0023] Figure 2 This is the circuit schematic diagram of the microcontroller control circuit.

[0024] Figure 3 This is the schematic diagram of the MOS tube switch circuit.

[0025] Figure 4 This is the circuit schematic diagram of the capacitor charging and discharging circuit.

[0026] Figure 5 This is the effect diagram of the present invention inputting 20V destruction voltage.

[0027] Figure 6 This is the effect diagram of the present invention inputting 25V destruction voltage.

[0028] Figure 7 This is the effect diagram of the present invention inputting 28V destruction voltage. DETAILED DESCRIPTION

[0029] The following is a combination of the appended examples of the present application Figure 1 -Attached Figure 7 , describes the technical solutions in the embodiments of this application. Example

[0030] This embodiment provides a method for quickly destroying a solid-state hard drive, which specifically includes the following steps: Receive an external destruction voltage signal, the amplitude range of which is 16V-32V; in this embodiment, the voltage is 28V; The receiving of the externally input destruction voltage signal specifically comprises generating the destruction voltage signal after receiving an external trigger instruction; A periodic square wave control signal is generated by a single chip microcomputer. The high and low level duty ratios of the square wave control signal are determined by the charge and discharge time of the capacitor charge and discharge circuit. The low level duration is 0.8-1.5ms, and the high level duration is 9-20ms.

[0031] In this embodiment, the high and low level duty ratios of the square wave control signal are determined by the charge and discharge time of the capacitor charge and discharge circuit, wherein the low level duration is 1 ms and the high level duration is 15 ms.

[0032] Based on the square wave control signal, the MOS tube switch circuit is controlled to switch the normal power supply circuit and the destruction circuit on and off; A pulse voltage is generated by a capacitor charge and discharge circuit, and the pulse voltage is applied to the power pin of the Flash chip of the solid-state drive to burn the storage chip and achieve the purpose of destroying data.

[0033] Furthermore, the amplitude of the destruction voltage signal is inputted externally, the input voltage range is 16V-32V, and the input is continuously inputted for more than 1 second. In this embodiment, the input voltage is 28V and the input is continuously inputted for 1 second.

[0034] Furthermore, experimental verification shows that when the pulse voltage peak is set to 28V, the single pulse duration does not exceed 10ms, and the pulse interval is 100ms, the Flash chip can be effectively burned and circuit overload can be avoided.

[0035] Furthermore, after the destruction is completed, the following steps are also included: Detect the burn status of the Flash chip. If it is not completely burned, the re-destruction process will be automatically triggered.

[0036] Specifically: the current value of the power pin of the Flash chip is detected by the monitoring module. If the current value is lower than the preset threshold, it is determined that the burning is complete; otherwise, the destruction process is triggered again.

[0037] It should be noted that the present invention periodically releases the electrical energy stored in the energy storage capacitor through the capacitor charging and discharging circuit to generate a pulse voltage, thereby avoiding the dependence of continuous high voltage on the power supply circuit. Example

[0038] This embodiment provides a device for rapidly destroying a solid-state hard drive, comprising: A signal receiving module, used for receiving an externally input destruction voltage signal; A single chip microcomputer control module, connected to the signal receiving module, for generating a periodic square wave control signal; A MOS tube switch module is connected to the single-chip microcomputer control module and is used to switch between the normal power supply circuit and the destruction circuit according to the square wave control signal; The capacitor charging and discharging module is connected to the MOS tube switch module and is used to generate a pulse voltage and output it to the Flash chip.

[0039] Furthermore, the capacitor charge and discharge module includes multiple energy storage capacitors connected in parallel, the capacity of a single capacitor is 0.1-10μF, the rated voltage is 63-100V, it is designed with a 50% derating, and the total capacitance is not less than 100μF.

[0040] In this embodiment, the capacitance of a single capacitor is 8 μF, the rated voltage is 68 V, and the total capacitance is 200 μF.

[0041] Furthermore, the MOS transistor switch module includes a combination circuit composed of an NMOS transistor and a PMOS transistor, which is used to completely isolate the connection between the normal power supply circuit and the Flash chip in the destroyed state. Example

[0042] The present invention provides a solid-state hard drive rapid hard destruction system, comprising the solid-state hard drive rapid hard destruction device described in Example 1; A power management unit, configured to provide an adjustable voltage input to the destruction device, wherein the voltage range is 16V to 32V; A monitoring module, used to detect voltage fluctuations and Flash chip status during the destruction process in real time, and to feed back abnormal signals to the single-chip control module; Communication interface, supports remote triggering of destruction instructions or receiving destruction status information.

[0043] Among them, the communication interface supports wireless communication protocols, including Wi-Fi, Bluetooth or 5G, for data interaction with cloud servers or mobile terminals.

[0044] This embodiment further discloses a computer-readable storage medium, wherein the computer program instructions are stored in the computer-readable storage medium. When the program is executed by a processor, the method for rapid hard destruction of a solid-state hard disk described in Implementation 1 is implemented. Example

[0045] This embodiment also discloses another multi-stage data destruction method based on single-chip microcomputer control, which is mainly based on the solid-state hard disk rapid destruction device described in Example 2 and specifically includes the following steps: The signal receiving module receives the destruction instruction, and the MOS tube switch module and the capacitor charging and discharging module are controlled by the single chip microcomputer; Real-time acquisition of the Flash chip surface temperature monitored by the temperature sensor and the real-time current value of the Flash power pin fed back by the current detection circuit; A multi-level state machine is embedded in the MCU firmware to dynamically adjust the destruction parameters based on the collected temperature and current values. The destruction parameters include voltage, pulse duty cycle, and stage duration. The multi-stage state machine controls the multi-stage destruction, including a preheating and pre-damage stage, a main destruction stage, an enhanced destruction stage, and a cooling and reset stage; Among them, low-voltage pulses are used in the preheating and pre-damage stages to gradually damage the internal structure of the Flash chip. The main destruction stage uses standard parameters to ensure the physical destruction of the core data area. The enhanced destruction stage is automatically triggered when the current value exceeds the threshold after the main destruction stage, and higher energy is applied to stubborn areas. The pulse output is stopped in the cooling and reset stage, and the system self-checks and generates a destruction report.

[0046] Furthermore, the dynamic adjustment of destruction parameters is specifically as follows: During the preheating and pre-damage stages, the voltage is 20V and can be dynamically adjusted in 2V steps through external input. The square wave duty cycle is 1:5, the number of pulses is 5, and the interval is 100ms. In the main destruction stage, the voltage is 28V, the square wave duty cycle is 1:10, and the pulse continues until the current detection value is lower than 10mA; In the enhanced destruction stage, the voltage is 32V, the square wave duty cycle is 1:15, the number of pulses is 3, and the interval is 50ms.

[0047] Furthermore, the multi-stage destruction method reuses the original monitoring module to realize the temperature and current data acquisition function. Based on the original mechanism of detecting the burnt state and triggering re-destruction, it is expanded to trigger the enhanced destruction stage according to the current threshold. The destruction voltage amplitude is dynamically adjusted through external input, and the duty cycle dynamic switching function is added on the basis of the original square wave generation logic.

[0048] In actual use, the multi-level destruction mechanism is based on the coordinated operation of hardware and software, and achieves complete data destruction by dynamically adjusting parameters in stages. The specific principle process is as follows: After the signal receiving module receives the destruction command, the entire system boots up. The existing capacitor charge and discharge module begins operating, providing the energy foundation for destruction. A newly added temperature sensor, tightly attached to the surface of the Flash chip, monitors chip temperature in real time. Excessive temperatures can affect destruction effectiveness or even damage the device, thus serving as a critical temperature warning. The current detection circuit, through a sampling resistor and op amp circuit, accurately captures the real-time current value at the Flash power pin. This current value provides a direct reflection of the chip's internal operating status and degree of damage.

[0049] A multi-stage state machine embedded within the microcontroller performs intelligent analysis and decision-making based on data from temperature sensors and current detection circuits. Based on pre-set logic rules, the state machine dynamically adjusts key parameters of the destruction process, such as voltage, pulse duty cycle, and the duration of each phase. This ensures that the destruction process thoroughly destroys data while avoiding issues caused by improper parameters.

[0050] During the preheating phase, the microcontroller controls the power management unit to output 20V, charging the capacitor bank to this voltage. The microcontroller then outputs a square wave control signal with a 1:5 duty cycle, controlling the MOSFET to continuously switch the destruction circuit on and off. Five pulses are delivered to the Flash chip, with a low-level pulse duration of 2ms and a high-level pulse duration of 10ms, separated by 100ms. These low-voltage pulses gradually damage the chip's internal structure. This gradual destruction evenly affects all internal components, preventing sudden high voltage overheating and incomplete burnout.

[0051] After preheating, the voltage is raised to the standard 28V. The square wave duty cycle is adjusted to 1:10, meaning a low level of 1ms and a high level of 10ms. Pulses are continuously output until the current detection value falls below the set threshold (e.g., 10mA), indicating that the core data area has been physically destroyed. During this process, if the temperature sensor detects that the chip temperature exceeds 80°C, the microcontroller automatically inserts a 100ms cooling interval to prevent excessive temperatures from affecting the destruction process and device safety.

[0052] After the primary destruction phase completes, if the current remains above the threshold, it indicates that data in stubborn areas has not been completely destroyed. Enhanced destruction is automatically triggered. The voltage is further increased to 32V, approaching the capacitor's rated voltage safety limit of 35V. The square wave duty cycle is changed to 1:15, with three consecutive pulses of 0.5ms low and 7.5ms high, each separated by 50ms. This applies higher energy to stubborn areas, ensuring that data cannot be recovered. After destruction is complete, the microcontroller controls the MOSFET to switch to normal power supply and ceases pulse output. If the device has an integrated cooling fan, the fan is activated to accelerate heat dissipation; otherwise, the chip is allowed to cool naturally. After the cooling process is complete, the system performs a self-test, checking the operating status of each module and generating a destruction report. The log is uploaded via the communication interface (Wi-Fi / 5G), recording key information such as the destruction success, peak voltage, and total time.

[0053] This method uses a multi-level destruction mechanism through real-time hardware monitoring and software intelligent regulation to process the Flash chip in stages, achieving efficient, thorough and secure data destruction.

[0054] In order to facilitate those skilled in the art to further understand the present invention, the present invention is further elaborated.

[0055] The existing hard destruction technology in the prior art converts the destruction voltage from 3.3V to 8V and uses the normal Flash power supply circuit to output it to the Flash chip, making it impossible to adjust the destruction voltage. The existing hard destruction technology burns the Flash chip by continuously converting the 3.3V to 8V voltage for a period of time, and all Flash chips are burned simultaneously. The front end must have sufficient power supply capacity, otherwise it will lead to insufficient power supply during the destruction process and incomplete destruction. Using the original normal power supply circuit to input the destruction voltage will burn other existing devices and circuits, and even cause the entire SSD and other devices to burn. This poses a significant safety risk. There is no dedicated destruction of the Flash chip that stores data, making the hard-destroyed SSD unusable and costly.

[0056] In view of the above shortcomings, the hard destruction in the present invention mainly consists of four parts: input destruction voltage as the starting signal, single chip microcomputer to control the burning time, MOS switch circuit to prevent burning other devices, and capacitor charging and discharging to burn the Flash chip. The main components are as follows: Figure 1 shown.

[0057] Including single chip microcomputer control circuit, MOS tube switch circuit, capacitor charging and discharging circuit; Among them, the single-chip microcomputer control circuit uses the external input destruction voltage as the starting signal, mainly to control the switching of normal power supply and hard destruction voltage, the total destruction time, and the capacitor charging and discharging time. The circuit schematic diagram of the single-chip microcomputer control circuit is as follows Figure 2 shown.

[0058] VDD is connected to the power supply VCC to power the chip; GND is connected to the ground to provide a reference potential; RST: reset pin; PA0-PA5: general-purpose input / output pins; VCC_EN_N: power enable pin, low level is valid; DES_EN0: may be a specific function enable pin.

[0059] Normal state: PA0 is high, VCC_EN_N is low, DES_EN0 is low; Destroy state: PA0 is low, VCC_EN_N is high, and DES_EN0 outputs a periodic square wave with a waveform of 1ms low and 10ms high.

[0060] The MOS tube switch circuit is controlled by the 10:1 cycle waveform output by the single chip microcomputer, a normal power supply and a hard destruction voltage switching signal, which mainly controls the release and shutdown of the destruction voltage in the capacitor charging and discharging circuit; it is also controlled by the switching signal to ensure safety; the principle of the MOS tube switch circuit is as follows Figure 3 shown.

[0061] The MOS transistor switch circuit includes a combination circuit composed of NMOS transistors and PMOS transistors, including Q1, Q2, Q3, Q5, Q6 and resistor R7; in, The gate of Q1 is connected to the signal VCC_EN_N, the source is grounded, and the drain is connected to the gate of Q2. The source of Q2 is grounded, and the drain is connected to the gate of Q3; Q3 drain is connected to VCC_R, and source output is PWR_NAND; Signal VCC_EN is connected to the node between Q1 and Q2.

[0062] One end of R7 is connected to VCC_R, and the other end is connected to the gate of Q6. Q6's source is grounded, and its drain outputs DES_EN0. Q5's drain is connected to VCC_NAND, and its gate cooperates with other nodes to switch the power supply path.

[0063] Normal state: Under normal working conditions, PWR_NAND is directly supplied to VCC_NAND to power the Flash.

[0064] Destroy state: In the destroy state, the power supply from PWR_NAND to VCC_NAND is cut off, and the destroy voltage is used for destruction. The circuit switches the power supply path between normal power supply and destroy state by turning on and off the transistor.

[0065] Among them, the capacitor charging and discharging circuit is controlled by the MOS tube switch circuit, which mainly outputs pulse voltage to burn the Flash chip; the capacitor charging and discharging circuit schematic is as follows Figure 4 shown.

[0066] The capacitor charge and discharge circuit consists of an input power supply 28V_IN, a switch, an energy storage capacitor C1, an output node VCC_R, and a ground terminal GND. 28V_IN is connected to one end of the switch, the other end of the switch is connected to VCC_R, VCC_R is connected to one end of the energy storage capacitor C1, and the other end of C1 is grounded (GND).

[0067] The switch is a MOS transistor or a relay. In this embodiment, the switch is a MOS transistor. Normal state: 28V_IN has no input, the switch is disconnected, and there is no destruction voltage.

[0068] Destruction state: 28V_IN input, the switch is closed, the capacitor is charged with 28V, and the Flash is burned.

[0069] The destruction voltage of this invention supports 16V-32V (typical value 28V), and the destruction voltage amplitude can be modified according to actual conditions. The hard destruction voltage is input externally, and when the external hard destruction voltage is input, it indicates that the hard destruction has begun. In actual situations, the external destruction voltage power supply circuit must also balance its own power supply capacity, safety, and implementation difficulty. The adjustable destruction voltage amplitude will greatly reduce the difficulty of actual circuit implementation.

[0070] To address the issue of insufficient front-end power supply caused by a sustained destruction voltage, the destruction voltage is not directly delivered to the Flash chip. Instead, the burnout is performed periodically by charging and discharging a capacitor. During the burnout process, the capacitor releases voltage under the control of the microcontroller, delivering the hard destruction voltage to the Flash chip, ensuring a more thorough hard destruction.

[0071] In actual use, the hard destroy circuit is separated from the normal power supply circuit: This isolation reduces the risk of false triggering of the hard destroy and protects other components and circuits besides the Flash chip. After the hard destroy is completed, the SSD can be used again by replacing the normal Flash chip, saving costs.

[0072] In order to ensure the security of data, this hard destruction technology provides a relatively simple and efficient data destruction method. Specifically, when receiving the destruction voltage from the external input, the charge and discharge circuit outputs the destruction voltage to the Flash chip through the control of the microcontroller and MOS tube switch circuit. At the same time, it will not cause damage to the entire solid-state drive. After replacing the Flash chip, it can be used again, and the application scenarios are broader.

[0073] Conduct a hard destruction test. The following is a diagram showing the effect of burning the Flash chip with different destruction voltages. Figure 5 、 Figure 6 and Figure 7 , which correspond to 20V, 25V and 28V voltages for destruction respectively; under the destruction voltages of 20V, 25V and 28V, the Flash chip is burned, ensuring that each Flash chip is fully burned and there is no risk of data recovery.

[0074] It should be noted that the processor in the present invention can be an integrated circuit chip with signal processing capabilities. The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. It can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0075] The foregoing is merely an embodiment of the present application and is not intended to limit the scope of protection of the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included within the scope of protection of the present application. It should be noted that similar reference numerals and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined or explained in subsequent figures.

Claims

1. A method for rapid destruction of a solid state hard drive, characterized in that: The specific steps include: Receive an external destruction voltage signal, where the amplitude range of the destruction voltage signal is 16V-32V; Generate a periodic square wave control signal through a single-chip microcomputer. The high and low level duty ratios of the square wave control signal are determined by the charge and discharge time of the capacitor charge and discharge circuit, wherein the low level duration is 0.8-1.5ms and the high level duration is 9-20ms. Based on the square wave control signal, the MOS tube switch circuit is controlled to switch the normal power supply circuit and the destruction circuit on and off; A pulse voltage is generated by a capacitor charge and discharge circuit, and the pulse voltage is applied to the power pin of the Flash chip of the solid-state drive to burn the storage chip and achieve the purpose of destroying data.

2. The method for rapid destruction of a solid-state hard drive according to claim 1, wherein: The amplitude of the destruction voltage signal is input externally, the input voltage range is 16V-32V, and the input is continuous for more than 1 second.

3. The method for rapid destruction of a solid-state hard drive according to claim 1, wherein: The duration of the pulse voltage does not exceed 0.8-1.5 ms, and the pulse interval is 10-30 ms, and the specific time is adjusted by the capacitor charging and discharging circuit.

4. The method for rapid destruction of a solid-state hard drive according to claim 1, wherein: After the destruction is completed, the burning status of the Flash chip is detected. If it is not completely burned, the destruction process is automatically triggered again.

5. A solid state hard drive rapid destruction device, characterized in that: include: A signal receiving module, used for receiving an externally input destruction voltage signal; A single chip microcomputer control module, connected to the signal receiving module, for generating a periodic square wave control signal; A MOS tube switch module is connected to the single-chip microcomputer control module and is used to switch between the normal power supply circuit and the destruction circuit according to the square wave control signal; The capacitor charging and discharging module is connected to the MOS tube switch module and is used to generate a pulse voltage and output it to the Flash chip.

6. The solid state hard drive rapid destruction device according to claim 5, characterized in that: The capacitor charge and discharge module includes multiple energy storage capacitors connected in parallel. The capacity of a single capacitor is 0.1-10 μF, the rated voltage is 63-100 V, it is designed with a 50% derating, and the total capacitance is not less than 100 μF.

7. The solid state hard drive rapid destruction device according to claim 5, characterized in that: The MOS transistor switch module includes a combination circuit composed of an NMOS transistor and a PMOS transistor, which is used to completely isolate the connection between the normal power supply circuit and the Flash chip in the destroyed state.

8. A solid state hard drive rapid destruction system, characterized in that: include: The solid state hard drive rapid hard destruction device according to any one of claims 5 to 7; A power management unit, configured to provide an adjustable voltage input for the destruction device, wherein the voltage range is 16V-32V; A monitoring module, used to detect voltage fluctuations and Flash chip status during the destruction process in real time, and to feed back abnormal signals to the single-chip control module; Communication interface, supports remote triggering of destruction instructions or receiving destruction status information.

9. A solid state hard drive rapid destruction system according to claim 8, characterized in that: The communication interface supports wireless communication protocols, including Wi-Fi, Bluetooth or 5G, and is used to interact with cloud servers or mobile terminals for data.

10. A computer-readable storage medium having computer program instructions stored therein, characterized in that: When the program is executed by a processor, the method for rapid hard destruction of a solid-state hard disk as described in any one of claims 1 to 4 is implemented.

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