Variable frequency display device and flicker compensation method thereof

Abstract

The invention provides a frequency-variable display device which comprises a display panel provided with a plurality of sub-pixels, an image driving circuit and a flicker compensation circuit. The image driving circuit is configured to write a data voltage through a data line and a reference voltage through a reference voltage line in each of the plurality of sub-pixels in a vertical effective period of one frame to achieve effective brightness, the flicker compensation circuit is configured to apply a compensation voltage to at least one of the data line and the reference voltage line in a vertical blanking period of the one frame to achieve blanking brightness lower than effective brightness.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2024-0022269 filed in Korea on February 16, 2024, the entire contents of which are incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a frequency-variable display device and a flicker compensation method thereof. Background Art

[0004] Frequency variable display devices change the frame rate of an image displayed on a screen based on properties of video data received from an external video source. Frequency variable display devices support a variable refresh rate (VRR) function that changes the frame rate within a predetermined frequency range.

[0005] When the frame rate is quickly changed from a low-speed frame to a high-speed frame or vice versa through VRR operation, users can recognize flickering caused by the recognition brightness deviation. In order to reduce the recognition brightness deviation, a brightness algorithm technology that adjusts the data gain of the frame rate can be used.

[0006] However, in VRR mode, the frequency information of the current frame may not be known until the end of the current frame. Therefore, conventional brightness algorithm technology determines the data gain of the current frame based on the frequency information of the previous frame, making it difficult to reduce the discernible brightness deviation between the first frame immediately after a rapid change in frame rate and the frame immediately before the first frame.

[0007] Therefore, there is a need for a display device having a configuration capable of preventing flicker or brightness deviation that is noticeable to a user when the driving frequency of the display device is changed. Summary of the Invention

[0008] In order to overcome the above problems of the prior art, the present disclosure can provide a frequency-variable display device and a flicker compensation method thereof, which can reduce the recognition brightness deviation occurring under the condition of rapid changes in frame rate.

[0009] To achieve these objects and other advantages and in accordance with the purposes of the present disclosure, as embodied and broadly described herein, a frequency-variable display device includes: a display panel having a plurality of sub-pixels disposed therein; an image driving circuit configured to write a data voltage through a data line and a reference voltage through a reference voltage line in each of the plurality of sub-pixels during a vertical effective period of a frame to achieve effective brightness; and a flicker compensation circuit configured to apply a compensation voltage to at least one of the data line and the reference voltage line during a vertical blanking period of the frame to achieve a blanking brightness lower than the effective brightness.

[0010] In another aspect of the present disclosure, a flicker compensation method for a frequency-variable display device is provided, the frequency-variable display device including a display panel provided with a plurality of sub-pixels, the method comprising: writing a data voltage through a data line and writing a reference voltage through a reference voltage line in each of the plurality of sub-pixels during a vertical effective period of a frame to achieve effective brightness, and applying a compensation voltage to at least one of the data line and the reference voltage line during a vertical blanking period of the frame to achieve a blanking brightness lower than the effective brightness. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. In the drawings:

[0012] Figure 1 is a block diagram illustrating a frequency variable display device according to an embodiment of the present disclosure;

[0013] Figure 2 is a diagram showing a connection configuration of one pixel according to an embodiment of the present disclosure;

[0014] Figure 3 is a diagram illustrating a vertical effective period and a vertical blanking period constituting one frame time according to an embodiment of the present disclosure;

[0015] Figure 4 is a diagram illustrating an example in which the length of a vertical front porch included in a vertical blanking period varies based on the level of a frame rate according to an embodiment of the present disclosure;

[0016] Figure 5 is a diagram illustrating an example of recognizing brightness based on a horizontal change in a frame rate according to an embodiment of the present disclosure;

[0017] Figure 6 is a diagram showing a deviation in recognition brightness that occurs under conditions of rapid changes in frame rate;

[0018] Figure 7 and 8 is a diagram showing an example in which visibility of a recognized luminance deviation occurring under conditions of rapid changes in frame rate at high grayscale levels is higher than that at low grayscale levels;

[0019] Figure 9 is a diagram showing a configuration of a flicker compensation circuit according to an embodiment of the present disclosure;

[0020] Figure 10 and Figure 11 is a driving timing diagram for describing a brightness control operation of a flicker compensation circuit according to an embodiment of the present disclosure;

[0021] Figure 12 is a diagram for describing an operation of one sub-pixel in a vertical front porch according to an embodiment of the present disclosure;

[0022] Figure 13 is a diagram illustrating an example in which the potential of the data line in the vertical front porch is a first compensation voltage less than a lower limit output value of the data voltage according to an embodiment of the present disclosure;

[0023] Figure 14 is a diagram showing an example in which the level of the first compensation voltage is reduced step by step in real time in proportion to the length of the vertical front edge within the first voltage control range according to an embodiment of the present disclosure;

[0024] Figure 15 is a diagram illustrating an example in which the potential of the reference voltage line in a vertical front porch is a second compensation voltage greater than the reference voltage according to an embodiment of the present disclosure;

[0025] Figure 16 is a diagram showing an example in which the level of the second compensation voltage increases step by step in real time in proportion to the length of the vertical front edge within the second voltage control range according to an embodiment of the present disclosure;

[0026] Figure 17 is a diagram illustrating relative sizes of recognized brightness deviations in a case where a brightness control operation is implemented in a vertical front porch or the like according to an embodiment of the present disclosure; and

[0027] Figure 18 is a diagram illustrating a flicker compensation method of a frequency variable display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which example embodiments of the present disclosure are shown. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the present disclosure to those skilled in the art.

[0029] The advantages and features of the present disclosure and their implementation methods will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0030] The shapes, sizes, ratios, angles, quantities, etc. used to describe the various embodiments of the present disclosure disclosed in the accompanying drawings are merely examples, and the present disclosure is not limited thereto. The same reference numerals always represent the same elements. Throughout the specification, the same elements are represented by the same reference numerals. As used herein, the terms "including," "having," "comprising," etc. indicate that other parts can be added, unless the term "only" is used. As used herein, the singular forms "a," "an," and "the" are intended to also include plural forms, unless the context clearly indicates otherwise.

[0031] Elements in various embodiments of the present disclosure are to be construed as including an error margin even if not explicitly stated.

[0032] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "above", "below", and "beside", unless "just" or "directly" is used, one or more other parts can be set between the two parts.

[0033] It should be understood that although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element without departing from the scope of the present disclosure. In addition, the term "can" includes all meanings and definitions of the word "may"

[0034] The following embodiments can be combined or combined with each other in part or in whole, and can be linked and operated in various technical ways. These embodiments can be performed independently of each other or in association with each other.

[0035] In the following description, when a detailed description of a related known function or configuration is determined to be unnecessary to make the key points of the present disclosure obscure, the detailed description will be omitted. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a block diagram illustrating a frequency variable display device according to an embodiment of the present disclosure.

[0037] refer to Figure 1 The display panel 100 may include a screen AA for displaying an input image. The screen AA may include a pixel array for displaying pixel data (hereinafter referred to as "image data") of the input image. The pixel array may include a plurality of data lines DL, a plurality of gate lines GL intersecting the data lines DL, a plurality of reference voltage lines, and a plurality of pixels.

[0038] Pixels can be arranged on the screen AA in a matrix type defined by data lines DL, gate lines GL, and reference voltage lines. Pixels can be arranged on the screen AA in various types such as a stripe type and a diamond type as well as a matrix type.

[0039] The pixel array can include a plurality of pixel columns and a plurality of pixel rows L1 to Ln intersecting the pixel columns. Each pixel column can include pixels arranged in the Y-axis direction. A pixel row can include pixels arranged in the X-axis direction. One vertical period can be a frame period required to write image data DATA for one frame in all pixels of the screen. One horizontal period can be the time obtained by dividing one frame period by the number of pixel rows L1 to Ln. One horizontal period can be the time required to write image data DATA for one pixel row of the shared gate line GL in the pixels of one pixel row.

[0040] Each pixel can include a red (R) sub-pixel 101 , a green (G) sub-pixel 101 , a blue (B) sub-pixel 101 , and a white (W) sub-pixel 101 for realizing color.

[0041] The frequency-variable display device according to an embodiment of the present disclosure can be implemented as an electroluminescent display device. In this case, the pixel circuit of the frequency-variable display device can include a light-emitting device, a driving element, one or more switching elements and a capacitor. The light-emitting device can be implemented as an organic light-emitting diode (OLED) or an inorganic light-emitting diode. The driving current that allows the light-emitting device to emit light can be adjusted based on the gate-source voltage of the driving element. Each of the driving element and the switching element can be implemented as a transistor. The semiconductor layer of the transistor can include amorphous silicon or polycrystalline silicon. The semiconductor layer of at least some of the transistors can include oxide. The pixel circuit can be connected to the data line DL and the gate line GL. Figure 1 , “D1 to D3” shown in circles can be data lines, and “Gn-2 to Gn” can be gate lines. In addition, each of the sub-pixels 101 can include the same pixel circuit configuration.

[0042] A touch sensor can be provided on the display panel 100. The touch sensor can be arranged as an on-cell or add-on type on the screen AA of the display panel 100, or can be implemented as an in-cell type touch sensor embedded in a pixel array. Touch input can be sensed by the touch sensor, or can be sensed only by the pixels even without a touch sensor.

[0043] The source driver 110 can convert the image data DATA received from the timing controller 130 into a gamma compensation voltage using a digital-to-analog converter (DAC) to generate a data voltage. The source driver 110 can provide the data voltage to the data line DL. The data voltage can be provided to the data line DL and applied to the gate electrode of the driving element through the switching element of the sub-pixel 101. The source driver 110 can provide the reference voltage Vref received from the power supply circuit 200 to the reference voltage line. The reference voltage Vref can be provided to the reference voltage line and applied to the source electrode of the driving element through the switching element of each sub-pixel 101.

[0044] The source driver 110 can be implemented using one or more source driver integrated circuits (ICs). The source driver IC can be connected to the timing controller 130 via an internal interface circuit. The internal interface circuit can be implemented as an embedded clock point-to-point interface (EPI). The source driver IC can also include a touch driver. The touch driver can generate touch sensor drive signals and can convert the charge changes of the touch sensor into touch raw data. The touch driver can transmit the touch raw data to the host system through a separate interface circuit. The separate interface circuit can be implemented as a serial peripheral interface (SPI), but is not limited thereto.

[0045] The gate driver 120 can be arranged outside the screen and not in the border area BZ where the image is displayed on the display panel 100. The gate driver 120 can sequentially provide gate signals synchronized with the data voltage to the gate lines GL under the control of the timing controller 130. The gate signals can simultaneously activate the pixel rows to which the data voltage is charged. The gate driver 120 can output the gate signals by using one or more shift registers and can shift the gate signals. The gate signals can include one or more scan signals and emission control signals. The gate signals can include a gate-on voltage VON and a gate-off voltage VOFF.

[0046] The timing controller 130 can receive image data DATA and timing signals synchronized with the image data DATA from the host system. The timing signals can include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock signal DCLK, and a data enable signal DE. The vertical synchronization signal Vsync can define a vertical period (e.g., one frame). The horizontal synchronization signal Hsync can define a horizontal period. The data enable signal DE can define the time during which the image data DATA is transmitted in the vertical period (e.g., a vertical active period). Another time in the vertical period other than the vertical active period can be a vertical blanking period. The data enable signal DE can swing during the vertical active period and can not swing during the vertical blanking period.

[0047] The timing controller 130 can generate a source timing control signal DDC for controlling the operation timing of the source driver 110 and a gate timing control signal GDC for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system.

[0048] The host system can be one of a television (TV), a set-top box, a navigation system, a personal computer (PC), a home theater, an automotive display system, a mobile device, and a wearable device. In the mobile device and the wearable device, the source driver 110, the timing controller 130, and the level shifter 140 can be integrated into one driver IC.

[0049] The level shifter 140 can shift the logic voltage level of the gate timing control signal GDC output from the timing controller 130 to the gate-on voltage VON or the gate-off voltage VOFF to provide it to the gate driver 120. The low logic voltage of the gate timing control signal GDC can be shifted to the gate-off voltage VOFF, and the high logic voltage of the gate timing control signal GDC can be shifted to the gate-on voltage VON.

[0050] The source driver 110 (e.g., a data driver) and the gate driver 120 can constitute an image driving circuit. The image driving circuit can write a reference voltage Vref and a data voltage for displaying an input image in a vertical effective period of one frame into the sub-pixel 101 to achieve effective brightness in the sub-pixel 101. The data voltage can be written into the sub-pixel 101 via the data line DL, and the reference voltage Vref can be written into the sub-pixel 101 via the reference voltage line.

[0051] The flicker compensation circuit 150 can apply a compensation voltage to at least one of the data line DL and the reference voltage line during the vertical blanking period of a frame to achieve a blanking brightness lower than the effective brightness. When the frame rate changes, the length of the vertical effective period can be fixed, but the length of the vertical blanking period can change. The flicker compensation circuit 150 can achieve a blanking brightness lower than the effective brightness during the vertical blanking period, thereby reducing the discernible brightness deviation between frames that occurs under conditions of rapid changes in the frame rate.

[0052] The flicker compensation circuit 150 can output a first compensation voltage to the data line DL and / or a second compensation voltage to the reference voltage line during the vertical blanking period to achieve blanking brightness. Based on the first compensation voltage and / or the second compensation voltage, the gate-source voltage of the driving element can be further reduced during the vertical blanking period than during the vertical active period, thereby reducing the current flowing in the driving element.

[0053] The flicker compensation circuit 150 can be integrated into the power supply circuit 200 .

[0054] The power supply circuit 200 is capable of generating various source voltages for panel driving. The power supply circuit 200 is capable of generating a gate-on voltage VON and a gate-off voltage VOFF for generating gate signals, generating a high-level source voltage EVDD and a low-level source voltage EVSS to be supplied to each sub-pixel 101, and generating a reference voltage Vref to be supplied to a reference voltage line.

[0055] Figure 2 is a diagram illustrating a connection configuration of one pixel PXL according to an embodiment of the present disclosure.

[0056] refer to Figure 2 , one pixel PXL can include four sub-pixels SP1 to SP4 that share a reference voltage line RL. The four sub-pixels SP1 to SP4 can be R, G, B, and W sub-pixels for constituting the same pixel (e.g., one pixel unit). Each of the sub-pixels SP1 to SP4 can include, for example, a light emitting device EL, a driving transistor DT, a storage capacitor Cst, a first switching transistor ST1, and a second switching transistor ST2.

[0057] The light-emitting device EL can emit light using a drive current supplied from the drive transistor DT to achieve brightness. The anode electrode of the light-emitting device EL can be connected to the second node N2, and the cathode electrode thereof can be connected to the input terminal of the low-level source voltage EVSS. In the same frame, the amount of current flowing through the light-emitting device EL can be further reduced during the vertical blanking period than during the vertical active period. This is likely because the gate-source voltage of the drive transistor DT is further reduced during the vertical blanking period than during the vertical active period due to a coupling effect.

[0058] The driving transistor DT can generate a driving current based on its gate-source voltage to provide to the light-emitting device EL. The gate electrode of the driving transistor DT can be connected to the first node N1, the drain electrode thereof can be connected to the input terminal of the high-level source voltage EVDD, and the source electrode thereof can be connected to the second node N2. In the same frame, the gate-source voltage of the driving transistor DT can decrease more significantly during the vertical blanking period than during the vertical active period. This may be because the compensation voltage is applied to one or more of the data line DL and the reference voltage line RL during the vertical blanking period.

[0059] A gate electrode of the first switching transistor ST1 can be connected to the gate line GL. A first electrode of the first switching transistor ST1 can be connected to the data line DL, and a second electrode thereof can be connected to the first node N1.

[0060] A gate electrode of the second switching transistor ST2 can be connected to the gate line GL. A first electrode of the second switching transistor ST2 can be connected to the reference voltage line RL, and a second electrode thereof can be connected to the second node N2.

[0061] A first electrode of the storage capacitor Cst can be connected to the first node N1 , and a second electrode thereof can be connected to the second node N2 .

[0062] The first switching transistor ST1 and the second switching transistor ST2 can be turned on based on a scanning signal SCAN having a gate-on voltage during a vertical active period. Thus, the gate electrode of the driving transistor DT can be connected to the data line DL, and the source electrode of the driving transistor DT can be connected to the reference voltage line RL. Therefore, a display programming operation for writing the data voltage Vdata and the reference voltage Vref can be performed. When the display programming operation is completed during the vertical active period, the first switching transistor ST1 and the second switching transistor ST2 can be turned off based on the scanning signal SCAN having a gate-off voltage.

[0063] The first switching transistor ST1 and the second switching transistor ST2 can be switched based on the vertical back porch VBP (see Figure 3 ). The first and second switching transistors ST1 and ST2 are turned on by the scanning signal SCAN having a gate-on voltage in the vertical back porch VBP. Therefore, the gate electrode of the driving transistor DT can be connected to the data line DL, and the source electrode of the driving transistor DT can be connected to the reference voltage line RL. Therefore, a sensing programming operation for the sensing process can be performed. When the sensing programming operation is completed in the vertical back porch VBP, the first switching transistor ST1 and the second switching transistor ST2 can be turned off based on the scanning signal SCAN having a gate-off voltage.

[0064] The first switching transistor ST1 and the second switching transistor ST2 can be based on the vertical front edge VFP (see Figure 3 ). The first switching transistor ST1 and the second switching transistor ST2 are turned on by the gate-off control voltage scan signal SCAN in the vertical front VFP. Thus, the gate electrode of the drive transistor DT can be connected to the data line DL, and the source electrode of the drive transistor DT can be connected to the reference voltage line RL. Therefore, a flicker compensation programming operation for writing one or more of the first compensation voltage AFIX1 and the second compensation voltage AFIX2 can be performed. In other words, the compensation voltages can be applied to at least one of the data line DL and the reference voltage line RL in the vertical front VFP. When the flicker compensation programming operation is completed in the vertical front VFP, the first switching transistor ST1 and the second switching transistor ST2 can be turned off based on the gate-off control voltage scan signal SCAN.

[0065] The first compensation voltage AFIX1 can be lower than the data voltage Vdata charged in the first node N1 of the subpixel during the vertical active period. In addition, the second compensation voltage AFIX2 can be higher than the reference voltage Vref charged in the second node N2 of the subpixel during the vertical active period.

[0066] The first switch SW1 and the second switch SW2 can also be connected to the reference voltage line RL. The first switch SW1 can connect the output terminal of the reference voltage Vref or the output terminal of the second compensation voltage AFIX2 to the reference voltage line RL. The second switch SW2 can connect the sensing circuit SU to the reference voltage line RL.

[0067] The first switch SW1 and the second switch SW2 can operate opposite to each other. That is, when the first switch SW1 is connected to the reference voltage line RL, the electrical connection between the second switch SW2 and the reference voltage line RL can be disconnected or open-circuited. On the other hand, when the second switch SW2 is connected to the reference voltage line RL, the electrical connection between the first switch SW1 and the reference voltage line RL can be disconnected or open-circuited.

[0068] When the second switch SW2 is connected to the reference voltage line RL, the sensing operation of the sensing circuit SU can be enabled. The sensing operation of the sensing circuit SU can be performed after the sensing programming operation is completed in the vertical trailing edge, so that changes in the electrical characteristics of each sub-pixel (for example, changes in the threshold voltage of the driving transistor and changes in the electron mobility) can be sensed.

[0069] Figure 3 is a diagram showing a vertical effective period and a vertical blanking period constituting one frame time. Figure 4 is a diagram showing an example in which the length of a vertical front porch included in a vertical blanking period varies based on the level of a frame rate;

[0070] refer to Figure 3, one frame time (vertical period) can be defined by the vertical synchronization signal Vsync. One frame time (vertical period) can be defined as the time interval between adjacent falling edges (or rising edges) of the vertical synchronization signal Vsync.

[0071] The vertical active period ACT and the vertical blanking period BLK in one frame time (vertical period) can be defined by the data enable signal DE. The vertical active period ACT can be a period during which the data enable signal DE swings, and the vertical blanking period BLK can be a period during which the data enable signal DE does not swing (e.g., maintains a logic low).

[0072] In a frame, the vertical blanking period BLK can be arranged separately with a vertical active period ACT in between. The vertical blanking period BLK can include a vertical back porch VBP arranged before the vertical active period ACT and a vertical front porch VFP arranged immediately after the vertical active period ACT. The vertical back porch VBP can be a period at the beginning of a frame before the image data is displayed, and the vertical front porch VFP can be a period at the end of a frame that starts just after the image data is displayed. For example, the vertical back porch VBP can be a short period at the beginning of a frame where no image data is transmitted, allowing the display hardware to reset and prepare for incoming image data, and the vertical front porch VFP occurring at the end of the frame can provide a similar type of buffer period before the start of the next vertical sync pulse to help ensure that the display device has enough time to complete processing the current frame before starting the next frame. The back porch and the front porch can help ensure a seamless transition between frames and prevent visual artifacts from occurring or being noticed by the audience.

[0073] The frequency variable display device according to an embodiment of the present disclosure can have a VRR mode in which a frame length is varied or adjustable. In the VRR mode, as Figure 4As shown, the frame rate can be changed to A Hz, B Hz, and C Hz. When the frame rate is changed, the length of one frame time can be changed to correspond thereto. At this time, each of the length of the vertical back porch VBP and the length of the vertical active period ACT can be fixed to a predetermined constant value, and the length of the vertical front porch VFP can be changed in proportion to the length of one frame time. In other words, the amount of time allocated to the vertical back porch VBP and the vertical active period ACT during one frame can be kept the same, and the amount of time allocated to the vertical front porch VFP can be adjusted (e.g., increased or decreased) based on the driving frequency. For example, based on a frame rate of A Hz (e.g., 240 Hz), the length of the vertical front porch VFP can be VFP1, and based on a frame rate of B Hz (e.g., 120 Hz), the length of the vertical front porch VFP can be VFP2, and based on a frame rate of C Hz (e.g., 60 Hz), the length of the vertical front porch VFP can be VFP3. Here, when A > B > C, and VFP1 < VFP2 < VFP3. For example, as the driving frequency becomes lower (e.g., slower), the length of the vertical front porch VFP can increase, while the time periods for the vertical back porch VBP and the vertical active period ACT remain the same or fixed.

[0074] In the vertical active period ACT having a fixed length, a display programming operation for writing an image can be performed.

[0075] In the vertical front porch VFP having a variable length, a flicker compensation operation for reducing brightness can be performed. The flicker compensation operation can be performed such that as the length of the vertical front porch VFP increases, the brightness is reduced more. In other words, as the vertical front porch VFP becomes longer, a greater amount of brightness is reduced.

[0076] The above-described sensing programming operation and sensing operation can be performed in the vertical back porch VBP having a fixed length. In the VRR mode, since the real-time (RT) sensing operation is performed in the vertical back porch VBP having a fixed length, the sensing line compensation algorithm can be applied in real time without error. The sensing line compensation algorithm can be a technique for differentially applying a compensation gain for brightness restoration based on the position of the pixel row where the sensing operation is performed, thereby improving the image quality. For example, when the sensing operation is performed in the blanking period whose length is changed based on the frame rate, it may be difficult to apply the sensing line compensation algorithm in real time. This may be because the length of the blanking period should be more reflected in the compensation gain, but the length of the blanking period may not be known until the end of the blanking period. That is, this may be because the length of the blanking period may not be known when the sensing line compensation algorithm is performed.

[0077] Figure 5 is a diagram showing an example of identifying brightness based on a horizontal change in the frame rate. Figure 6 is a diagram showing an identified brightness deviation that occurs under conditions of a rapid change in the frame rate. In addition, Figure 7 and 8 : is a diagram showing an example in which the visibility of the recognized luminance deviation occurring under the condition of rapid change of the frame rate is higher at a high grayscale level than at a low grayscale level.

[0078] Figure 5 and 6 The peak low point of can be the point at which the display programming operation is performed. The emission operation can be performed after the display programming operation is performed. The emission operation can be stopped while the display programming operation is being performed.

[0079] The display programming operation and the emission operation can be performed continuously in one frame. The number of display programming operations can increase as the number of frame arrangements within the pre-timing interval increases (i.e., the frame rate increases), and therefore, the identification brightness can be reduced. For example, the number of display programming operations within the pre-timing interval at a frame rate of 240 Hz can be twelve, the number of display programming operations within the pre-timing interval at a frame rate of 120 Hz can be six, and the number of display programming operations within the pre-timing interval at a frame rate of 60 Hz can be three. As a result, the real-time brightness integral value (e.g., identification brightness) of the frame rate of 240 Hz can be L1, the real-time brightness integral value (e.g., identification brightness) of the frame rate of 120 Hz can be L2 which is higher than L1, and the real-time brightness integral value (e.g., identification brightness) of the frame rate of 60 Hz can be L3 which is higher than L2. In other words, when the screen is driven at a low drive frequency (such as 60 Hz), the screen may appear brighter to the viewer because fewer display programming operations are performed, while when the screen is driven at a high drive frequency (such as 240 Hz), the screen may appear dimmer or blacker. Therefore, if the display device changes rapidly from a low drive frequency to a high drive frequency or vice versa, a change in brightness that is noticeable to the viewer may occur, which may impair the viewing experience.

[0080] As described above, assuming that the grayscale level of the displayed image is constant, the recognition brightness may be relatively high when the frame rate is low compared to when the frame rate is high. Therefore, when the frame rate changes from high to low, brightness deviation may occur due to changes in recognition brightness.

[0081] like Figure 7 and 8 As shown, frequency-dependent brightness deviations can be recognized more readily in low-grayscale periods than in high-grayscale periods. If the time taken to reach effective brightness saturation immediately after programming is defined as the brightness transition rate, the brightness transition rate of high-grayscale images can be relatively higher than that of low-grayscale images. Therefore, while the frequency-dependent brightness deviations may not be significantly recognized in high-grayscale images, they can be more clearly recognized when low-grayscale images are displayed.

[0082] Figure 9 is a diagram showing a configuration of the flicker compensation circuit 150 according to an embodiment of the present disclosure. Figure 10 and 11 1 is a driving timing diagram for describing a brightness control operation of the flicker compensation circuit 150 according to an embodiment of the present disclosure. Figure 12 is a diagram for describing the operation of one sub-pixel in a vertical front porch according to an embodiment of the present disclosure.

[0083] refer to Figures 9 to 12 In the vertical front edge VFP, the flicker compensation circuit 150 according to this embodiment can reduce the potential of the data line DL to the first compensation voltage AFIX1 and / or can increase the potential of the reference voltage line RL to the second compensation voltage AFIX2. The data line DL and the gate electrode of the drive transistor DT can be coupled to each other via the parasitic capacitor PC1, and the reference voltage line RL and the source electrode of the drive transistor DT can be coupled to each other via the parasitic capacitor PC2. Therefore, the gate-source voltage Vgs and the amount of the drive current Ids of the drive transistor DT can be reduced in the vertical front edge VFP, thereby providing a combined contribution to reducing the brightness of the light-emitting device EL.

[0084] The flicker compensation circuit 150 can control the levels of the first compensation voltage AFIX1 and the second compensation voltage AFIX2 in proportion to the length of the vertical front porch VFP. To this end, the flicker compensation circuit 150 can include a counter 152 and a voltage controller 154.

[0085] The length of the vertical front porch VFP defined by the vertical synchronization signal Vsync and the data enable signal DE can vary based on the frame rate. The counter 152 can count the length of the vertical front porch VFP using the reference clock RCLK to provide a real-time count value CNT to the voltage controller 154.

[0086] The voltage controller 154 can control the levels of the first compensation voltage AFIX1 and the second compensation voltage AFIX2 based on the real-time count value CNT corresponding to the length of the vertical front edge VFP.

[0087] Figure 13 is a diagram showing an example in which the potential of the data line in the vertical front is a first compensation voltage that is smaller than the lower limit output value of the data voltage. Figure 14 is a diagram illustrating an example in which the level of the first compensation voltage gradually decreases step by step in real time in proportion to the length of the vertical front edge within the first voltage control range.

[0088] refer to Figure 13The flicker compensation circuit 150 can change the level of the first compensation voltage AFIX1 within a first voltage control range VR1 based on the length of the vertical front edge VFP. In this case, the first voltage control range VR1 can be within a voltage range that is less than the lower limit output value of the data voltage Vdata corresponding to the black grayscale. In addition, the upper limit output value of the data voltage Vdata can correspond to the white grayscale.

[0089] By using the flicker compensation circuit 150, as Figure 14 As shown, the level of the first compensation voltage AFIX1 can be gradually reduced step by step in real time in proportion to the length of the vertical front edge VFP within the first voltage control range VR1.

[0090] The flicker compensation circuit 150 is capable of pre-storing a plurality of counting thresholds TH1 to TH3 having different sizes corresponding to a plurality of frame rates, and is capable of controlling the level of the first compensation voltage AFIX1 step by step downward through a sequential comparison operation between the plurality of counting thresholds TH1 to TH3 and a real-time count value of the length of the vertical front edge VFP.

[0091] Figure 15 is a diagram showing an example in which the potential of the reference voltage line in the vertical front porch is the second compensation voltage greater than the reference voltage. Figure 16 is a diagram showing an example in which the level of the second compensation voltage gradually increases step by step in real time in proportion to the length of the vertical front edge within the second voltage control range.

[0092] refer to Figure 15 The flicker compensation circuit 150 can change the level of the second compensation voltage AFIX2 within the second voltage control range VR2 based on the length of the vertical front porch VFP. In this case, the second voltage control range VR2 can be within a voltage range greater than the reference voltage Vref.

[0093] By using the flicker compensation circuit 150, as Figure 16 As shown, the level of the second compensation voltage AFIX2 can be gradually increased step by step in proportion to the length of the vertical front edge VFP within the second voltage control range VR2.

[0094] The flicker compensation circuit 150 can pre-store a plurality of count thresholds TH1 to TH3 having different sizes corresponding to a plurality of frame rates, and can gradually control the level of the second compensation voltage AFIX2 upward by sequentially comparing the plurality of count thresholds TH1 to TH3 with the real-time count value of the length of the vertical front porch VFP. For example, as the driving frequency changes from a high driving frequency to a low driving frequency, the vertical front porch VFP becomes longer, and the first compensation voltage AFIX1 applied to the data line during the vertical front porch VFP can be gradually reduced, while the second compensation voltage AFIX2 applied to the reference line can be gradually increased, and vice versa, so as to smooth out any deviation in brightness as the driving frequency is adjusted.

[0095] Figure 17 : is a graph showing the relative magnitude of the identified brightness deviation in the case where the brightness control operation is implemented in the vertical front porch and in the case where the brightness control operation is not implemented.

[0096] refer to Figure 17 In the conventional method (A) in which the brightness control operation is not implemented in the vertical front porch (VFP) when performing VRR operation, when the frame rate changes rapidly from a low-speed frame to a high-speed frame or vice versa, the user can recognize a flicker phenomenon caused by brightness deviation, which can impair the user's viewing experience. However, in B) of this embodiment, since the brightness control operation is implemented in the vertical front porch (VFP) when performing VRR operation, the recognition of brightness deviation can be reduced despite the rapid change condition of the frame rate, and the user can avoid recognizing the flicker phenomenon even when switching between different driving frequencies, and the display quality can be improved.

[0097] Figure 18 is a diagram illustrating a flicker compensation method of the frequency-variable display device according to the present embodiment.

[0098] refer to Figure 18 The flicker compensation method of the frequency variable display device according to this embodiment can write a data voltage through a data line and a reference voltage through a reference voltage line in each sub-pixel in a vertical effective period of one frame to achieve effective brightness (S10).

[0099] Subsequently, the flicker compensation method of the frequency variable display device according to the present embodiment can apply a compensation voltage to at least one of the data line and the reference voltage line in a vertical blanking period of one frame to achieve blanking brightness lower than effective brightness ( S20 ).

[0100] This embodiment can achieve the following effects.

[0101] This embodiment can reduce the recognition brightness deviation occurring under the condition of rapid changes in frame rate, thereby significantly improving display quality.

[0102] The effects according to the present disclosure are not limited to the above-described examples, and other various effects can be included in this specification.

[0103] While the present disclosure has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A display device, comprising: A display panel, the display panel comprising a plurality of sub-pixels; an image driving circuit configured to write a data voltage through a data line and a reference voltage through a reference voltage line in each of a plurality of sub-pixels during a vertical effective period of one frame to achieve effective brightness; as well as A flicker compensation circuit is configured to apply a compensation voltage to at least one of the data line and the reference voltage line during a vertical blanking period of the one frame to achieve a blanking brightness that is lower than the effective brightness.

2. The display device according to claim 1, wherein The vertical blanking period includes a vertical trailing edge before the vertical effective period in the one frame and a vertical leading edge after the vertical effective period in the one frame, wherein the length of the vertical back porch is fixed to a constant value, regardless of the length change of the one frame, and The length of the vertical front edge varies in proportion to the length of the frame.

3. The display device according to claim 2, wherein The flicker compensation circuit is further configured to apply the compensation voltage to the at least one of the data line and the reference voltage line in the vertical front porch of the one frame.

4. The display device according to claim 3, wherein The potential of the data line in the vertical effective period is the data voltage. wherein the potential of the data line in the vertical front changes from the data voltage to a first compensation voltage lower than the data voltage, and The gate-source voltage of the driving transistor included in each sub-pixel is lower in the vertical leading edge than in the vertical effective period.

5. The display device according to claim 4, wherein The level of the first compensation voltage is changed within a first voltage control range based on the length of the vertical front edge, and The first voltage control range is within a voltage range lower than a lower limit output value of the data voltage. The display device according to claim 5 , wherein: The level of the first compensation voltage decreases step by step in real time in proportion to the length of the vertical front edge within the first voltage control range.

7. The display device according to claim 3, wherein The potential of the reference voltage line in the vertical effective period is the reference voltage, wherein the potential of the reference voltage line in the vertical front edge changes from the reference voltage to a second compensation voltage greater than the reference voltage, and The gate-source voltage of the driving transistor included in each sub-pixel is lower in the vertical leading edge than in the vertical effective period.

8. The display device according to claim 7, wherein The level of the second compensation voltage varies within a second voltage control range based on the length of the vertical front edge, and The second voltage control range is within a voltage range greater than the reference voltage.

9. The display device according to claim 8, wherein The level of the second compensation voltage increases step by step in real time in proportion to the length of the vertical front edge within the second voltage control range.

10. A method for controlling a display device, the method comprising: During a vertical effective period of one frame, writing a data voltage through a data line connected to the at least one subpixel and a reference voltage through a reference voltage line connected to the at least one subpixel in at least one subpixel among a plurality of subpixels included in a display panel of the display device to achieve effective brightness; and A compensation voltage is applied to at least one of the data line and the reference voltage line in a vertical blanking period of the one frame to achieve blanking brightness, the blanking brightness being lower than the effective brightness.

11. The method according to claim 10, further comprising: In response to a change in the driving frequency of the display device, adjusting the length of the vertical front porch based on the length of the one frame while maintaining the length of the vertical back porch at a constant value, The one frame includes the vertical trailing porch, the vertical effective period and the vertical leading porch.

12. The method according to claim 11, further comprising: The compensation voltage is applied to at least one of the data line and the reference voltage line during the vertical front porch of the one frame.

13. The method according to claim 12, further comprising: providing the data voltage to the data line during the vertical active period of the one frame; and providing a first compensation voltage to the data line during the vertical front edge of the frame, The gate-source voltage of the driving transistor included in the at least one sub-pixel is lower in the vertical front edge than in the vertical effective period.

14. The method according to claim 12, further comprising: providing the reference voltage to the reference voltage line during the vertical active period of the one frame; and providing a second compensation voltage to the reference voltage line during the vertical front edge of the one frame, The gate-source voltage of the driving transistor included in the at least one sub-pixel is lower in the vertical front edge than in the vertical effective period.

15. A display device comprising: a display panel comprising a plurality of sub-pixels configured to display an image; and A controller configured to: performing a sensing operation on at least one of the plurality of sub-pixels during a vertical trailing porch period of a frame, displaying image data through the at least one sub-pixel during a vertical active period of the frame, and providing at least one compensation voltage to the at least one sub-pixel during a vertical leading porch period of the frame, and In response to changing the driving frequency of the display panel, the time length of the vertical front porch period is adjusted while the vertical back porch period and the vertical effective period of the frame are maintained at fixed time lengths.

16. The display device according to claim 15, wherein the controller is further configured to: In response to changing the driving from a first driving frequency to a second driving frequency lower than the first driving frequency, the time length of the vertical front porch period is increased.

17. The display device according to claim 15, wherein the controller is further configured to: In response to changing the driving from a first driving frequency to a second driving frequency higher than the first driving frequency, the time length of the vertical front porch period is reduced.

18. The display device according to claim 15, wherein the controller is further configured to: providing a first compensation voltage to a data line connected to the at least one subpixel during the vertical front period, and A second compensation voltage is provided to a reference line connected to the at least one subpixel during the vertical front period.

19. The display device according to claim 18, wherein The first compensation voltage is lower than a lower limit voltage of a voltage range of image data provided during the vertical effective period, and The second compensation voltage is greater than a reference voltage provided to the reference line during the vertical effective period.

20. The display device according to claim 18, wherein the controller is further configured to: reducing the first compensation voltage supplied to the data line in a stepwise manner during the vertical front porch period, and The second compensation voltage provided to the reference line is increased in a stepwise manner during the vertical front porch period.

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