Memory storage device and operation method thereof

Abstract

The invention provides a memory storage device and an operation method of the memory storage device. The memory storage device comprises a memory array and a controller circuit. The memory array is used for storing data. The controller circuit is coupled to the memory array. The controller circuit is used for receiving a reset signal and a trigger signal. The controller circuit performs a reset operation according to the reset signal. The controller circuit keeps supplying power to the memory array during a reset period according to the trigger signal.

Description

Technical Field

[0001] The present invention relates to a memory storage device and an operating method of the memory storage device. Background Art

[0002] Taking volatile memory as an example, data stored in a memory storage device disappears when power is removed. For example, dynamic random-access memory (DRAM) cannot retain stored data after being reset. However, in some applications, users may want to retain stored data after a DRAM reset to meet the requirements of fast boot-up. Summary of the Invention

[0003] The present invention provides a memory storage device and an operating method thereof, which can be reset without power failure and maintain the correctness of stored data after reset.

[0004] A memory storage device of the present invention includes a memory array and a controller circuit. The memory array is configured to store data. The controller circuit is coupled to the memory array. The controller circuit is configured to receive a reset signal and a trigger signal. The controller circuit performs a reset operation in response to the reset signal. The controller circuit maintains power to the memory array during the reset period in response to the trigger signal.

[0005] The operating method of the memory storage device of the present invention comprises: receiving a reset signal and a trigger signal; performing a reset operation according to the reset signal; and maintaining power supply to the memory array during the reset period according to the trigger signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram illustrating a memory storage device according to an embodiment of the present invention;

[0007] Figure 2 Show Figure 1 A waveform diagram of a trigger signal according to an embodiment;

[0008] Figure 3 A waveform diagram showing a trigger signal according to another embodiment of the present invention;

[0009] Figure 4 A block diagram illustrating a memory storage device according to an embodiment of the present invention;

[0010] Figure 5 A schematic diagram showing waveforms of a reset signal and a reference signal according to an embodiment of the present invention;

[0011] Figure 6 A flowchart showing a method for operating a memory storage device according to an embodiment of the present invention;

[0012] Figure 7A flowchart illustrating a method for operating a memory storage device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0013] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0014] Figure 1 A block diagram showing a memory storage device according to an embodiment of the present invention is shown. Figure 1 Memory storage device 100 includes a memory array 110 and a controller circuit 120. Controller circuit 120 is coupled to memory array 110. Controller circuit 120 is configured to receive a reset signal S1 and a trigger signal S2. Controller circuit 120 performs a reset operation based on reset signal S1. Controller circuit 120 maintains power to memory array 110 during the reset period based on trigger signal S2.

[0015] In this embodiment, the memory storage device 100 is, for example, a dynamic random-access memory (DRAM). By maintaining power to the memory array 110 during reset, the DRAM can be reset without powering off and maintain the accuracy of stored data after reset.

[0016] Figure 2 Show Figure 1 The waveform diagram of the trigger signal of the embodiment. Please refer to Figure 1 and Figure 2 , Figure 1 The trigger signal S2 of the embodiment can be a combination of external signals input to the pins of the memory storage device 100. The combination of external signals includes signal types or voltage levels. Specifically, the memory storage device 100 is, for example, a DRAM chip. The external signals input to the pins of the DRAM chip include signals such as CS#, RAS#, CAS#, WE#, and CKE, where CS# is a chip select signal, RAS# is a row address signal, CAS# is a column address signal, WE# is a write enable signal, and the reference signal CKE. Through the above-mentioned different types of signal combinations and / or voltage levels, the controller circuit 120 can be triggered to decide whether to keep the memory array 110 powered during reset.

[0017] Figure 2 The number, type, combination and voltage level of the external signals are only for illustration and are not intended to limit the present invention. In other embodiments, external signals of different numbers, types, combinations and voltage levels may also be used as the trigger signal S2.

[0018] Figure 3 FIG1 is a waveform diagram showing a trigger signal according to another embodiment of the present invention. Figure 1 and Figure 3 , Figure 1 The reset signal S1 of the embodiment can also be used as the trigger signal S2, and the duration of the reset signal S1 can be used to determine whether to trigger the controller circuit 120 to keep the power supply to the memory array 110 during the reset period. Figure 3 In the embodiment, reset signals S1 and S1' have a first level (low level) and a second level (high level). Compared to reset signal S1', the duration of the first level of reset signal S1 is longer. The longer duration of reset signal S1 can be used as trigger signal S2 to trigger the power supply maintenance operation. In other words, the duration of the first level of reset signal S1' can be used as threshold t1', and the reset signal S1 with a duration greater than threshold t1' can be used as trigger signal S2.

[0019] Conversely, in an embodiment, a reset signal S1' with a shorter duration can also serve as a trigger signal S2 to trigger the power-maintaining operation. In this example, the duration of the first level of the reset signal S1 can serve as the threshold t1, and the reset signal S1' with a duration less than the threshold t1 can serve as the trigger signal S2.

[0020] Figure 4 A block diagram showing a memory storage device according to an embodiment of the present invention is shown. Figure 4 The memory storage device 400 of this embodiment further includes a power supply circuit 430. The power supply circuit 430 is coupled to the memory array 110 and the controller circuit 120. The power supply circuit 430 is configured to receive an external power supply VDD0 and generate a power supply VDD based on the external power supply VDD0. The power supply VDD provides the power required by various circuit blocks within the memory storage device 400 to perform various operations.

[0021] The power supply circuit 430 provides power VDD to the memory array 110 during the reset period. The power supply circuit 430 can determine, based on instructions from the controller circuit 120, whether to maintain power to the memory array 110 during the reset period. Specifically, the power supply circuit 430 can continuously provide power VDD to the memory array 110 to ensure that the memory array 110 maintains the accuracy of the data stored therein after the reset.

[0022] In one embodiment, the controller circuit 120 may include a reset circuit block and a self-refresh circuit block for performing a reset operation and a self-refresh operation, respectively. The reset circuit block and the self-refresh circuit block may be implemented as logic circuits on an integrated circuit. For example, the functions associated with the reset circuit block and the self-refresh circuit block may be implemented as hardware such as various logic blocks, modules, and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs), and / or other processing units. The functions associated with the reset circuit block and the self-refresh circuit block may be implemented as hardware circuits such as various logic blocks, modules, and circuits in an integrated circuit using a hardware description language (HDL) (e.g., Verilog HDL or very high-speed integrated circuit (VHSIC) hardware description language (VHDL)) or other suitable programming languages. Furthermore, the memory array 110 , the controller circuit 120 , and the power supply circuit 430 may refer to common knowledge in the relevant fields for sufficient guidance, suggestions, and implementation instructions.

[0023] Figure 5 FIG1 shows a waveform diagram of the reset signal and the reference signal according to an embodiment of the present invention. Figure 1 and Figure 5 After the memory storage device 100 is powered on, the controller circuit 120 performs a reset operation and a self-refresh operation according to the reset signal S1 and the reference signal CKE.

[0024] Specifically, the controller circuit 120 first performs a reset operation based on the reset signal S1 and maintains power to the memory array 110 during a reset period T1 based on the trigger signal S2. In this embodiment, the controller circuit 120 performs a self-refresh operation on the memory array 110 only after the reset period T1 exceeds a predetermined time length. For example, the controller circuit 120 performs a self-refresh operation only after the reset operation lasts for more than 100 nanoseconds, ensuring that the operation of the memory storage device 100 complies with standard specifications.

[0025] Next, after completing the reset operation, the controller circuit 120 performs a self-refresh operation on the memory array 110 during a self-refresh period T2. In this embodiment, the controller circuit 120 stops the self-refresh operation based on the reference signal CKE. For example, after the reference signal CKE remains at a low level for a period of time T3, the controller circuit 120 performs a self-refresh operation on the memory array 110. When the reference signal CKE changes from a low level to a high level (time t2), the memory storage device 100 exits the self-refresh mode, and the controller circuit 120 stops the self-refresh operation on the memory array 110.

[0026] Figure 6 A flowchart showing the steps of the operating method of the memory storage device according to an embodiment of the present invention is shown. Figure 1 and Figure 6 The operating method of the memory storage device of this embodiment is at least applicable to Figure 1 The memory storage device 100 is a memory storage device 100, but the present invention is not limited thereto.

[0027] by Figure 1 Taking the memory storage device 100 as an example, in step S100, the controller circuit 120 receives a reset signal S1 and a trigger signal S2. In step S110, the controller circuit 120 performs a reset operation according to the reset signal S1. In step S120, the controller circuit 120 maintains power to the memory array 110 during a reset period T1 according to the trigger signal S2.

[0028] In addition, the operating method of the memory storage device of this embodiment can be Figures 1 to 5 Sufficient teachings, suggestions and implementation instructions are provided in the description of the embodiments, so they are not repeated here.

[0029] Figure 7 A flowchart showing the steps of the operating method of the memory storage device according to another embodiment of the present invention is shown. Figure 1 and Figure 7 The operating method of the memory storage device of this embodiment is at least applicable to Figure 1 The memory storage device 100 is a memory storage device 100, but the present invention is not limited thereto.

[0030] In step S200, a system, such as a processor circuit of a host system, sends a reset signal S1 to the memory storage device 100. In step S210, the controller circuit 120 receives the reset signal S1. Next, in step S220, the processor circuit determines whether to retain the data stored in the memory array 110.

[0031] If the data stored in the memory array 110 needs to be retained, the method proceeds to step S230. In step S230, the system sends a reset signal S1 and a trigger signal S2 to the memory storage device 100. Next, in step S240, the controller circuit 120 maintains power to the memory array 110 during the reset period T1 in response to the trigger signal S2. In step S250, the controller circuit 120 performs a self-refresh operation on the memory array 110 during the self-refresh period T2. In step S260, the controller circuit 120 stops the self-refresh operation on the memory array 110 in response to the reference signal CKE.

[0032] On the other hand, if the data stored in the memory array 110 does not need to be retained, the method proceeds to step S270 . In step S270 , the controller circuit 120 performs a reset operation but does not continuously supply power to the memory array 110 .

[0033] In summary, in embodiments of the present invention, the memory storage device can be reset without powering down, thereby retaining stored data after the reset. This allows the memory storage device to boot up quickly, minimizing downtime and quickly returning to its original state, making it less likely for the user to notice an abnormality.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory storage device comprising: Memory array for storing data; as well as The controller circuit is coupled to the memory array and is used to receive a reset signal and a trigger signal, wherein the controller circuit performs a reset operation according to the reset signal and keeps power supplied to the memory array during the reset period according to the trigger signal. 2 . The memory storage device according to claim 1 , wherein the controller circuit performs a self-refresh operation on the memory array after performing the reset operation. 3 . The memory storage device of claim 2 , wherein the controller circuit stops the self-refresh operation according to a reference signal. 4 . The memory storage device according to claim 2 , wherein the controller circuit performs the self-refresh operation on the memory array after the reset period exceeds a predetermined time length. 5 . The memory storage device according to claim 1 , wherein the trigger signal is a combination of external signals input to pins of the memory storage device, and the combination of external signals includes signal types or voltage levels. 6 . The memory storage device according to claim 1 , wherein the reset signal serves as the trigger signal, and the duration of the reset signal is used to determine whether to trigger an operation of maintaining power supply to the memory array during the reset period.

7. The memory storage device according to claim 1, further comprising: The power supply circuit is coupled to the memory array and the controller circuit and is used to provide power to the memory array during the reset period. The power supply circuit determines whether to keep powering the memory array during the reset period according to instructions from the controller circuit.

8. A method for operating a memory storage device, wherein the memory storage device comprises a memory array, the method comprising: Receive reset signal and trigger signal; Performing a reset operation according to the reset signal; as well as The memory array is powered on during a reset period according to the trigger signal. 9 . The method for operating a memory storage device according to claim 8 , further comprising performing a self-refresh operation on the memory array after performing the reset operation. 10 . The operating method of the memory storage device according to claim 9 , further comprising stopping the self-refresh operation according to a reference signal. 11 . The operating method of the memory storage device according to claim 9 , wherein the self-refresh operation is performed on the memory array after the reset period is greater than a preset time length. 12 . The operating method of the memory storage device according to claim 8 , wherein the trigger signal is a combination of external signals input to pins of the memory storage device, and the combination of external signals includes signal types or voltage levels. 13 . The operating method of the memory storage device according to claim 8 , wherein the reset signal serves as the trigger signal, and the duration of the reset signal is used to determine whether to trigger an operation of maintaining power supply to the memory array during the reset period.

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