Test circuit and test method

Abstract

The embodiment of the invention provides a test circuit and a test method, and the test circuit comprises a low-frequency filter circuit which is configured to receive a first signal subjected to CTLE processing, extract a low-frequency part in the first signal, and output the low-frequency part as a second signal; the power comparison circuit is configured to receive the first signal and the second signal, compare the first power of the first signal with the second power of the second signal, and output a first potential and a second potential which are respectively used for representing the first power and the second power; and the single-ended output circuit is configured to receive and compare the first potential and the second potential, and output a comparison result signal for representing the difference between the first potential and the second potential. The embodiment of the invention is beneficial to improving the test efficiency and the test accuracy.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a test circuit and a test method. Background Art

[0002] Some read / write memories, such as dynamic random access memory (DRAM), include an array of memory cells that store information. For example, some DRAM devices, such as synchronous dynamic RAM (SDRAM) devices, may have multiple memory banks with many addressable memory elements or cells included in the memory array. In use, a memory such as SDRAM can receive data input signals at a relatively high speed and store data in the memory cells based on the data input signals.

[0003] As memory operating speeds increase, the impact of channel attenuation during signal transmission becomes increasingly significant. To mitigate signal integrity issues, a continuous time linear equalizer (CTLE) is often used in memory receiver circuits to compensate for high-frequency signal attenuation. CTLEs can be designed with multiple adjustment settings, each with varying compensation capabilities.

[0004] In manufactured memories, CTLE functionality often needs to be tested and verified. However, current testing methods still need to be improved. Summary of the Invention

[0005] The embodiments of the present disclosure provide a test circuit and a test method, which are at least beneficial to improving test efficiency and test accuracy.

[0006] Some embodiments of the present disclosure provide a test circuit for use in CTLE function verification, the test circuit including: a low-frequency filtering circuit configured to receive a first signal processed by CTLE, extract a low-frequency portion of the first signal, and output the low-frequency portion as a second signal; a power comparison circuit configured to receive the first signal and the second signal, compare a first power of the first signal with a second power of the second signal, and output a first potential and a second potential for representing the first power and the second power, respectively; and a single-ended output circuit configured to receive and compare the first potential and the second potential, and output a comparison result signal for representing the difference between the first potential and the second potential.

[0007] In some embodiments, the low-frequency filtering circuit is further configured to amplify the low-frequency portion; and / or the second signal and the first signal have the same common-mode voltage.

[0008] In some embodiments, the first signal and the second signal are both differential signal pairs; the low-frequency filter circuit includes: a first PMOS transistor and a second PMOS transistor, wherein the gate of the first PMOS transistor and the gate of the second PMOS transistor respectively receive differential signals in the first signal, and the first end of the first PMOS transistor and the first end of the second PMOS transistor are both connected to a working power supply; a first resistor and a second resistor, wherein the first resistor is connected between the second end of the first PMOS transistor and the ground, and the second resistor is connected between the second end of the second PMOS transistor and the ground; a first capacitor and a second capacitor, wherein the first capacitor is connected between the second end of the first PMOS transistor and a first node, and the second capacitor is connected between the second end of the second PMOS transistor and the ground. between the second end of the PMOS tube and the second node, the first node and the second node are used to output the second signal; a third resistor and a fourth resistor, the third resistor and the fourth resistor are connected in series between the gate of the first PMOS tube and the first node, and the fourth resistor is directly coupled to the first node; a fifth resistor and a sixth resistor, the fifth resistor and the sixth resistor are connected in series between the gate of the second PMOS tube and the second node, and the sixth resistor is directly coupled to the second node, wherein the third resistor, the fourth resistor, the fifth resistor and the sixth resistor are all directly coupled to the common mode node; a third capacitor and a fourth capacitor, the third capacitor is connected in parallel with the first resistor, and the fourth capacitor is connected in parallel with the second resistor.

[0009] In some embodiments, the power comparison circuit includes: a first input pair of tubes, connected between the working power supply and the first potential node, for receiving the first signal, the first potential node is used to output the first potential, a second input pair of tubes, connected between the working power supply and the second potential node, for receiving the second signal, the second potential node is used to output the second potential; a third PMOS tube, connected between the working power supply and the first potential node, for receiving the common mode voltage; a seventh resistor and a fifth capacitor, connected in parallel between the first potential node and the ground terminal; an eighth resistor and a sixth capacitor, connected in parallel between the second potential node and the ground terminal.

[0010] In some embodiments, the sum of the width-to-length ratios of the first input pair of transistors and the width-to-length ratio of the third PMOS transistor is equal to the sum of the width-to-length ratios of the second input pair of transistors.

[0011] In some embodiments, the single-ended output circuit includes: a comparator, a ninth resistor, a tenth resistor, and an eleventh resistor, the ninth resistor being connected between the first potential and the positive input of the comparator, the tenth resistor being connected between the second potential and the negative input of the comparator, the eleventh resistor being connected between the negative input and the output of the comparator, and the output of the comparator being used to output the comparison result signal; and a seventh capacitor being connected between the output of the comparator and the ground.

[0012] In some embodiments, the single-ended output circuit further includes: a twelfth resistor, wherein the twelfth resistor is connected between the positive input terminal of the comparator and a reference voltage.

[0013] Other embodiments of the present disclosure further provide a test method, which is applied to a test circuit as provided in any of the above embodiments. The test method includes: providing a CTLE circuit, wherein the CTLE circuit is used to perform CTLE processing on a received signal, and the CTLE circuit has different gears; the test circuit receives a first signal processed by the CTLE at different gears and obtains the comparison result signal at the corresponding gear; and based on the voltage change trend of the comparison result signal at the different gears, obtains whether the CTLE processing is effective.

[0014] In some embodiments, the obtaining of whether the CTLE processing is effective based on the voltage change trend of the comparison result signal under different gears includes: obtaining whether the voltage of the comparison result signal gradually increases or decreases as the gear increases; if so, the CTLE processing is effective; if not, the CTLE processing is not effective.

[0015] In some embodiments, the different gears include an initial gear; the testing method further includes: adjusting parameters of the low-frequency filtering circuit so that the ratio of the difference between the power of the second signal and the power of the first signal at the initial gear to the power of the first signal is less than or equal to a preset ratio; using the low-frequency filtering circuit after parameter adjustment to receive the first signal processed by the CTLE of different gears.

[0016] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0017] In the technical solution of the test circuit provided in the embodiments of the present disclosure, to verify whether the CTLE function is effective, the first signal after CTLE processing is input into a low-frequency filter circuit, which can extract the low-frequency portion and output it as a second signal. The power comparison circuit outputs a first potential and a second potential representing the first power of the first signal and the second power of the second signal, and the first potential and the second potential are both DC potentials. The first potential and the second potential are input into a single-ended output circuit, which compares and amplifies the difference between the first potential and the second potential and outputs a comparison result signal. In this way, the test circuit can obtain comparison result signals at different gears, and the changing trends of the voltage values of the comparison result signals at different gears can be compared to determine whether the CTLE processing is effective, that is, whether the high-frequency compensation is effective. In this way, the test circuit provided in the embodiments of the present disclosure can determine whether the CTLE processing meets expectations without scanning the shmoo eye diagram, which is conducive to improving test efficiency and test accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A block diagram of a test circuit provided in an embodiment of the present disclosure;

[0020] Figure 2 A schematic diagram of a circuit structure of a low-frequency filter circuit provided in an embodiment of the present disclosure;

[0021] Figure 3 A schematic diagram of a circuit structure of a power comparison circuit provided in an embodiment of the present disclosure;

[0022] Figure 4 A schematic diagram of a circuit structure of a single-ended output circuit provided in an embodiment of the present disclosure;

[0023] Figure 5 Another circuit structure diagram of a single-ended output circuit provided in an embodiment of the present disclosure;

[0024] Figure 6 A schematic diagram of a flow chart of a testing method provided in an embodiment of the present disclosure;

[0025] Figure 7 A frequency characteristic diagram of a CTLE circuit provided in an embodiment of the present disclosure;

[0026] Figure 8 is a frequency characteristic diagram of the first signal after CTLE processing by the CTLE circuit;

[0027] Figure 9 The transient waveform diagrams of the first signal after being processed by the CTLE at different gears and the transient waveform diagram of the second signal generated by the test circuit;

[0028] Figure 10 A signal waveform diagram of a first potential and a second potential output by a power comparison circuit in a test circuit provided by an embodiment of the present disclosure;

[0029] Figure 11 This is a graph showing the changing trend of the comparison result signal output by the test circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] As can be seen from the background technology, the test efficiency and test accuracy of existing test methods need to be improved.

[0031] A commonly used test method currently is to perform CTLE processing of different gears on the received signal, scan the shmoo eye diagrams of the output signals after CTLE processing of different gears, compare the differences in the shapes of the eye diagrams, and perform analysis and reasoning based on the differences to evaluate whether the high-frequency compensation of the CTLE processing at each gear is effective. However, the characteristics of the eye diagram are affected by many factors, and it is difficult to directly test and evaluate the effect of CTLE processing, which affects the test efficiency and also causes the test accuracy to be improved. At least to solve or improve the above technical problems, the embodiment of the present disclosure provides a test circuit, which can verify whether different gears can show the expected improvement trend for high-frequency components, and at the same time can reduce the impact of the test circuit on the original frequency characteristics, reduce the design difficulty of the test circuit, and do not need to scan the shmoo eye diagram, thereby improving the test efficiency and test accuracy.

[0032] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to help readers better understand the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0033] In the description of the embodiments of the present disclosure, the technical terms "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present disclosure, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined. Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0034] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0035] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0036] In the description of the embodiments of the present disclosure, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings. They are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the embodiments of the present disclosure. For example, if the device or element in the figure is inverted, then the element described as being "below" or "below" or "below" or "bottom" of other elements or features will be oriented "above" or "top" of the other elements or features. Therefore, the term "below" can encompass both above and below orientations depending on the context in which the term is used, which will be apparent to those skilled in the art. The material can be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptors used herein can be interpreted accordingly.

[0037] In the accompanying drawings corresponding to the embodiments of the present disclosure, the thickness and area of each layer are exaggerated for better understanding and ease of description. In addition, when a component is described as being "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0038] In the description of the embodiments of the present disclosure, when a certain component "includes" another component, unless otherwise stated, other components are not excluded, and other components may be further included. A second component is formed or provided above or on the first component, or a second component is formed or provided on the surface of the first component, or a second component is formed or provided on one side of the first component. Embodiments in which the first component and the second component are in direct contact may be included, and embodiments in which additional components may be provided between the first component and the second component so that the first component and the second component may not be in direct contact may also be included. For the sake of simplicity and clarity, various components may be arbitrarily drawn in different proportions. In the accompanying drawings, some layers / components may be omitted for simplicity. Unless otherwise specified, a second component is formed or provided on the surface of the first component, which means that the first component is in direct contact with the second component. Among them, the above-mentioned "components" may refer to layers, films, regions, parts, structures, etc.

[0039] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0040] Figure 1 A block diagram of a test circuit provided in an embodiment of the present disclosure.

[0041] refer to Figure 1 The test circuit includes a low-frequency filter circuit 101, a power comparison circuit 102, and a single-ended output circuit 103. The low-frequency filter circuit 101 is configured to receive a first signal processed by CTLE, extract the low-frequency portion of the first signal, and output the low-frequency portion as a second signal. The power comparison circuit 102 is configured to receive the first signal and the second signal, compare the first power of the first signal with the second power of the second signal, and output a first potential and a second potential representing the first power and the second power, respectively. The single-ended output circuit 103 is configured to receive and compare the first potential and the second potential, and output a comparison result signal representing the difference between the first potential and the second potential.

[0042] In the above-mentioned test circuit, to verify whether the CTLE function is effective, the first signal after CTLE processing is input into the low-frequency filter circuit 101, which can extract the low-frequency portion and output it as the second signal. The power comparison circuit 102 outputs a first potential and a second potential representing the first power of the first signal and the second power of the second signal, and the first potential and the second potential are both DC potentials. The first potential and the second potential are sent to the single-ended output circuit 103, which compares and amplifies the difference between the first potential and the second potential and outputs a comparison result signal. In this way, the test circuit can obtain comparison result signals at different gears, and the changing trends of the voltage values of the comparison result signals at different gears can be compared to determine whether the CTLE processing is effective, that is, whether the high-frequency compensation is effective. In this way, the test circuit provided by the embodiment of the present disclosure does not need to scan the shmoo eye diagram.

[0043] The test circuit provided by the embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0044] The test circuit can be applied to a memory, which may be a dynamic random access memory (DRAM). The memory may also be a FeRAM (ferroelectric random access memory), a PCM (PCM-Phase Change Material) memory, or an MRAM (magnetic random access memory). The DRAM may be a DDR (Double Data Rate) memory or a LPDDR (Low Power Double Data Rate) memory.

[0045] The memory includes a CTLE circuit for performing CTLE processing on the signal. For example, after the signal passes through the CTLE circuit, the high-frequency components of the signal can be boosted as expected to compensate for channel attenuation during signal transmission. Furthermore, the CTLE circuit has different gears. At different gears, the CTLE circuit's ability to boost high-frequency components varies, resulting in different compensation effects through CTLE processing. For example, the higher the gear, the greater the CTLE circuit's ability to boost high-frequency components, and the better the compensation effect through CTLE processing.

[0046] The test circuit provided in the embodiments of the present disclosure can be applied to any semiconductor device provided with a CTLE circuit. The first signal and the second signal can both be differential signals. The first signal includes a first positive-phase signal and a first negative-phase signal, wherein the first positive-phase signal and the first negative-phase signal have opposite phases and equal amplitudes. The second signal includes a second positive-phase signal and a second negative-phase signal, wherein the second positive-phase signal and the second negative-phase signal have opposite phases and equal amplitudes.

[0047] The low-frequency filter circuit 101 is configured to cut off the high-frequency portion of the first signal and pass the low-frequency portion of the first signal.

[0048] The low-frequency filter circuit 101 can also be configured to amplify the low-frequency portion and output the amplified low-frequency portion as a second signal. For example, the test circuit is configured to receive a first signal output by the CTLE circuit after CTLE processing at an initial gear position. During the design phase, an ideal clock signal is input to the circuit's differential input. In this case, at the initial gear position, the parameters of the low-frequency filter circuit 101 are adjusted so that the low-frequency filter circuit 101 amplifies the low-frequency portion, and the ratio of the difference between the second power of the second signal and the first power of the first signal at the initial gear position to the power of the first signal is less than or equal to a preset ratio.

[0049] Parameter adjustment includes adjusting the parameters of at least one component in the low-frequency filter circuit 101. Accordingly, the low-frequency filter circuit 101 has the parameters after parameter adjustment. When the test circuit is used to receive the first signal output after CTLE at other gears of the CTLE circuit, the parameters of the low-frequency filter circuit 101 remain consistent with the parameters of the low-frequency filter circuit 101 at the initial gear.

[0050] The ratio of the difference between the second power of the second signal and the first power of the first signal at the above-mentioned initial gear position to the power of the first signal is less than or equal to a preset ratio. The advantages of such a setting include: at the initial gear position, the first power of the first signal and the second power of the second signal are close to each other, and the voltage of the comparison result signal is the preset voltage. In this way, the comparison result signals generated at different gear positions also fluctuate around the preset voltage. On the one hand, this helps to reduce the design difficulty of the power comparison circuit 102 and the single-ended output circuit 103. On the other hand, the voltage of the comparison result signals generated at different gear positions is within a controllable range. For example, the voltage of the comparison result signals at different gear positions has room to swing in the case of insufficient compensation after CTLE processing and corresponding over-compensation after CTLE processing.

[0051] The initial gear, also known as the default gear, refers to the gear with the weakest compensation effect on the CTLE process. In a specific example, the CTLE circuit may have eight gears, from the first gear to the eighth gear, with the first gear being the initial gear.

[0052] The preset ratio can be any value within the range of 0 to 10%, for example, 0.5%, 1%, 3%, 5%, 6%, or 9%. In the initial gear, the second power of the second signal generated by the low-frequency filter circuit 101 is the same as the first power of the first signal. The first signal can be considered as a full-frequency signal.

[0053] The low-frequency filter circuit 101 may also be configured such that the first signal and the second signal have the same common-mode voltage. In this way, when there is no input to the power comparison circuit 102, the common-mode voltage can be used to maintain the DC output value of the power comparison circuit 102 when there is no input.

[0054] In some embodiments, the low-frequency filter circuit 101 has the following transfer function:

[0055]

[0056] The above formula (1) describes the characteristics of a first-order low-pass filter, which is used to extract and amplify low-frequency signals. In this formula, A0 is the DC gain, i.e., the low-frequency gain, s is the complex frequency variable, and W is the cutoff angular frequency.

[0057] Compared with the passive RC network in the related art, the low-frequency filter circuit 101 provided by the embodiment of the present disclosure has less impact on the signal transmission characteristics, which is conducive to further improving the test accuracy.

[0058] Figure 2 A schematic diagram of a circuit structure of a low-frequency filter circuit provided in an embodiment of the present disclosure.

[0059] refer to Figure 2The low-frequency filter circuit 101 includes: a first PMOS transistor MP1 and a second PMOS transistor MP2, wherein the gates of the first PMOS transistor MP1 and the gates of the second PMOS transistor MP2 respectively receive differential signals of the first signal, and the first end of the first PMOS transistor MP1 and the first end of the second PMOS transistor MP2 are both connected to a working power supply VDD; a first resistor R1 and a second resistor R2, wherein the first resistor R1 is connected between the second end of the first PMOS transistor MP1 and a ground terminal (not labeled), and the second resistor R2 is connected between the second end of the second PMOS transistor MP2 and the ground terminal; a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 is connected between the second end of the first PMOS transistor MP1 and a first node (not labeled), and the second capacitor C2 is connected between the second end of the second PMOS transistor MP1 and a first node (not labeled). 2 and a second node (not labeled), the first node and the second node are used to output a second signal; a third resistor R3 and a fourth resistor R4, the third resistor R3 and the fourth resistor R4 are connected in series between the gate of the first PMOS transistor MP1 and the first node, and the fourth resistor R4 is directly coupled to the first node; a fifth resistor R5 and a sixth resistor R6, the fifth resistor R5 and the sixth resistor R6 are connected in series between the gate of the second PMOS transistor MP2 and the second node, and the sixth resistor R6 is directly coupled to the second node, wherein the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 are all directly coupled to a common-mode node (not labeled); a third capacitor C3 and a fourth capacitor C4, the third capacitor C3 is connected in parallel with the first resistor R1, and the fourth capacitor C4 is connected in parallel with the second resistor R2.

[0060] The gate of the first PMOS transistor MP1 is used to receive the first positive-phase signal inp_boost, and the gate of the second PMOS transistor MP2 is used to receive the first negative-phase signal inn_boost. The first node is used to output the second negative-phase signal inn_lp, the second node is used to output the second positive-phase signal inp_lp, and the common-mode node is used to output the common-mode voltage vcm. Both the first signal and the second signal have a common-mode voltage vcm.

[0061] The low-frequency filter circuit 101 may further include a zeroth PMOS transistor MP0. The zeroth PMOS transistor MP0 is connected between the operating power supply VDD and the first PMOS transistor MP1 and the second PMOS transistor MP2. The gate of the zeroth PMOS transistor MP0 is connected to a bias control signal bias. When the bias control signal bias is a high-level signal, the zeroth PMOS transistor MP0 is turned off. When the bias control signal bias is a low-level signal, the zeroth PMOS transistor MP0 is turned on.

[0062] It is understandable that in other embodiments, the first PMOS transistor and the second PMOS transistor may also be directly coupled to the working power supply.

[0063] In some examples, the third capacitor C3 and the fourth capacitor C4 are both variable capacitors, and the parameter adjustment described above may be adjusting the capacitance value of the third capacitor C3 and / or the fourth capacitor C4.

[0064] Figure 3 A schematic diagram of a circuit structure of the power comparison circuit 102 provided in an embodiment of the present disclosure.

[0065] refer to Figure 3 The power comparison circuit 102 includes: a first input pair of transistors, connected between the operating power supply VDD and a first potential node (unlabeled), for receiving a first signal, the first potential node being used to output a first potential boost; a second input pair of transistors, connected between the operating power supply VDD and a second potential node (unlabeled), for receiving a second signal, the second potential node being used to output a second potential lowpass; a third PMOS transistor M3, connected between the operating power supply VDD and the first potential node, for receiving a common-mode voltage vcm; a seventh resistor R7 and a fifth capacitor C5, connected in parallel between the first potential node and the ground terminal GND; an eighth resistor R8 and a sixth capacitor C6, connected in parallel between the second potential node and the ground terminal GND.

[0066] The first potential boost represents the power of the first signal, and the second potential lowpsss represents the power of the second signal.

[0067] The first input transistor pair includes a fourth PMOS transistor M4 and a fifth PMOS transistor M5. The gate of the fourth PMOS transistor M4 receives the first positive-phase signal inp_boost, and the gate of the fifth PMOS transistor M5 receives the first negative-phase signal inn_boost. The second input transistor pair includes a sixth PMOS transistor M2 and a seventh PMOS transistor M1. The gate of the sixth PMOS transistor M2 receives the second positive-phase signal inp_lp, and the gate of the seventh PMOS transistor M1 receives the second negative-phase signal inn_lp.

[0068] The current flowing through the second potential node is the first current I1, and the calculation formula of the first current I1 is as follows:

[0069]

[0070] Among them, V DMlp is the absolute value of the voltage difference between the second positive phase signal inp_lp and the second negative phase signal inn_lp, is the channel width-to-length ratio of the seventh PMOS transistor M1, is the channel width-to-length ratio of the sixth PMOS tube M2, V CM is the common mode voltage, μ is the carrier mobility, C is the capacitance per unit area of the oxide layer, V S is the source voltage, VTH is the threshold voltage.

[0071] The current flowing through the first potential node is the second current I2, and the calculation formula of the second current I2 is as follows:

[0072]

[0073] Among them, V DMap is the absolute value of the voltage difference between the first positive phase signal inp_boost and the first negative phase signal inn_boost, is the channel width-to-length ratio of the third PMOS tube M3, is the channel width-to-length ratio of the fourth PMOS transistor M4, is the channel width-to-length ratio of the fifth PMOS transistor M5.

[0074] The seventh resistor R7 and the eighth resistor R8 may have the same resistance value, which is r. The voltage difference between the first potential and the second potential output by the power comparison circuit 102 is as follows:

[0075] ΔV=(I2-I1)×r (4)

[0076] In some examples, the sum of the width-to-length ratios of the first input pair transistors and the width-to-length ratio of the third PMOS transistor M3 is equal to the sum of the width-to-length ratios of the second input pair transistors. are equal, then the value provided by the DC part in the first current I1 is equal to the value provided by the DC part in the second current I2, that is, and The voltage difference between the first potential and the second potential is:

[0077]

[0078] From the above formula, we can know that the differential mode voltage V DM (Including V DMlp and V DMap ), the channel width-to-length ratio of the third PMOS transistor M3, the channel width-to-length ratio of the fourth PMOS transistor M4, and the channel width-to-length ratio of the fifth PMOS transistor can be adjusted to adjust the multiple relationship between the first potential and the second potential.

[0079] refer to Figure 3 The power comparison circuit 102 may further include a switch tube MP3, which is connected between the working power supply VDD and the first input pair of tubes, between the working power supply VDD and the second input pair of tubes, and between the working power supply VDD and the third PMOS tube M3. The gate of the switch tube MP3 receives a bias control signal bias.

[0080] It is understandable that, in other embodiments, the first input pair transistors, the second input pair transistors, and the third PMOS transistor may also be directly coupled to the working power supply VDD.

[0081] Figure 4 A schematic diagram of a circuit structure of a single-ended output circuit provided in an embodiment of the present disclosure.

[0082] refer to Figure 4 The single-ended output circuit 103 includes: a comparator 113, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11. The ninth resistor R9 is connected between the first potential boost and the positive input terminal of the comparator 113, the tenth resistor R10 is connected between the second potential lowpass and the negative input terminal of the comparator 113, and the eleventh resistor R11 is connected between the negative input terminal and the output terminal of the comparator 113. The output terminal of the comparator 113 is used to output a comparison result signal OUT; the seventh capacitor C7 is connected between the output terminal of the comparator 113 and the ground terminal GND.

[0083] The resistance values of the ninth resistor R9 and the tenth resistor R10 can be the same, i.e., r1. The resistance value of the eleventh resistor R11 is r2. The voltage V OUT The calculation formula is as follows:

[0084]

[0085] It is understandable that in some cases, such as Figure 4 As shown, if the CTLE processing of the CTLE circuit is effective at each gear position, then as the gear position increases, the compensation capability of the CTLE processing increases, and the boost-lowpass difference between the first potential and the second potential should also gradually increase. Alternatively, in other examples, if the CTLE processing of the CTLE circuit is effective at each gear position, then as the gear position increases, the compensation capability of the CTLE processing increases, and the boost-lowpass difference between the first potential and the second potential should also gradually decrease.

[0086] Whether the boost-lowpass difference between the first potential and the second potential gradually increases or decreases is related to the phase relationship between the input nodes and output nodes in the low-frequency filter circuit 101, the power comparison circuit 102, and the single-ended output circuit 103. For example, in other embodiments, if the positive input terminal of the comparator receives the second potential and the negative input terminal of the comparator receives the first potential, and if the CTLE circuit performs CTLE processing at each gear, then the boost-lowpass difference between the first potential and the second potential gradually decreases as the gear increases.

[0087] Therefore, by comparing the voltage trends of the result signal OUT at different gear positions, we can determine whether the CTLE processing is effective at different gear positions. If the voltage trend increases or decreases as the gear position increases, it indicates that the CTLE processing is effective at all gear positions, that is, the CTLE compensation is in place as expected.

[0088] Figure 5 Another circuit structure diagram of a single-ended output circuit provided in an embodiment of the present disclosure.

[0089] refer to Figure 5 The single-ended output circuit 103 may further include: a twelfth resistor R12, the twelfth resistor R12 is connected between the positive input terminal of the comparator 113 and the reference voltage Vbase. Accordingly, the voltage V OUT The calculated value of is as follows:

[0090]

[0091] V base The difference between the first potential and the second potential is also superimposed on the reference voltage Vbase, so that the voltage of the comparison result signal OUT swings around the reference voltage, making it easier for the ATE (Automatic Test Equipment) machine to obtain the comparison result signal OUT.

[0092] The present disclosure also provides a test method that can be applied to the test circuit provided in the above embodiment. The test method will be described in detail below. It should be noted that the description in the above test circuit embodiment is also applicable to the embodiment of the test method below, and the description in the following test method embodiment is also applicable to the above test circuit. To avoid redundancy, the parts that are the same or corresponding to the above embodiment will not be described in detail below. For details, please refer to the detailed description of the above embodiment.

[0093] Figure 6 A flowchart of a testing method provided in an embodiment of the present disclosure.

[0094] refer to Figure 6 , the test methods include:

[0095] Step S11: providing a CTLE circuit, where the CTLE circuit is used to perform CTLE processing on the received signal, and the CTLE circuit has different gears.

[0096] Figure 7 is a frequency characteristic diagram of the CTLE circuit provided in an embodiment of the present disclosure, Figure 8 is a frequency characteristic diagram of the first signal after CTLE processing by the CTLE circuit. Figure 7 and Figure 8 In the figure, the horizontal and vertical scales represent the frequency (Hz) and the vertical scale represents the gain (db).

[0097] Step S12: The test circuit receives the first signal processed by the CTLE at different gears, and obtains a comparison result signal at the corresponding gear.

[0098] The different gears include an initial gear; the testing method further includes: adjusting parameters of the low-frequency filter circuit so that the ratio of the difference between the power of the second signal and the power of the first signal at the initial gear to the power of the first signal is less than or equal to a preset ratio; using the low-frequency filter circuit after parameter adjustment to receive the first signal processed by the CTLE at different gears.

[0099] For the description of the initial gear position and parameter adjustment, please refer to the corresponding description in the aforementioned test circuit.

[0100] Figure 9 are transient waveform diagrams of the first signal processed by the CTLE at different gears and the transient waveform diagram of the second signal generated by the test circuit, wherein: Figure 9 Schematic diagram of the first positive phase signal inp_boost and the second positive phase signal inp_lp. Figure 9 The horizontal axis represents time (μs), and the vertical axis represents transient voltage (mV). On the horizontal axis, 1.4757u refers to 1.4757μs, 1.4758u refers to 1.4758μs, 1.4759u refers to 1.4759μs, and 1.476u refers to 1.476μs. On the vertical axis, 0.2 refers to 0.2mV, 250m refers to 250mV, 0.3 refers to 0.3mV, 350m refers to 350mV, 0.4 refers to 0.4mV, and so on. We will not list them one by one here.

[0101] also, Figure 9 Among the multiple first signals, the first signal with a larger amplitude corresponds to a larger CTLE processing gear, and the first signal with a smaller amplitude corresponds to a smaller CTLE processing gear. Figure 9 The larger the gear, the greater the amplitude of the second signal output by the low-frequency filter circuit of the first signal.

[0102] Figure 10 This diagram shows the signal waveforms of the first and second potentials output by the power comparison circuit in the test circuit provided by an embodiment of the present disclosure. Different colors represent different gears. As compensation time progresses, at the same gear, the first potential is greater than the second potential, and the boost-lowpass difference between the first and second potentials tends to remain constant. If CTLE compensation is in place at all gears, the boost-lowpass value should increase or decrease with increasing gears. Figure 10 In the figure, the horizontal axis represents time (s), and the vertical axis represents transient voltage (mV). On the horizontal axis, 600n refers to 600ns (nanoseconds), 800n refers to 800ns, 1u refers to 1μs, 1.2u refers to 1.2μs, 1.4u refers to 1.4μs, and 1.6u refers to 1.6μs. On the vertical axis, 240m refers to 240mV, 260m refers to 260mV, 280m refers to 280mV, 0.3 refers to 0.3mV, and so on. We will not list them one by one here.

[0103] Step S13: Based on the voltage variation trend of the comparison result signal at different gears, obtaining whether the CTLE process is effective.

[0104] In some embodiments, based on the voltage change trend of the comparison result signal under different gears, whether the CTLE processing is effective is obtained, including: obtaining whether the voltage of the comparison result signal gradually increases or decreases as the gear increases; if so, the CTLE processing is effective; if not, the CTLE processing is not effective.

[0105] Figure 11 This is a change trend diagram of the comparison result signal output by the test circuit provided in an embodiment of the present disclosure, that is, a voltage change trend diagram of the comparison result signal. Figure 11 The horizontal axis represents the gear position, and the vertical axis represents the difference (mV) between the first potential and the second potential.

[0106] The test circuit includes six gears, from 1st to 6th, for illustration. If the CTLE processing meets expectations at each gear, the difference value shows an increasing trend. Whether the difference value shows an increasing trend is used to determine whether the CTLE processing is effective. If the CTLE processing meets expectations at each gear, the CTLE processing is effective. If the CTLE processing does not meet expectations at at least one gear, the CTLE processing is ineffective.

[0107] In some examples, the test circuit can be applied to pre-simulation test and post-simulation test to obtain voltage variation trends of comparison result signals of pre-simulation test and post-simulation test, respectively.

[0108] It's understandable that pre-layout simulation and post-layout simulation are two key verification stages in chip design and testing. Pre-layout simulation is performed before the physical chip layout is completed. It primarily verifies the functional correctness and basic timing behavior of the circuit based on the logic design or RTL (Register Transfer Level) code. Post-layout simulation is performed after the physical chip layout is completed. It combines parasitic parameters extracted from the actual layout (such as SPEF files) to verify the functional and timing characteristics of the circuit after actual physical implementation.

[0109] The pre-simulation test can theoretically verify whether the CTLE process is effective. The post-simulation test can physically verify whether the CTLE process is effective.

[0110] The above test circuit and method extract the low-frequency portion of the first signal at each level as a second signal and compare the second signal with the first signal to verify whether the CTLE circuit exhibits the expected trend of enhancing high-frequency components at each level. This test method eliminates the need to scan a shmoo eye diagram, making it more efficient and less susceptible to factors than an eye diagram. Even for test circuits that cannot scan an eye diagram to obtain results, the voltage value of the comparison result signal can be read, improving test efficiency while also enhancing test accuracy and verification completeness.

[0111] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A test circuit for CTLE function verification, characterized in that: include: a low-frequency filtering circuit configured to receive the first signal processed by the CTLE, extract a low-frequency portion of the first signal, and output the low-frequency portion as a second signal; a power comparison circuit configured to receive the first signal and the second signal, compare a first power of the first signal with a second power of the second signal, and output a first potential and a second potential representing the first power and the second power, respectively; The single-ended output circuit is configured to receive and compare the first potential and the second potential, and output a comparison result signal representing a difference between the first potential and the second potential.

2. The test circuit according to claim 1, wherein: The low-frequency filtering circuit is further configured to amplify the low-frequency portion; and / or the second signal and the first signal have the same common-mode voltage.

3. The test circuit according to claim 2, wherein: The first signal and the second signal are both differential signal pairs; the low-frequency filtering circuit includes: a first PMOS transistor and a second PMOS transistor, wherein a gate of the first PMOS transistor and a gate of the second PMOS transistor respectively receive differential signals of the first signal, and a first end of the first PMOS transistor and a first end of the second PMOS transistor are both connected to a working power supply; a first resistor and a second resistor, wherein the first resistor is connected between the second end of the first PMOS transistor and a ground terminal, and the second resistor is connected between the second end of the second PMOS transistor and the ground terminal; a first capacitor and a second capacitor, wherein the first capacitor is connected between the second end of the first PMOS transistor and a first node, and the second capacitor is connected between the second end of the second PMOS transistor and a second node, and the first node and the second node are used to output the second signal; a third resistor and a fourth resistor, wherein the third resistor and the fourth resistor are connected in series between the gate of the first PMOS transistor and the first node, and the fourth resistor is directly coupled to the first node; a fifth resistor and a sixth resistor, wherein the fifth resistor and the sixth resistor are connected in series between the gate of the second PMOS transistor and the second node, and the sixth resistor is directly coupled to the second node, wherein the third resistor, the fourth resistor, the fifth resistor, and the sixth resistor are all directly coupled to a common-mode node; a third capacitor and a fourth capacitor, wherein the third capacitor is connected in parallel with the first resistor, and the fourth capacitor is connected in parallel with the second resistor.

4. The test circuit according to claim 2, wherein: The power comparison circuit comprises: A first input pair of transistors is connected between the working power supply and a first potential node, and is used to receive the first signal. The first potential node is used to output a first potential. A second input pair of transistors is connected between the working power supply and a second potential node, and is used to receive the second signal. The second potential node is used to output a second potential. A third PMOS transistor is connected between the working power supply and the first potential node, and is used to receive the common mode voltage. a seventh resistor and a fifth capacitor connected in parallel between the first potential node and the ground terminal; An eighth resistor and a sixth capacitor are connected in parallel between the second potential node and the ground terminal.

5. The test circuit according to claim 4, characterized in that: The sum of the width-to-length ratios of the first input pair of transistors and the width-to-length ratio of the third PMOS transistor is equal to the sum of the width-to-length ratios of the second input pair of transistors.

6. The test circuit according to claim 1, wherein: The single-ended output circuit comprises: a comparator, a ninth resistor, a tenth resistor, and an eleventh resistor, wherein the ninth resistor is connected between the first potential and the positive input terminal of the comparator, the tenth resistor is connected between the second potential and the negative input terminal of the comparator, and the eleventh resistor is connected between the negative input terminal and the output terminal of the comparator, and the output terminal of the comparator is used to output the comparison result signal; The seventh capacitor is connected between the output terminal of the comparator and the ground terminal.

7. The test circuit according to claim 6, characterized in that: The single-ended output circuit further includes: A twelfth resistor is connected between the positive input terminal of the comparator and a reference voltage.

8. A testing method, applied to the test circuit according to any one of claims 1 to 7, characterized in that: include: Providing a CTLE circuit, the CTLE circuit is used to perform CTLE processing on the received signal, and the CTLE circuit has different gears; The test circuit receives the first signal processed by the CTLE at different gears, and obtains the comparison result signal at the corresponding gear; Whether the CTLE processing is effective is obtained based on the voltage change trend of the comparison result signal at different gears.

9. The testing method according to claim 8, characterized in that: The obtaining whether the CTLE processing is effective based on the voltage change trend of the comparison result signal at different gears includes: Obtaining whether the voltage of the comparison result signal gradually increases or decreases as the gear position increases; If yes, the CTLE process takes effect; If not, the CTLE process is not effective.

10. The testing method according to claim 8, characterized in that: The different gears include an initial gear; and the testing method further includes: Adjusting parameters of the low-frequency filter circuit so that a ratio of a difference between the power of the second signal and the power of the first signal at an initial gear position to the power of the first signal is less than or equal to a preset ratio; The low-frequency filter circuit after parameter adjustment is used to receive the first signal processed by the CTLE at different gears.

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