Ferroelectric capacitor, manufacturing method thereof and ferroelectric random access memory

Abstract

The invention provides a ferroelectric capacitor, a manufacturing method thereof and a ferroelectric random access memory. The ferroelectric capacitor comprises a substrate, a bottom electrode, a bottom insertion layer, a ferroelectric film layer and a top electrode which are sequentially arranged from bottom to top, the bottom insertion layer includes a niobium oxide layer, a tantalum oxide layer, or a stack of a niobium oxide layer and a tantalum oxide layer. By adding the bottom insertion layer made of niobium oxide or tantalum oxide materials, interface asymmetry is introduced, local enrichment of oxygen vacancies is caused, domain wall pinning sites are further formed, an internal bias field is caused, and therefore a large capacitance storage window is achieved, non-destructive reading can be conducted, decoupling of read-write durability is achieved, and the read-write performance is improved. And the device has low leakage current and high durability, and the problem of how to improve the device performance of the ferroelectric random access memory is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a ferroelectric capacitor and a manufacturing method thereof, and a ferroelectric random access memory. Background Art

[0002] Ferroelectric capacitors have a wide range of applications in various fields, including ferroelectric random access memory (FeRAM), sensors, and ferroelectric field-effect transistors (FeFETs). Ferroelectric capacitors primarily utilize the spontaneous polarization properties of ferroelectric materials, which can be reversed when an electric field is applied. This dynamic behavior allows ferroelectric materials to store and retain information in the polarization, or arrangement, of their dipoles.

[0003] FeRAM is a non-volatile memory that maintains data after power failure and has fast read and write speeds, making it suitable for applications requiring fast access and long-term data storage, such as personal computers, small devices, and security systems. However, FeRAM has a destructive read mechanism, and its durability is limited by the number of writes, which in turn affects the device's operating energy consumption and durability, limiting its widespread application.

[0004] To improve FeRAM device performance, it is necessary to decouple read and write endurance to enable non-destructive reading. While methods such as read voltage optimization, high-temperature baking, and electrode engineering to achieve a certain degree of decoupling between the dielectric constant storage window and the charge storage window can achieve this, they currently fall short of the requirements of target applications. Optimizing the read voltage can increase the storage window but increases device power consumption; high-temperature baking can enhance the imprinting effect but also increases leakage current and reduces endurance; electrode engineering is a more commonly used approach, but its effectiveness is limited and may be accompanied by a decrease in ferroelectric properties. Summary of the Invention

[0005] The object of the present invention is to provide a ferroelectric capacitor and a manufacturing method thereof, and a ferroelectric random access memory, so as to solve the problem of how to improve the device performance of the ferroelectric random access memory.

[0006] To solve the above technical problems, the present invention provides a ferroelectric capacitor, comprising a substrate, a bottom electrode, a bottom insertion layer, a ferroelectric thin film layer and a top electrode arranged in sequence from bottom to top; the bottom insertion layer comprises a niobium oxide layer, a tantalum oxide layer, or a stack of a niobium oxide layer and a tantalum oxide layer.

[0007] Optionally, in the ferroelectric capacitor, the substrate is a high-resistance silicon substrate.

[0008] Optionally, in the ferroelectric capacitor, the material of the bottom electrode is at least one of TiN, Ru, Pt, W or Mo; the material of the top electrode is at least one of TiN, Ru, Pt, W or Mo.

[0009] Optionally, in the ferroelectric capacitor, the material of the bottom electrode is the same as the material of the top electrode.

[0010] Optionally, in the ferroelectric capacitor, the thickness of the bottom electrode is 50-70 nm; the thickness of the top electrode is 50-70 nm.

[0011] Optionally, in the ferroelectric capacitor, the thickness of the bottom insertion layer is 1-2 nm.

[0012] Optionally, in the ferroelectric capacitor, the thickness of the ferroelectric thin film layer is 8-10 nm.

[0013] To solve the above technical problems, the present invention further provides a method for manufacturing a ferroelectric capacitor, for manufacturing the ferroelectric capacitor as described in any one of the above items, the manufacturing method comprising: providing a substrate; forming a bottom electrode on the substrate; forming a bottom insertion layer on the bottom electrode; forming a ferroelectric thin film layer on the bottom insertion layer; A top electrode is formed on the ferroelectric thin film layer.

[0014] Optionally, in the method for manufacturing the ferroelectric capacitor, the method for forming the bottom electrode on the substrate includes: Using magnetron sputtering technology, a 50~70nm thick metal is deposited on the substrate to form a bottom electrode.

[0015] Optionally, in the method for manufacturing the ferroelectric capacitor, the method for forming the bottom insertion layer on the bottom electrode includes: Atomic layer deposition (ALD) is used to deposit a 1-2 nm thick niobium oxide layer, a tantalum oxide layer, or a stack of niobium oxide and tantalum oxide layers on the bottom electrode to form a bottom insertion layer.

[0016] Optionally, in the method for manufacturing the ferroelectric capacitor, the method for forming the ferroelectric thin film layer on the bottom insertion layer includes: Using atomic layer deposition technology, 8~10nm of ferroelectric material is deposited on the bottom insertion layer to form a ferroelectric thin film layer.

[0017] Optionally, in the method for manufacturing the ferroelectric capacitor, the method for forming the top electrode on the ferroelectric thin film layer includes: Using magnetron sputtering technology, a 50-70 nm thick metal is deposited on the ferroelectric thin film layer to form a top electrode.

[0018] Optionally, in the manufacturing method of the ferroelectric capacitor, after forming the top electrode, the manufacturing method further includes: Patterning the top electrode.

[0019] Optionally, in the manufacturing method of the ferroelectric capacitor, after forming the top electrode, the manufacturing method further includes: The device is processed using a rapid thermal annealing process.

[0020] In order to solve the above technical problems, the present invention further provides a ferroelectric random access memory, comprising the ferroelectric capacitor as described in any one of the above items.

[0021] The present invention provides a ferroelectric capacitor, a manufacturing method thereof, and a ferroelectric random access memory, comprising a substrate, a bottom electrode, a bottom insertion layer, a ferroelectric thin film layer, and a top electrode, arranged sequentially from bottom to top; the bottom insertion layer comprises a niobium oxide layer, a tantalum oxide layer, or a stack of niobium oxide and tantalum oxide layers. By adding a bottom insertion layer of niobium oxide or tantalum oxide material, interface asymmetry is introduced, resulting in localized enrichment of oxygen vacancies, which in turn forms domain wall pinning sites and induces an internal bias field. This results in a larger capacitance storage window, enabling non-destructive reading and decoupling of read and write endurance. Furthermore, the device exhibits low leakage current and high endurance, addressing the problem of improving the device performance of ferroelectric random access memories. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic structural diagram of a ferroelectric capacitor provided in this embodiment; Figure 2 A flow chart of a method for manufacturing a ferroelectric capacitor provided in this embodiment; 3(A) to 3(F) are schematic structural diagrams of the ferroelectric capacitor provided in this embodiment at various steps; Figure 4 A characteristic result diagram of the ferroelectric capacitor provided in this embodiment obtained by characterizing it using glow discharge emission spectroscopy; Figure 5 A comparison diagram of the voltage and polarization intensity of the ferroelectric capacitor provided in this embodiment and the ferroelectric capacitor of the comparative example; Figure 6 A comparison diagram of the voltage and relative dielectric constant of the ferroelectric capacitor provided in this embodiment and the ferroelectric capacitor of a comparative example; Figure 7 A comparison chart of the number of write cycles and relative dielectric constant of the ferroelectric capacitor provided in this embodiment; Figure 8A graph showing test results of the read cycle count and charge storage window of the ferroelectric capacitor provided in this embodiment; The descriptions of the reference numerals are as follows: 100 - substrate; 200 - bottom electrode; 300 - bottom insertion layer; 400 - ferroelectric thin film layer; 500 - top electrode; 510 - patterned top electrode. DETAILED DESCRIPTION

[0023] The ferroelectric capacitor, its manufacturing method, and ferroelectric random access memory proposed in the present invention are further described in detail below, with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all simplified and not precisely scaled, and are used solely to facilitate and clearly illustrate the purpose of the embodiments of the present invention. Furthermore, the structures shown in the drawings are often portions of the actual structures. In particular, different drawings may require different emphasis and may use different scales.

[0024] It should be noted that the terms "first", "second", etc. in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, and are not used to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or are inherent to these processes, methods, products, or apparatuses.

[0025] Research has found that pentavalent oxides such as niobium oxide (Nb2O5) and tantalum oxide (Ta2O5) have lower oxygen vacancy formation energies than tetravalent oxides such as hafnium oxide (HfO2) and zirconium oxide (ZrO2). These pentavalent oxides are more likely to generate oxygen vacancies in the same oxygen environment, forming a fixed charge layer. This fixed charge layer induces an internal bias field, causing a shift in the electrochemical CV curve and creating a dielectric constant storage window. This provides a simple and effective approach to achieving non-destructive readout.

[0026] Based on this, this embodiment provides a ferroelectric capacitor, such as Figure 1 As shown, it includes a substrate 100, a bottom electrode 200, a bottom insertion layer 300, a ferroelectric thin film layer 400 and a top electrode 500 arranged in sequence from bottom to top; the bottom insertion layer 300 includes a niobium oxide layer, a tantalum oxide layer, or a stack of a niobium oxide layer and a tantalum oxide layer.

[0027] The ferroelectric capacitor provided in this embodiment introduces interface asymmetry by adding a bottom insertion layer 300 of niobium oxide or tantalum oxide material, resulting in local enrichment of oxygen vacancies, thereby forming domain wall pinning sites, causing an internal bias field, and thus having a large capacitance storage window, enabling non-destructive reading, and achieving decoupling of read and write endurance. The device has low leakage current and high durability, solving the problem of how to improve the device performance of ferroelectric random access memory.

[0028] Specifically, in this embodiment, the substrate 100 is a high-resistance silicon substrate.

[0029] Furthermore, in this embodiment, the bottom electrode 200 and the top electrode 500 are made of electrically conductive metallic materials, such as TiN, Ru, Pt, W, or Mo. The materials used for the bottom electrode 200 and the top electrode 500 can be the same or different.

[0030] In practical applications, the bottom electrode 200 and the top electrode 500 can be a single-layer structure or a multi-layer stacked structure, and the material selected for each layer should also be a metallic material. The structures of the bottom electrode 200 and the top electrode 500 can be the same or different.

[0031] In this embodiment, the thickness of the bottom electrode 200 is controlled to be 50-70 nm; the thickness of the top electrode 500 is controlled to be 50-70 nm. The thicknesses of the bottom electrode 200 and the top electrode 500 can be the same or different.

[0032] Preferably, in order to reduce process complexity, in this embodiment, the bottom electrode 200 and the top electrode 500 have the same material, structure, and thickness.

[0033] Furthermore, in this embodiment, the thickness of the bottom insertion layer 300 is controlled to be 1-2 nm.

[0034] Furthermore, in this embodiment, the ferroelectric thin film layer 400 is made of a ferroelectric material, for example, a hafnium-based ferroelectric thin film (HZO), and the thickness of the ferroelectric thin film layer 400 is controlled to be 8-10 nm.

[0035] The ferroelectric capacitor provided in this embodiment adds a bottom insertion layer 300 of niobium oxide or tantalum oxide material between the bottom electrode 200 and the ferroelectric thin film layer 400, so that the lower oxygen vacancy formation in the bottom insertion layer 300 causes the oxygen vacancies in the ferroelectric thin film layer 400 to migrate and accumulate in the bottom insertion layer 300, forming domain wall pinning, thereby generating an internal bias field; the internal bias causes the CV curve to shift and form a storage window at 0V. At the same time, the larger residual polarization value and smaller coercive electric field value help to increase the dielectric constant peak, thereby generating a larger storage window under the same internal bias field. Under the coordinated effect of these two factors, the ferroelectric capacitor provided in this embodiment achieves a larger storage window at a lower read voltage, realizes the decoupling of read and write endurance, and has low leakage current and high durability.

[0036] This embodiment also provides a method for manufacturing a ferroelectric capacitor, which is used to manufacture the ferroelectric capacitor as described above. Figure 2 As shown, the manufacturing method includes: S1, providing a substrate; S2, forming a bottom electrode on the substrate; S3, forming a bottom insertion layer on the bottom electrode; S4, forming a ferroelectric thin film layer on the bottom insertion layer; S5, forming a top electrode on the ferroelectric thin film layer.

[0037] The manufacturing method of the ferroelectric capacitor provided in this embodiment introduces interface asymmetry by adding a bottom insertion layer of niobium oxide or tantalum oxide material, resulting in local enrichment of oxygen vacancies, thereby forming domain wall pinning sites, causing an internal bias field, thereby having a large capacitance storage window, enabling non-destructive reading, and achieving decoupling of read and write endurance. The device has low leakage current and high durability, solving the problem of how to improve the device performance of ferroelectric random access memory.

[0038] Specifically, in this embodiment, in step S1 , as shown in FIG3(A) , a substrate 100 is provided.

[0039] In practical applications, the substrate 100 may be a high-resistance silicon substrate.

[0040] In other embodiments, the substrate 100 may be other types of substrates. In addition, an insulating layer may be formed on the surface of the substrate 100 .

[0041] Furthermore, in this embodiment, in step S2 , as shown in FIG. 3 (B) , a bottom electrode 200 is formed on the substrate 100 .

[0042] Specifically, a magnetron sputtering technique may be used to deposit a 50-70 nm thick metal, such as tungsten W, on the substrate 100 to form the bottom electrode 200. During the deposition and growth process, the Ar gas flow rate is 50 sccm and the sputtering power is 150 W.

[0043] Furthermore, in this embodiment, in step S3 , as shown in FIG. 3 (C ), a bottom insertion layer 300 is formed on the bottom electrode 200 .

[0044] Specifically, an atomic layer deposition (ALD) technique may be used to deposit a 1-2 nm thick niobium oxide layer, a tantalum oxide layer, or a stack of a niobium oxide layer and a tantalum oxide layer on the bottom electrode 200 to form the bottom insertion layer 300 .

[0045] In a specific embodiment, plasma enhanced atomic layer deposition (PEALD) is used to grow the bottom insertion layer 300 with a thickness of 1-2 nm. The growth process temperature is 270-290°C, and a single cycle of niobium oxide / tantalum oxide growth process is deposited, including 2s of niobium ethoxide (Nb2(OC2H5) 10 ) / Tantalum ethoxide (Ta2(OC2H5) 10 ) pulse, 3s N2 purge, 6s oxygen plasma pulse, 6s N2 purge.

[0046] Furthermore, in this embodiment, in step S4 , as shown in FIG. 3 (D ), a ferroelectric thin film layer 400 is formed on the bottom insertion layer 300 .

[0047] Specifically, the atomic layer deposition (ALD) technology may be used to deposit 8-10 nm of ferroelectric material on the bottom insertion layer 300 to form the ferroelectric thin film layer 400 .

[0048] In one specific embodiment, plasma-enhanced atomic layer deposition (PEALD) is used to grow an 8-10 nm thick HZO ferroelectric thin film 400. The growth process temperature is 270-290°C, and a single cycle of hafnium oxide growth includes a 0.5-second tetrakis(dimethylamino)hafnium (TDMAHf) pulse, a 6-second N2 purge, a 3-second oxygen plasma pulse, and a 2-second N2 purge. A single cycle of zirconium oxide growth includes a 0.5-second tetrakis(dimethylamino)zirconium (TDMAZr) pulse, a 6-second N2 purge, a 3-second oxygen plasma pulse, and a 2-second N2 purge.

[0049] Furthermore, in this embodiment, in step S5 , as shown in FIG. 3 (E) , a top electrode 500 is formed on the ferroelectric thin film layer 400 .

[0050] Specifically, similar to the process for forming the bottom electrode 200, a 50-70 nm thick metal, such as tungsten W, can be deposited on the ferroelectric thin film layer 400 using magnetron sputtering technology to form the top electrode 500. During the deposition and growth process, the Ar gas flow rate is 50 sccm and the sputtering power is 150 W.

[0051] Preferably, in this embodiment, the manufacturing method further includes: S6, patterned top electrode.

[0052] In this embodiment, the top electrode 500 can be patterned using a photolithography process. Specifically, ultraviolet lithography is used to define the electrode region of the device, and a dry etching process is used to etch the top electrode 500 of the device. The etching gases are SF6 and O2, the etching pressure is 3 Pa, the etching power is 50 W, and the etching time is 90 seconds. The photoresist is removed after etching: First, the device is immersed in acetone and allowed to stand until the top electrode structure is clear. Then, the device is immersed in isopropyl alcohol to remove residual acetone and other organic matter on the surface of the device. Finally, it is rinsed with deionized water and blown dry with nitrogen.

[0053] The device structure after patterning is shown in FIG. 3(F) , wherein the top electrode 500 is formed into a patterned top electrode 510 .

[0054] And, in this embodiment, the manufacturing method further includes: S7, treating the device using a rapid thermal annealing process.

[0055] Specifically, in this embodiment, rapid thermal annealing is performed in a nitrogen atmosphere at a heating rate of 15-20°C / s, an annealing temperature of 400-600°C, and an annealing time of 30-60 seconds. Rapid thermal annealing can eliminate device defects, activate donor and acceptor impurities, restore the crystal structure, and improve the device's electrical performance.

[0056] The method for manufacturing a ferroelectric capacitor provided in this embodiment utilizes atomic layer deposition technology to construct a high-dielectric-constant hafnium oxide-based ferroelectric thin film, facilitating the large-scale production of wafer-level memory devices. The entire manufacturing process of the ferroelectric capacitor provided in this embodiment is fully compatible with complementary metal oxide (CMOS) semiconductor processes. The ferroelectric capacitor produced by the manufacturing method provided in this embodiment has a simple device structure, a large memory window at a relatively low operating voltage, decoupling read and write endurance, and exhibits low leakage current and high endurance.

[0057] The device performance of the ferroelectric capacitor provided by the present application is described below with reference to a number of embodiments.

[0058] [Example 1] First, metal W is grown on the substrate using magnetron sputtering to form the bottom electrode. Then, a 2nm-thick Nb2O5 bottom insertion layer (denoted as Nb2O5-2nm) is grown using plasma-enhanced atomic layer deposition. Next, a HZO ferroelectric thin film is grown using plasma-enhanced atomic layer deposition. Finally, metal W is grown on the ferroelectric thin film using magnetron sputtering to form the top electrode, which is then patterned. Finally, the device undergoes rapid thermal annealing to obtain the final ferroelectric capacitor.

[0059] The bottom insertion layer of the ferroelectric capacitor provided in this embodiment was characterized by glow discharge emission spectroscopy, and the results are as follows: Figure 4 The results show that the thickness of the bottom insertion layer is 2nm, which meets the design requirements.

[0060] [Example 2] The difference from Example 1 is that in Example 2, a 1.5 nm thick bottom insertion layer of Nb2O5 material (denoted as Nb2O5-1.5 nm) is grown using plasma enhanced atomic layer deposition technology. The rest remains the same as Example 1.

[0061] [Example 3] The difference from Example 1 is that in Example 3, a bottom insertion layer of Nb2O5 material with a thickness of 1 nm (denoted as Nb2O5-1 nm) is grown using plasma enhanced atomic layer deposition technology. The rest remains the same as Example 1.

[0062] [Comparative Example] In the comparative example, the bottom insertion layer is not grown, that is, the manufacturing process steps of the bottom insertion layer are omitted, and the obtained device structure is substrate, bottom electrode, ferroelectric thin film layer and top electrode from bottom to top. The rest remains the same as in Example 1.

[0063] The ferroelectric capacitors obtained in Examples 1 to 3 and the ferroelectric capacitors obtained in the comparative example were tested under the test conditions of ±3V and 1kHz. The test results are shown in FIG. Figures 5 to 8 shown.

[0064] like Figure 5 As shown, compared with the control example without the Nb2O5 bottom insertion layer, the ferroelectric capacitor with the Nb2O5 bottom insertion layer has a significantly rightward shift in the polarization-voltage curve, a significant reduction in the coercive field, and no significant change in the remanent polarization value. The rightward shift in the polarization-voltage curve increases with the thickness of the Nb2O5 bottom insertion layer.

[0065] like Figure 6As shown, compared with the control without Nb2O5 bottom insertion layer, the ferroelectric capacitor with Nb2O5 bottom insertion layer has a significantly right-shifted dielectric constant-voltage curve (Vcross is greater than 0) and a large dielectric constant storage window CMW at 0 V ( ~ ), where the dielectric constant memory window (CMW) reaches as high as 12.3 when the thickness of the Nb2O5 bottom insertion layer is 2nm. Furthermore, the rightward shift of the dielectric constant-voltage curve (Vcross and CMW) increases with the thickness of the Nb2O5 bottom insertion layer.

[0066] like Figure 7 As shown, the ferroelectric capacitor with Nb2O5 bottom insertion layer provided by this embodiment has a write endurance, that is, a minimum number of write cycles of about 2×10 6 times. Figure 8 As shown, read endurance, that is, the number of read cycles reaches 10 11 At the same time, as the number of reads increases, the charge storage window decreases by only 4.6% at most, achieving decoupling of read and write endurance.

[0067] The above results and data show that the ferroelectric capacitor with a Nb2O5 bottom insertion layer provided in this embodiment can perform non-destructive reading and achieve decoupling of read and write endurance. The device has a simple structure, no wake-up effect, low leakage current and high durability, and solves the problem of how to improve the device performance of ferroelectric random access memory.

[0068] Furthermore, this embodiment further provides a ferroelectric random access memory (FeRAM), comprising the ferroelectric capacitor described above.

[0069] In practical applications, those skilled in the art can obtain the method and structure of the ferroelectric random access memory FeRAM of the present application by using the existing method of obtaining ferroelectric random access memory using ferroelectric capacitors, and this application will not elaborate on this.

[0070] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0071] The ferroelectric capacitor and its manufacturing method, as well as the ferroelectric random access memory provided in this embodiment, include a substrate, a bottom electrode, a bottom insertion layer, a ferroelectric thin film layer, and a top electrode, arranged sequentially from bottom to top; the bottom insertion layer comprises a niobium oxide layer, a tantalum oxide layer, or a stack of niobium oxide and tantalum oxide layers. By adding a bottom insertion layer of niobium oxide or tantalum oxide, interface asymmetry is introduced, resulting in localized enrichment of oxygen vacancies, which in turn forms domain wall pinning sites and induces an internal bias field. This results in a larger capacitance storage window, enabling non-destructive reading and decoupling of read and write endurance. Furthermore, the device exhibits low leakage current and high endurance, addressing the issue of improving the device performance of ferroelectric random access memories.

[0072] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A ferroelectric capacitor, characterized in that: The invention comprises a substrate, a bottom electrode, a bottom insertion layer, a ferroelectric film layer and a top electrode arranged in sequence from bottom to top; the bottom insertion layer comprises a niobium oxide layer, a tantalum oxide layer, or a stack of a niobium oxide layer and a tantalum oxide layer.

2. The ferroelectric capacitor according to claim 1, wherein The substrate is a high-resistance silicon substrate.

3. The ferroelectric capacitor according to claim 1, wherein The material of the bottom electrode is at least one of TiN, Ru, Pt, W or Mo; the material of the top electrode is at least one of TiN, Ru, Pt, W or Mo.

4. The ferroelectric capacitor according to claim 1, wherein The material of the bottom electrode is the same as that of the top electrode.

5. The ferroelectric capacitor according to claim 1, wherein The thickness of the bottom electrode is 50-70 nm; the thickness of the top electrode is 50-70 nm.

6. The ferroelectric capacitor according to claim 1, wherein The thickness of the bottom insertion layer is 1-2 nm.

7. The ferroelectric capacitor according to claim 1, wherein The thickness of the ferroelectric thin film layer is 8-10 nm.

8. A method for manufacturing a ferroelectric capacitor, for manufacturing the ferroelectric capacitor according to any one of claims 1 to 7, characterized in that: The manufacturing method comprises: providing a substrate; forming a bottom electrode on the substrate; forming a bottom insertion layer on the bottom electrode; forming a ferroelectric thin film layer on the bottom insertion layer; A top electrode is formed on the ferroelectric thin film layer.

9. The method for manufacturing a ferroelectric capacitor according to claim 8, wherein: The method for forming a bottom electrode on a substrate comprises: Using magnetron sputtering technology, a 50~70nm thick metal is deposited on the substrate to form a bottom electrode.

10. The method for manufacturing a ferroelectric capacitor according to claim 8, wherein: The method for forming a bottom insertion layer on a bottom electrode comprises: Atomic layer deposition (ALD) is used to deposit a 1-2 nm thick niobium oxide layer, a tantalum oxide layer, or a stack of niobium oxide and tantalum oxide layers on the bottom electrode to form a bottom insertion layer.

11. The method for manufacturing a ferroelectric capacitor according to claim 8, wherein: The method for forming a ferroelectric thin film layer on the bottom insertion layer comprises: Using atomic layer deposition technology, 8~10nm of ferroelectric material is deposited on the bottom insertion layer to form a ferroelectric thin film layer.

12. The method for manufacturing a ferroelectric capacitor according to claim 8, wherein: The method for forming a top electrode on a ferroelectric thin film layer comprises: Using magnetron sputtering technology, a 50-70 nm thick metal is deposited on the ferroelectric thin film layer to form a top electrode.

13. The method for manufacturing a ferroelectric capacitor according to claim 8, wherein: After forming the top electrode, the manufacturing method further includes: Patterning the top electrode.

14. The method for manufacturing a ferroelectric capacitor according to claim 8, wherein: After forming the top electrode, the manufacturing method further includes: The device is processed using a rapid thermal annealing process.

15. A ferroelectric random access memory, characterized in that: Comprising the ferroelectric capacitor according to any one of claims 1 to 7.

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