Solar cell and preparation method thereof

Abstract

The invention discloses a solar cell and a preparation method thereof, and relates to the field of photovoltaic technology. According to the preparation method of the solar cell, the energy of the laser irradiation area is controlled, so that when the first doped silicon layer and the first dielectric layer of the exposure area are etched subsequently, the edge etching depth of the exposure area is shallower, the middle etching depth of the exposure area is deeper, and the first groove can have an inclined side wall. When the second doped silicon layer is subsequently prepared, the second doped silicon layer is not deposited below the first doped silicon layer. And then the first doped silicon layer and the second doped silicon layer can be completely separated by manufacturing the second groove, so that minority carrier recombination and electric leakage channels caused by contact of the first doped silicon layer and the second doped silicon layer are reduced, and the performance of the solar cell is improved.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] Back-contact cells feature all electrode grid lines arranged on the back of the cell, with the PN junction and metal contacts located on the back of the cell in an interdigitated pattern. This reduces solar shading from the grid lines and improves cell conversion efficiency. TBC cells, also known as POLO-IBC cells, are a type of back-contact cell. They combine the tunnel oxide technology of TOPCon cells with the back-side electrode arrangement of IBC cells, significantly improving passivation and open-circuit voltage, resulting in higher photoelectric conversion efficiency.

[0003] The core of TBC cell fabrication lies in the preparation of the PN-poly doping structure. First, the p-type polysilicon doped region must be precisely patterned. Then, a portion of the p-type polysilicon layer is removed through chemical etching. The n-type polysilicon layer is then deposited, forming the interdigitated PN-poly doping structure. Excessive lateral etching during the removal of the p-type polysilicon layer can cause a portion of the subsequently deposited n-type polysilicon layer to overlap beneath the p-type polysilicon layer. This portion of the n-type polysilicon layer is difficult to remove and remains in the final product, leading to minority carrier recombination and leakage paths, thus affecting the performance of the solar cell. Summary of the Invention

[0004] The purpose of this application includes providing a solar cell and a preparation method thereof, which can reduce minority carrier recombination and leakage channels and improve the performance of the solar cell.

[0005] The embodiments of the present application can be implemented as follows: In a first aspect, the present application provides a method for preparing a solar cell, comprising: obtaining a silicon substrate having a front side and a back side opposite to each other; Prepare a first dielectric layer and a first doped silicon layer stacked in sequence on the back side of the silicon substrate; irradiating a local area of the first doped silicon layer with a laser, wherein the light energy per unit area at the edge of the exposure area is less than the light energy per unit area at the center of the exposure area; Etching the first doped silicon layer and the first dielectric layer in the exposed area using a wet etching process to obtain a first trench having an inclined sidewall, wherein the angle between the inclined sidewall and the bottom wall of the first trench is an obtuse angle; preparing a second dielectric layer and a second doped silicon layer stacked in sequence in the first trench to fill the first trench; removing a portion of the second dielectric layer and the second doped silicon layer adjacent to the inclined sidewall to form a second trench; A passivation layer is prepared on the front and back sides of the silicon substrate, and a first electrode connected to the first doped silicon layer and a second electrode connected to the second doped silicon layer are manufactured.

[0006] In an optional embodiment, the step of irradiating a local area of the first doped silicon layer with a laser includes: The light spot is used to scan along n scanning paths, where n≥2, the scanning path extends along a first direction, and the n scanning paths are arranged in a second direction, the first direction is perpendicular to the second direction, and two adjacent scanning paths partially overlap.

[0007] In an optional embodiment, the width W1 of the scanning path in the second direction and the width W2 of the overlapping area of two adjacent scanning paths in the second direction satisfy the relationship: W2=a×W1, where a ranges from 0.2 to 0.8.

[0008] In an optional embodiment, in the first scanning path and the nth scanning path in the second direction, the areas not covered by the adjacent scanning paths each account for 5% to 40% of the exposure area.

[0009] In an optional embodiment, the light spot is a rectangular light spot.

[0010] In an optional embodiment, the width of the light spot in the second direction is 100 μm to 400 μm.

[0011] In an optional embodiment, the step of irradiating a local area of the first doped silicon layer with a laser includes: Scanning is performed using a light spot along n scanning paths, where n ≥ 2, the scanning path extends along a first direction, the n scanning paths are spliced in a second direction, the first direction is perpendicular to the second direction, and the scanning speeds of the first scanning path and the nth scanning path in the second direction are greater than the scanning speeds of the second to n-1th scanning paths.

[0012] In an optional embodiment, the step of etching the first doped silicon layer and the first dielectric layer in the exposed area by using a wet etching process includes: soaking the exposed area with a first etching solution; Wash the exposed area with water; soaking the exposed area with a second etching solution; Wherein, the first etching solution and the second etching solution are both alkaline solutions, and the alkalinity of the first etching solution is stronger than that of the second etching solution.

[0013] In an optional embodiment, the exposure area is immersed in the first etching solution for 50 seconds to 200 seconds, and the exposure area is immersed in the second etching solution for 100 seconds to 400 seconds.

[0014] In an optional embodiment, the alkaline component in the first etching solution includes sodium hydroxide and / or potassium hydroxide, and the volume proportion of the alkaline component in the first etching solution is 5% to 10%; the alkaline component in the second etching solution includes sodium hydroxide and / or potassium hydroxide, and the volume proportion of the alkaline component in the second etching solution is 5% to 10%.

[0015] In an optional embodiment, the angle between the inclined side wall and the bottom wall of the first trench is 100° to 150°.

[0016] In an optional embodiment, the first doped silicon layer is p-type doped, and the second doped silicon layer is n-type doped.

[0017] In an optional embodiment, the material of the first dielectric layer and the second dielectric layer is silicon oxide.

[0018] In an optional embodiment, the step of preparing a passivation layer on the front and back sides of the silicon substrate comprises: depositing a first passivation layer on the front surface of the silicon substrate; A second passivation layer is deposited on the first doped silicon layer, the second doped silicon layer, and the bottom wall and the inclined sidewall of the second trench.

[0019] In an optional embodiment, the material of the passivation layer is selected from at least one of aluminum oxide, silicon oxide, silicon oxynitride and silicon nitride.

[0020] In a second aspect, the present application provides a solar cell, which is manufactured by the solar cell manufacturing method of any one of the aforementioned embodiments.

[0021] The solar cell and the method for manufacturing the same provided by the embodiments of the present application have the following beneficial effects: The method for preparing a solar cell provided in an embodiment of the present application includes: obtaining a silicon substrate having a front side and a back side; forming a first dielectric layer and a first doped silicon layer stacked in sequence on the back side of the silicon substrate; irradiating a local area of the first doped silicon layer with a laser, wherein the illumination energy per unit area at the edge of the exposed area is less than the illumination energy per unit area in the center of the exposed area; etching the first doped silicon layer and the first dielectric layer in the exposed area using a wet etching process to form a first trench having an inclined sidewall, wherein the angle between the inclined sidewall and the bottom wall of the first trench is an obtuse angle; forming a second dielectric layer and a second doped silicon layer stacked in sequence in the first trench to fill the first trench; removing a portion of the second dielectric layer and the second doped silicon layer in contact with the inclined sidewall to form a second trench; forming a passivation layer on the front side and the back side of the silicon substrate, and forming a first electrode connected to the first doped silicon layer and a second electrode connected to the second doped silicon layer. In the embodiment of the present application, by controlling the energy of the laser irradiation area, the illumination energy per unit area at the edge of the exposed area is less than the illumination energy per unit area in the center of the exposed area. Since higher light energy makes it easier to etch, when etching the first doped silicon layer and the first dielectric layer in the exposed area, the etching depth at the edge of the exposed area will be shallower and the etching depth in the middle will be deeper, so that the first trench can have inclined sidewalls and the opening width of the first trench is greater than the bottom width. When the second doped silicon layer is subsequently prepared, the second doped silicon layer will not be deposited below the first doped silicon layer. By making the second trench, the first doped silicon layer can be completely separated from the second doped silicon layer, thereby reducing the minority carrier recombination and leakage channel caused by the contact between the first doped silicon layer and the second doped silicon layer, and improving the performance of the solar cell.

[0022] The solar cell provided in the embodiment of the present application is manufactured by the above-mentioned manufacturing method and therefore has better photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 This is a flow chart of a method for preparing a solar cell in one embodiment of the present application; Figure 2 This is a schematic diagram of an embodiment of the present application after the first dielectric layer and the first doped silicon layer are prepared; Figure 3 A schematic diagram of each scanning path in an embodiment of the present application; Figure 4 A schematic diagram of various scanning paths in another embodiment of the present application; Figure 5 A schematic diagram of various scanning paths in another embodiment of the present application; Figure 6 This is a schematic diagram of an embodiment of the present application after etching to form a first trench; Figure 7 This is a scanning electron microscope (SEM) image of the second groove in one embodiment of the present application; Figure 8 This is a schematic diagram of an embodiment of the present application after the second dielectric layer and the second doped silicon layer are completed; Figure 9 This is a schematic diagram after the second groove is formed in one embodiment of the present application; Figure 10 This is a schematic diagram after the passivation layer and electrodes are manufactured in one embodiment of the present application.

[0025] Icon: 100 - silicon substrate; 110 - first dielectric layer; 120 - second dielectric layer; 200 - first doped silicon layer; 210 - first trench; 211 - inclined sidewall; 300 - second doped silicon layer; 310 - second trench; 400 - first passivation layer; 500 - second passivation layer; 610 - first electrode; 620 - second electrode. DETAILED DESCRIPTION

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0029] In the description of this application, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the invented product is usually placed when in use. It is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it cannot be understood as a limitation on this application.

[0030] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0031] It should be noted that, in the absence of conflict, the features in the embodiments of this application can be combined with each other.

[0032] In the related art, when manufacturing a TBC cell, a first doped silicon layer (such as a p-type polycrystalline silicon layer) is partially removed using wet etching. A second doped silicon layer (such as an n-type polycrystalline silicon layer) is then formed in the area where the first doped silicon layer was removed. A portion of the second doped silicon layer adjacent to the first doped silicon layer is then removed to form a trench separating the first and second doped silicon layers. However, due to the low precision of wet etching, the angle between the sidewalls and bottom of the trench formed when etching the first doped silicon layer is not perpendicular, but rather acute. This results in a portion of the subsequently formed second doped silicon layer being located at the angle between the sidewalls and bottom, that is, below the first doped silicon layer. When the portion of the second doped silicon layer adjacent to the first doped silicon layer is subsequently removed, the second doped silicon layer beneath the first doped silicon layer is likely to remain. This can lead to minority carrier recombination and leakage paths, affecting the performance of the solar cell. In addition, existing methods require a deeper chemical etching depth, usually more than 3μm, to achieve complete isolation of different doped silicon layers without residue risk, which results in the consumption of more chemicals and silicon substrate etching, which is not conducive to the thinning of silicon substrates and reducing production costs.

[0033] In order to improve at least one of the shortcomings of the above-mentioned related technologies, an embodiment of the present application provides a method for preparing a solar cell. By controlling the exposure, an inclined sidewall is formed when etching the first doped silicon layer, thereby preventing the subsequently prepared second doped silicon layer from being partially covered by the first doped silicon layer, thereby reducing the risk of the second doped silicon layer remaining under the first doped silicon layer, improving the problem of minority carrier recombination and leakage channel caused by the overlap of the first doped silicon layer and the second doped silicon layer, and improving the battery performance.

[0034] Figure 1 The flowchart of the method for preparing a solar cell in one embodiment of the present application is shown in FIG. The method for preparing a solar cell provided in the embodiment of the present application can be used to prepare a back contact cell, such as a TBC cell. Figure 1 As shown, taking the manufacture of TBC cells as an example, the method for manufacturing a solar cell provided in the embodiment of the present application includes the following steps: Step S100 , obtaining a silicon substrate 100 , wherein the silicon substrate 100 has a front side and a back side opposite to each other.

[0035] In this embodiment, the silicon substrate 100 can be made of high-purity single-crystal silicon. Single-crystal silicon has very high purity, which means that it contains very few impurities, which has obvious advantages in reducing carrier recombination and improving battery efficiency. In addition, the atomic arrangement of single-crystal silicon is regular and consistent, and the structure is uniform, which reduces the impact of defects such as grain boundaries on carrier transport. Optionally, the silicon substrate 100 uses n-type single-crystal silicon, which has a lower photo-induced degradation effect and a higher theoretical efficiency limit. In other embodiments, the silicon substrate 100 can also use p-type single-crystal silicon or other types of silicon. The type of silicon substrate 100 can be selected according to the specific battery design requirements.

[0036] In this embodiment, the silicon substrate 100 has opposite front and back sides, and the front and back sides of the silicon substrate 100 are spaced apart in the thickness direction of the silicon substrate 100. The front side of the silicon substrate 100 corresponds to the light-facing side of the solar cell, and the back side of the silicon substrate 100 corresponds to the light-receiving side of the solar cell.

[0037] Optionally, before preparing the first dielectric layer 110 and the first doped silicon layer 200, the back side of the silicon substrate 100 can be polished. After polishing, a square tower base structure can be formed on the back side of the silicon substrate 100. The multiple tower base structures can form a surface with a certain degree of undulation, increasing the bonding area between the subsequently grown film layer and the silicon substrate 100 and reducing the contact resistivity of the film layer structure. Polishing also facilitates subsequent micromachining steps, such as laser processing or chemical etching, to form precise electrode patterns. After polishing, defects on the surface of the silicon substrate 100 can be reduced, thereby improving the overall mechanical strength of the silicon substrate 100 and reducing the risk of cracks or breakage caused by stress concentration during the manufacturing process.

[0038] Optionally, the diagonal length of the square tower base structure is 18 μm to 40 μm.

[0039] In step S200 , a first dielectric layer 110 and a first doped silicon layer 200 are sequentially stacked on the back side of the silicon substrate 100 .

[0040] Figure 2 This is a schematic diagram of the first dielectric layer 110 and the first doped silicon layer 200 after they are prepared in one embodiment of the present application. Figure 2The front side of the silicon substrate 100 faces upward, and the back side faces downward. In this embodiment, a first dielectric layer 110 is first deposited on the back side of the silicon substrate 100. Optionally, the material of the first dielectric layer 110 is silicon oxide. Based on the quantum tunneling effect, the first dielectric layer 110 allows one type of carrier (typically minority carriers, such as holes in n-type silicon or electrons in p-type silicon) to pass through the first dielectric layer 110, while blocking another type of carrier. This selective transmission property helps reduce contact resistance and improve current collection efficiency. By reducing contact resistance and improving the selective transmission efficiency of carriers, the fill factor of the battery is also improved, further enhancing overall performance. By forming a relatively thin first dielectric layer 110 on the surface of the silicon substrate 100, surface defects can be effectively passivated, significantly reducing surface recombination, thereby improving the open-circuit voltage of the battery. Furthermore, the first doped silicon layer 200 deposited on the tunneling oxide layer generates a built-in electric field at the interface. This electric field attracts and accumulates carriers, shielding them from the influence of surface states, thereby enhancing the passivation effect. Through this dual passivation mechanism (chemical passivation and field effect passivation), the stability and reliability of the battery in long-term operation can be ensured, and performance degradation caused by environmental factors can be reduced.

[0041] Optionally, the thickness of the first dielectric layer 110 is 1 nm to 5 nm. The first dielectric layer 110 can be formed using a thermal oxidation method or a chemical vapor deposition process, such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). Specifically, the silicon substrate 100 can be placed in a chemical vapor deposition device, and high-purity oxygen can be introduced to grow the first dielectric layer 110 on the back side of the silicon substrate 100.

[0042] In this embodiment, the first doped silicon layer 200 is p-type doped polycrystalline silicon. The first doped silicon layer 200 can be formed using a chemical vapor deposition process. After forming the first dielectric layer 110, a silicon source (e.g., high-purity SiH4) is introduced to grow an intrinsic amorphous silicon layer on the first dielectric layer 110. The structure is then placed in a boron diffusion furnace and BCl3 is introduced for boron diffusion, thereby converting the intrinsic amorphous silicon layer into a p-type doped amorphous silicon layer. Annealing is then performed to achieve recrystallization, forming a p-type doped polycrystalline silicon layer, i.e., the first doped silicon layer 200.

[0043] Optionally, the deposition thickness of the intrinsic amorphous silicon layer is 200 nm to 400 nm, and the boron doping concentration of the first doped silicon layer 200 is 3×10 19 / cm 3 ~8×1019 / cm 3 The sheet resistance of the first doped silicon layer 200 is 100-200Ω / sq. It should be understood that during the formation of the first doped silicon layer 200, a layer of borosilicate glass (BSG) (not shown) with a thickness of 20nm-80nm is simultaneously formed on the surface of the first doped silicon layer 200. BSG has a certain degree of corrosion resistance and can serve as a mask in the subsequent wet etching process.

[0044] In step S300 , a local area of the first doped silicon layer 200 is irradiated with laser light, wherein the illumination energy per unit area at the edge of the exposure area is smaller than the illumination energy per unit area at the center of the exposure area.

[0045] In this embodiment, the exposed areas, including the second doped silicon layer 300 (n-type) to be subsequently formed and the spacer between the second doped silicon layer 300 and the first doped silicon layer 200, require removal; the unexposed areas are those that will remain. The BSG film can be melted or vaporized by the laser, or separated from the doped polysilicon layer, to achieve laser film opening. Therefore, during the subsequent wet etching process, the first doped silicon layer 200 and the first dielectric layer 110 in the exposed areas can be etched away, while the BSG film in the unexposed areas acts as a mask to protect the covered first doped silicon layer 200 and the first dielectric layer 110 from corrosion.

[0046] It should be understood that the greater the light energy per unit area, the more likely it is to be corroded during the subsequent wet etching process. Correspondingly, the smaller the light energy per unit area, the less likely it is to be corroded. In the embodiment of the present application, the light energy per unit area at the edge of the exposure area is less than the light energy per unit area in the middle of the exposure area. Therefore, during the subsequent etching process, the corrosion depth of the edge area is relatively shallow, while the corrosion depth of the middle area is relatively deep.

[0047] Optionally, the illumination energy per unit area in the middle of the exposure area is 210 mJ / cm 2 ~380 mJ / cm 2 The illumination energy per unit area of the edge is 150mJ / cm 2 ~300 mJ / cm 2 .

[0048] Figure 3 Schematic diagram of each scanning path in one embodiment of the present application. Figure 3As shown, in this embodiment, the step of using laser to irradiate a local area of the first doped silicon layer 200 includes: using a light spot to scan along n scanning paths, where n ≥ 2. The scanning path extends along the first direction, and the n scanning paths are arranged in the second direction. The first direction is perpendicular to the second direction, and two adjacent scanning paths partially overlap. It can be understood that the first doped silicon layer 200 and the second doped silicon layer 300 on the solar cell to be manufactured are arranged at intervals along the second direction, that is, according to Figure 3 The width of the scanning path in the second direction is the spot width of the laser.

[0049] Figure 3 There are four scanning paths in total, namely Figure 3 In the exposure area, multiple scanning paths are arranged along the second direction, and the two end edges of the exposure area in the second direction are exposed only once. This portion, i.e., the edge of the exposure area, has relatively low illumination energy per unit area. The scanning paths in the middle of the exposure area overlap, so the illumination energy per unit area is relatively high. Figure 3 In the figure, the left part of the scanning path L1 is not covered by the adjacent scanning path, so it forms the edge of the left side of the exposure area. The right part of the scanning path L4 is not covered by the adjacent scanning path, so it forms the edge of the right side of the exposure area. The middle part ( Figure 3 The shaded area in the middle) has at least two overlapping scanning paths.

[0050] Optionally, the width W1 of the scanning path in the second direction and the width W2 of the overlapping area of two adjacent scanning paths in the second direction satisfy the relationship: W2=a×W1, where a is in the range of 0.2 to 0.8. a can be any value among 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8 or a value between any two points. Figure 3 In the illustrated embodiment, W2=0.5×W1, that is, the width of the overlapping area between two adjacent scanning paths accounts for 50% of the width of a single scanning path.

[0051] The width of the scanning path (ie, the width of the light spot), the number of scanning paths, and the overlapping ratio of two adjacent scanning paths can be adjusted as needed. Figure 4 FIG. 1 is a schematic diagram of various scanning paths in another embodiment of the present application. Figure 4 In the embodiment shown, there are three scanning paths, namely M1, M2 and M3 from left to right in the figure. The left portion of scanning path M1 is not covered by the adjacent scanning path, and thus forms the left edge of the exposure area. The right portion of scanning path M3 is not covered by the adjacent scanning path, and thus forms the right edge of the exposure area. The middle portion ( Figure 3The shaded area in the middle) has at least two scanning paths overlapping. Figure 4 In this embodiment, the exposure energy of the exposure area increases stepwise from the edge to the middle. One-third of the area on each side of the scanning path M2 overlaps with the scanning path M1 and the scanning path M3 respectively, and this part is exposed twice; the middle one-third of the area of the scanning path M2 overlaps with both the scanning path M1 and the scanning path M3, and this part is exposed three times. Figure 4 In the illustrated embodiment, the width W1 of the scanning path in the second direction and the width W2 of the overlapping area of two adjacent scanning paths in the second direction satisfy the relationship: W2=a×W1, where a is 2 / 3.

[0052] Optionally, in the first scanning path and the nth scanning path in the second direction, the area not covered by the adjacent scanning path each accounts for 5% to 40% of the exposure area. Figure 3 In this embodiment, the first scanning path is scanning path L1, and the nth scanning path is L4. The areas not covered by the adjacent scanning paths each account for 20% of the exposure area. That is, in the entire exposure area, the edge area with weaker exposure accounts for 40%, and the middle area with stronger exposure accounts for 60%. Figure 4 In this embodiment, the first scanning path is scanning path M1, and the nth scanning path is M3. The areas not covered by adjacent scanning paths each account for 20% of the exposure area. That is, within the entire exposure area, the weaker edge areas account for 40%, and the stronger center areas account for 60%. In other embodiments, the proportion of the area exposed only once can be adjusted as needed.

[0053] In order to achieve that the illumination energy per unit area at the edge of the exposure area is less than the illumination energy per unit area at the center, other methods may be used. For example, in other embodiments, the step of irradiating a local area of the first doped silicon layer 200 with a laser includes: Scanning is performed using a light spot along n scanning paths, where n ≥ 2. The scanning paths extend along a first direction and are joined in a second direction, the first direction being perpendicular to the second direction. The scanning speeds of the first and nth scanning paths in the second direction are slower than the scanning speeds of the second through n-1th scanning paths. In this embodiment, the n scanning paths being joined in the second direction mean that adjacent scanning paths are connected without overlapping, or have minimal overlap (e.g., less than 5% of the scanning path width). It is understood that, assuming constant laser power, a faster scanning speed means a shorter exposure time for each scanning path and lower light energy per unit area; a slower scanning speed means a longer exposure time for each scanning path and higher light energy per unit area. Therefore, the faster scanning speeds of the first and nth scanning paths, which are at the edges of the exposure area, and slower scanning speeds of the second through n-1th scanning paths, can result in lower light energy per unit area at the edges of the exposure area compared to the center.

[0054] Figure 5 FIG. 1 is a schematic diagram of each scanning path in another embodiment of the present application. Figure 5 As shown, there are four scanning paths, namely Figure 5 N1, N2, N3, and N4 in the image; the scanning paths are connected but do not overlap. In the exposure area, multiple scanning paths are arranged along the second direction. The scanning speeds of the first scanning path N1 and the fourth scanning path N4 are higher than those of the second scanning path N2 and the third scanning path N3. Therefore, the illumination energy per unit area on the first scanning path N1 and the fourth scanning path N4 is relatively low, while the illumination energy per unit area on the second scanning path N2 and the third scanning path N3 is relatively high.

[0055] Optionally, the scanning speed of each scanning path is 10m / s~100m / s, wherein the scanning speed of the first scanning path and the nth scanning path is V1, and the scanning speed of the second to n-1th scanning paths is V2, V1=b×V2, and the value range of b is 1.2~3.

[0056] Optionally, the laser spot is a rectangular spot; further, the width of the spot in the second direction is 100 μm to 400 μm. It should be understood that in other embodiments, the spot size and shape can be selected as needed, such as a circular spot. Optionally, the laser uses green light or ultraviolet light, with a laser frequency of picoseconds or sub-femtoseconds. The laser power is 80 kW to 120 kW.

[0057] In step S400 , the first doped silicon layer 200 and the first dielectric layer 110 in the exposed area are etched by a wet etching process to obtain a first trench 210 having an inclined sidewall 211 . The angle between the inclined sidewall 211 and the bottom wall of the first trench 210 is an obtuse angle.

[0058] Figure 6 This is a schematic diagram of an embodiment of the present application after etching to form the first trench 210. Figure 6 As shown, due to the uneven exposure in step S300 , the edge etching depth of the exposed area is shallower than the middle etching depth, so the second trench 310 forms inclined sidewalls 211 on both sides in the width direction (corresponding to the second direction of laser scanning). Figure 7 This is a scanning electron microscope (SEM) image of the inclined sidewall 211 in one embodiment of the present application.

[0059] Optionally, step S400 may specifically include: Step S410, soaking the exposed area with a first etching solution; Step S420, washing the exposed area with water; Step S430: soaking the exposed area with a second etching solution.

[0060] Wherein, the first etching solution and the second etching solution are both alkaline solutions, and the alkalinity of the first etching solution is stronger than that of the second etching solution.

[0061] In this embodiment, the use of a first etchant with a relatively strong alkalinity can significantly improve etching efficiency. After the first etching, the first trench 210 is essentially formed. After the first etching, the inner wall surface of the first trench 210 may be relatively rough. However, etching with a second etchant with a relatively weak alkalinity can modify the inner wall of the first trench 210, making it smooth and flat. The unexposed areas are protected by the BSG film, so the first doped silicon layer 200 and the first dielectric layer 110 in the unexposed areas are not corroded.

[0062] In this embodiment, the angle A between the inclined side wall 211 and the bottom wall of the first groove 210 is 100°~150°, for example, the angle A is a point value among 100°, 110°, 120°, 130°, 140° and 150° or a value between any two points.

[0063] Optionally, the exposure area is immersed in the first etching solution for 50 seconds to 200 seconds, and the exposure area is immersed in the second etching solution for 100 seconds to 400 seconds.

[0064] Optionally, the alkaline component in the first etching solution includes sodium hydroxide and / or potassium hydroxide, and the volume proportion of the alkaline component in the first etching solution is 5% to 10%; the alkaline component in the second etching solution includes sodium hydroxide and / or potassium hydroxide, and the volume proportion of the alkaline component in the second etching solution is 5% to 10%. Furthermore, the first etching solution may also include a surfactant accounting for 0.1% to 1% by volume and an oxidant accounting for 1% to 5% by volume; the second etching solution may also include a surfactant accounting for 0.1% to 1% by volume. The surfactant may be sodium dodecylbenzene sulfonate, and the oxidant may be sodium hypochlorite.

[0065] After etching with the first etchant, the thickness of the BSG film on the first doped silicon layer 200 is reduced by 5 nm to 20 nm. After etching with the second etchant, the thickness of the BSG film on the first doped silicon layer 200 is reduced by 5 nm to 30 nm. The resulting first trench 210 has a depth of 0.2 μm to 4 μm. It should be understood that the depth of the first trench 210 should be greater than the combined thickness of the first dielectric layer 110, the first doped silicon layer 200, and the BSG film, so that the bottom wall of the first trench 210 is formed by the silicon substrate 100.

[0066] Since the first groove 210 in this embodiment is an inverted trapezoid (narrow bottom and wide opening), when etching to form a groove with the same opening width, the etching liquid used in this embodiment will be relatively small, thereby saving costs; at the same time, it can also reduce the precision requirements for laser film opening and wet etching.

[0067] In step S500 , a second dielectric layer 120 and a second doped silicon layer 300 are sequentially stacked in the first trench 210 to fill the first trench 210 .

[0068] Figure 8 This is a schematic diagram of an embodiment of the present application after the second dielectric layer 120 and the second doped silicon layer 300 are fabricated. In this embodiment, the material of the second dielectric layer 120 is silicon oxide. The second dielectric layer 120 can provide surface passivation, field effect passivation, and selective carrier transport. The specific function, principle, and preparation method of the second dielectric layer 120 can be referred to as the first dielectric layer 110 and will not be further described here.

[0069] In this embodiment, the second doped silicon layer 300 is n-type doped polycrystalline silicon. The second doped silicon layer 300 can be formed using a chemical vapor deposition process. After forming the second dielectric layer 120, a silicon source (e.g., high-purity SiH4) is introduced to grow an intrinsic amorphous silicon layer on the second dielectric layer 120. The structure is then placed in a phosphorus diffusion furnace and POCl3 is introduced for phosphorus diffusion, thereby converting the intrinsic amorphous silicon layer into an n-type doped amorphous silicon layer. Annealing is then performed to achieve recrystallization, forming an n-type doped polycrystalline silicon layer, i.e., the second doped silicon layer 300.

[0070] It should be understood that because the first trench 210 has inclined sidewalls 211, it has an outwardly open structure with a bottom width narrower than the opening width. Therefore, when depositing the second dielectric layer 120 and the second doped silicon layer 300, the second doped silicon layer 300 will not be deposited below the first doped silicon layer 200. A portion of the second doped silicon layer 300 will be above the first doped silicon layer 200. This portion of the second doped silicon layer 300 above the first doped silicon layer 200 will also be removed later (step S600), ultimately achieving complete isolation between the first doped silicon layer 200 and the second doped silicon layer 300. It should be understood that in this embodiment, the "below" of the first doped silicon layer 200 refers to the side of the first doped silicon layer 200 that is closest to the silicon substrate 100.

[0071] Optionally, the deposition thickness of the intrinsic amorphous silicon layer used to form the second doped silicon layer 300 is 200 nm to 400 nm, and the phosphorus doping concentration of the second doped silicon layer 300 is 3×10 19 / cm 3 ~8×10 19 / cm 3 The sheet resistance of the first doped silicon layer 200 is 100-200Ω / sq. It should be understood that during the formation of the second doped silicon layer 300, a layer of phosphosilicate glass (PSG) (not shown) with a thickness of 20nm-80nm is simultaneously formed on the surface of the second doped silicon layer 300. The PSG film has a certain degree of corrosion resistance and can serve as a mask in the subsequent wet etching process.

[0072] In step S600 , a portion of the second dielectric layer 120 and the second doped silicon layer 300 that are in contact with the inclined sidewall 211 are removed to form a second trench 310 .

[0073] Figure 9 This is a schematic diagram of the second trench 310 after being formed in one embodiment of the present application. In the embodiment of the present application, a laser can be used to irradiate the PSG film on the second doped silicon layer 300 to be removed to achieve film opening; then a wet etching process is used to remove a portion of the second dielectric layer 120 and the second doped silicon layer 300 where the inclined sidewall 211 is connected to form the second trench 310. The PSG film in the area not irradiated by the laser acts as a mask, and the second doped silicon layer 300 and the second dielectric layer 120 covered by it are not corroded. It should be understood that one of the sidewalls of the second trench 310 is the inclined sidewall 211 of the first trench 210. Therefore, the angle between at least one sidewall of the second trench 310 and its bottom wall is an obtuse angle.

[0074] Because the first doped silicon layer 200 does not cover the second doped silicon layer 300, when removing the portion of the second dielectric layer 120 and the second doped silicon layer 300 that is in contact with the inclined sidewall 211, the portion of the second doped silicon layer 300 that is in contact with the first doped silicon layer 200 can be easily and completely removed, and the second doped silicon layer 300 is unlikely to remain. This solves the problem of the prior art where a portion of the second doped silicon layer 300 is likely to remain in contact with the first doped silicon layer 200. After the second trench 310 is formed, the first doped silicon layer 200 and the second doped silicon layer 300 are completely separated.

[0075] In addition, since the second trench 310 in this embodiment is an inverted trapezoid (narrow bottom and wide opening), when etching to form trenches with the same opening width, the amount of etching solution used in this embodiment is relatively small, thereby saving costs.

[0076] In this embodiment, the other sidewall of the second groove 310 opposite the inclined sidewall 211 is vertical, i.e., it forms an angle of approximately 90° with the bottom wall. In other optional embodiments, the other sidewall of the second groove 310 opposite the inclined sidewall 211 can also be configured to form an obtuse angle with the bottom wall, such as an obtuse angle of 100° to 150° with the bottom wall.

[0077] In step S700 , a passivation layer is prepared on the front and back sides of the silicon substrate 100 , and a first electrode 610 connected to the first doped silicon layer 200 and a second electrode 620 connected to the second doped silicon layer 300 are fabricated.

[0078] Figure 10 This is a schematic diagram of the passivation layer and electrodes after fabrication in one embodiment of the present application. In this embodiment, before forming the passivation layer, the silicon substrate 100, on which the first doped silicon layer 200 and the second doped silicon layer 300 are deposited, can be acid-washed. The front surface of the silicon substrate 100 can then be textured to form a velvet surface. This velvet surface can reduce light reflection loss, improve light absorption efficiency, and reduce surface recombination, thereby improving battery performance.

[0079] Optionally, the passivation layer is made of at least one material selected from aluminum oxide, silicon oxide, silicon oxynitride, and silicon nitride. The passivation layer may be a single layer structure (e.g., an aluminum oxide layer, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer) or a composite layer structure of multiple materials. The passivation layer may be fabricated using an atomic layer deposition process or a chemical vapor deposition process.

[0080] Optionally, the step of preparing a passivation layer on the front and back sides of the silicon substrate 100 includes: depositing a first passivation layer 400 on the front side of the silicon substrate 100; and depositing a second passivation layer 500 on the first doped silicon layer 200, the second doped silicon layer 300, and the bottom wall and inclined sidewall 211 of the second trench 310.

[0081] During the electrode manufacturing process, the second electrode 620 can be printed on the second passivation layer 500 in the region corresponding to the second doped silicon layer 300; thereafter, the first electrode 610 can be printed on the first passivation layer 400 in the region corresponding to the first doped silicon layer 200; finally, the first electrode 610 and the second electrode 620 are sintered. Figure 10 The solar cell shown should be understood as follows: Figure 10 The structure shown is only a partial cross-section of the solar cell. In this embodiment, the first electrode 610 and the second electrode 620 are a grid line structure. The material of the first electrode 610 and the second electrode 620 can be a combination of one or more of silver, aluminum, and copper.

[0082] The embodiments of the present application further provide a solar cell, specifically a TBC cell, which can be manufactured by the solar cell manufacturing method provided in the above embodiments.

[0083] In summary, the embodiments of the present application provide a solar cell and a method for manufacturing the same. The method for manufacturing the solar cell includes: obtaining a silicon substrate 100, the silicon substrate 100 having a front surface and a back surface relative to each other; preparing a first dielectric layer 110 and a first doped silicon layer 200 stacked in sequence on the back surface of the silicon substrate 100; irradiating a local area of the first doped silicon layer 200 with a laser, wherein the light energy per unit area at the edge of the exposed area is less than the light energy per unit area in the middle of the exposed area; etching the first doped silicon layer 200 and the first dielectric layer 110 in the exposed area using a wet etching process to obtain a first trench 21 having an inclined sidewall 211. 0, the angle between the inclined sidewall 211 and the bottom wall of the first trench 210 is an obtuse angle; a second dielectric layer 120 and a second doped silicon layer 300 are stacked in sequence within the first trench 210 to fill the first trench 210; a portion of the second dielectric layer 120 and the second doped silicon layer 300 that is in contact with the inclined sidewall 211 is removed to form a second trench 310; a passivation layer is formed on the front and back surfaces of the silicon substrate 100, and a first electrode 610 connected to the first doped silicon layer 200 and a second electrode 620 connected to the second doped silicon layer 300 are fabricated. In this embodiment of the present application, by controlling the energy of the laser irradiation area, the unit area illumination energy at the edge of the exposure area is less than the unit area illumination energy in the center of the exposure area. Since higher light energy makes it easier to etch, when etching the first doped silicon layer 200 and the first dielectric layer 110 in the exposed area, the etching depth at the edge of the exposed area will be shallower and the etching depth in the middle will be deeper, so that the first trench 210 can have an inclined sidewall 211 and the opening width of the first trench 210 is greater than the bottom width. When the second doped silicon layer 300 is subsequently prepared, the second doped silicon layer 300 will not be deposited below the first doped silicon layer 200. By forming the second trench 310, the second doped silicon layer 300 in contact with the first doped silicon layer 200 can be completely removed, so that the first doped silicon layer 200 and the second doped silicon layer 300 are completely separated, thereby reducing minority carrier recombination and leakage channels caused by the contact between the first doped silicon layer 200 and the second doped silicon layer 300, thereby improving the performance of the solar cell. Since the opening width of the first trench 210 is greater than the bottom width, the first doped silicon layer 200 and the second doped silicon layer 300 can be effectively isolated without a deeper etching depth, thereby increasing the process window, facilitating future thinning and reducing the precision requirements for patterning equipment, greatly reducing production costs, and facilitating large-scale mass production.

[0084] The solar cell provided in the embodiment of the present application is manufactured by the above-mentioned manufacturing method and therefore has better photoelectric conversion efficiency.

[0085] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in this application should be covered by the scope of protection of the present application.

Claims

1. A method for preparing a solar cell, characterized in that: include: obtaining a silicon substrate having a front side and a back side opposite to each other; On the back side of the silicon substrate, a first dielectric layer and a first doped silicon layer are sequentially stacked; irradiating a local area of the first doped silicon layer with a laser, wherein the light energy per unit area at the edge of the exposure area is less than the light energy per unit area at the center of the exposure area; Etching the first doped silicon layer and the first dielectric layer in the exposed area by a wet etching process to obtain a first trench having an inclined sidewall, wherein the angle between the inclined sidewall and the bottom wall of the first trench is an obtuse angle; preparing a second dielectric layer and a second doped silicon layer stacked in sequence in the first trench to fill the first trench; removing a portion of the second dielectric layer and the second doped silicon layer adjacent to the inclined sidewall to form a second trench; A passivation layer is prepared on the front and back sides of the silicon substrate, and a first electrode connected to the first doped silicon layer and a second electrode connected to the second doped silicon layer are manufactured.

2. The method for preparing a solar cell according to claim 1, wherein: The step of irradiating a local area of the first doped silicon layer with a laser comprises: Scanning is performed along n scanning paths using a light spot, wherein n≥2, the scanning paths extend along a first direction, the n scanning paths are arranged in a second direction, the first direction is perpendicular to the second direction, and two adjacent scanning paths partially overlap.

3. The method for preparing a solar cell according to claim 2, wherein: The width W1 of the scanning path in the second direction and the width W2 of the overlapping area of two adjacent scanning paths in the second direction satisfy the relationship: W2=a×W1, where a ranges from 0.2 to 0.

8.

4. The method for preparing a solar cell according to claim 2, wherein: In the first scanning path and the nth scanning path in the second direction, areas not covered by adjacent scanning paths each account for 5% to 40% of the exposure area.

5. The method for preparing a solar cell according to claim 2, wherein: The light spot is a rectangular light spot.

6. The method for preparing a solar cell according to claim 2, wherein: The width of the light spot in the second direction is 100 μm to 400 μm.

7. The method for preparing a solar cell according to claim 1, wherein: The step of irradiating a local area of the first doped silicon layer with a laser comprises: Scanning is performed using a light spot along n scanning paths, where n ≥ 2, the scanning paths extend along a first direction, the n scanning paths are spliced in a second direction, the first direction is perpendicular to the second direction, and the scanning speeds of the first scanning path and the nth scanning path in the second direction are greater than the scanning speeds of the second to n-1th scanning paths.

8. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: The step of etching the first doped silicon layer and the first dielectric layer in the exposure area by using a wet etching process comprises: soaking the exposed area with a first etching solution; washing the exposed area with water; soaking the exposed area with a second etching solution; Wherein, the first etching solution and the second etching solution are both alkaline solutions, and the alkalinity of the first etching solution is stronger than that of the second etching solution.

9. The method for preparing a solar cell according to claim 8, wherein: The exposure area is immersed in the first etching solution for 50 seconds to 200 seconds, and the exposure area is immersed in the second etching solution for 100 seconds to 400 seconds.

10. The method for preparing a solar cell according to claim 8, wherein: The alkaline components in the first etching solution include sodium hydroxide and / or potassium hydroxide, and the volume proportion of the alkaline components in the first etching solution is 5% to 10%; the alkaline components in the second etching solution include sodium hydroxide and / or potassium hydroxide, and the volume proportion of the alkaline components in the second etching solution is 5% to 10%.

11. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: An included angle between the inclined side wall and the bottom wall of the first trench is 100° to 150°.

12. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: The first doped silicon layer is p-type doped, and the second doped silicon layer is n-type doped.

13. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: The first dielectric layer and the second dielectric layer are made of silicon oxide.

14. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: The step of preparing a passivation layer on the front and back sides of the silicon substrate comprises: Depositing a first passivation layer on the front surface of the silicon substrate; A second passivation layer is deposited on the first doped silicon layer, the second doped silicon layer, and the bottom wall and the inclined sidewall of the second trench.

15. The method for preparing a solar cell according to any one of claims 1 to 7, characterized in that: The material of the passivation layer is selected from at least one of aluminum oxide, silicon oxide, silicon oxynitride and silicon nitride.

16. A solar cell, characterized in that: The solar cell is prepared by the method for preparing the solar cell according to any one of claims 1 to 15.

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