Solar cell and solar cell module

By preparing deep holes on the surface of solar cell silicon wafers and setting passivation layers with different thicknesses, the problem of low absorption of large angle incident light is solved, and more efficient use of light energy is achieved.

CN120512955APending Publication Date: 2025-08-19LONGI GREEN ENERGY TECH CO LTD
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Patent Information

Application Number
CN202411217393.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-08-30
Publication Date
2025-08-19

AI Technical Summary

Technical Problem

The absorption rate of existing solar cells decreases significantly under large angle incident light conditions, making it difficult to achieve good omnidirectional light utilization.

Method used

A number of deep holes are prepared on the surface of the silicon wafer of the solar cell, and passivation layers of different thicknesses are provided at the orifices and on the side walls to increase the number of reflections of large angle incident light and optical transmission paths.

Benefits of technology

The absorption rate of solar cells to large-angle incident light is improved, the chance of light being reflected out of the battery is reduced, and the omnidirectional light utilization effect is enhanced.

✦ Generated by Eureka AI based on patent content.

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Abstract

The invention provides a solar cell and a solar cell module, and belongs to the technical field of solar cells. The solar cell comprises a silicon wafer, the silicon wafer is provided with a first surface and a second surface which are opposite, the first surface of the silicon wafer is provided with a plurality of deep holes, and each deep hole comprises a first hole opening located in the first surface; the first passivation layer is at least located on the first surface of the silicon wafer and the side wall of the deep hole; wherein the thickness of the first passivation layer located at the first hole is greater than the thickness of the first passivation layer which is far away from the first hole and located on the side wall and the first surface. According to the invention, the plurality of deep holes are formed in one surface of the silicon wafer, and the thickness of the first passivation layer at the first hole opening is different from the thickness of the first passivation layer at other positions, so that the optical path of the large-angle incident light in the solar cell is increased, the large-angle incident light is absorbed after being reflected for multiple times in the deep holes, and the optical path of the large-angle incident light is increased. And the absorption effect of the solar cell on large-angle incident light is improved.
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Description

Technical Field

[0001] At least one embodiment of the present application relates to a solar cell, and more particularly to a solar cell and a solar cell assembly. Background Art

[0002] As a pollution-free, renewable energy source, the development and utilization of solar energy has been rapidly developed, especially solar cells with high conversion efficiency have become the focus of current research.

[0003] To improve the light utilization efficiency of solar cells, various structures, such as inverted pyramids and upright pyramids, are currently used to trap light. These structures are designed with vertical light incidence in mind. When sunlight is incident at a high angle (for example, greater than 45 degrees from the vertical line of the silicon wafer), the absorption rate of sunlight decreases significantly. Summary of the Invention

[0004] In view of this, in order to improve the absorption rate of solar cells to sunlight, the present application provides a solar cell and a solar cell assembly.

[0005] According to an embodiment of one aspect of the present application, a solar cell is provided, comprising: a silicon wafer having a first surface and a second surface opposite to each other, the first surface of the silicon wafer having a plurality of deep holes, the deep holes including a first opening located on the first surface; and a first passivation layer located at least on the first surface of the silicon wafer and the sidewalls of the deep holes; wherein the thickness of the first passivation layer located at the first opening is greater than the thickness of the first passivation layer located away from the first opening and on the sidewalls and the first surface.

[0006] According to an embodiment of the present application, the thickness of the first passivation layer located on the sidewall and close to the first opening is greater than the thickness of the first passivation layer located on the sidewall and the first surface and away from the first opening.

[0007] According to an embodiment of the present application, the thickness of the first passivation layer located on the first surface is greater than the thickness of the first passivation layer located on the sidewall and away from the first opening.

[0008] According to an embodiment of the present application, the ratio of the depth of the deep hole to the thickness of the silicon wafer ranges from 50% to 90%.

[0009] According to an embodiment of the present application, the deep hole is a blind hole, the first passivation layer is also located at the bottom of the deep hole, and the thickness of the first passivation layer at the bottom of the deep hole is less than the thickness of the first passivation layer located on the side wall and away from the first hole opening.

[0010] According to an embodiment of the present application, the first passivation layer located at the first hole opening includes a first passivation layer located on the sidewall and close to the first hole opening, and / or a first passivation layer located on the first surface and close to the first hole opening; the length of the first passivation layer located on the sidewall and close to the first hole opening is 0.1% to 10% of the depth of the deep hole;

[0011] And / or, the length of the first passivation layer located on the first surface and close to the first hole opening is 0.1% to 10% of the depth of the deep hole.

[0012] According to an embodiment of the present application, the deep hole includes one of a cylindrical shape, a conical shape, and a truncated cone shape, or any combination thereof.

[0013] According to an embodiment of the present application, the diameter of the deep hole ranges from 20 μm to 200 μm.

[0014] According to an embodiment of the present application, the thickness of the first passivation layer ranges from 0.1 nm to 1000 nm.

[0015] According to an embodiment of the present application, a plurality of deep holes are distributed in an array on the first surface; and a distance between the cross-sectional centers of two adjacent deep holes is 20 μm to 300 μm.

[0016] According to an embodiment of the present application, a ratio of a projection area of the plurality of deep holes on the first surface to an area of the first surface is 0.4-0.85.

[0017] According to an embodiment of the present application, the deep hole is a through hole, and the deep hole further includes a second opening located on the second surface;

[0018] The solar cell also includes: a second passivation layer located on the second surface of the silicon wafer and the sidewalls of the deep hole; wherein the thickness of the second passivation layer located at the second hole opening is greater than the thickness of the second passivation layer located away from the second hole opening and on the sidewalls and second surface.

[0019] According to an embodiment of the present application, the thickness of the second passivation layer located on the sidewall and close to the second opening is greater than the thickness of the second passivation layer located on the sidewall and the second surface and away from the second opening.

[0020] According to an embodiment of another aspect of the present application, a solar cell is provided, comprising: a silicon wafer, the silicon wafer having a first surface and a second surface relative to each other, the silicon wafer having a plurality of deep holes passing through the silicon wafer, the deep holes comprising a first opening located on the first surface and a second opening located on the second surface; and a first passivation layer covering the first surface of the silicon wafer, the second surface of the silicon wafer, and the sidewalls of the deep holes; wherein the thickness of the first passivation layer located at the first opening and the second opening is greater than the thickness of the first passivation layer located away from the first opening and the second opening and located on the sidewalls, the first surface, and the second surface.

[0021] According to an embodiment of the present application, the thickness of the first passivation layer located on the sidewall and close to the first opening is greater than the thickness of the first passivation layer located away from the first opening and on the sidewall and the first surface.

[0022] According to an embodiment of the present application, the thickness of the first passivation layer located on the first surface and the second surface is greater than the thickness of the first passivation layer located away from the first opening and on the sidewall.

[0023] According to an embodiment of the present application, the first passivation layer located at the first orifice and the second orifice includes a first passivation layer located on the sidewall and close to the first orifice and / or the second orifice, and / or a first passivation layer located on the first surface and close to the first orifice and / or the second orifice;

[0024] The length of the first passivation layer located on the sidewall and close to the first hole opening and / or the second hole opening is 0.1% to 10% of the depth of the deep hole;

[0025] And / or, the length of the first passivation layer located on the first surface and close to the first hole opening and / or the second hole opening is 0.1% to 10% of the depth of the deep hole.

[0026] According to an embodiment of the present application, the diameter of the deep hole ranges from 20 μm to 200 μm.

[0027] According to an embodiment of the present application, the thickness of the first passivation layer ranges from 0.1 nm to 1000 nm.

[0028] According to an embodiment of the present application, a plurality of deep holes are distributed in an array on the first surface; and a distance between the cross-sectional centers of two adjacent deep holes is 20 μm to 300 μm.

[0029] According to an embodiment of the present application, a ratio of a projection area of the plurality of deep holes on the first surface to an area of the first surface is 0.4-0.85.

[0030] According to another embodiment of the present application, a solar cell assembly is provided, comprising the above-mentioned solar cell.

[0031] According to the solar cell provided in the above-mentioned embodiment of the present application, by setting a plurality of deep holes on the first surface of the silicon wafer, the number of reflections of large-angle incident light in the deep holes can be increased, thereby increasing the optical transmission path of large-angle incident light and reducing the probability of large-angle incident light being reflected out of the solar cell, thereby improving the absorption rate of the solar cell for large-angle incident light.

[0032] According to the solar cell provided in the above-mentioned embodiment of the present application, the thickness of the first passivation layer located at the hole mouth is greater than the thickness of the first passivation layer located away from the hole mouth and located on the side wall and the first surface. The first passivation layer located at the hole mouth has a greater thickness, which can reflect the sunlight reflected out of the hole mouth after multiple reflections in the deep hole into the deep hole again, and can further increase the optical transmission path of large-angle incident light in the deep hole, reduce the probability of large-angle incident light being reflected out of the solar cell, and help to further increase the absorption rate of the solar cell for large-angle incident light. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present application, and are not limitations to the present application.

[0034] Figure 1 A schematic cross-sectional view of a solar cell provided in an embodiment of the present application;

[0035] Figure 2A A schematic cross-sectional view of a silicon wafer having multiple deep holes provided in an embodiment of the present application;

[0036] Figure 2B A schematic top view of a silicon wafer having multiple deep holes provided in an embodiment of the present application;

[0037] Figure 2C A schematic cross-sectional view of a silicon wafer having multiple deep holes provided in another embodiment of the present application;

[0038] Figure 2D A schematic cross-sectional view of a silicon wafer having multiple deep holes provided in yet another embodiment of the present application;

[0039] Figure 3 A schematic cross-sectional view of a solar cell provided in another embodiment of the present application;

[0040] Figure 4 A schematic cross-sectional view of a silicon wafer having a plurality of through-holes provided in an embodiment of the present application;

[0041] Figure 5 A schematic diagram of the path of sunlight reflected from a pyramid structure in the related art;

[0042] Figure 6 A schematic diagram of the path of sunlight reflected from a deep hole structure in a solar cell with a passivation layer having no thickness difference provided by an embodiment of the present application;

[0043] Figure 7 A schematic diagram of the path of sunlight reflected from a deep hole structure in a solar cell provided by another embodiment of the present application;

[0044] Figure 8 A schematic cross-sectional view of a bifacial solar cell provided in an embodiment of the present application;

[0045] Figure 9 A schematic cross-sectional view of a back-contact solar cell provided in an embodiment of the present application; and

[0046] Figure 10 A schematic flow chart of a method for manufacturing a solar cell provided in an embodiment of the present application.

[0047] Description of reference numerals:

[0048] 1-Silicon wafer;

[0049] 11-Deep hole;

[0050] 2-first passivation layer;

[0051] 3- first electrode;

[0052] 4- Second passivation layer of bifacial solar cell;

[0053] 5- second electrode;

[0054] 61-first dielectric layer;

[0055] 71-first transport layer;

[0056] 62- second dielectric layer;

[0057] 72-second transport layer;

[0058] 8- second passivation layer;

[0059] 10- third electrode;

[0060] 20-Fourth electrode. DETAILED DESCRIPTION

[0061] To make the objectives, technical solutions, and advantages of this application more clearly understood, the present application will be further described in detail below with reference to specific embodiments and the accompanying drawings. However, this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the application thorough and complete and fully convey the scope of this application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals represent the same elements throughout.

[0062] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0063] In order to reduce the reflection of incident sunlight on the surface of solar cells, increase the absorption effect of incident sunlight, and improve power generation, a velvet structure with a pyramid structure and / or an inverted pyramid structure is usually designed on the surface through a velvet process. This velvet structure has a good anti-reflection effect for vertically incident light or light with a small incident angle, but has a poor anti-reflection effect for light with a large incident angle (the angle with the vertical line of the silicon wafer is greater than 45 degrees), that is, the omnidirectionality of the solar cell is poor. Solar cells with poor omnidirectionality need to set the optimal light receiving angle or use a tracking bracket to achieve a larger power generation. The optimal light receiving angle varies according to geographical location, time and season, making it difficult to adjust the fixed bracket in real time to achieve the optimal light receiving angle for the solar cell. Tracking brackets are usually expensive, so improving the omnidirectionality of solar cells is a relatively simple way to increase power generation.

[0064] In view of this, the present application provides a solar cell and a solar cell assembly to increase the absorption of light incident at a large angle.

[0065] Figure 1 A schematic cross-sectional view of a solar cell provided in an embodiment of the present application.

[0066] According to an exemplary embodiment of the present application, the present application provides a solar cell, referring to Figure 1 As shown, including:

[0067] A silicon wafer 1 having a first surface and a second surface opposite to each other, the first surface of the silicon wafer 1 having a plurality of deep holes 11, the deep holes 11 including a first opening located on the first surface; and

[0068] A first passivation layer 2 is located at least on the first surface of the silicon wafer 1 and the sidewalls of the deep hole 11;

[0069] The thickness of the first passivation layer 2 located at the first opening is greater than the thickness of the first passivation layer 2 located away from the first opening and on the sidewall and the first surface.

[0070] According to an embodiment of the present application, the silicon wafer 1 may be single crystal silicon or polycrystalline silicon.

[0071] According to an embodiment of the present application, the three-dimensional shape of the deep hole 11 includes but is not limited to one of cylindrical, conical and truncated cone shapes or any combination thereof, and can also be one of approximate cylindrical, conical and truncated cone shapes or any combination thereof.

[0072] Figure 2A A schematic cross-sectional view of a silicon wafer with multiple deep holes provided in an embodiment of the present application.

[0073] Figure 2B A schematic top view of a silicon wafer with multiple deep holes provided in an embodiment of the present application.

[0074] refer to Figure 2A 、 Figure 2B As shown, a plurality of deep holes 11 are provided on the first surface of the silicon wafer 1 .

[0075] According to an embodiment of the present application, the three-dimensional shape of the deep hole 11 is cylindrical.

[0076] Figure 2C A schematic cross-sectional view of a silicon wafer having multiple deep holes provided in accordance with another embodiment of the present application.

[0077] According to the embodiments of this application, reference Figure 2C As shown, the three-dimensional shape of the deep hole 11 is an inverted cone.

[0078] Figure 2D A schematic cross-sectional view of a silicon wafer having multiple deep holes is provided in accordance with yet another embodiment of the present application.

[0079] According to the embodiments of this application, reference Figure 2D As shown, the three-dimensional shape of the deep hole 11 is an inverted truncated cone.

[0080] According to an embodiment of the present application, the thickness of the first passivation layer 2 located on the sidewall and close to the first opening is greater than the thickness of the first passivation layer 2 located on the sidewall and the first surface and away from the first opening.

[0081] According to an embodiment of the present application, the thickness of the first passivation layer 2 located on the first surface is greater than the thickness of the first passivation layer 2 located on the sidewall and away from the first opening.

[0082] According to the embodiments of the present application, the ratio of the depth of deep hole 11 to the thickness of silicon wafer 1 ranges from 50% to 90%, and can be, for example, 50%, 60%, 70%, 80%, or 90%, but is not limited to these values. If the depth of deep hole 11 is too small, less than 50% of the thickness of silicon wafer 1, the technical effect of increasing the optical path length of light incident at large angles may be difficult to achieve, or the effect may be less significant.

[0083] According to an embodiment of the present application, the thickness of the silicon wafer 1 is 90μm~180μm, for example, it can be 90μm, 95μm, 100μm, 130μm, 150μm, 180μm, but is not limited to the listed values; the depth of the deep hole 11 is 45μm~162μm, for example, it can be 45μm, 50μm, 80μm, 100μm, 150μm, 162μm, but is not limited to the listed values.

[0084] According to an embodiment of the present application, a plurality of deep holes 11 are distributed in an array on the first surface; the spacing between the cross-sectional centers of two adjacent deep holes 11 is 20 μm to 300 μm, for example, it can be 20 nm, 50 nm, 100 nm, 150 nm, 200 nm, 300 nm, but is not limited to the listed values.

[0085] According to an embodiment of the present application, the ratio of the projected area of the multiple deep holes 11 on the first surface to the area of the first surface is 0.4 to 0.85. For example, the ratio can be 0.4, 0.5, 0.6, 0.8, or 0.85, but is not limited to these values. If the projected area of the multiple deep holes 11 on the first surface is too small, the technical effect of increasing the optical path length of high-angle incident light cannot be achieved. If the projected area of the multiple deep holes 11 on the first surface is too large, the mechanical properties of the silicon wafer 1 and the solar cell containing the silicon wafer 1 will be impaired.

[0086] According to the embodiments of the present application, the diameter of the deep hole 11 ranges from 20 μm to 200 μm, for example, 20 μm, 50 μm, 100 μm, 150 μm, and 200 μm, but is not limited to these values. If the diameter of the deep hole 11 is too small, the first passivation layer 2 cannot be effectively deposited into the deep hole to cover the bottom surface of the deep hole and complete the passivation requirement. If the diameter of the deep hole 11 is too large, the mechanical strength of the solar cell will be reduced.

[0087] According to an embodiment of the present application, the thickness of the first passivation layer 2 on the silicon wafer 1 ranges from 0.1 nm to 1000 nm, for example, 0.1 nm, 100 nm, 300 nm, 500 nm, and 1000 nm, but is not limited to these values. If the thickness of the first passivation layer 2 is too small, for example, less than 0.1 nm, it is difficult to deposit a uniform film layer to achieve surface passivation and anti-reflection functions. If the thickness of the first passivation layer 2 is too large, it is not conducive to effectively absorbing incident sunlight, and it increases the cost of the preparation process, resulting in waste.

[0088] According to an embodiment of the present application, the thickness of the first passivation layer 2 located on the sidewall and close to the first orifice is 0.1 nm to 1000 nm higher than the thickness of the first passivation layer 2 located at other positions of the sidewall (located on the sidewall and away from the first orifice). For example, it can be 0.1 nm, 100 nm, 300 nm, 500 nm, or 1000 nm, but is not limited to the values listed.

[0089] According to an embodiment of the present application, the deep hole 11 is a blind hole, and the first passivation layer 2 is also located on the bottom surface of the deep hole 11 to achieve the passivation and anti-reflection functions of the bottom surface of the deep hole 11; wherein the thickness of the first passivation layer 2 located on the bottom surface of the deep hole 11 is less than the thickness of the first passivation layer 2 located on the side wall and away from the first hole opening.

[0090] According to an embodiment of the present application, the thickness of the first passivation layer 2 at the bottom of the deep hole 11 is less than the thickness of the first passivation layer 2 located on the sidewall away from the first hole opening, and the thickness of the first passivation layer 2 at the bottom of the deep hole 11 is less than the thickness of the first passivation layer 2 located on the sidewall and close to the first hole opening. The thickness of the first passivation layer 2 at the bottom of the deep hole should be controlled within the above relationship. If the thickness is too thick, the first passivation layer 2 may overfill the deep hole, increase the possibility of the first passivation layer 2 absorbing incident light, and reduce the utilization rate of the incident light by the silicon substrate.

[0091] According to an embodiment of the present application, the length of the first passivation layer 2 located on the side wall and close to the first hole in the thickness direction of the silicon wafer 1 is 0.1% to 10% of the depth of the deep hole; for example, it can be 0.1%, 1%, 5%, or 10%, but is not limited to the values listed.

[0092] According to an embodiment of the present application, the length of the first passivation layer 2 located on the first surface and close to the first orifice from the first surface toward the first orifice is 0.1% to 10% of the depth of the deep hole; for example, it can be 0.1%, 1%, 5%, or 10%, but is not limited to the values listed.

[0093] According to an embodiment of the present application, deep hole 11 is a through hole; deep hole 11 also includes a second opening located on the second surface. The solar cell further includes a second passivation layer located on the second surface of the silicon wafer and on the sidewalls of the deep hole; the thickness of the second passivation layer located at the second opening is greater than the thickness of the second passivation layer located away from the second opening and on the sidewalls and second surface.

[0094] According to an embodiment of the present application, the thickness of the second passivation layer located on the sidewall and close to the second opening is greater than the thickness of the second passivation layer located on the sidewall and the second surface and away from the second opening.

[0095] Figure 3 A schematic cross-sectional view of a solar cell provided in accordance with another embodiment of the present application.

[0096] According to an exemplary embodiment of the present application, the present application provides a solar cell, referring to Figure 3 As shown, including:

[0097] A silicon wafer 1 having a first surface and a second surface opposite to each other, the silicon wafer having a plurality of deep holes 11 penetrating the silicon wafer, the deep holes 11 including a first opening located on the first surface and a second opening located on the second surface; and

[0098] a first passivation layer 2 covering the first surface of the silicon wafer 1, the second surface of the silicon wafer 1 and the sidewalls of the deep hole 11;

[0099] The thickness of the first passivation layer 2 at the first and second openings is greater than the thickness of the first passivation layer 2 away from the first and second openings and located on the sidewalls, the first surface, and the second surface.

[0100] According to an embodiment of the present application, the three-dimensional shape of the deep hole 11 is cylindrical.

[0101] According to an embodiment of the present application, the thickness of the first passivation layer 2 located on the sidewall and close to the first hole is greater than the thickness of the first passivation layer 2 located away from the first hole and on the sidewall and the first surface.

[0102] According to an embodiment of the present application, the thickness of the first passivation layer 2 located on the first surface and the second surface is greater than the thickness of the first passivation layer 2 located away from the first opening and on the sidewall.

[0103] Figure 4 A schematic cross-sectional view of a silicon wafer having multiple through-holes provided in an embodiment of the present application.

[0104] According to the embodiments of this application, reference Figure 4 As shown, the three-dimensional shape of the deep hole 11 can be an inverted truncated cone.

[0105] According to an embodiment of the present application, the thickness of the silicon wafer 1 is 90 μm to 180 μm, for example, 90 μm, 95 μm, 100 μm, 130 μm, 150 μm, or 180 μm, but is not limited to the values listed above.

[0106] According to an embodiment of the present application, a plurality of deep holes 11 are distributed in an array on the first surface; the spacing between the cross-sectional centers of two adjacent deep holes 11 is 20 μm to 300 μm, for example, it can be 20 nm, 50 nm, 100 nm, 150 nm, 200 nm, 300 nm, but is not limited to the listed values.

[0107] According to an embodiment of the present application, the ratio of the projected area of the multiple deep holes 11 on the first surface to the area of the first surface is 0.4 to 0.85. For example, the ratio can be 0.4, 0.5, 0.6, 0.8, or 0.85, but is not limited to these values. If the projected area of the multiple deep holes 11 on the first surface is too small, the technical effect of increasing the optical path length of high-angle incident light cannot be achieved. If the projected area of the multiple deep holes 11 on the first surface is too large, the mechanical properties of the silicon wafer 1 and the solar cell containing the silicon wafer 1 will be impaired.

[0108] According to the embodiments of the present application, the diameter of the deep hole 11 ranges from 20 μm to 200 μm, for example, 20 μm, 50 μm, 100 μm, 150 μm, and 200 μm, but is not limited to these values. If the diameter of the deep hole 11 is too small, the first passivation layer 2 cannot be effectively deposited into the deep hole to cover the bottom surface of the deep hole and complete the passivation requirement. If the diameter of the deep hole 11 is too large, the mechanical strength of the solar cell will be reduced.

[0109] According to an embodiment of the present application, the thickness of the first passivation layer 2 located on the silicon wafer 1 ranges from 0.1 nm to 1000 nm, for example, it can be 0.1 nm, 100 nm, 300 nm, 500 nm, 1000 nm, but is not limited to the listed values.

[0110] According to an embodiment of the present application, the thickness of the first passivation layer 2 located on the sidewall and close to the first orifice and the second orifice is 0.1nm~1000nm higher than the thickness of the first passivation layer 11 located at other positions of the sidewall (located on the sidewall and away from the first orifice). For example, it can be 0.1nm, 100nm, 300nm, 500nm, 1000nm, but is not limited to the listed values.

[0111] According to an embodiment of the present application, the thickness of the first passivation layer 2 located on the first surface and the second surface is greater than the thickness of the first passivation layer 2 located at other positions of the sidewall.

[0112] According to an embodiment of the present application, the first passivation layer located at the first orifice and the second orifice includes a first passivation layer located on the side wall and close to the first orifice and / or the second orifice, and / or a first passivation layer located on the first surface and close to the first orifice and / or the second orifice; the length of the first passivation layer 2 located on the side wall and close to the first orifice and / or the second orifice along the direction perpendicular to the thickness of the silicon wafer is 0.1% to 10% of the depth of the deep hole 11.

[0113] According to an embodiment of the present application, a length of the first passivation layer 2 located on the first surface and close to the first hole and / or the second hole from the first surface toward the first hole is 0.1% to 10% of the depth of the deep hole.

[0114] Figure 5Schematic diagram of the path of sunlight reflected from the pyramid structure in a solar cell in the related art.

[0115] refer to Figure 5 As shown, the surface of the solar cell body close to the first surface of the silicon wafer is the light-receiving surface of the cell body, that is, the surface that directly contacts the incident light. Incident light with an angle of incidence greater than or equal to 45 degrees can be defined as high-angle incident light, where the incident angle of the incident light is β, and β is greater than 45 degrees.

[0116] According to the embodiments of the present application, the path of large-angle incident light reflected by the pyramid structure is short. In other words, the solar cell with a velvet structure has a good absorption effect on small-angle incident light α, but a poor absorption effect on large-angle incident light β.

[0117] Figure 6 A schematic diagram of the path of sunlight reflected from a deep hole structure in a solar cell with a passivation layer having no thickness difference provided in an embodiment of the present application.

[0118] refer to Figure 6 As shown in the figure, when high-angle incident light strikes the light-receiving surface of the solar cell body, it can undergo multiple reflections within the deep hole structure of the solar cell. This increases the optical transmission path of the high-angle incident light β and reduces the probability of high-angle incident light being reflected out of the solar cell, thereby improving the solar cell's absorption rate of high-angle incident light. However, when the incident light is reflected from the bottom surface to the hole opening, it will be directly reflected out of the hole opening, reducing the utilization rate of light in the silicon wafer.

[0119] Figure 7 A schematic diagram of the path of sunlight reflected from a deep hole structure in a solar cell provided in another embodiment of the present application.

[0120] According to an embodiment of the present application, the thickness of the first passivation layer 2 located at the first opening is greater than the thickness of the first passivation layer 2 located away from the first opening and on the sidewall and the first surface.

[0121] refer to Figure 7 As shown, large-angle incident light is irradiated onto the light-receiving surface of the solar cell body. The large-angle incident light can be reflected multiple times in the deep hole structure of the solar cell. The thickness of the first passivation layer 2 located at the first hole mouth is greater than the thickness of the first passivation layer 2 located on the side wall and the first surface away from the first hole mouth. The first passivation layer located at the hole mouth has a greater thickness, which can reflect the sunlight reflected out of the hole mouth after multiple reflections in the deep hole (the light path indicated by the dotted line in the figure) back into the deep hole, which can further increase the optical transmission path of the large-angle incident light, reduce the probability of the large-angle incident light being reflected out of the solar cell, and thus further improve the absorption rate of the solar cell for large-angle incident light.

[0122] According to the embodiments of the present application, the depth of the deep hole and the difference in thickness of the first passivation layer film at different positions can be determined according to the specific application scenario of the battery assembly including the solar cell. Specifically, for application scenarios where large-angle incident light accounts for a large proportion, the projection size of the deep hole on the surface of the battery body can be increased, or the number of deep holes can be increased, so that the ratio of the projection area of the deep hole on the surface of the battery body to the surface area of the battery body is larger; or the thickness difference of the first passivation layer film at different positions is increased, thereby increasing the absorption effect of the solar cell for large-angle incident light. For application scenarios where large-angle incident light accounts for a small proportion, the projection size of the deep hole on the surface of the battery body can be reduced, or the number of deep holes can be reduced, so that the ratio of the projection area of the deep hole on the surface of the battery body to the surface area of the battery body is smaller, so that the solar cell has a better absorption effect for the incident light.

[0123] According to an embodiment of the present application, the solar cell is a bifacial solar cell or a back-contact solar cell.

[0124] According to an embodiment of the present application, the solar cell is a solar cell with double-sided electrodes, such as a tunneling oxide passivated contact cell (Thin Oxide Passivated Contact, TOPCon), a heterojunction cell (Heterojunction with Intrinsic Thin-layer, HJT) and a passivated emitter and rear cell (Passivated Emitter and Rear Cell, PERC).

[0125] Figure 8 A schematic cross-sectional view of a bifacial solar cell according to an embodiment of the present application.

[0126] According to an exemplary embodiment of the present application, the present application provides a double-sided solar cell, referring to Figure 8 As shown, including:

[0127] A silicon wafer 1 having a first surface and a second surface relative to each other, the first surface of the silicon wafer 1 having a plurality of deep holes 11, the deep holes 11 including a first opening located on the first surface; a first passivation layer 2 located at least on the first surface of the silicon wafer 1 and the sidewalls of the deep holes; wherein the thickness of the first passivation layer 2 located at the first opening is greater than the thickness of the first passivation layer 2 located away from the first opening and on the sidewalls and the first surface.

[0128] According to an embodiment of the present application, the first passivation layer 2 is also located on the bottom surface of the deep hole 11. The first electrode 3 is located at a non-deep hole position on the first surface, or the first electrode 3 covers a portion of the deep hole.

[0129] According to an embodiment of the present application, the above-mentioned bifacial solar cell further includes: a second passivation layer 4 located on the second surface of the silicon wafer 1 , and a second electrode 5 located on the second passivation layer 4 and electrically connected to the silicon substrate.

[0130] According to the embodiment of the present application, the material of the first passivation layer 2 is not limited here, as long as it can achieve the surface passivation or anti-reflection function of the first surface, and the thickness of the first passivation layer located on the side wall and close to the first hole is greater than the thickness of the first passivation layer located at other positions of the side wall. The first passivation layer 2 may include Al2O3, SiO2, SiN x , a single layer or stacked structure of one or more materials selected from doped polysilicon and amorphous silicon.

[0131] According to an embodiment of the present application, the first passivation layer 2 may be a multi-layer structure. For example, the first passivation layer 2 may include an Al2O3 layer and a SiN layer formed on the Al2O3 layer. x The layers respectively serve the functions of surface passivation and anti-reflection of the first surface of the solar cell.

[0132] According to an embodiment of the present application, the first passivation layer 2 sequentially includes silicon oxide, doped polysilicon, an Al 2 O 3 layer, and SiNx formed on the Al 2 O 3 layer.

[0133] According to an embodiment of the present application, the first passivation layer 2 includes intrinsic amorphous silicon and doped amorphous silicon in sequence.

[0134] According to an embodiment of the present application, the second passivation layer 4 may also be a multi-layer structure. For example, the second passivation layer 4 may include silicon oxide, doped polycrystalline silicon and silicon nitride in sequence, or may include intrinsic amorphous silicon and doped amorphous silicon in sequence, thereby realizing the second surface passivation or anti-reflection function of the solar cell.

[0135] When both the first passivation layer 2 and the second passivation layer 4 include doped polysilicon or doped amorphous silicon, their doping types are opposite.

[0136] According to an embodiment of the present application, the solar cell is a solar cell having a single-sided electrode, such as an interdigitated back contact cell (IBC).

[0137] Figure 9 A schematic cross-sectional view of a back-contact solar cell provided in an embodiment of the present application.

[0138] According to an exemplary embodiment of the present application, the present application provides a back contact solar cell, referring to Figure 9 As shown, including:

[0139] A silicon wafer 1 having a first surface and a second surface relative to each other, the first surface of the silicon wafer 1 having a plurality of deep holes 11, the deep holes 11 including a first opening located on the first surface; a first passivation layer 2 located at least on the first surface of the silicon wafer 1 and the sidewalls of the deep holes; wherein the thickness of the first passivation layer 2 located at the first opening is greater than the thickness of the first passivation layer 2 located away from the first opening and on the sidewalls and the first surface.

[0140] According to an embodiment of the present application, the battery body includes a silicon wafer 1, a first passivation layer 2 formed on a first surface of the silicon wafer 1, and a second passivation layer 8, a third electrode 10 and a fourth electrode 20 arranged on a second surface of the silicon wafer 1.

[0141] According to an embodiment of the present application, the first passivation layer 2 is disposed on the bottom surface and sidewalls of the deep hole 11, and is also disposed on the region of the silicon wafer 1 where the deep hole 11 is not formed. The second passivation layer 8 is disposed on the second surface of the silicon wafer 1, and the third electrode 10 and the fourth electrode 20 are located on the second surface.

[0142] According to the embodiment of the present application, the first passivation layer 2 may be a single layer or a multi-layer structure. For example, the first passivation layer 2 may include SiO2, SiN x , Al2O3, a single layer or stacked layer structure of one or more materials plays the role of surface passivation and anti-reflection of the first surface of the solar cell.

[0143] According to an embodiment of the present application, the first passivation layer 2 includes an Al2O3 layer and a SiN layer formed on the Al2O3 layer. x .

[0144] According to an embodiment of the present application, the second passivation layer 8 is a single layer or a stacked layer structure formed by one or more of silicon nitride and aluminum oxide. The second passivation layer 8 can play the role of surface field passivation and anti-reflection of the second surface of the solar cell.

[0145] According to an embodiment of the present application, a first dielectric layer 61 and a first transmission layer 71 may be provided between the third electrode 10 and the silicon wafer 1, the first dielectric layer 61 being provided on the second surface of the silicon wafer 1, and the first transmission layer 71 being provided on the side of the first dielectric layer 61 away from the silicon wafer 1; a second dielectric layer 62 and a second transmission layer 72 are provided between the fourth electrode 20 and the silicon wafer 1, the second dielectric layer 62 being provided on the second surface of the silicon wafer 1, and the second transmission layer 72 being provided on the side of the second dielectric layer 62 away from the silicon wafer 1.

[0146] According to an embodiment of the present application, when the silicon wafer 1 uses an n-type crystalline silicon wafer, the first transmission layer 71 can be n-type doped polysilicon, the second transmission layer 72 can be p-type doped polysilicon, and the first dielectric layer 61 and the second dielectric layer 62 are alternately arranged on the second surface of the silicon wafer 1.

[0147] According to an embodiment of the present application, when the first transmission layer 71 and the second transmission layer 72 are doped polysilicon, the first dielectric layer 61 and the second dielectric layer 62 are silicon oxide.

[0148] According to an embodiment of the present application, when the first transmission layer 71 and the second transmission layer 72 are doped amorphous silicon, the first dielectric layer 61 and the second dielectric layer 62 are intrinsic amorphous silicon.

[0149] According to an exemplary embodiment of the present application, the present application provides a solar cell assembly including the above-mentioned solar cell.

[0150] Figure 10 A schematic flow chart of a method for manufacturing a solar cell provided in an embodiment of the present application.

[0151] According to an exemplary embodiment of the present application, the present application provides a method for manufacturing a solar cell, referring to Figure 10 As shown, it includes: operation S01 to operation S02.

[0152] In operation S01 , a silicon wafer 1 having a plurality of deep holes 11 is prepared. The deep holes 11 include first openings located on a first surface of the silicon wafer 1 .

[0153] According to an embodiment of the present application, a plurality of deep holes 11 are prepared on the first surface of the silicon wafer 1 using laser or DRIE technology, and the depth of the deep holes 11 is less than or equal to the thickness of the silicon wafer 1 .

[0154] In operation S02 , a first passivation layer 2 is deposited on the first surface of the silicon wafer 1 , so that the thickness of the first passivation layer 2 at the first opening is greater than the thickness of the first passivation layer 2 away from the first opening and located on the sidewall and the first surface.

[0155] According to an embodiment of the present application, the first passivation layer 2 is deposited on the first surface of the silicon wafer 1 by chemical deposition or physical deposition.

[0156] According to an embodiment of the present application, the first passivation layer 2 includes but is not limited to any one or more of hydrogenated amorphous silicon, polysilicon, silicon oxide, aluminum oxide, and silicon nitride.

[0157] According to an embodiment of the present application, the first passivation layer 2 includes a plurality of passivation layers, and the preparation processes of different passivation layers in the multi-layer passivation layers are different. Silicon oxide is usually prepared by thermal oxidation, and amorphous silicon and polycrystalline silicon are usually prepared by chemical vapor deposition (CVD). For example, polycrystalline silicon is generally prepared by low-pressure chemical vapor deposition (LPCVD), aluminum oxide is usually prepared by atomic layer deposition (ALD), and silicon nitride is usually prepared by plasma-enhanced chemical vapor deposition (PECVD).

[0158] According to the embodiments of the present application, the thickness difference range of the first passivation layer located at different positions is the thickness difference of a single film layer or a stacked layer, wherein the thickness difference between the amorphous silicon / polycrystalline silicon layer located on the sidewall and near the hole mouth and the amorphous silicon / polycrystalline silicon layer located at other positions of the sidewall is 0.1~50nm, and the thickness difference between the silicon nitride layer located on the sidewall and near the hole mouth and the silicon nitride layer located at other positions of the sidewall is 0.1~100nm.

[0159] According to the solar cell provided in the above-mentioned embodiment of the present application, by setting a plurality of deep holes on the first surface of the silicon wafer, the number of reflections of large-angle incident light in the deep holes can be increased, thereby increasing the optical transmission path of large-angle incident light and reducing the probability of large-angle incident light being reflected out of the solar cell, thereby improving the absorption rate of the solar cell for large-angle incident light.

[0160] According to the solar cell provided in the above-mentioned embodiment of the present application, the thickness of the first passivation layer located at the hole mouth is greater than the thickness of the first passivation layer located away from the hole mouth and located on the side wall and the first surface. The first passivation layer located at the hole mouth has a greater thickness, which can reflect the sunlight reflected out of the hole mouth after multiple reflections in the deep hole into the deep hole again, and can further increase the optical transmission path of large-angle incident light in the deep hole, reduce the probability of large-angle incident light being reflected out of the solar cell, and help to further increase the absorption rate of the solar cell for large-angle incident light.

[0161] The use of ordinal numbers such as "first," "second," and "third" in the specification and claims to modify corresponding elements does not in itself mean that the elements have any ordinal number, nor does it represent the order of one element relative to another or the order in the manufacturing method. The use of such ordinal numbers is only used to clearly distinguish one element with a certain name from another element with the same name.

[0162] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of this application. It should be understood that the above is only a specific embodiment of this application and is not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A solar cell, characterized in that: include: A silicon wafer (1), the silicon wafer (1) having a first surface and a second surface opposite to each other, the first surface of the silicon wafer having a plurality of deep holes (11), the deep holes (11) including a first opening located on the first surface; as well as A first passivation layer (2) is located at least on the first surface of the silicon wafer (1) and the sidewall of the deep hole; The thickness of the first passivation layer (2) located at the first opening is greater than the thickness of the first passivation layer (2) located away from the first opening and on the sidewall and the first surface.

2. The solar cell according to claim 1, wherein The thickness of the first passivation layer (2) located on the sidewall and close to the first orifice is greater than the thickness of the first passivation layer (2) located on the sidewall and the first surface and away from the first orifice.

3. The solar cell according to claim 1, wherein The thickness of the first passivation layer (2) located on the first surface is greater than the thickness of the first passivation layer (2) located on the sidewall and away from the first hole.

4. The solar cell according to claim 1, wherein The ratio of the depth of the deep hole (11) to the thickness of the silicon wafer (1) is in the range of 50% to 90%.

5. The solar cell according to claim 1, wherein The deep hole (11) is a blind hole, and the first passivation layer (2) is also located on the bottom surface of the deep hole (11). The thickness of the first passivation layer (2) located on the bottom surface of the deep hole (11) is smaller than the thickness of the first passivation layer (2) located on the side wall and away from the first hole opening.

6. The solar cell according to claim 1, wherein The first passivation layer (2) located at the first orifice includes a first passivation layer (2) located on the sidewall and close to the first orifice, and / or a first passivation layer (2) located on the first surface and close to the first orifice; The length of the first passivation layer (2) located on the side wall and close to the first hole opening is 0.1% to 10% of the depth of the deep hole (11); And / or, the length of the first passivation layer (2) located on the first surface and close to the first hole opening is 0.1% to 10% of the depth of the deep hole (11).

7. The solar cell according to claim 1, wherein The deep hole (11) comprises one of a cylindrical, conical and truncated cone shape or any combination thereof.

8. The solar cell according to claim 1, wherein The diameter of the deep hole (11) ranges from 20 μm to 200 μm.

9. The solar cell according to claim 1, wherein The thickness of the first passivation layer (2) ranges from 0.1 nm to 1000 nm.

10. The solar cell according to claim 1, wherein The deep hole (11) is a through hole, and the deep hole (11) further comprises a second opening located on the second surface; The solar cell further comprises: A second passivation layer is located on the second surface of the silicon wafer and the sidewall of the deep hole (11); The thickness of the second passivation layer located at the second opening is greater than the thickness of the second passivation layer located away from the second opening and located on the sidewall and the second surface.

11. The solar cell according to claim 10, characterized in that The thickness of the second passivation layer located on the sidewall and close to the second orifice is greater than the thickness of the second passivation layer (2) located on the sidewall and the second surface and away from the second orifice.

12. A solar cell, characterized in that: include: A silicon wafer (1), the silicon wafer (1) having a first surface and a second surface opposite to each other, the silicon wafer having a plurality of deep holes (11) penetrating the silicon wafer, the deep holes (11) comprising a first opening located on the first surface and a second opening located on the second surface; as well as a first passivation layer (2) covering the first surface of the silicon wafer (1), the second surface of the silicon wafer (1), and the sidewalls of the deep hole (11); The thickness of the first passivation layer (2) located at the first orifice and the second orifice is greater than the thickness of the first passivation layer (2) located away from the first orifice and the second orifice and located at the side wall, the first surface and the second surface.

13. The solar cell according to claim 12, wherein: The thickness of the first passivation layer (2) located on the sidewall and close to the first hole is greater than the thickness of the first passivation layer (2) located away from the first hole and on the sidewall and the first surface.

14. The solar cell according to claim 12, wherein: The thickness of the first passivation layer (2) located on the first surface and the second surface is greater than the thickness of the first passivation layer (2) located away from the first hole and on the side wall.

15. The solar cell according to claim 12, wherein: The first passivation layer located at the first orifice and the second orifice includes a first passivation layer located on the sidewall and close to the first orifice and / or the second orifice, and / or a first passivation layer located on the first surface and close to the first orifice and / or the second orifice; The length of the first passivation layer (2) located on the sidewall and close to the first hole opening and / or the second hole opening is 0.1% to 10% of the depth of the deep hole; And / or, the length of the first passivation layer (2) located on the first surface and close to the first hole opening and / or the second hole opening is 0.1% to 10% of the depth of the deep hole.

16. A solar cell module, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 15.

Citation Information

Patent Citations

  • Photovoltaic cell and photovoltaic assembly

    EP4250373A1

  • Through wafer via structures for concentrated photovoltaic cells

    US8866002B1

  • Vertical pillar structured photovoltaic devices with mirrors and optical claddings

    WO2012065048A1