State switching method and apparatus for processor, electronic device, and storage medium

Abstract

The application discloses a state switching method of a processor, which is applied to a processor driving layer. The method can comprise the following steps: copying first cache data in a first storage unit of the processor to a first storage position when the processor is in an idle state; the first storage position is located in a second storage unit outside the processor; switching a first cache pointer pointing to the first cache data to the first storage position; switching a state of the processor from a first working state to a second working state; power consumption of the processor in the second working state is less than that in the first working state; and the processor is used for reading the first cache data from the first storage position based on the first cache pointer and displaying.

Description

TECHNICAL FIELD

[0001] The present application relates to, but is not limited to, the technical field of computer technology, and in particular to a state switching method and device of a processor, an electronic device, and a storage medium. BACKGROUND

[0002] During the running of a graphics processing unit (GPU), the video memory on a graphics card is usually one of the modules with the highest power consumption, accounting for 40% of the entire GPU power consumption. At present, the GPU can reduce the frequency and voltage under low performance demand and enter a low power consumption state; however, the video memory still needs to be accessed and operated in the low power consumption state. In order to normally access and operate the video memory without affecting the display function of the display screen, the degree of frequency and voltage reduction is limited, resulting in a still high power consumption of the GPU. SUMMARY

[0003] Embodiments of the present application provide a state switching method and device of a processor, an electronic device, and a storage medium, which can reduce the power consumption of a storage unit in the processor and thus reduce the power consumption of the processor.

[0004] The technical solution of the present application is implemented as follows:

[0005] Embodiments of the present application provide a state switching method of a processor, applied to a processor driver layer, comprising:

[0006] In a case where the processor is in an idle state, first cache data in a first storage unit of the processor is copied to a first storage location; the first storage location is located in a second storage unit outside the processor; a first cache pointer pointing to the first cache data is switched to the first storage location; the state of the processor is switched from a first working state to a second working state; the power consumption of the processor in the second working state is less than that in the first working state; and the processor is configured to read the first cache data from the first storage location based on the first cache pointer and display.

[0007] Embodiments of the present application provide a state switching device of a processor, comprising:

[0008] A copying module is configured to copy first cache data in a first storage unit of the processor to a first storage location in a case where the processor is in an idle state; the first storage location is located in a second storage unit outside the processor.

[0009] A switching module is configured to switch a first cache pointer pointing to the first cache data to the first storage location.

[0010] The switching module is further configured to switch the state of the processor from a first working state to a second working state, the power consumption of the processor in the second working state is less than that in the first working state, and the processor is configured to read the first cache data from the first storage location based on the first cache pointer and display.

[0011] The embodiment of the present application provides an electronic device, comprising:

[0012] A memory is configured to store a computer program.

[0013] A processor is configured to execute the state switching method of the processor when executing the computer program.

[0014] The embodiment of the present application provides a storage medium storing a computer program, and the computer program is configured to realize the state switching method of the processor when the processor executes.

[0015] The embodiment of the present application provides a state switching method, device, electronic device and storage medium of a processor. Since the processor driver layer copies the first cache data of the current display screen from the first storage unit to the first storage location outside the processor, and switches the pointing of the first cache pointer pointing to the first cache data to the first storage location, when the processor is in an idle state and enters a second working state, the first storage location outside the processor can be accessed to obtain the first cache data, so that the display screen can be normally displayed without accessing the first storage unit. In this way, when the processor enters the second working state, not only the frequency and voltage of the processor can be reduced, but also the power supply of the first storage unit can be reduced, so that the power consumption of the processor can be reduced.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the technical solutions of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0017] The drawings incorporated into the specification and forming a part of the specification, show embodiments consistent with the present application, and together with the specification, serve to explain the technical solutions of the present application.

[0018] Figure 1 A state switching method of a processor provided by the embodiment of the present application Figure 1 ;

[0019] Figure 2 A state switching method of a processor provided by the embodiment of the present application Figure 1 ;

[0020] Figure 3 A state switching method of a processor provided by the embodiment of the present applicationFigure 2 ;

[0021] Figure 4 A flowchart of a state switching method of a processor provided for an embodiment of the present application Figure 2 ;

[0022] Figure 5 A flowchart of a state switching method of a processor provided for an embodiment of the present application Figure 3 ;

[0023] Figure 6 A flowchart of a state switching method of a processor provided for an embodiment of the present application Figure 4 ;

[0024] Figure 7 A structural composition diagram of a state switching device of a processor provided for an embodiment of the present application

[0025] Figure 8 A structural composition diagram of an electronic device provided for an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present application clearer, the following will further describe the present application in conjunction with the accompanying drawings, and the described embodiments should not be regarded as limiting the present application, and all other embodiments obtained by those skilled in the art without making creative efforts fall within the scope of protection of the present application.

[0027] In the following description, "some embodiments" are related to a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0028] In the following description, the terms "first\second\third" are only to distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that "first\second\third" can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application, and are not intended to limit the present application.

[0030] For the purpose of understanding the present application, before the embodiments of the present application are described, the application background in the embodiments of the present application is described.

[0031] In the related art, the frequency and voltage of a processor core are generally reduced when the performance requirement of the processor is low, so as to control the frequency and voltage of the processor (such as a graphics card) and reduce the power consumption of the processor. For example, taking a graphics processor as an example, when the performance requirement is high, the frequency of the processor core is 1800 MHZ, and the voltage is the highest. At this time, the memory, that is, the transmission rate of the graphics double data rate (GDDR) is 16 Gbps. After entering the low-power state (the second working state), the frequency of the processor core is 300 MHZ, the voltage is 1 / 3 of the original, and the transmission rate of the GDDR is reduced to 1 Gbps. It should be noted that the cache pointer generally points to the storage location of the display data of the current display image in the memory. After the memory is reduced in frequency, in order to ensure the normal display function of the display, the storage location pointed to by the cache pointer needs to be accessed, and the display data in the storage location is read for display. Therefore, the degree of reduction of the frequency and voltage of the graphics card is limited, resulting in that the power consumption of the processor in the second working state is still high; and when the memory needs to be operated and data is written, in order to reduce the problem of display flicker or screen flashing, the operation time needs to be short enough and cannot affect the access of the memory, resulting in that the tolerance requirement for the operation time of the memory is high. If the operation time is to be ensured to be short enough, not only a special GDDR needs to be used, but also a GDDR team needs to spend a lot of time to adjust and verify various parameters of the special GDDR.

[0032] To solve the above problems, an embodiment of the present application provides a processor state switching method and device, an electronic device and a storage medium. The state switching method is arranged in the processor driving layer of the electronic device. The electronic device can be a device provided with a processor and display function, such as a notebook computer, a tablet computer, a desktop computer, a smart television, a mobile device (such as a mobile phone, a portable video player, a personal digital assistant, a portable game device), etc.

[0033] Figure 1 An optional flowchart of a processor state switching method is shown, as shown in Figure 1 The method can include the following steps.

[0034] S101, in the case where the processor is in an idle state, copying first cache data in a first storage unit of the processor to a first storage location; the first storage location is located in a second storage unit outside the processor.

[0035] In the embodiments of the present application, the first cache data is display data of a current display screen on the display screen. In some embodiments, the first cache data can be display data of a frame of the current display screen. When determining that the processor is in the idle state, the processor driver layer can copy the first cache data in the first storage unit to a first storage location in a second storage unit other than the processor, and switch a first cache pointer of the first cache data to the first storage location. In this way, the processor driver layer does not need to access the first storage unit in the processor, but can obtain the first cache data by accessing the first storage location in the second storage unit. Here, the second storage unit can be a system memory or a running memory, and the embodiments of the present application do not limit this.

[0036] In some possible implementation manners, the first storage unit is an on-chip storage unit of the processor. For example, if the processor is a graphics processor, the first storage unit can be a display memory.

[0037] In some embodiments, the processor driver layer can obtain an idle duration of the processor, and determine that the processor is in the idle state when the idle duration is greater than or equal to an idle threshold. In the embodiments of the present application, the idle threshold can be set according to actual needs, and the embodiments of the present application do not limit this.

[0038] In some embodiments, the first storage location can be a free storage location in the second storage unit. In some embodiments, the processor can determine the first storage location in the second storage unit according to the size of the first cache data, and the first storage location is used to represent a continuous free storage space in the second storage unit. Here, the manner of determining the first storage location can be set according to actual needs, and the embodiments of the present application do not limit this.

[0039] In the embodiments of the present application, the processor driver layer can interact with a system (Operating System, OS), receive a system instruction from the system, store the system instruction in an instruction queue, and sequentially issue the system instruction to a firmware system running on the second storage unit. The firmware system distributes the system instruction to a target component in the processor, and each target component executes the instruction. For example, when any application is started and the current display screen on the display screen needs to be changed, a system instruction can be received. When the processor executes the system instruction, the processor is in the first working state.

[0040] In the embodiments of the present application, the processor driver layer can also receive a screen refresh indication. In response to the screen refresh indication, the second storage unit is accessed, the display data of the current display screen is read from the second storage unit, and the current display screen is obtained based on the display data. For example, if the time display precision on the display screen is minute, the processor driver layer can receive a screen refresh indication when changing from 12:00 to 12:01; if the time display precision on the display screen is date, the processor driver layer can receive a screen refresh indication when changing from “2024 / 06 / 12” to “2024 / 06 / 13”. When the processor driver layer receives the screen refresh indication, the processor driver layer can be in the first working state.

[0041] In some embodiments, the power consumption of the processor in the second working state is less than the power consumption in the first working state.

[0042] In some possible implementations, the processor is in the second working state, i.e., the processor is not in the first working state, which means that the first storage unit of the processor is not accessed or operated. The processor driver can determine that the processor is idle when it is determined that all system instructions are executed and no screen refresh indication is received. In some embodiments, the processor driver layer can determine that all system instructions are executed when there is no system instruction to be executed in the instruction queue and no audio / video component is running in the processor.

[0043] S102, switching the first cache pointer pointing to the first cache data to the first storage location.

[0044] In the embodiments of the present application, the storage location of the first cache data is the location pointed to by the first cache pointer. The processor driver layer includes a display driver layer, which is responsible for driving various target components and can also switch the location pointed to by the first cache pointer. Here, the processor driver layer can record the storage location of the first cache data in the first storage unit, i.e., the second storage location. After the processor driver layer copies the first cache data to the first storage location, the processor driver layer can switch the location pointed to by the first cache pointer from the second storage location to the first storage location. In this way, when the processor driver layer needs to read the first cache data, the processor driver layer reads from the location pointed to by the first cache pointer, i.e., the first storage location, instead of reading the first cache data in the first storage unit (such as the video memory), thereby avoiding accessing the first storage unit.

[0045] S103, switching the state of the processor from the first working state to the second working state; the power consumption of the processor in the second working state is less than the power consumption in the first working state; and the processor is configured to read the first cache data from the first storage location based on the first cache pointer and display.

[0046] In the embodiments of the present application, the processor driving layer can switch the state of the processor from the first working state to the second working state when the processor is in an idle state.

[0047] In some embodiments, the switching of the state of the processor from the first working state to the second working state comprises at least one of the following:

[0048] reducing the frequency of the processor;

[0049] reducing the voltage of the processor;

[0050] setting the first storage unit of the processor to a lowest power consumption state; the first storage unit in the lowest power consumption state is used to maintain data without loss.

[0051] In some embodiments, the running parameters of the processor in the second working state are less than those in the first working state; the running parameters comprise the frequency, the voltage, and the power supply of the first storage unit.

[0052] In some embodiments, the power consumption state of the first storage unit can be reflected by the power supply of the first storage unit. When the power supply of the first storage unit is the second power supply, the first storage unit is set to the lowest power consumption state.

[0053] In some possible implementations, in the first working state, the frequency of the processor is the first frequency, the voltage is the first voltage, and the power supply of the first storage unit is the first power supply; in the second working state, the frequency of the processor is the second frequency, the voltage is the second voltage, and the power supply of the first storage unit is the second power supply. The second frequency is less than the first frequency, the second voltage is less than the first voltage, and the second power supply is less than the first power supply.

[0054] In some embodiments, the second power supply can be the lowest power supply, which is only used to maintain the power supply for data storage in the first storage unit; it is equivalent to powering off the first storage unit, but the data is still retained. In some embodiments, the second power supply can be set according to actual needs, and the embodiments of the present application do not make any limitation. In some embodiments, the first storage unit in the second power supply can be understood as the first storage unit in a power down state.

[0055] In the embodiments of the present application, the first frequency, the first voltage, and the first power supply, and the second frequency, the second voltage, and the second power supply can be set according to actual needs, and the embodiments of the present application do not make any limitation.

[0056] In the second working state, the processor driving layer does not execute system instructions and does not refresh the screen, but can acquire the first cache data in the first storage location to maintain the display of the current display screen on the display screen without accessing the first storage unit.

[0057] It can be understood that, since the processor driving layer copies the first cache data of the current display screen from the first storage unit to the first storage location outside the processor and switches the pointing of the first cache pointer pointing to the first cache data to the first storage location, when the processor enters the second working state due to the idle state of the processor, the first cache data in the first storage location outside the processor can be accessed to maintain the normal display of the display screen without accessing the first storage unit. In this way, when the processor enters the second working state, not only the frequency and voltage of the processor can be reduced, but also the power supply of the first storage unit can be reduced, so that the power consumption of the processor is reduced. The present application realizes the first case of entering a low-power-consumption state to make the second storage unit (GDDR) in a power down state, breaks through the bottleneck that the GDDR can only be reduced in frequency but cannot be powered down, and makes the power consumption of the processor lower when in a low-power-consumption state.

[0058] In some embodiments of the present application, the method can further include:

[0059] S1011, in a case where the idle duration of the processor satisfies a duration threshold, determining that the processor is in an idle state.

[0060] The idle duration includes a duration for which the processor is idle; and the processor is determined to be idle in a case where one or more of the following conditions is satisfied:

[0061] There is no system instruction to be executed;

[0062] No screen refresh instruction is received;

[0063] A target component in the processor is not running; the target component is a component that uses the storage location when running.

[0064] In some embodiments, the processor driving layer can determine whether there is a system instruction to be executed in the instruction queue, obtain a first determination result, determine whether a refresh instruction is received by the screen, obtain a second determination result, and determine whether a target component in the processor is running, obtain a third determination result. The target component in the processor is a component that uses the storage location when running. In a case where the first determination result indicates that there is no system instruction to be executed in the instruction queue, the second determination result indicates that no refresh instruction is received, and the third determination result indicates that the target component is not running, the processor driving layer can determine that the processor is idle.

[0065] In some embodiments, in the case that the processor is a graphic processor, the target component can be an audio component and a video component.

[0066] In some embodiments, the processor driver layer can obtain the first judgment result, the second judgment result and the third judgment result in a preset judgment order. The preset judgment order can be set as needed, and the embodiments of the present application do not limit it.

[0067] In some embodiments, the idle duration is determined by an idle timer. The idle timer is started in response to the processor being idle, and the idle timer is stopped in response to the processor exiting the idle state.

[0068] In the embodiments of the present application, the processor can take the duration of the idle state of the processor as the idle duration. In this way, the processor can identify whether the processor is idle according to the idle condition, and then obtain the idle duration of the processor, which can improve the accuracy of determining the idle duration.

[0069] In some embodiments of the present application, in the case that the processor is determined to be idle, the idle timer is started to time, and the timing duration of the idle timer is the idle duration.

[0070] It should be noted that the timing duration of the idle timer is set and can be set by the processor driver layer. When the idle timer times according to the timing duration, the low-power operation is triggered after the timing duration (i.e. the idle duration) expires. Here, the timing duration of the idle timer is understood as the idle duration. The driver layer does not need to obtain the idle duration, and the timer will not enter the low-power state until the timing duration expires.

[0071] In the embodiments of the present application, after the processor driver layer determines that the processor is idle, the idle timer is started, the idle timer starts timing, and the timing duration is obtained. The timing duration is the idle duration.

[0072] In some embodiments, the idle timer can issue a timing prompt when the timing duration is greater than or equal to the idle threshold, i.e. the timing duration expires. The processor driver layer can determine that the idle duration is greater than or equal to the idle threshold when the timing prompt is received, i.e. the timing of the idle timer expires. Then, the first cache data is copied to the first storage location, the position pointed to by the first cache pointer is switched, and the state of the processor is switched to the second working state.

[0073] Exemplarily, Figure 2 A process of determining an idle duration is shown, as shown in Figure 2 The process can include:

[0074] S11, take the first to-be-executed instruction in the instruction queue as a current system instruction, and execute the current system instruction.

[0075] In S11, the to-be-executed instructions in the instruction queue are stored in the order of reception, and the first to-be-executed instruction refers to the one with the earliest reception order in the instruction queue. After the processor driver layer issues the first to-be-executed instruction in the instruction queue to the firmware system, the firmware system will issue the instruction to the target component for execution. At this time, the next to-be-executed instruction of the original first to-be-executed instruction in the instruction queue will become the new first to-be-executed instruction.

[0076] S12, judge whether the current system instruction is executed; if yes, execute S13, otherwise continue to execute S12.

[0077] S13, judge whether the instruction queue is empty; if yes, execute S14, otherwise execute S11.

[0078] In S13, if the instruction queue is not empty, it indicates that there are still to-be-executed instructions in the instruction queue, and the processor driver layer needs to continue to issue the new first to-be-executed instruction in the instruction queue as a new current system instruction, and execute the new current system instruction. It should be noted that in the case where the target component of the new current system instruction is not running, the firmware system can directly issue the new current system instruction; in the case where the target component of the new current system instruction is running, the firmware system needs to wait until the target component finishes running before issuing the new current system instruction.

[0079] S14, judge whether a screen refresh instruction is received; if yes, execute S16, otherwise execute S15.

[0080] In S14, if the processor driver layer receives the screen refresh instruction, it needs to access the first storage unit to obtain new first cache data, display a new current display screen by using the new first cache data, and realize screen refresh.

[0081] S15, judge whether the target component is idle; if yes, execute S17, otherwise execute S18.

[0082] In S15, the target component (such as the video component and the audio component) is idle, indicating that all to-be-executed instructions of the processor are executed.

[0083] S16, read new first cache data, display a current display screen based on the new first cache data, and go to S11.

[0084] S17, start an idle timer according to an idle duration.

[0085] S18, wait until the target component finishes running, and execute S11.

[0086] In S18, the processor driver layer can receive a system instruction and / or a screen refresh instruction during the waiting time for the end of the running of the target component. Thus, after the running of the target component ends, the processor driver layer needs to start the determination process of the idle time length from S11 again.

[0087] In some embodiments of the present application, the processor driver layer can close the idle timer if the system instruction or the screen refresh instruction is received when the idle timer is started.

[0088] In the embodiments of the present application, if the system instruction or the screen refresh instruction is received after the idle timer is started, the processor driver layer needs to execute the system instruction and re-read the display data of the current display screen, that is, the processor needs to enter the first working state. At this time, the processor driver layer can close the idle timer. It should be noted that after the idle timer is closed, the timing time is set to 0, and the timing starts from 0 next time the idle timer is started. Thus, in the case that the duration of the idle processor is less than the idle threshold, the processor driver layer can timely close the idle timer, thereby improving the accuracy of the idle time length.

[0089] Based on Figure 2 , Figure 3 An idle time length determination process is shown, which can further include the following steps after S17, as shown in Figure 3

[0090] S19, receiving a screen refresh instruction.

[0091] S20, receiving a system instruction.

[0092] S21, closing the idle timer.

[0093] In the embodiments of the present application, the processor driver layer can receive the screen refresh instruction and / or the system instruction at any time. If the screen refresh instruction and / or the system instruction is received in the first working state, the processor driver layer needs to determine whether the idle timer is started. If yes, the idle timer needs to be closed; otherwise, the screen refresh instruction and / or the system instruction is executed.

[0094] In some embodiments of the present application, the power supply of the first storage unit is the minimum power supply; the minimum power supply is used to meet the data storage requirement of the first storage unit; before the state of the processor is switched from the first working state to the second working state in S103, the processor driver layer can also stop running the firmware system; the firmware system runs on the first storage unit.

[0095] ​In the embodiment of the present application, after the processor enters the second working state, the processor driver layer can not process the system instruction, and thus can not issue the system instruction to the firmware system. In this way, the processor driver layer can also stop running the firmware system before entering the second working state, further reducing the power supply requirement of the first storage unit.

[0096] In the embodiment of the present application, in the second working state, the power supply of the first storage unit can be the minimum power supply, which is only used to meet the data storage requirement of the first storage unit, so that the data in the first storage unit can be retained. Thus, the power consumption of the processor is further reduced.

[0097] Based on Figure 2 , Figure 4 A state switching process of a processor is shown, as shown in FIG. 1, the process can include: Figure 4

[0098] S31, the time length is greater than or equal to the idle threshold

[0099] In the embodiment of the present application, the idle threshold is the value when the time length expires.

[0100] S32, the first cache data is copied to the first storage location.

[0101] In S32, the second storage unit where the first storage location is located can be the system memory.

[0102] S33, the position pointed to by the first cache pointer is switched to the first storage location.

[0103] S34, the firmware system is stopped running.

[0104] In S34, the processor driver layer can execute S34 and S32-S33 at the same time, can execute S34 first and then execute S32-S33, or can execute S32-S33 first and then execute S34. The embodiment of the present application does not limit this.

[0105] S35, the frequency, voltage and power supply of the first storage unit of the processor are reduced, and the processor enters the second working state.

[0106] In S35, the power supply of the first storage unit is the minimum power supply, and the minimum power supply is only used to retain the data stored on the first storage unit; that is, the first storage unit of the processor is set to the minimum power consumption state; the first storage unit in the minimum power consumption state is used to maintain the data without loss.

[0107] ​In this embodiment, in the second operating state, not only are the processor's clock frequency and voltage reduced, but the power supply to the first storage unit is also adjusted to the minimum power supply, so that the operating requirements of the firmware system are not required, which can significantly reduce the processor's power consumption.

[0108] In some embodiments of this application, the implementation after switching the processor state from the first working state to the second working state in S103 is as follows: Figure 5 As shown, it may include:

[0109] S201. In response to the processor exiting the idle state, the state of the processor is switched from the second working state to the first working state.

[0110] The processor exits the idle state if at least one of the following conditions is met:

[0111] Received system instructions to be executed;

[0112] Received screen refresh instruction;

[0113] The target component in the processor begins to run.

[0114] In some embodiments, upon receiving a system instruction or screen refresh instruction, or upon the target component starting to run, the processor state is switched from a second operating state to a first operating state.

[0115] In this embodiment, after the processor enters the second operating state, if the processor driver layer receives a system instruction or screen refresh instruction, or the target component starts running, it needs to switch the processor back to the first operating state. The processor driver layer needs to switch the main frequency from the second frequency back to the first frequency, the voltage from the second voltage back to the first voltage, and the power supply of the first memory unit from the second power supply back to the first power supply, thereby ensuring the normal operation of the processor.

[0116] S202. Switch the location pointed to by the first cache pointer from the first storage location back to the second storage location; the second storage location is the location of the first cached data in the first storage unit.

[0117] In this embodiment, after the processor switches back to the first operating state, the first storage unit can be accessed normally. The processor driver layer needs to switch the location pointed to by the first cache pointer from the first storage location back to the location of the first cached data in the first storage unit, i.e., the second storage location. Specifically, when the processor enters the second operating state, the processor driver layer needs to record the second storage location so that when the processor re-enters the first operating state, the location pointed to by the first cache pointer can be switched back.

[0118] It can be understood that, in the case that the processor needs to execute a system instruction or perform a screen refresh, the processor driver layer can increase the frequency, voltage and power supply, and then restore the first cache pointer to the second storage location, so as to restore the processor to the first working state. In this way, the processor driver layer can flexibly switch between the second working state and the first working state according to the actual working condition of the processor, and save the power consumption of the processor while ensuring the normal working of the processor.

[0119] Exemplarily, the electronic device is a notebook computer. In the case that the notebook computer is not operated by a user, the current display screen does not change, and the processor is in an idle state after meeting the conditions of the above embodiments. In the case that the processor is in the idle state, the processor driver layer can switch the processor to the second working state. In the second working state, the processor is reduced in frequency, voltage and power supply. That is, in the case that the user does not operate the computer, the power consumption of the processor can be greatly reduced due to the reduced power supply of the first storage unit. In the case that the power supply of the first storage unit is only the minimum power supply, 80% of the power consumption can be saved, and the power consumption of the processor is only a few watts, which is reduced by 95%. In this way, the heat generated by the notebook computer is greatly reduced, which can play a role in protecting the motherboard and prolonging the service life of the motherboard. After the processor enters the second working state, if the user operates the mouse, for example, opens the recycle bin, or an application program such as a game, the processor driver layer can receive a corresponding system instruction; or when the time displayed on the display screen changes, the processor driver layer can receive a screen refresh instruction. At this time, the processor driver layer can switch the processor from the second working state back to the first working state. Since the first storage unit is not accessed in the second working state, the power consumption can be reduced to the minimum, greatly reducing the power consumption of the processor. The switching of the first cache pointer to the first storage location, combined with the interception of the processor driver layer to the access to the first storage unit, can ensure that there is no access to the first storage unit during the operation of the first storage unit, thereby reducing the tolerance requirement for the operation time of the first storage unit.

[0120] In some embodiments of the present application, before the state of the processor is switched from the second working state to the first working state in S201, the processor driver layer stores the system instruction in an instruction queue in the case that the system instruction is received; after the state of the processor is switched from the second working state to the first working state, the processor driver layer issues the system instruction in the instruction queue to the firmware system in the case that the instruction queue is not empty; and the system instruction is issued to the target component through the firmware system.

[0121] In the embodiments of the present application, the processor driver layer executes the system instruction only in the first working state. When the processor is in the second working state, if the processor driver layer receives the system instruction, the processor driver layer needs to store the system execution in the instruction queue first, and then execute the to-be-executed instruction in the instruction queue in sequence after the processor returns to the first working state.

[0122] In the embodiments of the present application, after the processor driver layer returns to the first working state from the second working state, it can be judged whether the instruction queue is empty. If the instruction queue is not empty, the to-be-executed instruction in the instruction queue is issued to the firmware system, and the firmware system issues the to-be-executed instruction to the target component, and then the target component executes the to-be-executed instruction.

[0123] It can be understood that in the second working state, the processor driver layer can still receive the system instruction. Since the system instruction can be stored in the instruction queue, after the processor returns to the first working state, it can still be executed in sequence according to the storage order in the instruction queue, that is, in the order of receiving the system instruction; in this way, the influence of the state switching process of the processor on the execution order of the system instruction can be reduced.

[0124] In some embodiments of the present application, before the state of the processor is switched from the second working state to the first working state in S201, the processor driver layer needs to feed back instruction receiving response information to the system in the case of receiving the system instruction. In some embodiments, the processor driver layer needs to feed back execution completion response information to the system after determining that the system instruction is executed. The system can take the time when the instruction receiving response information is received as the starting time, and take the time when the execution completion response information is received as the ending time, to obtain the execution duration of the system instruction. If the execution duration is less than the execution threshold, it indicates that the system instruction is executed successfully. If the processor driver layer has a problem in state switching or has a problem in the execution process in the first working state, it will not be able to feed back the execution completion response information in time; in this way, the system cannot receive the execution completion response information within the execution threshold duration after receiving the instruction receiving response information, and then the system can determine that the execution process of the system instruction is not smooth. The execution threshold can be set according to actual needs, and the embodiments of the present application are not limited. In this way, the system can determine the execution of the system instruction in time according to the information fed back by the processor driver layer.

[0125] Exemplarily, the execution threshold is 2s. The processor driver layer receives the system instruction 1 in the second working state, feeds back instruction receiving response information to the system, and switches the state of the processor to the first working state. Then, the system instructions in the instruction queue are sequentially issued. If the system instruction 1 has not been executed after the processor driver layer feeds back the instruction receiving response information within 2s, that is, the system fails to receive the execution completion response information within the duration of the execution threshold, it can be determined that the system instruction execution is abnormal.

[0126] In some embodiments of the present application, before the system instructions in the instruction queue are sequentially issued to the firmware system, the processor driver layer needs to reload the firmware system in the case that the firmware system stops running.

[0127] In the embodiments of the present application, if the firmware system stops running when the processor enters the second working state, the processor driver layer reloads the firmware system when switching the processor back to the first working state. In this way, the processor driver layer reduces the power consumption of the processor by stopping the running of the firmware system, and at the same time, timely restores the firmware system to ensure the execution of the system instruction.

[0128] In some embodiments, after the processor driver layer receives the system instruction, the processor driver layer can first determine whether the firmware system is running before issuing the system instruction to the firmware system. If the firmware system is running, the system instruction can be issued; if the firmware system stops running, the firmware system needs to be reloaded, and then issued after the firmware system runs.

[0129] Figure 6 A state switching process of a processor is shown, as shown in Figure 6 The process of switching the processor from the second working state to the first working state by the processor driver layer can include:

[0130] S41, determining whether a screen refresh instruction is received; if yes, performing S45; otherwise, continuing to perform S41.

[0131] S42, determining whether a system instruction is received; if yes, performing S43; otherwise, continuing to perform S42.

[0132] In the second working state of the processor, the processor driver layer can not be limited to the execution order of S41 and S42.

[0133] S43, storing the system instruction in the instruction queue.

[0134] S44, feeding back instruction receiving response information to the system.

[0135] The execution sequence of S43 and S44 can be set according to actual needs after the processor driving layer receives the system instruction. In some embodiments, S43 and S44 can be executed simultaneously.

[0136] S45, increasing the frequency, voltage and power supply of the first storage unit of the processor, and the processor enters the first working state.

[0137] S46, reloading the firmware system.

[0138] S47, switching the first cache pointer back to the second storage location.

[0139] S48, based on the first cache data in the second storage location, performing screen display.

[0140] S49, in the case where the instruction queue is not empty, sequentially issuing the to-be-executed instructions in the instruction queue to the firmware system.

[0141] The execution sequence of S48 and S49 is not limited in the embodiments of the present application. In some embodiments, both can be executed simultaneously.

[0142] It should be noted that, in the second working state, the processor receives any one of the screen refresh indication and the system instruction, and needs to adjust the frequency, voltage and power supply of the first storage unit back to the first working state. In the process of switching the processor back to the first working state due to the screen refresh indication, the system instruction can also be received. Therefore, after the processor driving layer executes S47, the processor driving layer not only needs to perform screen display based on the first cache data in the first storage unit, but also needs to determine whether the instruction queue is empty, and sequentially issue the to-be-executed instructions in the case where the instruction queue is not empty.

[0143] In some embodiments of the present application, before copying the first cache data in the first storage unit to the first storage location in the case where the processor is in the idle state in S101, the implementation can further include: in the case where it is determined that the received storage unit allocation request comes from the first application program, allocating an application storage space for the first application program in the second storage unit; the storage unit allocation request is used to request an operation space in the first storage unit; and the first application program is an application program that directly accesses the operation space through the system.

[0144] In the embodiment of the present application, the first application program is an application program that can directly access the first storage unit through the system. The first application program can access the first storage unit randomly. Since the access is not through the processor driver layer, the processor driver layer cannot block it. Thus, after the processor enters the second working state, if the first application program accesses the first storage unit, the processor driver layer cannot switch the processor back to the first working state in time, affecting the running of the first application program.

[0145] In the embodiment of the present application, the processor driver layer includes a user mode driver (UMD) layer. The first application program needs to send a storage unit allocation request to the UMD to apply for an operation space in the first storage unit. At this time, the UMD can not allocate an operation space for the first application program in the first storage unit, but allocate an application storage space for the first application program in the second storage unit outside the processor as the operation space of the first application program. Thus, the first application program can access the storage space in the second storage unit to perform data operation in the case of needing data operation. In this way, when the processor enters the second working state, even if the first storage unit cannot be accessed, the running of the first application program will not be affected.

[0146] In some embodiments, the second storage unit can be a system memory.

[0147] In some embodiments of the present application, the processor driver layer compares the application program corresponding to the storage unit allocation request with the application programs in the program list upon receiving the storage unit allocation request, to obtain a comparison result. The application programs in the program list are all the first application program. In the case that the comparison result represents that the program list includes the application program, it is determined that the storage unit allocation request comes from the first application program.

[0148] In the embodiment of the present application, the UMD can establish a program list. The application programs in the program list are all the first application program. Upon receiving a storage unit allocation request of any application program, the UMD can compare the application program with the application programs in the program list. If the application program is an application program in the program list, it can be determined that the storage unit allocation request comes from the first application program. Thus, the GPU driver layer can quickly determine the storage unit allocation request coming from the first application program, improving the response efficiency of the processor driver layer to the storage unit allocation request.

[0149] Based on the foregoing embodiments, the embodiments of the present application provide a state switching apparatus of a processor, which comprises units and modules included in the units, and can be implemented by a processor in an electronic device. Of course, the state switching apparatus of the processor can also be implemented by a specific logic circuit. In the implementation process, the processor can be a graphics processing unit (GPU), a microprocessor unit (MPU), a digital signal processor (DSP), a field programmable gate array (FPGA), or the like.

[0150] Figure 7 A state switching apparatus of a processor is shown, as shown in Figure 7 The state switching apparatus 700 can comprise:

[0151] A copying module 701 is configured to copy first cache data in a first storage unit of the processor to a first storage location when the processor is in an idle state; the first storage location is located in a second storage unit outside the processor;

[0152] A switching module 702 is configured to switch a first cache pointer pointing to the first cache data to the first storage location;

[0153] The switching module 702 is further configured to switch the state of the processor from a first working state to a second working state; the power consumption of the processor in the second working state is less than that in the first working state; the processor is used to read the first cache data from the first storage location based on the first cache pointer and display.

[0154] In some embodiments, the state switching apparatus 700 further comprises a determination module; the determination module is configured to determine that the processor is in an idle state when an idle duration of the processor satisfies a duration threshold; wherein the idle duration comprises a duration of the processor being idle.

[0155] In some embodiments, the switching module 702 is further configured to stop running a firmware system; the firmware system runs on the first storage unit.

[0156] In some embodiments, the switching of the state of the processor from the first working state to the second working state comprises at least one of the following: reducing the frequency of the processor; reducing the voltage of the processor; setting the first storage unit of the processor to a lowest power consumption state; the first storage unit in the lowest power consumption state is used to maintain data without loss.

[0157] In some embodiments, the switching module 702 is further configured to, in response to the processor exiting the idle state, switch the state of the processor from the second working state to the first working state; switch the position pointed to by the first cache pointer from the first storage location back to a second storage location; the second storage location being the position of the first cache data in the first storage unit.

[0158] In some embodiments, the state switching apparatus 700 further comprises an instruction processing module; the instruction processing module is configured to, before switching the state of the processor from the second working state to the first working state, in a case where the system instruction is received, store the system instruction in an instruction queue; after switching the state of the processor from the second working state to the first working state, in a case where the instruction queue is not empty, issue the system instruction in the instruction queue to a firmware system; issue the system instruction to a target component through the firmware system.

[0159] In some embodiments, the switching module 702 is further configured to, before sequentially issuing the system instruction in the instruction queue to the firmware system, in a case where the firmware system stops running, reload the firmware system.

[0160] In some embodiments, the state switching apparatus 700 further comprises a storage allocation module; the storage allocation module is configured to, in a case where it is determined that a received storage unit allocation request is from a first application program, allocate application storage space for the first application program in the second storage unit; the storage unit allocation request is used to request operating space in the first storage unit; the first application program is an application program that directly accesses the operating space through the system.

[0161] The above apparatus embodiments are similar to the above method embodiments in description, and have similar beneficial effects as the method embodiments. In some embodiments, the apparatus provided by the embodiments of the present application has functions or includes modules that can be used to execute the methods described in the above method embodiments. For technical details of the present application that are not disclosed in the apparatus embodiments of the present application, please refer to the description of the method embodiments of the present application.

[0162] It should be noted that, in the embodiments of the present application, if the processor state switching method described above is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product in essence or the part that contributes to the related art, which is stored in a storage medium, includes a number of instructions to make an electronic device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the methods described in the embodiments of the present application. The storage medium described above includes: a U disk, a mobile hard disk, a read-only memory (ReadOnly Memory, ROM), a magnetic disk or an optical disk, and various media that can store program codes. Thus, the embodiments of the present application are not limited to any specific hardware, software or firmware, or any combination of hardware, software and firmware.

[0163] The embodiments of the present application provide an electronic device, including a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements part or all of the steps of the above method when executing the program.

[0164] The embodiments of the present application provide a computer readable storage medium, which stores a computer program, and is used for implementing part or all of the steps of the above method when the computer program is executed by a processor. The computer readable storage medium can be transitory or non-transitory.

[0165] The embodiments of the present application provide a computer program, which includes computer readable code, and when the computer readable code is run in a computer device, a processor in the computer device executes part or all of the steps of the above method.

[0166] The embodiments of the present application provide a computer program product, which includes a non-transitory computer readable storage medium storing a computer program, and when the computer program is read and executed, part or all of the steps of the above method are implemented. The computer program product can be implemented by hardware, software or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium, and in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0167] It should be noted that the above description of the various embodiments tends to emphasize differences between the various embodiments, and the same or similar elements can be mutually referred to. The above description of the device, storage medium, computer program and computer program product embodiments is similar to the description of the method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the device, storage medium, computer program and computer program product embodiments of the present application, please refer to the description of the method embodiments of the present application.

[0168] It should be noted that, Figure 8 A schematic diagram of a hardware entity of an electronic device in an embodiment of the present application is shown in FIG. 8, which includes a processor 801, a communication interface 802 and a memory 803, wherein: Figure 8 The processor 801 generally controls the overall operation of the electronic device 800, and is configured to perform the state switching method of the processor when executing a computer program.

[0169] The communication interface 802 can enable the computer device to communicate with other terminals or servers through a network.

[0170] The memory 803 is configured to store instructions and applications executable by the processor 801, and can also cache data to be processed by the processor 801 and modules in the computer device 800 (e.g., image data, audio data, voice communication data and video communication data) that have been processed or are to be processed, which can be implemented by FLASH or Random Access Memory (RAM). The processor 801, the communication interface 802 and the memory 803 can transmit data through the bus 804.

[0171] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of each step / process does not mean the order of execution, and the execution order of each step / process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above sequence number of the embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0172] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of each step / process does not mean the order of execution, and the execution order of each step / process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above sequence number of the embodiments of the present application is only for description, not representing the advantages and disadvantages of the embodiments.

[0173] It should be noted that, in the present document, the terms "comprising", "including", or any other variant thereof are intended to cover a non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements are not required to only those elements, but can include other elements not expressly listed or inherent to such processes, methods, articles, or apparatuses. Without further limitation, an element preceded by "comprises a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0174] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The above-described device embodiments are merely illustrative. For example, the division of the units is merely a logical function division, and actual implementation can have another division manner. For example, multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the various components shown or discussed can be indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other form.

[0175] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; they can be located in one place or distributed on multiple network units; and some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0176] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0177] The above is only an embodiment of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement and improvement made within the spirit and scope of the present application shall be included in the protection scope of the present application.

Claims

1. A processor state switching method, applied to the processor driver layer, characterized in that, include: When the processor is in an idle state, the first cache data in the first storage unit of the processor is copied to the first storage location; The first storage location is located in a second storage unit outside the processor; The first cached data is the display data of the currently displayed screen; Switch the first cache pointer that points to the first cached data to the first storage location; Switch the processor's state from a first operating state to a second operating state; The processor consumes less power in the second operating state than in the first operating state; the processor is used to read the first cached data from the first storage location based on the first cache pointer and display it.

2. The state switching method according to claim 1, characterized in that, The method further includes: If the idle time of the processor meets the duration threshold, the processor is determined to be in an idle state. The idle time includes the duration during which the processor is idle.

3. The state switching method according to claim 1 or 2, characterized in that, The method further includes: Stop running the firmware system; the firmware system runs on the first storage unit.

4. The state switching method according to claim 1 or 2, characterized in that, Switching the processor's state from the first operating state to the second operating state includes at least one of the following: Reduce the processor's clock speed; Reduce the voltage of the processor; The first storage unit of the processor is set to the lowest power consumption state; the first storage unit in the lowest power consumption state is used to prevent data loss.

5. The state switching method according to claim 1 or 2, characterized in that, The method further includes: In response to the processor exiting the idle state, the state of the processor is switched from the second working state to the first working state; Switch the location pointed to by the first cache pointer from the first storage location back to the second storage location; the second storage location is the location of the first cached data in the first storage unit.

6. The state switching method according to claim 5, characterized in that, Before switching the processor's state from the second operating state to the first operating state, the method further includes: Upon receiving a system instruction, the system instruction is stored in the instruction queue; After switching the processor's state from the second operating state to the first operating state, the method further includes: If the instruction queue is not empty, the system instructions in the instruction queue are sent to the firmware system; the firmware system then sends the system instructions to the target component.

7. The state switching method according to claim 1 or 2, characterized in that, The method further includes: If it is determined that the received storage unit allocation request comes from a first application, application storage space is allocated for the first application in the second storage unit; the storage unit allocation request is used to request operating space in the first storage unit; the first application is an application that directly accesses the operating space through the system.

8. A processor state switching device, characterized in that, include: The copy module is configured to copy first cache data from the first storage unit of the processor to a first storage location when the processor is in an idle state. The first storage location is located in a second storage unit outside the processor; The first cached data is the display data of the currently displayed screen; The switching module is configured to switch the first cache pointer pointing to the first cached data to the first storage location; The switching module is further configured to switch the state of the processor from a first working state to a second working state; the power consumption of the processor in the second working state is less than the power consumption in the first working state; the processor is used to read the first cached data from the first storage location based on the first cache pointer and display it.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to perform the processor state switching method as described in any one of claims 1 to 7 when executing a computer program.

10. A storage medium, characterized in that, The processor contains a computer program for implementing the processor state switching method according to any one of claims 1 to 7 when executed by the processor.

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