Model generation method for SRAM analysis

Abstract

The application discloses a model generation method for SRAM analysis, and belongs to the technical field of semiconductors. The method comprises the following steps: acquiring a measured value data set, and calculating a three-dimensional distribution covariance matrix according to threshold voltages in the measured value data set, and then calculating a three-dimensional Mahalanobis distance; determining an equiprobable ellipsoid in a three-dimensional space according to a specified probability value, and extracting an equiprobable data set located on the surface of the equiprobable ellipsoid; calculating a two-dimensional distribution covariance matrix according to the threshold voltages and drain currents in the measured value data set, and then calculating a two-dimensional Mahalanobis distance; determining an equiprobable ellipse in a two-dimensional plane according to the specified probability value, and determining corresponding drain currents on the equiprobable ellipse; and calculating an offset value according to the threshold voltages in the equiprobable data set and the drain currents determined on the equiprobable ellipse. The model generation method for SRAM analysis provided by the application can improve the accuracy of predicting the yield.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor, and particularly relates to a model generation method for SRAM analysis. BACKGROUND

[0002] In the analysis of static random access memory (SRAM), a simulation program with integrated circuit emphasis (SPICE) can be used to simulate the SRAM. When using the SPICE model to predict the yield, five corners (typical-typical / fast-fast / slow-slow / fast-slow / slow-fast) are used. However, in the SPICE model, only four analysis points can be determined, and the unbalanced corners (fast-slow / slow-fast) are not necessarily the measured values, which results in insufficient accuracy of the unbalanced corner parameters. Since the preset sigma is located in the region surrounded by the four analysis points, the boundary values of the sigma interval are ambiguous.

[0003] In the prediction of the yield of the SARM, the deviation of the pMOS threshold voltage and the deviation of the nMOS threshold voltage in the SRAM are set on the coordinate axes of a two-dimensional plane coordinate system. In the two-dimensional plane, the window of the SRAM action range is compared with the sigma interval, and the margin of the sigma interval is calculated for the window of the action range. However, since the boundary values of the sigma interval are ambiguous, the yield cannot be accurately predicted.

[0004] When using the Monte Carlo simulation or other methods to improve the prediction accuracy of the yield, a large amount of calculation is required to determine the boundary values, which occupies the computing resources for a long time. For example, when using the 6 sigma model, only 3 or 4 boundary values can appear in 1 million analysis points. SUMMARY

[0005] The present application aims to provide a model generation method for SRAM analysis, which can solve the problem of inaccurate yield prediction and the problem of large amount of calculation required to improve the prediction accuracy of the yield.

[0006] To solve the above technical problems, the present application is implemented by the following technical scheme:

[0007] The present application provides a model generation method for SRAM analysis, which at least includes the following steps:

[0008] acquiring a measured value data set, and the measured value data set including threshold voltages and drain currents of pull-down transistors, threshold voltages and drain currents of pull-up transistors, and threshold voltages and drain currents of pass-gate transistors;

[0009] assigning the threshold voltages of the pull-down transistors, the threshold voltages of the pull-up transistors, and the threshold voltages of the pass-gate transistors to coordinate axes of a three-dimensional space, and calculating a three-dimensional distribution covariance matrix according to the threshold voltages in the measured value data set, and further calculating a three-dimensional Mahalanobis distance of the measured value data set;

[0010] determining an equiprobable ellipsoid in the three-dimensional space according to a specified probability value, and extracting an equiprobable data set located on a surface of the equiprobable ellipsoid;

[0011] assigning the threshold voltages and the drain currents to coordinate axes of a two-dimensional plane for each of the pull-down transistors, the pull-up transistors, and the pass-gate transistors, and calculating a two-dimensional distribution covariance matrix according to the threshold voltages and the drain currents in the measured value data set, and further calculating a two-dimensional Mahalanobis distance of the measured value data set;

[0012] determining an equiprobable ellipse in the two-dimensional plane according to a specified probability value, and determining drain currents corresponding to the threshold voltages in the equiprobable data set on the equiprobable ellipse;

[0013] calculating an offset value according to the threshold voltages in the equiprobable data set and the drain currents determined on the equiprobable ellipse, and writing the offset value into a network list.

[0014] In an embodiment of the present application, when the equiprobable ellipsoid is acquired, probability value data for determining a probability value for determining a size of the equiprobable ellipsoid in the three-dimensional space is acquired.

[0015] In an embodiment of the present application, when the equiprobable ellipse is acquired, probability value data for determining a probability value for determining a size of the equiprobable ellipse in the two-dimensional plane is acquired.

[0016] In an embodiment of the present application, the probability value data is determined by 1σ, 3σ, or 6σ.

[0017] In an embodiment of the present application, when the number of equiprobable data sets is acquired, a coarse density of the selected equiprobable data sets is set on a surface of the equiprobable ellipsoid, imitating vertices FF, SS, FS, and SF of a corner model.

[0018] In one embodiment of the present application, when the drain current is associated with the threshold voltage according to the equal-probability ellipse, the threshold voltage included in the equal-probability data set is determined on the long axis of the equal-probability ellipse.

[0019] In one embodiment of the present application, when the drain current is associated with the threshold voltage according to the equal-probability ellipse, the threshold voltage included in the equal-probability data set is determined on the long axis of the equal-probability ellipse.

[0020] In one embodiment of the present application, the model generation method further comprises the following step: SPICE calculates the margin of the action range of the SRAM according to the network list of the SPICE model.

[0021] In one embodiment of the present application, when the margin is calculated, SPICE assigns the deviation of the threshold voltage of the pMOS and the deviation of the threshold voltage of the nMOS to the coordinate axes of the two-dimensional plane.

[0022] In one embodiment of the present application, the margin is read from the analysis point with respect to the standby-time current boundary line of the fast-fast side, the access speed boundary and the data retention boundary line of the slow-slow side, the readout boundary line of the fast-slow side, and the write boundary line of the slow-fast side, and then the boundary value of the σ interval is obtained.

[0023] In summary, the model generation method for SRAM analysis provided by the present application has the unexpected effect that: first, the voltage value extracted from the equal-probability ellipsoid 43, i.e., the boundary of the σ interval, is determined according to the threshold voltage of each MOSFET in the SARM unit. Then, the voltage value of the threshold voltage Vt and the current value of the drain current Id are determined on the equal-probability ellipse (line) according to each σ value, and the current value is calculated from the equal-probability ellipse according to the extracted voltage value (boundary value), i.e., the boundary value of the σ interval. Therefore, any boundary value can be determined with high precision according to the equal-probability ellipsoid and the equal-probability ellipse. Therefore, the model generation method for SRAM analysis provided by the present application can not only reduce the resources for calculation, but also determine the manufacturing deviation of the device characteristics of the SRAM unit with high precision, and can not only reduce the resources for calculation, but also perform the yield analysis of the SRAM with high precision.

[0024] Of course, implementing any product of the present application does not necessarily require achieving all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0026] Figure 1 The circuit diagram of the SRAM unit in an embodiment of the present application.

[0027] Figure 2 The structural block diagram of the circuit simulation system in an embodiment of the present application.

[0028] Figure 3 The action flow chart of the circuit simulation system in an embodiment of the present application.

[0029] Figure 4 The conceptual diagram of the mapping data in an embodiment of the present application.

[0030] Figure 5 The conceptual diagram of the equal-probability ellipsoid determined in a three-dimensional space according to the Mahalanobis distance in an embodiment of the present application.

[0031] Figure 6 The conceptual diagram of the each surplus and angle model of the SRAM in an embodiment of the present application.

[0032] Figure 7 The conceptual diagram of the equal-probability ellipse determined in a two-dimensional plane according to the Mahalanobis distance in an embodiment of the present application.

[0033] Figure 8 The conceptual diagram of the offset value in an embodiment of the present application.

[0034] Figure 9 The conceptual diagram of the simulation result drawn for the boundary line in an embodiment of the present application.

[0035] Label explanation:

[0036] 11, SRAM cell; 12, CMOS inverter; 13, CMOS inverter; 12a, pMOSFET (pull-up transistor); 12b, nMOSFET (pull-down transistor); 13a, pMOSFET (pull-up transistor); 13b, nMOSFET (pull-down transistor); 14, nMOSFET (pass-gate transistor); 15, nMOSFET (pass-gate transistor); 21, circuit simulation system; 22, first Mahalanobis distance calculation section; 23, second Mahalanobis distance calculation section; 24, first matrix data; 25, temporary storage device; 26, first equiprobable data; 27, equiprobable data set; 29, second matrix data; 31, second equiprobable data; 32, target data set; 33, SPICE model correction section; 34, SPICE; 35, offset data; 36, input interface; 37, measured value data set; 38, probability value data; 39, SPICE model; 41, arithmetic processing device; 43, equiprobable ellipsoid; 45, equiprobable ellipse; 46, analysis point. DETAILED DESCRIPTION

[0037] Other advantages and embodiments of the present application will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, among which:

[0038] It is to be understood that the drawings are designed solely for the purpose of illustration and are not intended to limit the scope of the application. There can be many variations made to the details of the application without departing from the scope of the application. It is to be understood that all related terms explicitly or implicitly included in this specification and drawings are intended to be interpreted as encompassing their broadest forms and meanings.

[0039] In the present application, it should be noted that, as terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like appear, the orientation or positional relationship indicated thereby is based on the orientation or positional relationship shown in the drawings, and is merely for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element indicated thereby must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, as terms such as "first", "second" appear, they are merely for description and differentiation purposes, and cannot be understood as indicating or implying relative importance.

[0040] Reference will now be made to Figure 1As shown, the SRAM cell 11 includes two CMOS (Complementary Metal Oxide Semiconductor) inverters and two nMOSFETs (n-Metal-Oxide-Semiconductor Field-Effect Transistor), i.e. CMOS inverter 12 and CMOS inverter 13, nMOSFET 14 and nMOSFET 15. The nMOSFET 14 and nMOSFET 15 are connected to the CMOS inverter 12 and CMOS inverter 13 respectively. In the CMOS inverter 12, the drain of the pMOSFET 12a and the drain of the nMOSFET 12b are connected in series, and the connection point between the series-connected pMOSFET 12a and nMOSFET 12b forms a storage node N. In the CMOS inverter 13, the drain of the pMOSFET 13a and the drain of the nMOSFET 13b are connected in series, and the connection point between the series-connected pMOSFET 13a and nMOSFET 13b forms a storage node . The storage node N and the storage node are complementary storage nodes. The source of the pMOSFET 12a and the source of the pMOSFET 13a are electrically connected to an operating voltage VDD, and the source of the nMOSFET 12b and the source of the nMOSFET 13b are electrically connected to a reference voltage GND. Among them, the pMOSFET 12a and the pMOSFET 13a are load transistors (or pull-up transistors PU), and the nMOSFET 12a and the nMOSFET 13a are drive transistors (or pull-down transistors PD).

[0041] Please refer to Figure 1 As shown, the storage node N is electrically connected to the gate of the pMOSFET 13a and the gate of the nMOSFET 13b. The source of the nMOSFET 14 is electrically connected to the storage node N, and the drain of the nMOSFET 14 is electrically connected to a bit line 16. The storage node is electrically connected to the gate of the pMOSFET 12a and the gate of the nMOSFET 12b. The source of the nMOSFET 15 is electrically connected to the storage node The drain of nMOSFET15 is electrically connected to bit line 17, and bit lines 17 and 16 are complementary bit lines. Bit line 18 is electrically connected to the gates of nMOSFET14 and nMOSFET15. Among them, nMOSFET14 and nMOSFET15 are transfer transistors (or (pass-gate transistor) PG).

[0042] Please see Figure 1 As shown, during writing to SRAM cell 11, the potential of word line 18 is set to high (H), the potential of bit line 16 is set to high (H), and the potential of complementary bit line 17 is set to low (L). At this time, nMOSFET 14 is in the ON state, and the potential of memory node N rises due to the potential of bit line 16, becoming high (H). On the other hand, the potential of complementary memory node... The potential becomes a low potential (L).

[0043] Please see Figure 1 As shown, when SRAM cell 11 is in power-off standby mode, the potential of storage node N is high (H). Therefore, nMOSFET 13b is in the on state, and pMOSFET 13a is in the off state. The potential remains low (L). On the other hand, due to the storage node The potential of the storage node N is low (L), therefore, nMOSFET12b is in the off state, pMOSFET12a is in the on state, and the potential of storage node N remains high (H).

[0044] Please see Figure 1 As shown, when SRAM cell 11 is read, the potential of word line 18 is set to a high potential (H), nMOSFET 14 and nMOSFET 15 are in the on state, and memory node N and memory node The potentials are read out to bit line 16 and bit line 17, respectively.

[0045] Please see Figure 2As shown in the embodiment of the present application, the circuit simulation system 21 includes a first mahalanobis distance calculation unit 22 and a second mahalanobis distance calculation unit 23. The first mahalanobis distance calculation unit 22 calculates a three-dimensional mahalanobis distance according to the distribution of the threshold voltage Vtpd of the pull-down transistor PD, the threshold voltage Vtpu of the pull-up transistor PU and the threshold voltage Vtpg of the pass-gate transistor PG in the coordinate axes of a three-dimensional coordinate system. The second mahalanobis distance calculation unit 23 calculates a two-dimensional mahalanobis distance according to the distribution of the threshold voltage Vt and the drain current Id of the pull-down transistor PD, the pull-up transistor PU and the pass-gate transistor PG in the coordinate axes of a two-dimensional coordinate system.

[0046] Referring to Figure 2 As shown in the embodiment of the present application, for one SRAM cell, a data set of threshold voltage can be obtained. The data set of threshold voltage includes the threshold voltage Vtpd of the pull-down transistor PD, the threshold voltage Vtpu of the pull-up transistor PU and the threshold voltage Vtpg of the pass-gate transistor PG in one SRAM cell. The first mahalanobis distance calculation unit 22 calculates a three-dimensional distribution covariance matrix according to the plurality of data sets (Vtpd, Vtpu, Vtpg) of the plurality of SRAM cells, and obtains the first matrix data 24 for determining the mahalanobis distance based on the three-dimensional distribution covariance matrix, and stores the first matrix data 24 in the temporary storage device 25.

[0047] Referring to Figure 2 As shown in the embodiment of the present application, the first mahalanobis distance calculation unit 22 calculates the three-dimensional mahalanobis distance of the plurality of data sets (Vtpd, Vtpu, Vtpg) of the plurality of SRAM cells according to the three-dimensional distribution covariance matrix, and calculates an equiprobable ellipsoid according to the specified probability value nσ. The size of the equiprobable ellipsoid is determined according to the specified probability value nσ. The first equiprobable data 26 is determined for the calculated equiprobable ellipsoid, and the first equiprobable data 26 is stored in the temporary storage device 25.

[0048] Referring to Figure 2 As shown in the embodiment of the present application, the first mahalanobis distance calculation unit 22 extracts the equiprobable data set 27 located on the surface of the equiprobable ellipsoid in the three-dimensional space of the three-dimensional mahalanobis distance coordinate. The extracted equiprobable data set 27 is stored in the temporary storage device 25. The equiprobable data set 27 includes the threshold voltage Vtpd of the pull-down transistor PD, the threshold voltage Vtpu of the pull-up transistor PU and the threshold voltage Vtpg of the pass-gate transistor PG.

[0049] Referring to Figure 2As shown in the drawing, in one embodiment of the present application, a data set (Vt, Id) of a threshold voltage and a drain current is obtained for one threshold voltage. The second Mahalanobis distance calculation section 23 calculates a two-dimensional distribution covariance matrix from a plurality of data sets (Vt, Id) corresponding to each of the pull-down transistor PD, the pull-up transistor PU, and the pass-gate transistor PG. A second matrix data 29 of the determined Mahalanobis distance is obtained on the basis of the two-dimensional distribution covariance matrix, and the second matrix data 29 is stored in the temporary storage 25.

[0050] Referring to Figure 2 As shown in the drawing, in one embodiment of the present application, the second Mahalanobis distance calculation section 23 calculates a two-dimensional Mahalanobis distance of a plurality of data sets (Vt, Id) from the two-dimensional distribution covariance matrix, and calculates an equal-probability ellipse from a specified probability value nσ. The size of the equal-probability ellipse is determined in accordance with the specified probability value nσ. The second equal-probability data 31 is determined for the calculated equal-probability ellipse, and the second equal-probability data 31 is stored in the temporary storage 25.

[0051] Referring to Figure 2 As shown in the drawing, in one embodiment of the present application, the second Mahalanobis distance calculation section 23 obtains a target data set 32 on the equal-probability ellipse in a two-dimensional plane of the two-dimensional Mahalanobis distance coordinates. The target data set 32 includes a threshold voltage Vt and a drain current Id. The target data set 32 of the determined threshold voltage Vt and the drain current Id is stored in the temporary storage 25.

[0052] Referring to Figure 2 As shown in the drawing, in one embodiment of the present application, the circuit simulation system 21 further includes a SPICE model correction section 33 and a SPICE 34. The SPICE model correction section 33 calculates an offset value, i.e., offset data 35, for the SPICE model from the target data set 32. The SPICE 34 simulates the operation of the SRAM cell from a network list of the SPICE model. The offset data 35 is stored in the temporary storage 25. The offset value is registered in the network list of the SPICE model. The SPICE 34 calculates a margin for the operation range of the SRAM from the network list of the SPICE model. In calculating the margin, the SPICE 34 assigns a threshold voltage deviation ΔVt of the pMOS and a threshold voltage deviation ΔVt of the nMOS to the coordinate axes of the two-dimensional plane. The first Mahalanobis distance calculation section 22, the second Mahalanobis distance calculation section 23, and the SPICE model correction section 33 constitute a model generation apparatus for implementing the model generation method according to the embodiment of the present application. The model generation apparatus is combined with the SPICE 34 to constitute the circuit simulation system 21.

[0053] Referring to Figure 2As shown in the drawing, in one embodiment of the present application, the circuit simulation system 21 includes an input interface 36 connected to the first Mahalanobis distance calculation section 22, the second Mahalanobis distance calculation section 23, and the SPICE model correction section 33. The measured value data set 37 and the probability value data 38 are input from the input interface 36 to the first Mahalanobis distance calculation section 22 and the second Mahalanobis distance calculation section 23. The measured value data set 37 can be stored in a mass storage device (for example, a hard disk drive HDD) or can be acquired directly from a wafer inspection device. For each SRAM cell, the measured value data set 37 includes the voltage value of the threshold voltage Vtpd of the pull-down transistor PD and the current value of the drain current Idpd, the voltage value of the threshold voltage Vtpu of the pull-up transistor PU and the current value of the drain current Idpu, and the voltage value of the threshold voltage Vtpg of the pass-gate transistor PG and the current value of the drain current Idpg. The measured value data set 37 is described in the map data. The voltage value of the threshold voltage Vt and the current value of the drain current Id are measured by a TEG (Test Element Group) provided on the wafer.

[0054] Referring to Figure 2 As shown in the drawing, in one embodiment of the present application, the probability value data 38 is a probability value for determining an equiprobable ellipsoid and the size of the equiprobable ellipsoid. The probability value data 38 is acquired from a keyboard or another input device, and the probability value can be arbitrarily set. Here, the probability value is determined by σ (1σ, 3σ, 6σ, etc.), for example.

[0055] Referring to Figure 2 As shown in the drawing, in one embodiment of the present application, the SPICE model 39 can be delivered to the SPICE model correction section 33 through the input interface 36. The SPICE model 39 determines a standard pMOSFET model and an nMOSFET model. The SPICE model 39 can be stored in a mass storage device.

[0056] Referring to Figure 3 As shown in the drawing, in one embodiment of the present application, the first Mahalanobis distance calculation section 22, the second Mahalanobis distance calculation section 23, and the SPICE model correction section 33 can be implemented by an arithmetic processing device (processor) 41. When the first Mahalanobis distance calculation section 22, the second Mahalanobis distance calculation section 23, and the SPICE model correction section 33 are to be implemented, the arithmetic processing device 41 acquires a software program from a mass storage device. The arithmetic processing device 41 stores the software program and data in a temporary storage device 25 while executing the software program. At this time, the arithmetic processing device 41 is provided in a computer device, for example.

[0057] Referring to Figure 4As shown, in one embodiment of the present application, when the circuit simulation system 21 is used, the steps S1 to S11 are specifically included. In step S1, the mapping data (multi-point measurement data) is acquired. In conjunction with Figure 3 As shown, in the mapping data, the measured value data set 37 of the SRAM cell 11 is inputted for each SRAM cell 11. When the mapping data is formed, the threshold voltage Vt and the drain current Id of the pMOSFET 12a, the pMOSFET 13a, the nMOSFET 12b, the nMOSFET 13b, the nMOSFET 14 and the nMOSFET 15 in one SRAM cell 11 can be measured by the TEG formed on the wafer. Among them, the SRAM cell 11 of the TEG is five-point measured by one wafer. The mapping data is stored in the mass storage device.

[0058] Referring to Figure 3 As shown, in one embodiment of the present application, in step S2, the σ value is acquired. The σ value is specified, for example, by inputting through a keyboard or other input device. When the σ value is specified, the probability value is determined, i.e., the probability value data 38 is generated. The probability value data 38 is stored in the temporary storage device 25.

[0059] Referring to Figure 3 As shown, in one embodiment of the present application, in step S3, the first Mahalanobis distance calculation unit 22 calculates the three-dimensional distribution covariance matrix according to the threshold voltage Vtpd of the pMOSFET 12a and the pMOSFET 13a, the threshold voltage Vtpu of the nMOSFET 12b and the nMOSFET 13b, and the threshold voltage Vtpg of the nMOSFET 14 and the nMOSFET 15. Among them, the data set (Vtpd, Vtpu, Vtpg) of the threshold voltage is acquired from the measured value data set 37 in the mapping data. The first Mahalanobis distance calculation unit 22 generates the first matrix data 24 (three-dimensional distribution covariance matrix). The first matrix data 24 is stored in the temporary storage device 25.

[0060] Referring to Figure 5 As shown, in one embodiment of the present application, in step S4, the first Mahalanobis distance calculation unit 22 calculates the three-dimensional Mahalanobis distance according to the three-dimensional distribution covariance matrix. In conjunction with Figure 3 As shown, according to the calculated Mahalanobis distance, the equiprobability ellipsoid 43 is determined in the three-dimensional space of the three-dimensional coordinate system. The size of the equiprobability ellipsoid is determined by the probability value data 38. The first Mahalanobis distance calculation unit 22 generates the first equiprobability data 26. The first equiprobability data 26 is stored in the temporary storage device 25.

[0061] Referring to Figure 6In the embodiment of the present application, the first Mahalanobis distance calculating section 22 extracts the equiprobable data sets 27 on the surface of the equiprobable ellipsoid in step S5. The number n of the equiprobable data sets 27 can be arbitrarily set. In conjunction with Figure 3 When the number n of the equiprobable data sets 27 is set, the density of the selected equiprobable data sets 27 on the surface of the equiprobable ellipsoid 43 can be set in the same manner as the vertices FF (fast-fast), SS (slow-slow), FS (fast-slow), and SF (slow-fast) of the corner model. The first Mahalanobis distance calculating section 22 generates the equiprobable data sets 27. The equiprobable data sets 27 are stored in the temporary storage 25.

[0062] Referring to Figure 3 In the embodiment of the present application, the second Mahalanobis distance calculating section 23 calculates the two-dimensional distribution covariance matrix from the threshold voltages Vt and the drain currents Id of the pMOSFET 12a, the pMOSFET 13a, the nMOSFET 12b, the nMOSFET 13b, the nMOSFET 14, and the nMOSFET 15 in step S6. When the two-dimensional distribution covariance matrix is calculated, the second Mahalanobis distance calculating section 23 assigns the threshold voltages Vt and the drain voltages Id to the coordinate axes of the two-dimensional coordinate system. The data sets (Vt, Id) of the threshold voltages and the drain currents are obtained from the measured value data sets 37 of the mapping data. The second Mahalanobis distance calculating section 23 generates the second matrix data 29. The second matrix data 29 are stored in the temporary storage 25.

[0063] Referring to Figure 7 In the embodiment of the present application, the second Mahalanobis distance calculating section 23 calculates the two-dimensional Mahalanobis distance from the two-dimensional distribution covariance matrix in step S7. In conjunction with Figure 3 The equiprobable ellipsoid 45 is determined in the two-dimensional plane of the two-dimensional coordinate system from the calculated two-dimensional Mahalanobis distance. The size of the equiprobable ellipsoid 45 is determined by the probability value data 38. The second Mahalanobis distance calculating section 23 generates the second equiprobable data 31. The second equiprobable data 31 are stored in the temporary storage 25.

[0064] Referring to Figure 3In the embodiment of the present application, as shown in FIG. 6, in step S8, the second Mahalanobis distance calculation section 23 associates the drain current Id with the threshold voltage Vt based on the equal-probability ellipse 45. On the major axis of the equal-probability ellipse 45, the threshold voltage Vt included in the equal-probability data set 27 is determined. At the intersection of the line orthogonal to the major axis and the equal-probability ellipse 45, the drain current Id is determined. For example, if the analysis is fast, the intersection is selected in the region of a larger value of the drain current Id compared to the major axis. For example, if the analysis is slow, the intersection is selected in the region of a smaller value of the drain current Id compared to the major axis. The second Mahalanobis distance calculation section 23 generates the target data set 32. The target data set 32 is stored in the temporary storage 25.

[0065] Referring to Figure 8 In the embodiment of the present application, as shown in FIG. 6, in step S9, the SPICE model correction section 33 calculates the offset value of the SPICE model. When the offset value is calculated, the SPICE model correction section 33 acquires the SPICE model 39. In conjunction with Figure 3 As shown, the SPICE model correction section 33 determines the difference between the threshold voltage Vt and the drain current Id of the SPICE model 39 and the target data set 32. The SPICE model correction section 33 generates the offset data 35. The offset data 35 is stored in the temporary storage 25. In step S10, the SPICE model correction section 33 writes the offset value to the net list of the SPICE 34. When the offset value is calculated, the optimization of the SPICE 34 can also be used.

[0066] Referring to Figure 9 In the embodiment of the present application, as shown in FIG. 6, in step S11, the SPICE 34 calculates the margin of the operation range of the SRAM based on the net list of the SPICE model. In conjunction with Figure 3 As shown, when the margin is calculated, the SPICE 34 assigns the deviation ΔVt of the threshold voltage of the pMOS and the deviation ΔVt of the threshold voltage of the nMOS to the coordinate axes of the two-dimensional coordinate system. The SPICE 34 performs simulation based on the net list including the offset value for each target data set 32. At the boundaries of the σ intervals, the results of the simulation (analysis points 46) are plotted. From the analysis points 46, the margin is read with respect to the standby current boundary line on the fast-fast side, the access speed boundary and the data retention boundary line on the slow-slow side, the readout boundary line on the fast-slow side, and the write boundary line on the slow-fast side. Thus, the boundary values of the σ intervals can be determined for each σ value, and the yield can be predicted.

[0067] Referring to Figure 3As shown, when the three-dimensional Mahalanobis distance is calculated in the three-dimensional coordinate system based on the threshold voltage Vtpd of the pMOSFET 12a and the pMOSFET 13a, the threshold voltage Vtpu of the nMOSFET 12b and the nMOSFET 13b, and the threshold voltage Vtpg of the nMOSFET 14 and the nMOSFET 15, the current value of the threshold voltage Vtpd, Vtpu, Vtpg is determined on the surface of the equal-probability ellipsoid 43 in the three-dimensional space for each σ value. The voltage value is extracted from the determined equal-probability ellipsoid 43 for each threshold voltage Vtpd of the pMOSFET 12a and the pMOSFET 13a, the threshold voltage Vtpu of the nMOSFET 12b and the nMOSFET 13b, and the threshold voltage Vtpg of the nMOSFET 14 and the nMOSFET 15. The extracted voltage value represents the boundary value of the σ interval. When the two-dimensional Mahalanobis distance is calculated in the two-dimensional coordinate system based on the threshold voltage Vt and the drain current Id for each of the pMOSFET 12a, the pMOSFET 13a, the nMOSFET 12b, the nMOSFET 13b, the nMOSFET 14, and the nMOSFET 15, the voltage value of the threshold voltage Vt and the current value of the drain current Id are determined on the equal-probability ellipse (line) 45 in the two-dimensional plane for each σ value. The current value is calculated from the equal-probability ellipse 45 based on the extracted voltage value (boundary value). The calculated current value represents the boundary value of the σ interval. Therefore, any boundary value is determined with high accuracy based on the equal-probability ellipsoid 43 and the equal-probability ellipse 45. Thus, the model generation method for SRAM analysis according to the present application can determine the manufacturing variation of the device characteristics of the SRAM cell 11 with high accuracy while reducing the resources for calculation. Further, the model generation method for SRAM analysis according to the present application can also perform the yield analysis of the SRAM while reducing the resources for calculation.

[0068] Referring to ​ As shown, in the present embodiment, the size of the equal-probability ellipsoid 43 is determined in the three-dimensional space based on the probability value data 38 when the equal-probability ellipsoid 43 is calculated. The size of the equal-probability ellipsoid 43 is determined by the probability value data 38. The manufacturing variation of the device characteristics of the SRAM cell 11 is calculated for each probability value (σ value). Similarly, the size of the equal-probability ellipse 45 is determined in the two-dimensional plane based on the probability value data 38 when the equal-probability ellipse 45 is calculated. The size of the equal-probability ellipse 45 is specified by the probability value data 38. The manufacturing variation of the device characteristics of the SRAM cell 11 is calculated for each probability value.

[0069] The above disclosed embodiments of the present application are only used to help explain the present application. The embodiments do not describe all of the details of the present application, and the present application is not limited to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of the present specification. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well understand and utilize the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A model generation method for SRAM analysis, characterized by, The method comprises the following steps: acquiring a measured value data set, and the measured value data set comprising threshold voltages and drain currents of pull-down transistors, threshold voltages and drain currents of pull-up transistors, and threshold voltages and drain currents of pass-gate transistors; allocating the threshold voltages of the pull-down transistors, the threshold voltages of the pull-up transistors, and the threshold voltages of the pass-gate transistors to coordinate axes of a three-dimensional space, and calculating a three-dimensional distribution covariance matrix according to the threshold voltages in the measured value data set, and further calculating a three-dimensional Mahalanobis distance of the measured value data set; determining an equiprobable ellipsoid in the three-dimensional space according to a specified probability value, and extracting an equiprobable data set located on a surface of the equiprobable ellipsoid; allocating threshold voltages and drain currents to coordinate axes of a two-dimensional plane for each of the pull-down transistors, the pull-up transistors, and the pass-gate transistors, and calculating a two-dimensional distribution covariance matrix according to the threshold voltages and the drain currents corresponding to each of the pull-down transistors, the pull-up transistors, and the pass-gate transistors in the measured value data set, and further calculating a two-dimensional Mahalanobis distance of the measured value data set; determining an equiprobable ellipse in the two-dimensional plane according to a specified probability value, and determining drain currents corresponding to the threshold voltages in the equiprobable data set on the equiprobable ellipse; calculating an offset value according to the threshold voltages in the equiprobable data set and the drain currents determined on the equiprobable ellipse, and writing the offset value into a network list.

2. The model generation method for SRAM analysis according to claim 1, wherein, When the equiprobable ellipsoid is acquired, probability value data for determining a probability value for determining a size of the equiprobable ellipsoid in the three-dimensional space is acquired.

3. The model generation method for SRAM analysis according to claim 1, wherein, When the equiprobable ellipse is acquired, probability value data for determining a probability value for determining a size of the equiprobable ellipse in the two-dimensional plane is acquired.

4. The model generation method for SRAM analysis according to claim 2 or claim 3, characterized by, The probability value data is determined by 1σ, 3σ, or 6σ.

5. The model generation method for SRAM analysis according to claim 1, wherein, When the number of equiprobable data sets is acquired, a coarse density of the selected equiprobable data sets is set on a surface of the equiprobable ellipsoid, imitating vertices FF, SS, FS, and SF of a corner model.

6. The model generation method for SRAM analysis according to claim 1, wherein, The model generation method further comprises the following step: SPICE calculates a margin for an operation range of the SRAM according to the network list of the SPICE model.

7. The method of claim 6, wherein, When the margin is calculated, SPICE allocates a deviation of a threshold voltage of a pMOS and a deviation of a threshold voltage of an nMOS to coordinate axes of a two-dimensional plane.

8. The method for model generation for SRAM analysis according to claim 7, wherein, From the analysis point, a margin is read with respect to a standby time current boundary line of a fast-fast side, an access speed boundary and a data retention boundary line of a slow-slow side, a readout boundary line of a fast-slow side, and a write boundary line of a slow-fast side, and further acquiring a boundary value of a σ interval.

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