Time delay jitter optimization method and device, equipment and storage medium

Abstract

The invention provides a time delay jitter optimization method and device, equipment and a storage medium, and the method comprises the steps: obtaining the end-to-end time delay data of a vehicle, carrying out the spectrum analysis of the end-to-end time delay data, and obtaining a time delay parameter set of the end-to-end time delay data; according to the time delay parameter set, identifying whether the end-to-end time delay data contains abnormal time delay jitter data; and in response to the fact that the end-to-end delay data contains abnormal delay jitter data, delay jitter optimization is carried out on a control link of the vehicle. The accuracy and precision of identifying the abnormal delay jitter of the control link of the vehicle are improved, the delay jitter optimization is carried out when the abnormal delay jitter of the control link of the vehicle is identified, the accuracy of the delay jitter optimization is improved, the influence degree of the abnormal delay jitter on the vehicle performance is reduced, and the stability of the vehicle performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of assisted driving technology, and in particular to a method, apparatus, device, and storage medium for optimizing delay jitter. Background Art

[0002] With the development of technology, more and more vehicles are equipped with assisted driving systems. In this scenario, the vehicle's assisted driving system can provide people with assisted driving services through end-to-end information transmission. During the end-to-end information transmission process, there may be end-to-end delay.

[0003] Among them, the end-to-end delay may experience abnormal jitter, which may have a certain degree of impact on the vehicle's assisted driving function. Summary of the Invention

[0004] The present disclosure aims to solve one of the technical problems in the related art at least to a certain extent.

[0005] To this end, a first aspect of the present disclosure proposes a method for optimizing delay jitter.

[0006] A second aspect of the present disclosure provides a device for optimizing delay jitter.

[0007] A third aspect of the present disclosure provides an electronic device.

[0008] A fourth aspect of the present disclosure provides a computer-readable storage medium.

[0009] A first aspect of the present disclosure proposes a method for optimizing delay jitter, comprising: obtaining end-to-end delay data of a vehicle, performing spectral analysis on the end-to-end delay data, and obtaining a delay parameter set for the end-to-end delay data; identifying, based on the delay parameter set, whether the end-to-end delay data includes abnormal delay jitter data; and, in response to identifying that the end-to-end delay data includes the abnormal delay jitter data, optimizing delay jitter for a control link of the vehicle.

[0010] The delay jitter optimization method proposed in the first aspect of the present disclosure identifies whether there is abnormal delay jitter in the vehicle's control link through a delay parameter set obtained from end-to-end delay data, thereby improving the accuracy and precision of identifying abnormal delay jitter in the vehicle's control link. When abnormal delay jitter is identified in the vehicle's control link, delay jitter optimization is performed, thereby improving the accuracy of delay jitter optimization, thereby reducing the impact of abnormal delay jitter on vehicle performance, improving the stability of vehicle performance, and optimizing vehicle driving safety.

[0011] The first aspect of the present disclosure provides a method for optimizing delay jitter, further comprising the following technical features:

[0012] According to one embodiment of the present disclosure, the acquiring of the end-to-end delay data of the vehicle and performing spectral analysis on the end-to-end delay data to obtain a delay parameter set of the end-to-end delay data include: performing spectral analysis on the end-to-end delay data to obtain a delay deterministic parameter of the end-to-end delay data, an abnormal jitter frequency set, and a jitter spectrum parameter of each abnormal jitter frequency in the abnormal jitter frequency set, wherein the delay deterministic parameter is used to characterize the delay stability of the end-to-end delay data; obtaining the delay parameter set of the end-to-end delay data according to the delay deterministic parameter, the abnormal jitter frequency set, and the jitter spectrum parameter of each abnormal jitter frequency in the abnormal jitter frequency set.

[0013] Based on the spectrum analysis of end-to-end delay data, the accuracy of obtaining delay deterministic parameters, abnormal jitter frequency sets and jitter spectrum parameters of each abnormal jitter frequency is improved, thereby improving the accuracy of obtaining the delay parameter set of end-to-end delay data.

[0014] According to one embodiment of the present disclosure, the spectral analysis is performed on the end-to-end delay data to obtain a delay deterministic parameter of the end-to-end delay data, wherein the delay deterministic parameter is used to characterize the delay stability of the end-to-end delay data, including: performing a Fourier transform on the end-to-end delay data to obtain a delay frequency domain representation of the end-to-end delay data; and obtaining a zero-frequency component in the delay frequency domain representation to determine the delay deterministic parameter of the end-to-end delay data.

[0015] Based on the frequency domain representation of delay and the acquisition of zero-frequency components in the frequency domain representation of delay, accurate positioning and acquisition of delay deterministic parameters in end-to-end delay data are achieved.

[0016] According to one embodiment of the present disclosure, the spectral analysis of the end-to-end delay data to obtain an abnormal jitter frequency set of the end-to-end delay data and jitter spectrum parameters of each abnormal jitter frequency in the abnormal jitter frequency set includes: filtering out non-zero frequency components from the delay frequency domain representation according to the delay deterministic parameter; filtering out each abnormal jitter frequency from the non-zero frequency components according to a preset jitter frequency threshold to determine the abnormal jitter frequency set; and obtaining the half-width at half-maximum of the spectrum of each abnormal jitter frequency in the abnormal jitter frequency set from the delay frequency domain representation to determine the jitter spectrum parameters of each abnormal jitter frequency.

[0017] Non-zero frequency components are screened based on delay deterministic parameters, improving the accuracy of screening non-zero frequency components in the delay frequency domain representation. Abnormal jitter frequency sets are determined from the non-zero frequency components, narrowing the acquisition range of abnormal jitter frequency sets and improving the efficiency and accuracy of acquiring abnormal jitter frequency sets. The jitter frequency parameters of each abnormal jitter frequency are determined based on the half-width of the spectrum, so that the jitter frequency parameters carry the frequency domain characteristics of the abnormal jitter frequency.

[0018] According to one embodiment of the present disclosure, identifying whether the end-to-end delay data includes abnormal delay jitter data based on the delay parameter set includes: determining the abnormal jitter judgment condition for each delay parameter in the delay parameter set; and for any delay parameter, in response to the delay parameter matching the corresponding abnormal jitter judgment condition, determining that the end-to-end delay data includes abnormal delay jitter data.

[0019] Based on the preset abnormal jitter determination condition, it is determined that the end-to-end delay data contains abnormal delay jitter data, thereby improving the determination accuracy of whether the end-to-end delay data contains abnormal delay jitter data.

[0020] According to one embodiment of the present disclosure, in response to identifying that the end-to-end delay data contains the abnormal delay jitter data, the delay jitter optimization of the control link of the vehicle includes: in response to the end-to-end delay data containing the abnormal delay jitter data, obtaining the abnormal jitter frequency corresponding to the abnormal delay jitter data, and performing delay jitter optimization on the control link of the vehicle based on the abnormal jitter frequency.

[0021] Based on the abnormal jitter frequency, the abnormal delay jitter in the end-to-end delay is accurately located, and then the delay jitter of the vehicle control link is optimized based on the abnormal jitter frequency, thereby improving the accuracy of delay jitter optimization.

[0022] According to one embodiment of the present disclosure, the method further includes: determining the abnormal jitter cause corresponding to the end-to-end delay data based on the abnormal jitter frequency, and determining a jitter optimization strategy for the abnormal delay jitter data according to the abnormal jitter cause; and performing delay jitter optimization on the control link of the vehicle according to the jitter optimization strategy.

[0023] Based on the abnormal jitter frequency, the system accurately locates abnormal delay jitter in end-to-end delay, improves the accuracy of determining the cause of abnormal jitter in end-to-end delay data, and obtains the corresponding jitter optimization strategy based on the abnormal jitter cause. This improves the match between the jitter optimization strategy and the abnormal delay jitter of end-to-end delay, and improves the effect of delay jitter optimization for end-to-end delay.

[0024] A second aspect of the present disclosure provides a delay jitter optimization device, comprising: an acquisition module for acquiring end-to-end delay data of a vehicle and performing spectral analysis on the end-to-end delay data to obtain a delay parameter set for the end-to-end delay data; an identification module for identifying, based on the delay parameter set, whether the end-to-end delay data includes abnormal delay jitter data; and an optimization module for optimizing delay jitter for a control link of the vehicle in response to identifying that the end-to-end delay data includes the abnormal delay jitter data.

[0025] The delay jitter optimization device proposed in the second aspect of the present disclosure identifies whether there is abnormal delay jitter in the vehicle's control link through a delay parameter set obtained from end-to-end delay data, thereby improving the accuracy and precision of identifying abnormal delay jitter in the vehicle's control link. When abnormal delay jitter is identified in the vehicle's control link, delay jitter optimization is performed, thereby improving the accuracy of delay jitter optimization, thereby reducing the impact of abnormal delay jitter on vehicle performance, improving the stability of vehicle performance, and optimizing vehicle driving safety.

[0026] A third aspect of the present disclosure proposes an electronic device, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the instructions to implement the delay jitter optimization method proposed in the first aspect above.

[0027] The electronic device proposed in the third aspect of the present disclosure improves the accuracy and precision of identifying abnormal delay jitter in the vehicle's control link by adopting the delay jitter optimization method proposed in the first aspect above, and performs delay jitter optimization when abnormal delay jitter is identified in the vehicle's control link, thereby improving the accuracy of delay jitter optimization, thereby reducing the impact of abnormal delay jitter on vehicle performance, improving the stability of vehicle performance, and optimizing vehicle driving safety.

[0028] In a fourth aspect, the present disclosure proposes a computer-readable storage medium. When instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device can execute the delay jitter optimization method proposed in the first aspect.

[0029] The computer-readable storage medium proposed in the fourth aspect of the present disclosure improves the accuracy and precision of identifying abnormal delay jitter in the vehicle's control link by adopting the delay jitter optimization method proposed in the first aspect above, and performs delay jitter optimization when abnormal delay jitter is identified in the vehicle's control link, thereby improving the accuracy of delay jitter optimization, thereby reducing the impact of abnormal delay jitter on vehicle performance, improving the stability of vehicle performance, and optimizing vehicle driving safety.

[0030] It should be understood that the contents described in the present disclosure are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and / or additional aspects and advantages of the present disclosure will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0032] Figure 1 This is a flow chart of a method for optimizing delay jitter according to an embodiment of the present disclosure;

[0033] Figure 2 This is a flow chart of a method for optimizing delay jitter according to another embodiment of the present disclosure;

[0034] Figure 3 This is a flow chart of a method for optimizing delay jitter according to another embodiment of the present disclosure;

[0035] FIG4( a ) is a schematic diagram of frequency domain data of delay jitter according to an embodiment of the present disclosure;

[0036] FIG4( b ) is a schematic diagram of frequency domain data of delay jitter according to another embodiment of the present disclosure;

[0037] Figure 5 This is a structural diagram of a device for optimizing delay jitter according to an embodiment of the present disclosure;

[0038] Figure 6 A block diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] The following describes in detail embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0040] The following describes a method, apparatus, device, and storage medium for optimizing delay jitter proposed in embodiments of the present disclosure with reference to the accompanying drawings.

[0041] Figure 1 FIG. 1 is a flow chart of a method for optimizing delay jitter according to an embodiment of the present disclosure. Figure 1 As shown, the method includes:

[0042] S101 , acquiring end-to-end delay data of a vehicle, and performing spectrum analysis on the end-to-end delay data to obtain a delay parameter set of the end-to-end delay data.

[0043] During daily vehicle operation, information exchange between various functional systems is achieved through control links. This process can result in end-to-end latency. This control link encompasses not only basic data transmission (communication), but also computing, decision-making, and collaborative control based on information sharing.

[0044] Optionally, the relevant state of the end-to-end delay on the control link of the vehicle may be detected, and the data obtained by the detection may be determined as the end-to-end delay data of the control link of the vehicle.

[0045] In the embodiment of the present disclosure, the end-to-end delay data can be algorithmically analyzed and processed based on a preset data analysis algorithm, and then the end-to-end delay jitter state of the vehicle's control link obtained based on the end-to-end delay data can be determined according to the results of the algorithm analysis.

[0046] Optionally, spectrum analysis can be performed on the end-to-end delay data based on a preset spectrum analysis algorithm. The spectrum analysis algorithm can be used to obtain the delay jitter of the vehicle's control link during operation based on the end-to-end delay data. Specifically, spectrum analysis can be performed based on the end-to-end delay data to obtain relevant parameters that can characterize the delay jitter of the vehicle's control link. These parameters are the delay parameters corresponding to the end-to-end delay data, and the set of these delay parameters can be used as the delay parameter set corresponding to the end-to-end detection data.

[0047] S102: Identify, based on the delay parameter set, whether the end-to-end delay data includes abnormal delay jitter data.

[0048] In the embodiment of the present disclosure, the delay parameter set can be understood as a parameter set used to describe the jitter of the end-to-end delay of the vehicle's control link. In this scenario, it is possible to identify whether there is abnormal jitter in the end-to-end delay of the vehicle's control link based on the various delay parameters in the delay parameter set.

[0049] Optionally, each delay parameter in the delay parameter set can be analyzed and identified based on a preset judgment and analysis algorithm, and then, based on the results of the analysis and identification, it is determined whether each delay parameter contains data that can be used to characterize abnormal jitter in the end-to-end delay of the vehicle's control link. This part of the data is the abnormal delay jitter data in the end-to-end delay data.

[0050] S103 : In response to identifying that the end-to-end delay data includes abnormal delay jitter data, performing delay jitter optimization on a control link of the vehicle.

[0051] In the embodiment of the present disclosure, when it is identified that the end-to-end delay data contains abnormal delay jitter data, it can be determined that the end-to-end delay of the current vehicle's control link has abnormal jitter. In this scenario, the end-to-end delay of the vehicle's control link needs to be repaired and optimized.

[0052] Among them, a delay jitter optimization method corresponding to the abnormal delay jitter data can be obtained, and the vehicle's hardware facilities and software algorithms can be adjusted based on this method to eliminate the abnormal jitter of the end-to-end delay of the vehicle's control link, thereby achieving delay jitter optimization of the vehicle's control link.

[0053] The delay jitter optimization method proposed in the present disclosure obtains the end-to-end delay data of the vehicle's control link, and performs spectrum analysis on the end-to-end delay data to obtain a corresponding delay parameter set. It identifies whether the end-to-end delay data contains abnormal delay jitter data based on the delay parameter set, and when it is identified that the end-to-end delay data contains abnormal delay jitter data, the vehicle's control link is optimized for delay jitter. In the present disclosure, the delay parameter set obtained through the end-to-end delay data is used to identify whether the vehicle's control link has abnormal delay jitter, thereby improving the accuracy and precision of identifying abnormal delay jitter in the vehicle's control link. When it is identified that the vehicle's control link has abnormal delay jitter, delay jitter optimization is performed, thereby improving the accuracy of delay jitter optimization, thereby reducing the impact of abnormal delay jitter on vehicle performance, improving the stability of vehicle performance, and optimizing vehicle driving safety.

[0054] In the above embodiment, the optimization method for delay jitter can also be combined with Figure 2 understand, Figure 2 FIG. 1 is a flow chart of a method for optimizing delay jitter according to another embodiment of the present disclosure. Figure 2 As shown, the method includes:

[0055] S201: Perform spectrum analysis on the end-to-end delay data to obtain a delay determinism parameter of the end-to-end delay data, an abnormal jitter frequency set, and a jitter spectrum parameter of each abnormal jitter frequency in the abnormal jitter frequency set. The delay determinism parameter is used to characterize the delay stability of the end-to-end delay data.

[0056] In the embodiments of the present disclosure, the end-to-end delay data can be algorithmically processed based on the spectrum acquisition algorithm in the related art to obtain the spectrum corresponding to the end-to-end delay data, and then the spectrum is subjected to spectrum analysis to obtain the delay parameter set corresponding to the end-to-end delay data.

[0057] Optionally, the delay parameter set corresponding to the end-to-end delay data includes relevant parameters for describing the determinism of the end-to-end delay of the vehicle's control link. This part of the parameters can be determined as the delay deterministic parameters in the end-to-end delay data.

[0058] It can be understood that the stability of the end-to-end delay of the vehicle control link can be obtained based on the delay determinism parameter. The acquisition of the delay determinism parameter can be understood in conjunction with the following:

[0059] Optionally, Fourier transform is performed on the end-to-end delay data to obtain a delay frequency domain representation of the end-to-end delay data.

[0060] In an embodiment of the present disclosure, the end-to-end delay data can be Fourier transformed based on the Fourier transform algorithm in the related art, and the frequency domain representation corresponding to the end-to-end delay data can be obtained based on the result of the Fourier transform as the delay frequency domain representation of the end-to-end delay data.

[0061] Optionally, a zero-frequency component in the frequency-domain representation of the delay is obtained to determine a delay deterministic parameter of the end-to-end delay data.

[0062] In the disclosed embodiment, there is a certain degree of correlation between the stability of the end-to-end delay corresponding to the vehicle's control link and the zero-frequency component in the delay frequency domain representation. It can be understood that the stronger the stability of the end-to-end delay, the more zero-frequency components in the corresponding delay frequency domain representation.

[0063] In this scenario, the zero-frequency component in the delay frequency domain representation corresponding to the end-to-end delay data can be obtained, and the delay deterministic parameter used to describe the end-to-end delay stability of the vehicle's control link can be obtained based on the zero-frequency component through a preset algorithm.

[0064] The algorithm can be understood based on the following formula:

[0065]

[0066] In the above formula, [0,f δ ] represents the zero frequency component in the delay frequency domain representation, f δ Indicates experience value, The frequency domain representation of the end-to-end delay obtained by Fourier transforming the end-to-end delay data. G is a constant with a value range of [0, 1]. The closer the value of G is to 1, the higher the certainty of the end-to-end delay corresponding to the vehicle's control link.

[0067] In the embodiment of the present disclosure, based on a preset algorithm, some frequencies that meet the set conditions can be screened out from the delay frequency domain representation of the end-to-end delay data. These partial frequencies are the abnormal jitter frequencies in the delay frequency domain representation, and then an abnormal jitter frequency set composed of the abnormal jitter frequencies is obtained.

[0068] The acquisition of abnormal jitter frequency sets and related parameters can be understood in conjunction with the following:

[0069] Optionally, non-zero frequency components are screened out from the frequency domain representation of the delay according to the delay deterministic parameter.

[0070] In the embodiment of the present disclosure, the zero-frequency component can be understood as the frequency component in the delay frequency domain representation used to characterize that the end-to-end delay does not have abnormal jitter. In this scenario, non-zero frequency components other than the zero-frequency component can be filtered out from the delay frequency domain representation based on the acquired delay deterministic parameters. This part of the non-zero frequency components can be understood as the frequency component in the delay frequency domain representation used to characterize that the end-to-end delay may have abnormal jitter.

[0071] The time delay frequency domain representation may be processed based on a frequency component screening method in related technologies, thereby screening out non-zero frequency components in the time delay frequency domain representation.

[0072] Optionally, according to a preset jitter frequency threshold, each abnormal jitter frequency is screened out from the non-zero frequency components to determine an abnormal jitter frequency set.

[0073] In the embodiment of the present disclosure, there is a preset jitter frequency threshold for the end-to-end delay. It can be understood that for any jitter frequency, when the jitter frequency is greater than or equal to the jitter frequency threshold, it can be determined that the jitter frequency is an abnormal jitter frequency.

[0074] In this scenario, each non-zero frequency in the non-zero frequency component represented by the delay frequency domain can be compared with the preset jitter frequency threshold. For any non-zero frequency, when the non-zero frequency is greater than or equal to the jitter frequency threshold, it can be determined that the delay jitter corresponding to the non-zero frequency is abnormal jitter in the end-to-end delay, and the non-zero frequency can be determined as the abnormal jitter frequency in the non-zero frequency component.

[0075] Furthermore, based on the various abnormal jitter frequencies screened out from the non-zero frequency components, an abnormal jitter frequency set corresponding to the end-to-end delay data is formed.

[0076] As an example, the abnormal jitter frequency set can be expressed based on the following formula:

[0077]

[0078] In the above expression, F represents the abnormal jitter frequency set, represents the frequency domain representation of the time delay, and f represents the non-zero frequency.

[0079] Optionally, the spectrum half-width of each abnormal jitter frequency in the abnormal jitter frequency set is obtained from the frequency domain representation of the time delay to determine the jitter spectrum parameter of each abnormal jitter frequency.

[0080] In the embodiment of the present disclosure, for any abnormal jitter frequency, the half-width of the spectrum corresponding to the abnormal jitter frequency can be obtained from the delay frequency domain representation based on the spectrum half-width acquisition algorithm in the related art, as the jitter spectrum parameter of the abnormal jitter frequency.

[0081] It should be noted that, for the abnormal jitter frequency, there is a certain degree of correlation between the singleness of the jitter cause of the abnormal jitter frequency and the half-width of the spectrum corresponding to the abnormal jitter frequency. It can be understood that the smaller the value of the half-width of the spectrum for the abnormal jitter frequency, the stronger the singleness of the abnormal jitter cause corresponding to the abnormal jitter frequency.

[0082] S202 : Obtain a delay parameter set for end-to-end delay data according to the delay deterministic parameter, the abnormal jitter frequency set, and the jitter spectrum parameter of each abnormal jitter frequency in the abnormal jitter frequency set.

[0083] In an embodiment of the present disclosure, a method for obtaining a data set in the related art can be obtained, and data set integration processing can be performed on the delay deterministic parameters, the abnormal jitter frequency set, and the jitter spectrum parameters of each abnormal jitter frequency in the abnormal jitter frequency set, and the integrated data set can be determined as the delay parameter set obtained based on the end-to-end delay data.

[0084] S203: Obtain abnormal jitter determination conditions for each delay parameter in the delay parameter set.

[0085] In the disclosed embodiment, the jitter that occurs in the end-to-end delay of the vehicle's control link may be normal jitter or abnormal jitter. In this scenario, the critical parameter values ​​under each parameter item when abnormal jitter occurs in the end-to-end delay can be obtained. Among them, for any delay parameter, the abnormal judgment condition under the parameter item to which the delay parameter belongs can be set based on the critical parameter value under the parameter item, and the abnormal judgment condition can be used as the abnormal jitter judgment condition corresponding to the delay parameter under the parameter item.

[0086] For example, for the jitter frequency parameter item to which the abnormal jitter frequency belongs, the jitter frequency critical value under the jitter frequency parameter item can be obtained when abnormal jitter occurs in the end-to-end delay of the vehicle's control link. Based on the critical value, the abnormal judgment condition under the jitter frequency parameter item is set. For the abnormal jitter frequency that is the delay parameter under the jitter frequency parameter item, the abnormal judgment condition can be determined as the abnormal jitter judgment condition corresponding to the abnormal jitter frequency.

[0087] S204 : For any delay parameter, in response to the delay parameter matching the corresponding abnormal jitter determination condition, determining that the end-to-end delay data includes abnormal delay jitter data.

[0088] In an embodiment of the present disclosure, each delay parameter in the delay parameter set can be judged based on a preset judgment method, and whether the delay parameter set contains partial data that matches the abnormal jitter judgment condition can be identified based on the judgment result, wherein the partial data that matches the abnormal jitter judgment condition can be determined as abnormal delay jitter data in the end-to-end delay data.

[0089] Optionally, for any delay parameter, when it is identified that the delay parameter is abnormal delay jitter data, it can be determined that the end-to-end delay data contains abnormal delay jitter data.

[0090] In the embodiments of the present disclosure, the determination of whether the delay parameter is abnormal delay jitter data can also be understood in conjunction with the following:

[0091] Optionally, for any delay parameter, in response to the delay parameter being greater than or equal to a preset delay parameter threshold, it is determined that the delay parameter matches the corresponding abnormal jitter determination condition.

[0092] In an embodiment of the present disclosure, each delay parameter in the delay parameter set has its own set delay parameter threshold. In this scenario, for any delay parameter, when the delay parameter is greater than or equal to its corresponding delay parameter threshold, it can be determined that the delay parameter may be data collected in a scenario where abnormal jitter occurs in the end-to-end delay. Furthermore, the delay parameter can be determined as abnormal delay jitter data that matches its corresponding abnormal jitter determination condition.

[0093] S205 , in response to identifying that the end-to-end delay data includes abnormal delay jitter data, performing delay jitter optimization on a control link of the vehicle.

[0094] Optionally, in response to the end-to-end delay data including abnormal delay jitter data, an abnormal jitter frequency corresponding to the abnormal delay jitter data is obtained, and delay jitter optimization is performed on the control link of the vehicle based on the abnormal jitter frequency.

[0095] In an embodiment of the present disclosure, there is a certain degree of correlation between the cause of abnormal jitter in the end-to-end delay and the abnormal jitter frequency corresponding to the abnormal jitter. In this scenario, when it is identified that the end-to-end delay data contains abnormal jitter data, the jitter frequency corresponding to the abnormal delay jitter data can be obtained as the abnormal jitter frequency, and the cause of the abnormal jitter in the end-to-end delay is determined based on the abnormal jitter frequency, and then the vehicle's control link is optimized for the abnormal jitter of the end-to-end delay based on the cause, wherein the corresponding operation of the optimization is the corresponding operation of the delay jitter optimization of the vehicle's control link.

[0096] Optionally, based on the abnormal jitter frequency, the abnormal jitter cause corresponding to the end-to-end delay data is determined, and a jitter optimization strategy for the abnormal delay jitter data is determined according to the abnormal jitter cause, and the delay jitter optimization of the vehicle control link is performed according to the jitter optimization strategy.

[0097] In an embodiment of the present disclosure, the cause of abnormal jitter in the end-to-end delay of the vehicle's control link can be determined as an abnormal jitter cause, wherein each abnormal jitter cause has its own optimization strategy. Based on the abnormal jitter cause determination method in the related technology, the specific abnormal jitter cause of the vehicle's control link can be determined based on the abnormal jitter frequency, and then the end-to-end delay delay jitter of the vehicle's control link can be optimized based on the jitter optimization strategy corresponding to the abnormal jitter cause.

[0098] Optionally, when an abnormality occurs in some hardware facilities on the vehicle side, it may cause abnormal jitter in the end-to-end delay of the vehicle's control link. In this scenario, the relevant judgment conditions corresponding to the abnormal jitter caused by the hardware facilities can be obtained, and the abnormal jitter frequency can be compared with the judgment conditions. When the abnormal jitter frequency matches the judgment conditions, it can be determined that the abnormal jitter frequency in the current end-to-end delay is caused by an abnormality in the hardware facilities on the vehicle side.

[0099] In this scenario, the relevant hardware facilities can be checked and processed to optimize the delay jitter of the vehicle's control link.

[0100] Optionally, when an abnormality occurs in the software algorithm deployed on the vehicle side, it may cause abnormal jitter in the end-to-end delay of the vehicle's control link. In this scenario, the cause of the abnormal jitter can be checked and determined based on the abnormal jitter frequency based on the judgment method in the relevant technology. Among them, when it is determined that the cause of the abnormal jitter corresponding to the abnormal jitter frequency is due to the software algorithm dimension, the software algorithm used in the vehicle's control link can be checked, and the software algorithm can be repaired and adjusted based on the checking results, thereby achieving delay jitter optimization of the vehicle's control link.

[0101] The delay jitter optimization method proposed in the present invention obtains descriptive data of end-to-end delay stability by acquiring delay deterministic parameters, and obtains a delay parameter set based on the delay deterministic parameters, an abnormal jitter frequency set, and a jitter spectrum parameter, thereby improving the recognition accuracy and precision of end-to-end delay abnormal jitter identification for the vehicle control link based on the delay parameter set, performing delay jitter optimization when abnormal delay jitter is identified in the vehicle control link, thereby improving the accuracy of delay jitter optimization, thereby reducing the impact of abnormal delay jitter on vehicle performance, improving the stability of vehicle performance, and optimizing vehicle driving safety.

[0102] To better understand the above embodiments, Figure 3 , Figure 3 This is a flowchart of a delay jitter optimization method according to another embodiment of the present disclosure.

[0103] like Figure 3 As shown, the end-to-end delay data of the vehicle side can be detected and collected, and the end-to-end delay data of the vehicle side can be uploaded to the cloud through the communication link between the vehicle side and the cloud side.

[0104] like Figure 3 As shown, the cloud is equipped with a cloud storage function. After the end-to-end delay data is uploaded to the cloud, it can be stored in a preset storage area through the cloud storage function. Figure 3 The Fourier transform analysis module shown retrieves the end-to-end delay data from the storage area and performs Fourier transform on it to obtain the delay frequency domain representation corresponding to the end-to-end delay data, and then obtains the delay frequency domain representation from the delay frequency domain representation. Figure 3 The delay deterministic parameters, abnormal jitter frequency set and spectrum peak half-maximum width of each abnormal jitter frequency are shown.

[0105] Further, through Figure 3 The delay deterministic parameters, abnormal jitter frequency set and the spectrum peak half-maximum width of each abnormal jitter frequency are shown, and the delay parameter set of the end-to-end delay data is obtained, as shown in FIG. Figure 3 As shown, each delay parameter in the delay parameter set can be analyzed and verified, and based on the analysis and verification results, it can be determined whether the end-to-end delay data contains abnormal jitter data.

[0106] Optionally, when it is identified that the end-to-end delay data contains abnormal jitter data, the abnormal cause corresponding to the abnormal jitter data can be used to Figure 3 The vehicle control link at the vehicle end is shown to be optimized for delay jitter.

[0107] The delay jitter optimization method proposed in the present invention obtains descriptive data of end-to-end delay stability by acquiring delay deterministic parameters, and obtains a delay parameter set based on the delay deterministic parameters, an abnormal jitter frequency set, and a jitter spectrum parameter, thereby improving the recognition accuracy and precision of end-to-end delay abnormal jitter identification for the vehicle control link based on the delay parameter set, performing delay jitter optimization when abnormal delay jitter is identified in the vehicle control link, thereby improving the accuracy of delay jitter optimization, thereby reducing the impact of abnormal delay jitter on vehicle performance, improving the stability of vehicle performance, and optimizing vehicle driving safety.

[0108] The delay jitter optimization method proposed in this disclosure can also be understood in conjunction with the following:

[0109] As shown in Figure 4(a), Figure 4(a) shows frequency domain data without delay jitter optimization. Based on the delay jitter optimization method proposed in the above embodiment, the control link of the vehicle to which the end-to-end delay data corresponding to Figure 4(a) belongs can be optimized for delay jitter. The frequency domain data of the end-to-end delay of the control link of the vehicle after delay jitter optimization can be shown in Figure 4(b).

[0110] As shown in FIG4(a) and FIG4(b), after the delay jitter optimization, the abnormal jitter of the end-to-end delay of the vehicle control link is reduced.

[0111] The delay jitter optimization method proposed in the present invention obtains descriptive data of end-to-end delay stability by acquiring delay deterministic parameters, and obtains a delay parameter set based on the delay deterministic parameters, an abnormal jitter frequency set, and a jitter spectrum parameter, thereby improving the recognition accuracy and precision of end-to-end delay abnormal jitter identification for the vehicle control link based on the delay parameter set, performing delay jitter optimization when abnormal delay jitter is identified in the vehicle control link, thereby improving the accuracy of delay jitter optimization, thereby reducing the impact of abnormal delay jitter on vehicle performance, improving the stability of vehicle performance, and optimizing vehicle driving safety.

[0112] Corresponding to the delay jitter optimization methods proposed in the above-mentioned embodiments, an embodiment of the present disclosure also proposes a delay jitter optimization device. Since the delay jitter optimization device proposed in the embodiment of the present disclosure corresponds to the delay jitter optimization methods proposed in the above-mentioned embodiments, the implementation method of the above-mentioned delay jitter optimization method is also applicable to the delay jitter optimization device proposed in the embodiment of the present disclosure, and will not be described in detail in the following embodiments.

[0113] Figure 5 FIG. 1 is a structural diagram of a device for optimizing delay jitter according to an embodiment of the present disclosure. Figure 5As shown, the delay jitter optimization device 500 includes an acquisition module 51, an identification module 52 and an optimization module 53, wherein:

[0114] An acquisition module 51 is configured to acquire end-to-end delay data of a vehicle and perform spectrum analysis on the end-to-end delay data to obtain a delay parameter set of the end-to-end delay data;

[0115] An identification module 52 is configured to identify whether the end-to-end delay data contains abnormal delay jitter data based on the delay parameter set;

[0116] The optimization module 53 is configured to optimize the delay jitter of the vehicle control link in response to identifying that the end-to-end delay data includes abnormal delay jitter data.

[0117] In an embodiment of the present disclosure, the acquisition module 51 is further used to: perform spectral analysis on the end-to-end delay data to obtain delay determinism parameters, an abnormal jitter frequency set, and jitter spectrum parameters of each abnormal jitter frequency in the abnormal jitter frequency set of the end-to-end delay data, wherein the delay determinism parameters are used to characterize the delay stability of the end-to-end delay data; and obtain the delay parameter set of the end-to-end delay data based on the delay determinism parameters, the abnormal jitter frequency set, and the jitter spectrum parameters of each abnormal jitter frequency in the abnormal jitter frequency set.

[0118] In the embodiment of the present disclosure, the acquisition module 51 is further used to: perform Fourier transform on the end-to-end delay data to obtain a delay frequency domain representation of the end-to-end delay data; and obtain a zero-frequency component in the delay frequency domain representation to determine a delay deterministic parameter of the end-to-end delay data.

[0119] In the embodiment of the present disclosure, the acquisition module 51 is further used to: filter out non-zero frequency components from the delay frequency domain representation based on the delay deterministic parameter; filter out each abnormal jitter frequency from the non-zero frequency components based on a preset jitter frequency threshold to determine an abnormal jitter frequency set; and obtain the half-width at half-maximum of the spectrum of each abnormal jitter frequency in the abnormal jitter frequency set from the delay frequency domain representation to determine the jitter spectrum parameters of each abnormal jitter frequency.

[0120] In the embodiment of the present disclosure, the identification module 52 is further configured to: obtain an abnormal jitter determination condition for each delay parameter in the delay parameter set; and for any delay parameter, determine, in response to the delay parameter matching the corresponding abnormal jitter determination condition, whether abnormal delay jitter data exists in the end-to-end delay data.

[0121] In the embodiment of the present disclosure, the identification module 52 is further configured to: for any delay parameter, in response to the delay parameter being greater than or equal to a preset delay parameter threshold, determine that the delay parameter matches a corresponding abnormal jitter determination condition.

[0122] In the embodiment of the present disclosure, the optimization module 53 is further used to: in response to the presence of abnormal delay jitter data in the end-to-end delay data, obtain the abnormal jitter frequency corresponding to the abnormal delay jitter data, and optimize the delay jitter of the vehicle control link based on the abnormal jitter frequency.

[0123] In the disclosed embodiment, the optimization module 53 is further used to: determine the abnormal jitter cause corresponding to the end-to-end delay data based on the abnormal jitter frequency, and determine the jitter optimization strategy for the abnormal delay jitter data according to the abnormal jitter cause; and optimize the delay jitter of the vehicle control link according to the jitter optimization strategy.

[0124] The delay jitter optimization device proposed in the present disclosure obtains the end-to-end delay data of the vehicle's control link, and performs spectrum analysis on the end-to-end delay data to obtain a corresponding delay parameter set. It identifies whether the end-to-end delay data contains abnormal delay jitter data based on the delay parameter set, and optimizes the vehicle's control link for delay jitter when it is identified that the end-to-end delay data contains abnormal delay jitter data. In the present disclosure, the delay parameter set obtained through the end-to-end delay data is used to identify whether the vehicle's control link has abnormal delay jitter, thereby improving the accuracy and precision of identifying abnormal delay jitter in the vehicle's control link. When it is identified that the vehicle's control link has abnormal delay jitter, delay jitter optimization is performed, thereby improving the accuracy of delay jitter optimization, thereby reducing the impact of abnormal delay jitter on vehicle performance, improving the stability of vehicle performance, and optimizing vehicle driving safety.

[0125] To achieve the above embodiments, the present disclosure also provides an electronic device, a computer-readable storage medium, and a computer program product.

[0126] Figure 5 FIG. 5 is a block diagram of an electronic device 500 according to an embodiment of the present disclosure. Figure 5 As shown, the electronic device 500 includes a memory 501, a processor 502, and a computer program stored in the memory 501 and executable on the processor 502. When the processor 502 executes the program instructions, the delay jitter optimization method provided in the above embodiment is implemented.

[0127] Optionally, the electronic device may be a server device or a separate processing platform.

[0128] In order to implement the above embodiments, the present disclosure further proposes a non-transitory computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the delay jitter optimization method provided in the above embodiments is implemented.

[0129] In order to implement the above embodiments, the present disclosure further provides a computer program product having a computer program stored thereon. When the computer program is executed by a processor, the method for optimizing delay jitter provided in the above embodiments is implemented.

[0130] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0131] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0132] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may be performed out of the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by those skilled in the art to which the embodiments of the present disclosure belong.

[0133] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering, or processing in another suitable manner as necessary, and then stored in a computer memory.

[0134] It should be understood that various parts of the present disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used to implement the present invention: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field-programmable gate array (FPGA), etc.

[0135] Those skilled in the art will understand that all or part of the steps in the method of the above embodiment can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.

[0136] In addition, the functional units in the various embodiments of the present disclosure may be integrated into a single processing module, or each unit may exist physically separately, or two or more units may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or in the form of software functional modules. If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may also be stored in a computer-readable storage medium.

[0137] The storage medium mentioned above may be a read-only memory, a magnetic disk, or an optical disk, etc. Although the embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. A person of ordinary skill in the art may make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

[0138] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0139] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A method for optimizing delay jitter, characterized in that: The method comprises: Acquiring end-to-end delay data of the vehicle, and performing spectrum analysis on the end-to-end delay data to obtain a delay parameter set of the end-to-end delay data; identifying, according to the delay parameter set, whether the end-to-end delay data includes abnormal delay jitter data; In response to identifying that the end-to-end delay data includes the abnormal delay jitter data, delay jitter optimization is performed on the control link of the vehicle.

2. The method according to claim 1, characterized in that The acquiring end-to-end delay data of the vehicle and performing spectrum analysis on the end-to-end delay data to obtain a delay parameter set for the end-to-end delay data includes: Performing spectrum analysis on the end-to-end delay data to obtain a delay deterministic parameter of the end-to-end delay data, an abnormal jitter frequency set, and a jitter spectrum parameter of each abnormal jitter frequency in the abnormal jitter frequency set, wherein the delay deterministic parameter is used to characterize the delay stability of the end-to-end delay data; The delay parameter set of the end-to-end delay data is obtained according to the delay deterministic parameter, the abnormal jitter frequency set, and the jitter spectrum parameter of each abnormal jitter frequency in the abnormal jitter frequency set.

3. The method according to claim 2, characterized in that The performing spectrum analysis on the end-to-end delay data to obtain a delay determinism parameter of the end-to-end delay data, wherein the delay determinism parameter is used to characterize the delay stability of the end-to-end delay data, includes: Performing Fourier transform on the end-to-end delay data to obtain a delay frequency domain representation of the end-to-end delay data; A zero-frequency component in the frequency-domain representation of the time delay is obtained to determine the time delay deterministic parameter of the end-to-end time delay data.

4. The method according to claim 2, characterized in that The performing spectrum analysis on the end-to-end delay data to obtain an abnormal jitter frequency set of the end-to-end delay data and a jitter spectrum parameter of each abnormal jitter frequency in the abnormal jitter frequency set includes: Filtering non-zero frequency components from the frequency domain representation of the time delay according to the time delay deterministic parameter; According to a preset jitter frequency threshold, each abnormal jitter frequency is screened out from the non-zero frequency components to determine the abnormal jitter frequency set; The frequency spectrum half-maximum width of each abnormal jitter frequency in the abnormal jitter frequency set is obtained from the frequency domain representation of the time delay to determine the jitter spectrum parameter of each abnormal jitter frequency.

5. The method according to claim 1, wherein The identifying, according to the delay parameter set, whether the end-to-end delay data includes abnormal delay jitter data includes: Determining abnormal jitter determination conditions for each delay parameter in the delay parameter set; For any delay parameter, in response to the delay parameter matching a corresponding abnormal jitter determination condition, it is determined that the end-to-end delay data includes abnormal delay jitter data.

6. The method according to claim 1, characterized in that In response to identifying that the end-to-end delay data includes the abnormal delay jitter data, optimizing the delay jitter of the control link of the vehicle includes: In response to the end-to-end delay data including the abnormal delay jitter data, an abnormal jitter frequency corresponding to the abnormal delay jitter data is obtained, and delay jitter optimization is performed on the control link of the vehicle based on the abnormal jitter frequency.

7. The method according to claim 6, characterized in that The method further comprises: Determining an abnormal jitter cause corresponding to the end-to-end delay data based on the abnormal jitter frequency, and determining a jitter optimization strategy for the abnormal delay jitter data according to the abnormal jitter cause; Delay jitter optimization is performed on the control link of the vehicle according to the jitter optimization strategy.

8. A device for optimizing delay jitter, characterized in that: The device comprises: an acquisition module, configured to acquire end-to-end delay data of a vehicle, and perform spectrum analysis on the end-to-end delay data to obtain a delay parameter set of the end-to-end delay data; an identification module, configured to identify, based on the delay parameter set, whether the end-to-end delay data includes abnormal delay jitter data; An optimization module is configured to, in response to identifying that the end-to-end delay data includes the abnormal delay jitter data, optimize the delay jitter of the control link of the vehicle.

9. The device according to claim 8, wherein: The acquisition module is further used to: Performing spectrum analysis on the end-to-end delay data to obtain a delay deterministic parameter of the end-to-end delay data, an abnormal jitter frequency set, and a jitter spectrum parameter of each abnormal jitter frequency in the abnormal jitter frequency set, wherein the delay deterministic parameter is used to characterize the delay stability of the end-to-end delay data; The delay parameter set of the end-to-end delay data is obtained according to the delay deterministic parameter, the abnormal jitter frequency set, and the jitter spectrum parameter of each abnormal jitter frequency in the abnormal jitter frequency set.

10. The device according to claim 9, characterized in that The acquisition module is further used to: Performing Fourier transform on the end-to-end delay data to obtain a delay frequency domain representation of the end-to-end delay data; A zero-frequency component in the frequency-domain representation of the time delay is obtained to determine the time delay deterministic parameter of the end-to-end time delay data.

11. The device according to claim 9, characterized in that The acquisition module is further used to: Filtering non-zero frequency components from the frequency domain representation of the time delay according to the time delay deterministic parameter; According to a preset jitter frequency threshold, each abnormal jitter frequency is screened out from the non-zero frequency components to determine the abnormal jitter frequency set; The frequency spectrum half-maximum width of each abnormal jitter frequency in the abnormal jitter frequency set is obtained from the frequency domain representation of the time delay to determine the jitter spectrum parameter of each abnormal jitter frequency.

12. An electronic device, characterized in that: include: processor; a memory for storing executable instructions for the processor; The processor is configured to execute instructions to implement the method according to any one of claims 1 to 7.

13. A computer-readable storage medium, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method according to any one of claims 1 to 7.

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