Multi-chip module packaging techniques for advanced driver assistance system applications

Abstract

The invention relates to a multi-chip module packaging technique for advanced driver assistance system applications. Aspects of the present disclosure relate to automotive level MCM techniques that may include an advanced driver assistance system (ADAS) system-on-chip and a plurality of dynamic random access memories (DRAMs) in one package. In addition, a thermo-mechanical test carrier (TMTV) may be used to simulate ADAS chips on an ADAS system from a thermal, mechanical, or manufacturability perspective. There may be a system that includes a plurality of MCM components designed into a custom printed circuit board (PCB) having a liquid cooling system.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 554,082, filed on February 15, 2024, entitled “MULTI-CHIP-MODULE PACKAGE TECHNOLOGY FOR ADAS APPLICATION,” which is incorporated herein by reference in its entirety. Background Art

[0003] A multi-chip module (MCM) is typically an electronic assembly (such as a package with multiple conductor terminals or "pins") in which multiple integrated circuits (ICs or "chips"), semiconductor dies, or other discrete components can be integrated onto a common substrate, typically so that in use, the MCM can be considered a larger IC. MCM packaging can allow manufacturers to use multiple components to achieve modularity or improve yield compared to traditional monolithic IC approaches. In addition, some ICs have very similar or identical pins when used multiple times within a system. A carefully designed substrate can allow these dies to be stacked in a vertical configuration, resulting in a smaller footprint for the resulting MCM, as area can be at a premium in miniature electronic device design.

[0004] As part of the manufacturing process, packaged or unpackaged integrated circuits may undergo environmental testing. In this testing, the integrated circuit device may be subjected to electrical testing (e.g., "test mode") to confirm functionality when subjected to environmental stresses. For example, the integrated circuit may be heated or cooled to its specification limits during electrical testing. In some cases, such as for qualification testing, the integrated circuit may be subjected to stresses exceeding its specifications, for example, to identify failure points or establish a protection band around its environmental specifications.

[0005] Various aspects of the subject technology can help improve the overall cost, reliability, and efficiency of circuits or other electronic components. Summary of the Invention

[0006] This specification generally relates to automotive-grade MCM technology that can include an Advanced Driver Assistance System (ADAS) system-on-chip (SoC) and multiple dynamic random access memories (DRAMs) in a single package. Additionally, a thermomechanical test vehicle (TMTV) can be used to simulate the ADAS chip on an ADAS system from a thermal, mechanical, or manufacturability perspective. A system can include multiple MCM components designed into a custom printed circuit board (PCB) with a liquid cooling system. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Certain features of the subject technology are set forth in the appended claims.For illustrative purposes, however, several embodiments of the subject technology are set forth in the following figures.

[0008] Figure 1 An example view of a multi-chip module (MCM) is shown, which may include an ADAS system-on-chip (SoC) and multiple DRAMs in a co-package.

[0009] Figure 2A An example side cross-sectional view of chip packaging technology on a substrate is shown.

[0010] Figure 2B An example side cross-sectional view of chip packaging technology on a printed circuit board is shown.

[0011] Figure 3 An example MCM and cover are shown.

[0012] Figure 4A and Figure 4B An example MCM is shown that takes the TIM into account.

[0013] Figure 5A An example liquid cooling configuration associated with a TMTV is shown.

[0014] Figure 5B An example board associated with TMTV is shown.

[0015] Figure 6 An example TMTV design feature summary is shown.

[0016] Figure 7 An example die crack sensor configuration is shown.

[0017] Figure 8 Example capacitor-related TMTV design features are shown.

[0018] Figure 9 Example corner bumps and stacked vias associated with TMTV design features are shown. DETAILED DESCRIPTION

[0019] The specific embodiments set forth below are intended to be used as a description of various configurations of the subject technology, and are not intended to represent the only configuration that can be put into practice. The accompanying drawings are incorporated herein and constitute a part of the specific embodiments. In order to provide a comprehensive understanding of the subject technology, the specific embodiments include specific details. However, the subject technology is not limited to the specific details set forth herein, and one or more other specific implementations can be used to put it into practice. In one or more specific implementations, well-known structures and components are shown in block diagram form to avoid confusion between the concepts of the subject technology.

[0020] like Figure 1 As shown, a multi-chip module (MCM) 100 may include a processor 101 (e.g., an ADAS SoC) and a plurality of DRAMs (e.g., DRAM 104, DRAM 105, or DRAM 106) co-packaged with the processor 101, which may allow for implementation of double data rate (DDR) bandwidth requirements at the ADAS system level, resulting in reduced cost, increased power delivery, or further optimization. Figure 1 Three DRAMs are shown, but there may be any suitable number of DRAMs surrounding the processor 101. The number of DRAMs implemented may be based on memory bandwidth requirements (eg, the memory bandwidth (BW) requirements of the ADAS SoC, given the available DRAMs).

[0021] The disclosed MCM can meet the critical DDR bandwidth requirements of ADAS SoCs by ensuring data rates (e.g., LPDDR5x 8.5gbps) and ensuring signal and power quality, which would be difficult to meet if the DRAM was originally integrated at the board level. This in turn can help save system costs related to DRAM, which may include the following assumption: if the MCM theme as shown in Figure 2 is implemented, the same total bandwidth is required regardless of the DRAM integration scheme (co-package or on-board). Figure 2A and Figure 2B An example comparison of an MCM and a flip chip ball grid array (FCBGA) is shown. Figure 2A An example side cross-sectional view of a chip packaging technology on a substrate is shown. MCM 100 may include a printed circuit board (PCB) 109, a substrate 108, a processor 101 (e.g., SoC 101) or a memory 104 (e.g., DRAM 104). As shown in FIG2 , processor 101 and memory 104 may be on the same substrate 108 and may be connected via the substrate 108. Figure 2B An example side cross-sectional view of chip packaging technology on a PCB is shown. Figure 2B As shown, MCM 110 may include PCB 119, substrate 118, processor 111 (e.g., SoC 111), or memory 114 (e.g., DRAM 104). As shown in FIG2 , processor 111 may be on substrate 118, and memory 114 may be on PCB 119. Connections between processor 111 and memory 114 may be made through at least substrate 118 and PCB 119.

[0022] The disclosed MCM 100 can help achieve reduced cost and more efficient power delivery for ACM3 systems due to one or more of the following three considerations. A first consideration may be that high-density DRAM signal routing can be performed on the MCM 100 rather than on a PCB, thereby saving costs by using a standard through-hole printed circuit board (PCB) instead of a more expensive microvia type. A second consideration may be that packaging the DRAM 104 on the MCM architecture allows for a smaller PCB area and a smaller system cold plate form factor. The form factor reduction opportunity can be a significant portion of the total footprint reduction (e.g., approximately 70% or more) compared to an on-board SoC + DRAM. The board design can be simplified without DDR, and the SoC / DRAM can be used as a known good unit for system-level startup. A third consideration may be that because the customized MCM ball grid array (ball pitch and ball pattern) facilitates optimized PCB backside capacitor placement, better power delivery (e.g., reduced power-related noise) can be achieved, and poor power delivery planes caused by DRAM routing on the PCB 109 can be eliminated, as well as the power management integrated circuit (PMIC) being closer to the SoC's critical IP load points to reduce IR drop. In one example, when considering other packaging technologies such as MCM 110, the total power-related noise margin can be reduced by more than 50%, the worst-case voltage drop can be reduced by more than 50%, the DC resistance can be reduced by more than 30%, or the AC inductance (ACI) can be reduced by more than 40%.

[0023] Beyond the SoC die, other aspects of the package or PCB layout can be optimized for overall system-level performance. In one example, the core IP can be placed at the leading edge of the die to ensure direct access to die-side capacitors, enabling fast di / dt transient response for the power delivery network and close access to the PMIC placed on the PCB.

[0024] The disclosed subject matter may be associated with automotive-grade MCM technology that can include an ADAS SoC 101 and multiple DRAMs 104 in a single package. As disclosed herein, a multi-chip module (MCM) 100 can integrate DRAMs 104 with SoC 101 as one integral ball grid array component for applications such as autonomous driving.

[0025] As disclosed, the DRAM 104 can be placed around the SoC 101. The more symmetrical the configuration, such as in a "butterfly" floor plan, the greater the likelihood that warpage, if it occurs, will be more uniform. The design and signal / power performance of each SoC PHY to DRAM can be repeated across multiple instances to provide predictable system-level performance when multiple DRAMs are operated under various user conditions. A SoC in an approximately central location in the package floor plan can help save approximately 3C-5C maximum junction temperature (Tjmax) at key IP (such as a machine learning engine), thereby helping to improve performance or save power. Such a structure can be mechanically balanced, which can achieve uniform warpage distribution, thereby facilitating a robust surface mount technology (SMT) process when assembled on the PCB 109.

[0026] Figure 3 An example thermal cover 130 that can be combined with the MCM 100 is shown. The thermal cover 130 can include a boss 131, a landing surface 133, or a cavity 135. The thermal cover 130 can be made of nickel-plated copper (Ni-plated Cu) with a boss design, such as Figure 3 As shown. The thermal cover 130 can be made of copper (Cu) plated with nickel (Ni). The thermal conductivity (about 385 W / m·K at room temperature) and mechanical properties of copper make it suitable for use as the main structural material, while the nickel plating can provide protection to the surface from oxidation or corrosion. The nickel plating thickness can be adopted based on the requirements of the specific application. The thermal cover 130 can alternatively be made of other thermally conductive materials such as aluminum (Al), copper tungsten (Cu-W), copper molybdenum (Cu-Mo), or other suitable metals or metal alloys with appropriate thermal or mechanical properties for semiconductor packaging applications. Table 1 shows example considerations associated with the thermal cover 130.

[0027] Table 1

[0028]

[0029] The disclosed boss configuration of the thermal cover 130 can address inefficiencies caused by the Z-height difference between the SoC silicon and the DRAM components. As shown, the boss 131 can be placed above the SoC 101 or the DRAM 104, whichever is shortest (typically the SoC 101), or above multiple components (e.g., one or more DRAMs 104, 105, 106 and the SoC 101). In one example, where the SoC 101 has a distinct cavity (e.g., cavity 135), it may be desirable to reduce the size of the cavity 135 between the thermal cover 130 and the SoC 101. Therefore, the thermal cover 130 can be formed with the boss 131 associated with the thermal cover 130 (e.g., a boss overhang or protrusion), which can improve performance.

[0030] Figure 4A and Figure 4B The cross-sectional views of FIG. 1 and FIG. 2 respectively illustrate example structures with and without a DRAM thermal interface material (TIM) implementation. Figure 4A , a first configuration depicts MCM 100 implementing DRAM TIM 137, wherein SoC 101 may be surrounded by multiple DRAM components (e.g., DRAM 104, DRAM 105, DRAM 106) on substrate 108. When tested, thermal maps have shown a substantially uniform temperature gradient across the package surface, as indicated by the coloring (e.g., green) indicating effective heat dissipation.

[0031] refer to Figure 4B , the second configuration depicts the Figure 4A A similar semiconductor package arrangement, but without DRAM TIM 137. When tested, several areas on the thermal map showed significantly elevated temperatures, such as around the DRAM areas (e.g., areas around DRAM 104, DRAM 105, DRAM 106), which is indicated by coloring (e.g., red) indicating less effective heat dissipation.

[0032] As disclosed, a thermal interface material (TIM) can be placed on top of DRAM 104 to provide a low thermal impedance path for DRAM 104, which can achieve a lower Tjmax for DRAM 104 and, in turn, help increase available DRAM bandwidth by approximately 20% from reduced DRAM refresh cycles. Material selection and tolerance analysis can ensure that the TIM volume on the DRAM is adequate but not overflowing, which can be a significant driver. With a DRAM TIM, the DRAM junction temperature can be reduced by approximately thirty degrees or more when tested. Without a TIM, the peak junction temperature can reach reliability limits (e.g., 110 degrees Celsius).

[0033] Continuing with reference to thermal lid 130, a thicker Cu lid (e.g., a boss overhang) on ​​top of SoC 101 can provide lower thermal impedance and lower Tjmax for critical IP. Intentionally designed lid cavity 135 depth and boss 131 overhang can optimize thermal benefits by minimizing thermal interface material (TIM) bondline thickness or compensate for TIM delamination at the edge of the SoC die, a common degradation after reliability stress testing. The selection of a TIM for SoC 101 can be modeled and characterized to balance thermal benefits and mechanical stresses resulting from chip-package interactions.

[0034] For TIM, microfilm insulation can be selected, such as a construction substrate based on Ajinomoto Build-up Film (ABF). The bill of materials (BOM), stack-up, or area can be selected based on high-speed serializer / deserializer (SerDes) signal loss requirements, DDR and high-speed SerDes signal and power fan-out requirements, core IP power delivery requirements, or ball grid array requirements for ball count / pin map and ball pitch.

[0035] Figure 5A A perspective view of an example test plate apparatus 140 (eg, a liquid-cooled cold plate) that may be associated with an MCM thermo-mechanical test vehicle (TMTV) is shown. Figure 5B A perspective view of an opened test board assembly 140 is shown. In some examples, to qualify the MCM 100 as an automotive-grade ADAS component, a combined thermal and mechanical daisy-chain test vehicle, a thermo-mechanical test vehicle (TMTV), can be used to simulate the thermal, mechanical, and reliability aspects of a fully functional MCM on an ADAS system board with a complete thermal / mechanical enclosure, as further disclosed herein.

[0036] Figure 5A is a perspective view of a test board apparatus 140 showing a top surface of a substrate having mounting areas 141 and 142, connectors 144 (e.g., power or signal connectors) disposed along a first edge, thermal management features, and thermal monitoring elements integrated into the substrate surface. Figure 5B is an exploded perspective view of test board assembly 140 showing a plurality of integrated components. Mounting area 141 and mounting area 142 are configured to receive semiconductor components. Connector 144 may include a plurality of pins configured for power delivery. Thermal management features may include fluid channels 146 configured for coolant circulation. A thermal monitoring element 147 may be disposed adjacent to mounting area 141 or mounting area 142, wherein thermal monitoring element 147 may be configured to measure a temperature distribution across the mounting area. Test board assembly 140 may be configured to evaluate thermal performance parameters, which may include junction temperature, thermal resistance, or power delivery characteristics of a multi-chip semiconductor package mounted thereon.

[0037] As disclosed herein, the thermal design and characterization of the TMTV 140 can impact the die, package, PCB, liquid cooling cold plate, external power supply, or data acquisition system. For the die, heaters and sensors can be designed to be embedded within a two-layer metal daisy-chain silicon. Heater and sensor placement can be based on the SoC IP power consumption and thermal map.

[0038] Package substrate and PCB design features can be specified to provide a low thermal resistance path, while PCB edge power and sense pin connectors can be selected to meet the requirements.

[0039] A liquid cooling based cold plate can be designed for the TMTV140 so that the SoC and DRAM thermals can be characterized according to the liquid coolant flow rate and temperature specified by the automotive user conditions.

[0040] Other thermal characterization components can be designed and specified, such as coolers, flow meters, pressure transducers, etc. A thermal characterization plan can be developed to characterize the SoC junction temperature under different user conditions, such as full mission mode, process mode, or gear protection safety mode, as well as other modes that can be used for on-road or off-road driving.

[0041] MCM technology development can utilize the mechanical daisy chain feature in the TMTV 140, along with other features, to evaluate connectivity and reliability from die to substrate to PCB. The daisy chain design simulates functional paths while enabling high-resolution test capabilities across multiple package interfaces, such as Figures 6 to 9 shown.

[0042] refer to Figure 6 Table 2 provides an example TMTV design feature summary matrix that lists the various test structures throughout the package. This example may include bump daisy chains (60 balls total) distributed across the periphery and core areas, multiple stacked via configurations, monitoring points, die crack sensors, and dedicated DDR connection test structures. Figure 6 An example schematic diagram of a ball grid array level daisy chain connection is shown. The example layout diagram features test areas arranged in a grid pattern with designated HSIO (High Speed ​​Input / Output) areas indicated.

[0043] Table 2

[0044]

[0045]

[0046] Figure 7 An example die crack sensor implementation is shown, showing a daisy-chain configuration between metal layers Mr1 and Mr2. In one example, the sensor design incorporates precise dimensional control, including a minimum line width of approximately 0.45 μm, a via diameter of approximately 0.41 μm, and a seal ring spacing of approximately 0.225 μm. Combined with post-dicing optical inspection, this configuration can enable monitoring of potential die crack formation during reliability testing.

[0047] Figure 8 An example capacitor test structure layout and verification method is shown. The design can include designated test areas with specific connectivity and inspection criteria, which can allow evaluation of capacitor functionality, short circuits, or the overall capacitance characteristics of the entire package.

[0048] Figure 9An example die corner stress sensor design is shown through flip chip bumps and underlying stacked vias in the flip chip substrate. Figure 9 A corner bump and stacked via implementation strategy is presented, featuring different stacked via configurations between different layer combinations (L1-L4, L1-L3, L2-L5, L2-L4) at each corner of the processor die. This design can enable monitoring of mechanical stress effects and electrical connections at package locations considered critical.

[0049] During the MCM substrate manufacturing and die assembly processes, daisy chains are tested based on their resistance targets and acceptable resistance excursion ranges to report initial yield loss over time and component- and board-level reliability stress degradation, categorized by per-daisy-chain coverage. Daisy-chain structures that fail or barely pass the test are then analyzed using electrical and physical failure analysis techniques to identify root causes and solutions. These findings are then applied to fully functional chip package design and BOM selection.

[0050] Multiple MCM packages are designed into a product that simulates an ADAS board, such as Figure 5B As shown, the board stackup and BOM adhere to the product requirements. In addition to the two MCM components, edge connectors are placed to provide power for thermal testing, as well as signal channels for daisy-chain resistance testing during in-situ and ex-situ stress testing of system-level reliability. Stress conditions can be created according to the specified system requirements, and this TMTV 140 setup is capable of performing comprehensive thermal characterization and reliability testing, including power temperature cycling, shock, vibration, temperature cycling, or temperature humidity.

[0051] The system enclosure can include a liquid-cooled cold plate. Backside metal-based stiffeners can be designed to implement a force-controlled cold plate fastening mechanism, which is crucial to ensure a minimum TIM2 thickness (the thermal interface between the cold plate and the MCM) and thereby reduce the thermal impedance path from the fully functional MCM to the external cooling system. Otherwise, the Tjmax loss of the SoC is estimated to be as high as 10°C.

[0052] The methods, systems, or devices disclosed herein may be incorporated into electric vehicles or other devices. A multi-chip module (MCM) and a thermomechanical test vehicle (TMTV) are disclosed herein. The MCM may include dynamic random access memory (DRAM) and a system-on-chip (SoC), wherein the DRAM and SoC are integrated into a single ball grid array component for various applications. The DRAM may be placed symmetrically around the SoC, with some implementations resembling a butterfly-shaped layout. When the DRAM is placed approximately symmetrically (or radially distributed) around the SoC, a butterfly-shaped layout or a similar layout may be formed. The MCM may also include a thermal cover that may be constructed of nickel and copper with a boss design. Applications of the MCM may include integration into a vehicle (e.g., an electric vehicle) or use in an autonomous driving system. The TMTV may include a thermal and mechanical daisy-chain test vehicle that simulates the thermal, mechanical, and reliability aspects of an MCM on an advanced driver assistance system (ADAS) board with a thermal or mechanical enclosure. In addition, the TMTV may include a die, a package substrate, a liquid-cooled cold plate, or a data acquisition system. Other TMTV components may include a cooler, a flow meter, or a pressure transducer.

[0053] A test device and associated features are disclosed herein. A test device may include: a substrate having a first mounting area and a second mounting area configured to receive a semiconductor component; a plurality of connectors positioned along a first edge of the substrate, the connectors including a plurality of pins configured for power or signal transmission; a plurality of fluid channels integrated into the substrate, the fluid channels configured for coolant circulation; a plurality of thermal monitoring elements positioned adjacent to the first and second mounting areas, the thermal monitoring elements configured to measure temperature distribution; or a plurality of alignment features configured to secure a thermal solution to the substrate while maintaining a predetermined contact pressure with the semiconductor component. The thermal monitoring elements may include temperature sensors configured to measure the junction temperature of the semiconductor component and may be configured to measure thermal resistance between the semiconductor component and the thermal solution. The plurality of connectors may include a first connector configured for power transmission or a second connector configured for signal transmission. The plurality of fluid channels may include an inlet port configured to receive coolant, an outlet port configured to discharge coolant, or a plurality of fluid channels connecting the inlet port to the outlet port. A thermal interface layer may be provided between the mounting area and the thermal solution, the thermal interface layer being configured to provide thermal coupling between the semiconductor component and the thermal solution. All combinations of this and the above paragraphs (including removal or addition of elements) are contemplated in a manner consistent with other portions of the detailed description.

[0054] Unless otherwise specified, an element mentioned in the singular is not intended to mean one and only one, but rather one or more. For example, "a" module may refer to one or more modules. Without further constraints, an element beginning with "a," "an," "the," or "said" does not exclude the presence of additional identical elements.

[0055] Headings and subheadings, if any, are used for convenience only and do not limit the invention. The word "exemplary" is used to mean serving as an example or illustration. To the extent that the terms "including" or "having" are used, such terms are intended to be inclusive in a manner similar to the term "comprising," as understood when "including" is used as a transitional word in a claim. Relational terms such as first and second may be used to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions.

[0056] Phrases such as an aspect, this aspect, another aspect, some aspects, one or more aspects, a specific implementation, this specific implementation, another specific implementation, some specific implementations, one or more specific implementations, an embodiment, this embodiment, another embodiment, some embodiments, one or more embodiments, a configuration, this configuration, another configuration, some configurations, one or more configurations, the subject technology, the disclosure, the disclosure, other variations thereof, etc., are for convenience and do not imply that the disclosure associated with such phrases is essential to the subject technology or that such disclosure applies to all configurations of the subject technology. The disclosure associated with such phrases may apply to all configurations or one or more configurations. The disclosure associated with such phrases may provide one or more examples. Phrases such as an aspect or some aspects may refer to one or more aspects, and vice versa, and this applies similarly to the other aforementioned phrases.

[0057] The phrase "at least one of" following a list of items, with the terms "and" or "or" used to separate any of those items, modifies the list as a whole, not each of its constituent items. The phrase "at least one of" does not require selection of at least one item; rather, the phrase allows for the meaning of at least one of any of those items, and / or at least one of any combination of those items, and / or at least one of each of those items. As an example, each of the phrases "at least one of A, B, and C" or "at least one of A, B, or C" means only A, only B, or only C; any combination of A, B, and C; and / or at least one of each of A, B, and C.

[0058] It should be understood that the specific order or level of the disclosed steps, operations or processes is an illustration of an exemplary method. Unless otherwise clearly stated, it should be understood that the specific order or level of steps, operations or processes can be performed in different orders. Some of the steps, operations or processes can be performed simultaneously. The attached method claims (if any) present the elements of various steps, operations or processes in a sample order and are not meant to be limited to the specific order or level presented. These can be performed continuously, linearly, in parallel or in different orders. It should be understood that the described instructions, operations or systems can usually be integrated together in a single software / hardware product or packaged into multiple software / hardware products.

[0059] In one aspect, the term "coupled" or the like may refer to a direct coupling. In another aspect, the term "coupled" or the like may refer to an indirect coupling.

[0060] Terms such as top, bottom, front, back, side, horizontal, vertical, etc. refer to an arbitrary reference frame other than the ordinary gravitational reference frame. Thus, such terms may extend upward, downward, diagonally, or horizontally in a gravitational reference frame.

[0061] The present disclosure is provided to enable any person skilled in the art to practice the various aspects described herein. In some instances, well-known structures and components are shown in block diagram form to avoid confusion about the various concepts of the subject technology. The present disclosure provides various examples of the subject technology, and the subject technology is not limited to these examples. Various modifications to these aspects will be readily apparent to those skilled in the art, and the principles described herein may be applied to other aspects.

[0062] All structural and functional equivalents of the various elements of the various aspects described throughout this disclosure are known or will later become known to those of ordinary skill in the art, and these equivalents are expressly incorporated herein by reference and are intended to be included in the claims. In addition, nothing disclosed herein is intended to serve the public, regardless of whether such disclosure is explicitly stated in the claims. No claim element should be interpreted under the provisions of 35 U.S.C. § 112(f) unless the element is explicitly stated using the phrase "means for..." or, in the case of a method claim, the element is stated using the phrase "step for..."

[0063] Those skilled in the art will appreciate that the various illustrative blocks, modules, elements, parts, methods and algorithms described herein can be implemented as hardware, electronic hardware, computer software or a combination thereof. In order to illustrate this interchangeability of hardware and software, various illustrative blocks, modules, elements, parts, methods and algorithms have been generally described above in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application. Various components and blocks can be arranged differently (e.g., arranged in different orders or divided in different ways), all of which do not depart from the scope of the present subject technology.

[0064] The invention title, background technology, figure description, abstract of the specification and drawings are hereby incorporated into this disclosure and are provided as illustrative examples of the present disclosure rather than as limiting descriptions. It is submitted with the understanding that they will not be used to limit the scope or meaning of the claims. In addition, in the detailed description, it can be seen that for the purpose of simplifying the present disclosure, the description provides illustrative examples and various features are grouped together in various specific implementations. The method of the present disclosure should not be interpreted as reflecting an intention that the claimed subject matter requires more features than those expressly stated in each claim. On the contrary, as reflected in the claims, the inventive subject matter lies in less than all the features of a single disclosed configuration or operation. The claims are hereby incorporated into the detailed description, with each claim independently serving as a separately claimed subject matter.

[0065] The claims are not intended to be limited to the aspects described herein, but should be given the full scope consistent with the language of the claims and encompassing all legal equivalents. Nevertheless, none of the claims is intended to encompass subject matter that fails to meet the requirements of applicable patent law, nor should they be interpreted in such a manner.

Claims

1. A multi-chip module (MCM), comprising: Dynamic random access memory (DRAM); and System on a chip (SoC) wherein the DRAM and the SoC are integrated as one unitary ball grid array component for application.

2. The MCM of claim 1, wherein the DRAM is positioned approximately symmetrically around the SoC.

3. The MCM of claim 1, wherein the DRAMs are positioned to form a butterfly-shaped floor plan. The MCM of claim 1 , further comprising a thermal cover.

5. The MCM of claim 4, wherein the thermal cover comprises nickel and copper, and wherein the thermal cover employs a boss design. The MCM of claim 4 , wherein the thermal cover comprises nickel-plated copper.

7. The MCM of claim 4, wherein the thermal cover further comprises a first material and a second material, wherein the first material is configured to provide a threshold thermal conductivity.

8. The MCM of claim 7, wherein the second material is configured to provide protection against a threshold level of corrosion.

9. The MCM of claim 7, wherein the first material comprises copper tungsten.

10. The MCM of claim 7, wherein the first material comprises copper molybdenum.

11. The MCM of claim 4, further comprising a thermal interface material (TIM), wherein the TIM is positioned over one or more of the DRAMs.

12. The MCM of claim 11, wherein the TIM comprises a specialized polymer film.

13. The MCM of claim 4, wherein the thermal cover comprises a chamber. The MCM of claim 4 , wherein the thermal cover comprises a boss above the SoC.

15. The MCM of claim 4, wherein the thermal cover comprises a boss over one or more of the DRAMs.

16. The MCM of claim 1, wherein the MCM is integrated into an electric vehicle.

17. The MCM of claim 1, wherein the application is an autonomous driving application.

18. A thermomechanical test vehicle (TMTV), comprising: tube core; Package substrate; and Liquid cooled cold plates.

19. The TMTV according to claim 18, further comprising: cooler; and Flow meter.

20. The TMTV of claim 19, further comprising a pressure transducer.

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