Integrated semiconductor device and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, in particular to an integrated semiconductor device and a preparation method thereof. The preparation method can comprise the following steps: providing a substrate, the substrate comprising a first conductive type SGT substrate region and a second conductive type BCD substrate region arranged transversely; forming at least one shallow trench isolation structure in the BCD substrate region; forming a withstand voltage gate trench structure and a shielding gate trench structure in at least the SGT substrate region, the shielding gate trench structure comprising a shielding gate, a control gate, a shielding gate oxide layer and a control gate oxide layer, the shielding gate oxide layer isolating the shielding gate from the substrate, the control gate oxide layer isolating the control gate from the substrate and isolating the shielding gate from the control gate; and forming an isolation oxide layer covering at least the surface of the shielding gate trench structure, the isolation oxide layer being continuous with the control gate oxide layer. The application can reduce the IGSS leakage risk of the SGT device and minimize the cross-influence of the integrated SGT device and BCD device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an integrated semiconductor device and a preparation method thereof. BACKGROUND

[0002] In the preparation process of integrated BCD (Bipolar CMOS DMOS, Bipolar-CMOS-DMOS) and SGT (Shielded Gate Trench, Shielded Gate Trench) devices, the SGT device structure is usually prepared in the integrated chip first, such as the SGT MOSFET (SGT Metal-Oxide-Semiconductor Field-Effect Transistor, Shielded Gate Trench Metal-Oxide-Semiconductor Field-Effect Transistor) structure, and then the BCD device structure is prepared to realize the integration of the two devices in the same chip. However, in the preparation process, the trench isolation structure of the BCD device needs high-temperature annealing treatment, which is easy to cause the IGSS (Gate Reverse Current, Gate Reverse Current) leakage problem of the SGT device. SUMMARY

[0003] To solve the above technical problems, the present application discloses, in one aspect, a preparation method of an integrated semiconductor device, which comprises:

[0004] providing a substrate, the substrate comprising a first conductive type SGT substrate region and a second conductive type BCD substrate region arranged laterally;

[0005] forming at least one shallow trench isolation structure in the BCD substrate region;

[0006] forming a voltage-resistant gate trench structure and a shielded gate trench structure in at least the SGT substrate region, the shielded gate trench structure comprising a shielded gate, a control gate, a shielded gate oxide layer and a control gate oxide layer, the shielded gate oxide layer isolating the shielded gate and the substrate, and the control gate oxide layer isolating the control gate and the substrate, and isolating the shielded gate and the control gate;

[0007] forming an isolation oxide layer covering at least the surface of the shielded gate trench structure, the isolation oxide layer being continuous with the control gate oxide layer.

[0008] In a possible implementation, the thickness of at least part of the control gate oxide layer is not more than a preset thickness, and the preset thickness is 70-130 A.

[0009] In a possible implementation, the control gate oxide layer is formed by surface oxidation treatment of at least the shielded gate and the trench wall of the shielded gate trench structure.

[0010] In a possible implementation manner, the preparation method further comprises:

[0011] The isolation oxide layer is formed by performing surface oxidation treatment on at least the control gate.

[0012] In a possible implementation manner, forming at least one shallow trench isolation structure in the BCD substrate region includes:

[0013] forming a pad oxide layer covering the BCD substrate region and the SGT substrate region on the substrate, and a first mask layer stacked on the pad oxide layer;

[0014] forming at least one first etching window located in the BCD base region on the first mask layer and the pad oxide layer based on a patterning process, and performing trench etching on the BCD base region based on the first etching window to obtain at least one shallow trench;

[0015] Filling the shallow trench with an isolation material to form the at least one shallow trench isolation structure;

[0016] The first mask layer is removed.

[0017] In a possible implementation manner, forming a voltage-resistant gate trench structure and a shielding gate trench structure at least in the SGT substrate region includes:

[0018] forming a second mask layer spanning the SGT substrate region and the BCD substrate region, wherein the second mask layer is stacked on the pad oxide layer;

[0019] forming at least one second etching window located at least in the SGT base region on the second mask layer and the pad oxide layer based on a patterning process, and performing trench etching on the SGT base region based on the second etching window to obtain a plurality of deep trenches;

[0020] Filling the plurality of deep trenches with a gate material to form at least one gate filling structure;

[0021] The voltage-resistant gate trench structure and the shielding gate trench structure are formed based on the at least one gate filling structure, and the voltage-resistant gate trench structure in the SGT substrate region is adjacent to the BCD substrate region.

[0022] In a possible embodiment, the second mask layer includes a hard mask layer stacked on the pad oxide layer and a mask oxide layer stacked on the hard mask layer, and filling the multiple deep trenches with a gate material to form at least one gate filling structure includes:

[0023] performing a trench wall oxidation process on the plurality of deep trenches to form an initial oxide layer covering the deep trench walls, the initial oxide layer being continuous with the pad oxide layer;

[0024] filling the deep trenches with a gate material to form a first fill layer filling the deep trenches and covering the second mask layer;

[0025] performing a thinning process on the first fill layer with the hard mask layer or the pad oxide layer as a stop layer to obtain at least one gate fill structure isolated from each other, the at least one gate fill structure including a first gate fill structure corresponding to the voltage-resisting gate trench structure and a second gate fill structure corresponding to the shield gate trench structure.

[0026] In a possible implementation, the forming of the voltage-resisting gate trench structure and the shield gate trench structure based on the at least one gate fill structure includes:

[0027] shielding the first gate fill structure;

[0028] performing an etch-back process on the second gate fill structure to form the shield gate;

[0029] removing the unshielded initial oxide layer and the pad oxide layer to expose an unshielded substrate surface, part of the deep trench walls and part of the shield gate, the initial oxide layer remaining in the exposed deep trenches forming the shield gate oxide layer;

[0030] performing an oxidation process on the exposed part of the shield gate, the exposed deep trench walls and the exposed substrate surface to form the control gate oxide layer, and removing the shielding layer;

[0031] depositing a gate material to backfill the etched-back deep trenches to form a second fill layer filling the deep trenches and covering the substrate;

[0032] performing a thinning process on the second fill layer with the hard mask layer or the pad oxide layer as a stop layer until the second fill layer is flush with the hard mask layer or flush with the pad oxide layer to obtain a thinned second fill layer;

[0033] etching the thinned second fill layer and the exposed first gate fill structure to expose the control gate oxide layer of the substrate surface to obtain the voltage-resisting gate trench structure and the control gate located above the shield gate.

[0034] In a possible implementation, the forming of the isolation oxide layer covering at least the surface of the shield gate trench structure includes:

[0035] performing a surface oxide layer removal on the substrate to expose the substrate surface;

[0036] Surface oxidation treatment is performed on the surface of the substrate, the voltage-resistant gate trench structure, and the control gate of the shielding gate trench structure to obtain the isolation oxide layer.

[0037] In a possible implementation manner, the gate filling structure is formed using the pad oxide layer as a stop layer, and forming the voltage-resistant gate trench structure and the shielding gate trench structure based on the at least one gate filling structure includes:

[0038] shielding the first gate filling structure;

[0039] Performing back etching on the second gate filling structure to form the shielding gate;

[0040] Removing the unmasked initial oxide layer and the pad oxide layer to expose the unmasked substrate surface, a portion of the deep trench wall and a portion of the shielding gate, and the initial oxide layer remaining in the exposed deep trench forms the shielding gate oxide layer;

[0041] removing the shielding layer and the shielded pad oxide layer, and forming the voltage-resistant gate trench structure;

[0042] forming a control gate oxide layer covering the exposed portion of the shielding gate, the exposed deep trench wall, the surface of the voltage-resistant gate trench structure, and the surface of the substrate;

[0043] Depositing a gate material to backfill the back-etched deep trench to form a second filling layer filling the deep trench and covering the control gate oxide layer;

[0044] The control gate oxide layer is used as a stop layer, and the second filling layer is thinned until the second filling layer is flush with the control gate oxide layer, thereby obtaining the control gate located above the shielding gate.

[0045] In a possible implementation manner, forming an isolation oxide layer that at least covers a surface of the shield gate trench structure includes:

[0046] The control gate of the shielding gate trench structure is subjected to surface oxidation treatment to form an isolation oxide layer continuous with the control gate oxide layer.

[0047] In a possible implementation manner, removing the shielding layer and the shielded pad oxide layer to obtain a voltage-resistant gate trench structure flush with the substrate surface includes:

[0048] removing the shielding layer;

[0049] performing oxidation treatment on the exposed portion of the shielding gate, the exposed deep trench wall, the exposed substrate surface, and the surface of the first gate filling structure to form a sacrificial oxide layer, wherein the sacrificial oxide layer is continuous with the shielded pad oxide layer;

[0050] The sacrificial oxide layer and the shielded pad oxide layer are removed to obtain the voltage-resistant gate trench structure.

[0051] In a possible implementation manner, after forming the isolation oxide layer at least covering the surface of the shield gate trench structure, the preparation method further includes:

[0052] Doping structures are formed in the SGT substrate region and the BCD substrate region based on an ion implantation process. At least a portion of the doping structure in the SGT substrate region and at least a portion of the doping structure in the BCD substrate region are formed in the same ion implantation process.

[0053] In another aspect, the present application discloses an integrated semiconductor device, comprising:

[0054] A substrate comprising a SGT substrate region of a first conductivity type and a BCD substrate region of a second conductivity type arranged laterally;

[0055] at least one shallow trench isolation structure located in the BCD substrate region;

[0056] A voltage-resistant gate trench structure located in the SGT substrate region;

[0057] A shield gate trench structure located in the SGT substrate region, comprising a shield gate, a control gate, a shield gate oxide layer and a control gate oxide layer, wherein the shield gate oxide layer isolates the shield gate from the substrate, the control gate oxide layer isolates the control gate from the substrate, and isolates the shield gate from the control gate;

[0058] The isolation oxide layer at least covers the surface of the voltage-resistant gate trench structure and the surface of the shielding gate trench structure, and is continuous with the control gate oxide layer.

[0059] In a possible implementation manner, the thickness of at least a portion of the control gate oxide layer does not exceed a preset thickness, and the preset thickness is 70-130 Å.

[0060] In another aspect, the present application further discloses an integrated circuit, which includes the above-mentioned integrated semiconductor device.

[0061] In another aspect, the present application further discloses an electronic device, which includes the above-mentioned integrated semiconductor device.

[0062] Based on the above technical solution, this application has the following beneficial effects:

[0063] The technical solution of this application utilizes a substrate comprising a laterally arranged SGT substrate region of a first conductivity type and a BCD substrate region of a second conductivity type. Prior to fabricating the SGT device structure, a shallow trench isolation structure is formed in the BCD substrate. This allows for a high-temperature annealing process for the trench isolation structure to be completed before the SGT device gate fabrication process, thereby reducing the risk of IGS leakage in the SGT device. Furthermore, the SGT device gate structure is fabricated prior to fabricating the BCD device's functional elements, further reducing the impact of high-temperature processes such as SGT annealing on the BCD device, thereby minimizing the cross-effects of SGT and BCD device integration. Furthermore, by simultaneously etching and filling trenches at least to the SGT substrate region to form a voltage-resistant gate trench structure and a shielding gate trench structure, the two devices can share common processes without adding additional complex processes, thereby reducing fabrication costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0065] Figure 1 A schematic flow chart of a method for preparing an integrated semiconductor device provided in accordance with an exemplary embodiment of the present application;

[0066] Figure 2-22 A schematic cross-sectional view of an integrated semiconductor device during preparation according to an embodiment of the present application;

[0067] Figure 23-31 A schematic cross-sectional view of another integrated semiconductor device during preparation according to an embodiment of the present application;

[0068] Figures 32-34 A schematic cross-sectional view of another integrated semiconductor device during preparation according to an embodiment of the present application;

[0069] Figures 35-41 A schematic cross-sectional view of another integrated semiconductor device during preparation according to an embodiment of the present application.

[0070] The following is a supplementary description of the accompanying drawings:

[0071] 100 - substrate, 101 - SGT substrate region, 102 - BCD substrate region, 103 - epitaxial layer, 104 - substrate layer, 201 - pad oxide layer, 202 - deep trench, 203 - second mask layer, 203a - hard mask layer, 203b - mask oxide layer, 204 - initial oxide layer, 205 - first filling layer, 206 - voltage-resistant gate trench structure, 207 - gate filling structure, 208 - shield Gate oxide layer, 209-shielding gate trench structure, 210-shielding gate, 211-control gate, 212-control gate oxide layer, 213-second etching window, 214-second filling layer, 215-isolation oxide layer, 216-shielding layer, 217-annular spacer, 301-shallow trench, 302-shallow trench isolation structure, 303-first mask layer, 304-first etching window, 401-doping structure. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0073] References to "one embodiment" or "embodiment" herein refer to specific features, structures, or characteristics that may be included in at least one implementation of the present application. Throughout the description of this application, it should be understood that the terms "upper," "lower," "top," and "bottom," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely for ease of description and simplification. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature designated "first" or "second" may explicitly or implicitly include one or more of such features. Furthermore, the terms "first," "second," etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It should be understood that such terms are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0074] When a numerical range is disclosed herein, the above range is considered to be continuous and includes the minimum and maximum values ​​of the range, as well as every value between such minimum and maximum values. Further, when a range refers to an integer, every integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe a feature or characteristic, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all subranges included therein. For example, a specified range from "1 to 10" should be considered to include any and all subranges between a minimum of 1 and a maximum of 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0075] The term "layer" as used in this application refers to a portion of a material that includes an area having a certain thickness. A layer can extend over the entire underlying or superstructure, or can extend over a localized area of ​​the underlying or superstructure. In addition, a layer can be an area of ​​a homogeneous or heterogeneous continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a shaped surface. A layer can include multiple layers. For example, the substrate 100 can include multiple sublayers, etc., and can be made of the same or different materials.

[0076] It should be understood that the definitions of “consistent” and “vertical” used in this application refer to basic consistency or basic verticality that satisfies process errors, and do not refer to absolute consistency or absolute verticality in the physical sense.

[0077] It should be understood that the "plane" used in this application, such as "first plane", "second plane", etc., refers to the XY plane of the substrate 100, substrate structure or device, etc., corresponding to the XY plane of the integrated semiconductor device, "in-plane direction", "lateral" refers to the direction parallel to the XY plane, "thickness direction", "trench depth direction" or "longitudinal" refers to the Z direction relative to the XY plane.

[0078] The following combination Figure 1-41 The present invention introduces a method for manufacturing an integrated semiconductor device provided in an embodiment of the present invention. Figure 1 It is a flow chart of a method for preparing an integrated semiconductor device. This specification provides method operation steps such as the embodiments or flow charts, but based on routine or non-creative work, more or fewer operation steps may be included. The order of steps listed in the embodiments is only one way of executing the steps among many steps and does not represent the only execution order. When the actual preparation method is executed, it can be executed in the order shown in the embodiments or the drawings or in parallel. The preparation method may include S11-S14:

[0079] S11: providing a substrate 100, the substrate 100 comprising a first conductive type SGT substrate region 101 and a second conductive type BCD substrate region 102 arranged laterally.

[0080] In particular, the substrate 100 is a semiconductor base capable of being processed for semiconductor devices. For example, the substrate 100 can be made of at least one of silicon, a material containing silicon (such as a III-V compound semiconductor material such as gallium arsenide (GaAs)), silicon on insulator (SOI), or other types of semiconductor materials capable of forming the substrate 100.

[0081] In possible embodiments, the substrate 100 can be a continuous structure, such as a wafer substrate, or can comprise a substrate layer 104 and an epitaxial layer 103. The epitaxial layer 103 can be formed by an epitaxial growth process, and can be a homo-epitaxial layer 103 that can continue to grow along the lattice direction of the substrate layer 104, or can be a hetero-epitaxial layer 103. The process conditions such as growth temperature can be the same as existing processes or can be adjusted as appropriate. The epitaxial layer 103 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic vapor deposition (ALD), or other methods. For example, the material of the epitaxial layer 103 can include silicon, germanium, gallium arsenide, gallium phosphide (GaP), gallium nitride (GaN), or other materials that can be epitaxially grown or deposited on the substrate layer 104 and capable of being processed for device regions. In possible embodiments, referring to FIG. 1, the SGT substrate region 101 and the BCD substrate region 102 can be formed in the epitaxial layer 103. Figure 2

[0082] In particular, the SGT substrate region 101 is a region of the substrate 100 for forming SGT devices, and the BCD substrate region 102 is a region of the substrate 100 for forming BCD devices. In possible embodiments, the SGT substrate region 101 and the BCD substrate region 102 are adjacent to each other to facilitate the preparation of a communication structure between the two types of devices. In one embodiment, the first conductive type is N-type and the second conductive type is P-type. In another embodiment, the first conductive type is P-type and the second conductive type is N-type. For example, the SGT substrate region 101 is an N-type deep well region, and the BCD substrate region 102 is a P-type deep well region.

[0083] S12: forming at least one shallow trench isolation structure 302 in the BCD substrate region 102. ​

[0084] Specifically, refer to Figure 3 At least one shallow trench isolation (STI) structure 302 is laterally spaced apart in the BCD substrate region 102. The BCD substrate region 102 is processed based on the shallow trench 301 process to form at least one spaced apart shallow trench isolation structure 302. The shallow trench isolation structure 302 provides electrical isolation between components in the BCD device.

[0085] In some embodiments, reference Figure 3-5 , S12 may specifically include S121-S124:

[0086] S121 : forming a pad oxide layer 201 covering the BCD substrate region 102 and the SGT substrate region 101 on the substrate 100 , and a first mask layer 303 stacked on the pad oxide layer 201 ;

[0087] S122: forming at least one first etching window 304 located in the BCD substrate region 102 on the first mask layer 303 and the pad oxide layer 201 based on a patterning process, and performing trench etching on the BCD substrate region 102 based on the first etching window 304 to obtain at least one shallow trench 301;

[0088] S123: Filling the shallow trench 301 with an isolation material to form at least one shallow trench isolation structure 302;

[0089] S124: removing the first mask layer.

[0090] Specifically, refer to Figure 3 A pad oxide layer 201 is formed on the substrate 100, spanning the SGT substrate region 101 and the BCD substrate region 102. A first mask layer 303 is then formed and stacked on the pad oxide layer 201. A first etching window 304 is formed through the first mask layer 303 and the pad oxide layer 201 based on a patterning process to expose the region of the substrate 100 corresponding to the shallow trench 301 in the BCD substrate region 102. Subsequently, shallow trench etching is performed using the pad oxide layer 201 and the first mask layer 303 as etch barriers to form a plurality of shallow trenches 301.

[0091] Specifically, refer to Figure 3The pad oxide layer 201 and the first mask layer 303 cover at least the BCD substrate region 102 and may also cover the active area (AA) of the SGT substrate region 101. The pad oxide layer 201 is used to isolate and protect the substrate surface to prevent contamination and reduce stress on the first mask layer 303. The pad oxide layer 201 can be formed on the substrate 100 through thermal oxidation or deposition processes. Optionally, the material of the pad oxide layer 201 may include, but is not limited to, silicon dioxide. The first mask layer 303 can be used for pattern transfer and improve the accuracy of patterned etching. Specifically, it can be formed through a deposition process. Optionally, the material of the first mask layer 303 may include at least one of silicon nitride, titanium nitride, silicon dioxide, etc., or may be other materials capable of pattern transfer. In one embodiment, the pad oxide layer 201 is a silicon oxide layer formed through thermal oxidation, and the first mask layer 303 is a deposited silicon nitride layer.

[0092] Optionally, the deposition process can be implemented using a chemical vapor deposition (CVD) process, such as plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPECVD), subatmospheric pressure chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other types of chemical vapor deposition processes.

[0093] Specifically, the formation process of the first etching window 304 may specifically include: coating a photoresist on the first mask layer 303, and performing a patterned exposure process on the photoresist, using the patterned photoresist as an etching barrier layer, etching the first mask layer 303 and the pad oxide layer 201 to form the first etching window 304.

[0094] Optionally, the shallow trench 301 can be etched using a wet etching process, such as using phosphoric acid as the etching solution for wet etching, or a dry etching process, including but not limited to at least one of ion milling etching, plasma etching, reactive ion etching, and laser ablation, such as plasma etching using a mixed gas of C4F8 and O2.

[0095] In some embodiments, reference Figure 4, an isolation material is deposited based on a deposition process to form a third filling layer that fills the shallow trench 301 and covers the first mask layer 303. The third filling layer is thinned until the first mask layer 303 is exposed, and then the first mask layer 303 is removed. Using the pad oxide layer 201 as a stop layer, the initially formed shallow trench isolation structure 302 is further thinned until the shallow trench isolation structure 302 is flush with the pad oxide layer 201. Deposition processes include, but are not limited to, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, plasma-enhanced atomic layer deposition, etc. The thinning process can be a chemical mechanical planarization process, such as a chemical mechanical polishing process (CMP). Specifically, the material of the shallow trench isolation structure 302 can include, but is not limited to, silicon dioxide, etc.

[0096] Understandably, if the STI structure is fabricated after the SGT device is fabricated, if the control gate oxide layer or the oxide layer on the top surface of the gate is too thin, for example, less than a predetermined thickness, then the SGT device may experience IGSS leakage when the STI annealing temperature (e.g., above 1100°C) is high. In this embodiment, the STI structure is formed before the BCD substrate region 102 is fabricated, thus preventing the high-temperature STI fabrication process from affecting the performance of the SGT device. Furthermore, the first mask layer 303 of the pad oxide layer 201 protects the substrate 100, which improves the performance of the subsequent SGT and BCD devices.

[0097] S13 : forming a voltage-sustaining gate trench structure 206 and a shielding gate trench structure 209 at least in the SGT substrate region 101 .

[0098] Specifically, refer to Figure 19 , 30 and 39, the voltage-resistant gate trench structure 206 is located between the shielding gate trench structure 209 and the BCD substrate region 102, and the voltage-resistant gate trench structure 206 of the SGT substrate region 101 is arranged adjacent to the BCD substrate region 102. The voltage-resistant gate trench structure 206 can adjust the electric field distribution and transfer the high electric field from the device surface to the body, thereby avoiding breakdown caused by local electric field concentration, thereby significantly improving the breakdown voltage, optimizing the device electric field and voltage resistance, and this structure can eliminate the lateral JFET effect (Junction Field-Effect Transistor Effect), shorten the carrier path, and reduce conduction loss.

[0099] In a possible implementation, reference Figure 19, 30 and 39, the shielded gate trench structure 209 includes a shielded gate 210, a control gate 211, a shielded gate oxide layer 208, and a control gate oxide layer 212. Specifically, the shielded gate 210 is located at the bottom of the trench, and the control gate 211 is located at the top of the trench. The control gate 211 is used to control the channel conduction and cutoff of the SGT device, and the shielded gate 210 is used to adjust the electric field distribution in the channel.

[0100] In possible implementations, Figure 19 , 30 and 39, the shield gate oxide layer 208 isolates the shield gate 210 from the substrate 100, and is specifically located between the deep trench wall and the shield gate 210. The control gate oxide layer 212 isolates the control gate 211 from the substrate 100, and isolates the shield gate 210 from the control gate 211. Specifically, part of the control gate oxide layer 212 is located on the deep trench wall, and part of the control gate oxide layer 212 is located between the bottom of the control gate 211 and the shield gate 210, and is continuous with the shield gate oxide layer 208, that is, the control gate oxide layer 212 and the shield gate oxide layer 208 form a continuous film layer, thereby achieving electrical isolation between the shield gate 210 and the substrate 100, the control gate 211 and the shield gate 210, and the control gate 211 and the substrate 100.

[0101] In some cases, reference Figure 30 and 39 A portion of the control gate oxide layer 212 extends from the deep trench wall to the substrate surface and covers at least a portion of the active area surface of the SGT substrate region 101, and at least partially covers the active area surface of the SGT substrate region 101. Specifically, the shield gate oxide layer 208 and the control gate oxide layer 212 can be made of silicon oxide or the like.

[0102] In a possible embodiment, the thickness of at least a portion of the control gate oxide layer 212 does not exceed a predetermined thickness, which is 70-130 Å. Preferably, the thickness of the control gate oxide layer 212 on the substrate surface and / or the isolation oxide layer 215 on the deep trench wall does not exceed a predetermined thickness, thereby improving the ion implantation effect while providing isolation protection. In a preferred embodiment, the thickness of the control gate oxide layer 212 on the substrate surface and the isolation oxide layer 215 on the deep trench wall is 70-130 Å.

[0103] In some embodiments, the control gate oxide layer 212 is formed by a deposition process after forming the shield gate 210. In other embodiments, the control gate oxide layer 212 is formed by performing a surface oxidation treatment on at least the shield gate 210 and the trench walls of the shield gate trench structure 209, thereby ensuring the continuity and uniformity of the control gate oxide layer 212.

[0104] Understandably, reference Figure 23-41In the case where the BCD device has a voltage-resistant gate trench structure 206, the voltage-resistant gate trench structure 206 of the SGT substrate region 101 and the BCD substrate region 102 can be formed simultaneously based on S13, thereby forming the trench structures in the two devices based on the same deep trench 202 process, simplifying the process.

[0105] S14 : forming an isolation oxide layer 215 covering at least the surface of the shield gate trench structure 209 .

[0106] Specifically, the isolation oxide layer 215 covers at least the surface of the control gate 211, and may also cover the surface of the voltage-resistant gate trench structure 206 and / or at least part of the surface of the substrate 100, so as to avoid damage to the control gate 211 and the voltage-resistant gate trench structure 206 in subsequent processes, such as blocking ion implantation damage.

[0107] In some embodiments, the isolation oxide layer 215 can be formed by a deposition process. Optionally, the deposition process includes but is not limited to plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, plasma-enhanced atomic layer deposition, etc. Exemplarily, the isolation oxide layer 215 can be formed by HDPCVD, and the material of the isolation oxide layer 215 can include but is not limited to silicon dioxide.

[0108] In other embodiments, reference Figure 21 , 31, 34 and 41, the isolation oxide layer 215 is formed by surface oxidation of at least the control gate 211. When other oxide layers exist on the substrate surface, such as the residual pad oxide layer 201 and the control gate oxide layer 212, the isolation oxide layer 215 is continuous with the other oxide layers on the substrate surface. Specifically, the surface oxidation process can be implemented based on a thermal oxidation process. By thermally oxidizing the exposed surface of the control gate 211 or the exposed surface of the withstand gate trench structure 206, an isolation oxide layer 215 capable of isolating implant damage is formed, thereby avoiding IGSS (Gate Reverse Current) leakage problems and preventing the oxide layer on the substrate surface from thickening, thereby ensuring the effectiveness of subsequent ion implantation in the active area.

[0109] In some embodiments, the thickness of the portion of the isolation oxide layer 215 covering the control gate 211 and the voltage-resistant gate trench structure 206 is higher than a preset isolation thickness. The preset isolation thickness may be 100-120 Å, preferably 110 Å, to provide effective isolation protection.

[0110] In some embodiments, the thickness of the portion of the isolation oxide layer 215 covering the substrate surface is no greater than the aforementioned predetermined thickness.

[0111] Based on some or all of the above embodiments, in some embodiments, reference Figure 6-19, Figure 23-30 , Figure 32 ,as well as Figures 35-39 S13: forming the voltage-resistant gate trench structure 206 and the shielding gate trench structure 209 at least in the SGT substrate region 101 may include S131-S134:

[0112] S131: forming a second mask layer 203 spanning the SGT substrate region 101 and the BCD substrate region 102;

[0113] S132: forming at least one second etching window 213 located at least in the SGT substrate region 101 on the second mask layer 203 and the pad oxide layer 201 based on a patterning process, and performing trench etching on the SGT substrate region 101 based on the second etching window 213 to obtain a plurality of deep trenches 202;

[0114] S133: Filling the plurality of deep trenches 202 with a gate material to form at least one gate filling structure 207;

[0115] S134 : forming a voltage-resistant gate trench structure 206 and a shielding gate trench structure 209 based on the at least one gate filling structure 207 , wherein the voltage-resistant gate trench structure 206 of the SGT substrate region 101 is adjacent to the BCD substrate region 102 .

[0116] Specifically, refer to Figure 6 The second mask layer 203 can at least cover the active area (ActiveArea, AA) of the SGT substrate region 101 and the active area of ​​the BCD substrate region 102, or can cover the SGT substrate region 101 and the BCD substrate region 102. After removing the first mask layer 303, a second mask layer 203 can be formed by a deposition process, etc. The second mask layer 203 is stacked on the pad oxide layer 201 and covers the shallow trench isolation structure 302 to protect the shallow trench isolation structure 302 and the substrate 100 structure during deep trench etching and subsequent processes.

[0117] In some embodiments, reference Figure 6The second mask layer 203 may include a hard mask layer 203a stacked on the pad oxide layer 201 and a mask oxide layer 203b stacked on the hard mask layer 203a. The hard mask layer 203a can be used for pattern transfer and to improve the accuracy of patterned etching. It can be formed using a deposition process. Optionally, the material of the hard mask layer 203a may include at least one of silicon nitride, titanium nitride, silicon dioxide, etc., or may also be other materials that can achieve pattern transfer. The mask oxide layer 203b can further improve the etching accuracy. In one embodiment, the hard mask layer 203a may be a deposited silicon nitride layer, and the mask oxide layer 203b may be a deposited silicon oxide layer. In some embodiments, the thickness of the hard mask layer 203a is 1000-3000A, preferably 1500A. The thickness of the mask oxide layer 203b is 2000A-4000A, preferably 3000A.

[0118] Specifically, refer to Figure 7 The second etching window 213 is formed based on a patterning process. The second etching window 213 penetrates the second mask layer 203 to expose the substrate 100 area corresponding to the deep trench 202. Then, deep trench etching is performed using the second mask layer 203 as an etching barrier layer to form a plurality of deep trenches 202. The patterning process of the second mask layer 203 may include: coating a photoresist on the mask oxide layer 203b, performing a patterned exposure process on the photoresist, and etching the mask oxide layer 203b and the hard mask layer 203a using the patterned photoresist as a barrier layer to form the second etching window 213. Optionally, the deep trench etching may be performed using a wet etching process, such as using phosphoric acid as an etching solution for wet etching, or a dry etching process, including but not limited to at least one of ion milling etching, plasma etching, reactive ion etching, and laser ablation, such as plasma etching using a mixed gas of C4F8 and O2.

[0119] Specifically, refer to Figure 7 and 23 The multiple deep trenches 202 are laterally distributed at least in the SGT substrate region 101, and may also be laterally distributed in both the SGT substrate region 101 and the BCD substrate region 102. It is understood that the deep trenches 202 in the SGT substrate region 101 and the BCD substrate region 102 can be formed simultaneously in the same etching process, thereby integrating the trench etching steps for both devices and reducing process costs. In some embodiments, the width of the deep trenches 202 in the shield gate trench structure 209 and / or the withstand gate trench structure 206 is 0.4 μm to 0.6 μm, preferably 0.5 μm.

[0120] Specifically, after forming a plurality of deep trenches 202, each deep trench 202 is filled with gate material by gate material deposition to form isolated gate filling structures 207, which are then fabricated into a voltage-resistant gate trench structure 206 and a shielding gate trench structure 209. Deep trench etching is performed based on the second mask layer 203 to fabricate the gate trench structure, which improves structural fabrication accuracy, facilitates trench integration fabrication of SGT devices and BCD devices, and simplifies the integration process.

[0121] In a specific embodiment, referring to Figure 8-11 and Figure 23 S133: Filling the plurality of deep trenches 202 with a gate material to form at least one gate filling structure 207 may include S1331-S1333:

[0122] S1331: performing a trench wall oxidation process on the plurality of deep trenches 202 to form an initial oxide layer 204 covering the deep trench walls;

[0123] S1332: filling the deep trench 202 with a gate material to form a first filling layer 205 that fills the deep trench 202 and covers the second mask layer 203;

[0124] S1333: Using the hard mask layer 203a or the pad oxide layer 201 as a stop layer, the first filling layer 205 is thinned to obtain at least one gate filling structure 207 isolated from each other.

[0125] Specifically, refer to Figure 8 , the exposed deep trench walls can be thermally oxidized to oxidize the substrate 100 material into an initial oxide layer 204 of a certain thickness. Alternatively, a sacrificial oxide layer can be formed on the deep trench walls by thermal oxidation, the sacrificial oxide layer removed by etching, and then the walls of the deep trench 202 can be oxidized by thermal oxidation to form the initial oxide layer 204. By first forming and then removing the sacrificial oxide layer, the trench wall defects formed during the deep trench etching process can be removed, and the trench wall can be flattened, which is beneficial for the subsequent preparation of the gate structure. In one embodiment, the thickness of the initial oxide layer 204 is 2000 Å-2500 Å.

[0126] Specifically, refer to Figure 8 The initial oxide layer 204 is continuous with the pad oxide layer 201 to achieve isolation between the gate filling structure 207 and the substrate 100, preventing the gate material of the substrate 100 from penetrating. Part of the initial oxide layer 204 can be used as a field oxide layer of the SGT device. Figure 9, gate material is deposited based on a deposition process, and after filling the deep trench 202, deposition is continued to cover the surface of the second mask layer 203, thereby obtaining a first filling layer 205. Then, the first filling layer 205 is thinned based on a chemical mechanical polishing process, thereby removing redundantly deposited gate material, and obtaining gate filling structures 207 isolated from each other. In some embodiments, reference Figure 10-11 , using the hard mask layer 203a as a stop layer to thin the first filling layer 205 until the hard mask layer 203a is exposed. In other embodiments, referring to Figure 23 , using the pad oxide layer 201 as a stop layer, the first filling layer 205 is thinned to expose the pad oxide layer 201. In other embodiments, the first filling layer 205 is thinned to expose the pad oxide layer 201 on the substrate surface based on a chemical mechanical planarization process, and the pad oxide layer 201 on the substrate surface is further thinned to a first thickness to reduce the oxide layer thickness on the substrate surface, thereby reducing the step difference of the voltage-resistant gate trench structure 206, the shielding gate trench structure 209 and other device areas in the subsequent preparation process, and flattening the surface of the SGT device area and the BCD device area. In one embodiment, the pad oxide layer 201 can be thinned to half of its original thickness. In one embodiment, the first thickness can be 900-1200A.

[0127] Specifically, the material of the initial oxide layer 204 may include but is not limited to silicon dioxide, and the material of the first filling layer 205 may include but is not limited to polysilicon.

[0128] Specifically, at least one gate filling structure 207 includes a first gate filling structure 207 corresponding to the voltage-resistant gate trench structure 206 and a second gate filling structure 207 corresponding to the shielding gate trench structure 209. The second gate filling structure 207 is located in the SGT base region 101, referring to Figure 23 The first gate filling structure 207 can be used to form a voltage-resistant gate trench structure 206 of the SGT substrate region 101, or can also be used to form a voltage-resistant gate trench structure 206 of the BCD substrate region 102. The voltage-resistant gate trench structure 206 of the SGT substrate region 101 is disposed adjacent to the BCD substrate region 102.

[0129] In a specific embodiment, referring to Figure 12-19 , Figure 23-30 and Figures 35-39 S134 forms a voltage-resistant gate trench structure 206 and a shielding gate trench structure 209 based on at least one gate filling structure 207, including S1341a-S1347a:

[0130] S1341a: shielding the first gate filling structure 207;

[0131] S1342a: Performing etching back on the second gate filling structure 207 to form a shielding gate 210;

[0132] S1343a: removing the unmasked initial oxide layer 204 and the pad oxide layer 201 to expose the unmasked substrate surface, part of the deep trench sidewall and part of the shield gate 210, the remaining initial oxide layer 204 in the exposed deep trench 202 forms a shield gate oxide layer 208;

[0133] S1344a: performing an oxidation process on the exposed part of the shield gate 210, the exposed deep trench sidewall and the exposed substrate surface to form a control gate oxide layer 212, and removing the mask layer 216;

[0134] S1345a: depositing a gate material to refill the etched deep trench 202 to form a second fill layer 214 filling the deep trench 202 and covering over the substrate 100;

[0135] S1346a: performing a thinning process on the second fill layer 214 with the hard mask layer 203a or the pad oxide layer 201 as a stop layer, until the second fill layer 214 is flush with the hard mask layer 203a or flush with the pad oxide layer 201, to obtain a thinned second fill layer 214;

[0136] S1347a: etching the thinned second fill layer 214 and the exposed first gate fill structure 207 to expose the control gate oxide layer 212 of the substrate surface, to obtain a voltage gate trench structure 206 and a control gate 211 over the shield gate 210.

[0137] Specifically, referring to Figure 12 and Figure 24 the photoresist layer can cover at least the SGT substrate region 101 and the BCD substrate region 102, and exposure can be performed to remove at least the photoresist region on the second voltage gate fill structure to expose the second gate fill structure 207 and shield and protect the first gate fill structure 207. It can be understood that the shallow trench isolation structure 302 of the BCD substrate region 102 can also be shielded at the same time, thereby reducing the risk of damage to the shallow trench isolation structure 302. Then, a gate material etch-back is performed to remove part of the second gate fill structure 207, and the remaining part of the second gate fill structure 207 is used to form the shield gate 210, and the etch-back depth is determined based on the trench structure and electric field distribution requirements of the SGT device. Optionally, the etch-back process can be implemented based on wet etching or dry etching, and the wet etching can be, for example, acid etching, and the dry etching can be, for example, plasma etching.

[0138] In some cases, referring to Figure 11-14The thinning of the first filling layer 205 uses the hard mask layer 203a as a stop layer. After the back etching process, the exposed hard mask layer 203a area, the pad oxide layer 201 area, the initial oxide layer 204 area of ​​the deep trench wall exposed after the back etching, and the initial oxide layer 204 area on the partial side wall of the shielding gate 210 are removed, thereby exposing the unmasked substrate 100 and the deep trench wall, and exposing the partial side wall of the top of the shielding gate 210 after the initial oxide layer 204 is etched.

[0139] In some cases, reference Figure 23-25 The thinning of the first filling layer 205 stops at the pad oxide layer 201, or after thinning to the pad oxide layer 201, the pad oxide layer 201 is further thinned to the first thickness. Then, after the etching back process, the exposed pad oxide layer 201 area, the initial oxide layer 204 area on the deep trench wall exposed after etching back, and the initial oxide layer 204 area on the partial sidewall of the shielding gate 210 are removed, thereby exposing the unmasked substrate 100 and the deep trench wall, and the initial oxide layer 204 is etched to expose the partial sidewall of the top of the shielding gate 210. It can be understood that in this embodiment, the exposed pad oxide layer 201 and the partial initial oxide layer 204 can be removed by the etching process to obtain the shielding gate oxide layer 208, which can serve as the field oxide layer of the shielding gate 210.

[0140] Next, refer to Figure 15 and Figure 26 The exposed shield gate 210, deep trench wall and substrate surface are oxidized by a thermal oxidation process, thereby achieving in-situ oxidation at the above-mentioned locations, forming a control gate oxide layer 212 that is continuous with the remaining pad oxide layer 201 and the shield gate oxide layer 208. In this way, the shield gate 210, the deep trench wall and the active area surface are covered by a simple etching back, masking and in-situ oxidation process, without the need for additional patterning and masking, while avoiding the problem of excessive thickness or uneven thickness of the oxide layer caused by oxide layer deposition, so as to isolate the shield gate 210 and avoid the adverse effects of film stress, thereby protecting the active area of ​​the substrate 100. In addition, if combined with the aforementioned thinning treatment of the pad oxide layer 201, the thickness of the pad oxide layer 201 retained by masking is made close to the thickness of the oxide layer formed by in-situ oxidation on the substrate surface, while reducing the field oxide thickness, the step difference on the substrate surface is avoided, thereby optimizing device performance.

[0141] Understandably, reference Figure 15 and Figure 26 Due to the difference between the gate material and the substrate 100 material, the thickness of the control gate oxide layer 212 formed by thermal oxidation, located on the substrate 100, is smaller than the thickness of the area located on the surface of the shield gate 210. This ensures the shield gate electric field control effect while improving the electrical isolation effect between the shield gate 210 and the control gate 211.

[0142] refer to Figure 16-17 and Figures 27-28 After forming the control gate oxide layer 212, the remaining shielding layer 216 is removed to expose the hard mask layer 203a (eg Figure 16 as shown) or the remaining pad oxide layer 201 (as shown Figure 27 As shown in FIG), the gate material is backfilled based on the deposition process, and the backfill depth exceeds the back etching depth of the deep trench 202 to form a covering control gate oxide layer 212 and a covering residual hard mask layer 203a (as shown in FIG). Figure 17 as shown) or pad oxide layer 201 (as shown Figure 28 The second filling layer 214 is shown in FIG. 1 , and the thickness of the second filling layer 214 is set based on process requirements.

[0143] In some cases, reference Figure 18-19 , using the remaining hard mask layer 203a as a stop layer, the second filling layer 214 is thinned based on a chemical mechanical polishing process to expose the hard mask layer 203a and expose the surface of the first gate filling structure 207, which is flush with the hard mask layer 203a, and then the thinned second filling layer 214 is etched back to expose the control gate oxide layer 212, and the top of the first gate filling structure 207 is cooperatively etched. After etching, the second filling layer 214 forms control gates 211 spaced from each other, and the etched first gate filling structure 207 forms a voltage-resistant gate trench structure 206. The residual hard mask layer 203a can avoid process damage to the shallow trench isolation structure 302.

[0144] In other cases, reference Figures 29-30 The remaining pad oxide layer 201 is used as a stop layer. The second filling layer 214 is thinned to the pad oxide layer 201 based on a chemical mechanical polishing process, and the surface of the first gate filling structure 207 is exposed. The surface is flush with the pad oxide layer 201. The thinned second filling layer 214 is then etched back to expose the control gate oxide layer 212. The top of the first gate filling structure 207 is cooperatively etched. After the second filling layer 214 is etched, each control gate 211 spaced apart from each other is formed. The first gate filling structure 207 is etched to form a voltage-resistant gate trench structure 206. In this way, the hard mask layer 203a is removed in the previous process, thereby saving the subsequent removal step of the remaining hard mask layer 203a and simplifying the process. In addition, when the first filling layer is thinned, the pad oxide layer is used as a stop layer, saving an oxide layer removal step. The remaining pad oxide layer is used as a stop layer for thinning the second filling layer, so that the channel length can be accurately controlled by controlling the etching time of the thinned second filling layer.

[0145] Specifically, refer to Figure 16, 27 and 37, there is an annular spacer 217 between the isolation oxide layer 215 on the shielding gate 210 and the isolation oxide layer 215 on the deep trench wall, and both are continuous with the shielding gate oxide layer 208 retained in the deep trench 202, and the control gate 211 fills the top of the shielding gate 210 and the annular spacer 217, forming a plug structure with the shielding gate 210.

[0146] Accordingly, in some cases, in this embodiment, forming the isolation oxide layer 215 that at least covers the surface of the shield gate trench structure 209 in S14 may specifically include: removing the remaining hard mask layer 203a, and performing surface oxidation on the control gate 211 of the voltage-withstand gate trench structure 206 and the shield gate trench structure 209 to obtain the isolation oxide layer 215. The control gate oxide layer 212, the isolation oxide layer 215, and the remaining pad oxide layer 201 on the surface of the substrate are continuous.

[0147] In other cases, when the hard mask layer 203a does not exist, Figure 31 S14 forming an isolation oxide layer 215 covering at least the surface of the shield gate trench structure 209 may specifically include directly performing surface oxidation on the control gate 211 of the voltage-withstand gate trench structure 206 and the shield gate trench structure 209 to form the isolation oxide layer 215. The control gate oxide layer 212, the isolation oxide layer 215, and the remaining pad oxide layer 201 on the substrate surface are continuous.

[0148] In other cases, reference Figure 20-21 and Figures 32-33 S14 forming the isolation oxide layer 215 at least covering the surface of the shield gate trench structure 209 may specifically include S141-S142:

[0149] S141: removing the surface oxide layer of the substrate 100 to expose the substrate surface;

[0150] S142 : performing surface oxidation treatment on the substrate surface, the voltage-resistant gate trench structure 206 , and the control gate 211 of the shielding gate trench structure 209 to obtain an isolation oxide layer 215 .

[0151] Specifically, when the hard mask layer 203 a remains, the hard mask layer 203 a is removed first and then S141 is performed. When there is no residual hard mask layer 203 a , S141 is performed after the control gate 211 is formed.

[0152] Specifically, the control gate oxide layer 212 region and the residual pad oxide layer 201 on the surface of the substrate are removed based on an etching process or a chemical mechanical polishing process to achieve the removal of the surface oxide layer of the substrate 100, thereby exposing the substrate surface of the SGT substrate region 101 and the BCD substrate region 102. Then, an oxide layer is formed in situ on the substrate surface, the surface of the voltage-resistant gate trench structure 206 and the surface of the control gate 211 by thermal oxidation treatment to obtain an isolation oxide layer 215. In this way, by removing the surface oxide layer and then self-oxidizing, a thin, uniform and flat isolation oxide layer 215 region is formed on the surface of the substrate, which is beneficial to the subsequent ion implantation effect and implantation depth control. At the same time, based on the oxidation characteristics of the gate material, a relatively thick isolation oxide layer 215 region is formed on the surface of the control gate 211 and the voltage-resistant gate trench structure 206 to achieve a better implantation protection effect. The top surface and / or bottom surface of the isolation oxide layer 215 region on the surface of the control gate 211 and the voltage-resistant gate trench structure 206 is a curved surface, forming a semi-ellipsoidal or ellipsoidal shape.

[0153] In a possible embodiment, the thickness of the isolation oxide layer 215 on the substrate surface is not greater than a predetermined thickness of 70-130 Å, so as to provide isolation protection while improving the ion implantation effect. In a preferred embodiment, the thickness of the isolation oxide layer 215 on the substrate surface is 70-130 Å.

[0154] In a possible implementation, the thickness of the isolation oxide layer 215 covering the control gate 211 and the voltage-resistant gate trench structure 206 is higher than a preset isolation thickness. The preset isolation thickness may be 100-120 Å, preferably 110 Å, to provide effective isolation protection.

[0155] In another specific embodiment, the gate filling structure 207 is formed by using the pad oxide layer 201 as a stop layer. Figure 23-25 and Figures 35-41 S134: forming a voltage-resistant gate trench structure 206 and a shielding gate trench structure 209 based on at least one gate filling structure 207 may include S1341b-S1347b:

[0156] S1341b: shielding the first gate filling structure 207;

[0157] S1342b: Performing back etching on the second gate filling structure 207 to form a shielding gate 210;

[0158] S1343b: removing the unmasked initial oxide layer 204 and the pad oxide layer 201 to expose the unmasked substrate surface, a portion of the deep trench wall, and a portion of the shielding gate 210;

[0159] S1344b: removing the shielding layer 216 and the shielded pad oxide layer 201, and forming a voltage-resistant gate trench structure 206;

[0160] S1345b: forming a control gate oxide layer 212 covering the exposed portion of the shield gate 210, the exposed deep trench wall, the surface of the voltage-resistant gate trench structure 206 and the surface of the substrate;

[0161] S1346b: depositing a gate material to backfill the deep trench 202 after the back-etching, forming a second filling layer 214 filling the deep trench 202 and covering the control gate oxide layer 212;

[0162] S1347b: Using the control gate oxide layer 212 as a stop layer, the second filling layer 214 is thinned until the second filling layer 214 is flush with the control gate oxide layer 212 , thereby obtaining a control gate 211 located above the shielding gate 210 .

[0163] Specifically, refer to Figure 24 A photoresist layer can be formed to cover at least the SGT substrate region 101 and the BCD substrate region 102. Exposure is then performed to remove at least the photoresist region on the second voltage-stable gate fill structure, exposing the second gate fill structure 207 while shielding and protecting the first gate fill structure 207. It is understood that the shallow trench isolation structure 302 in the BCD substrate region 102 can also be shielded at the same time, thereby reducing the risk of damage to the shallow trench isolation structure 302. The gate material is then etched back to remove a portion of the second gate fill structure 207. The remaining portion of the second gate fill structure 207 is used to form the shield gate 210.

[0164] refer to Figure 25 The thinning of the first filling layer 205 stops at the pad oxide layer 201, or after thinning to the pad oxide layer 201, the pad oxide layer 201 is further thinned to the first thickness. After the etching back process, the exposed pad oxide layer 201 area, the initial oxide layer 204 area on the deep trench wall exposed after etching back, and the initial oxide layer 204 area on the sidewall of the shield gate 210 are removed, thereby exposing the unmasked substrate 100 and the deep trench wall. After etching the initial oxide layer 204, the sidewall of the top of the shield gate 210 is exposed. The initial oxide layer 204 remaining in the exposed deep trench 202 forms the shield gate oxide layer 208.

[0165] Next, refer to Figures 35-36, removing the remaining shielding layer 216 and the pad oxide layer 201 blocked by the shielding layer 216. In some cases, S1344b may specifically include: removing the shielding layer 216; simultaneously removing the pad oxide layer 201 and the top of the first gate filling structure 207 based on a chemical mechanical polishing process to expose the substrate surface and obtain a voltage-resistant gate trench structure 206 flush with the substrate surface. In other cases, S1344b may specifically include: removing the shielding layer 216; oxidizing the exposed portion of the shielding gate 210, the exposed deep trench wall, the exposed substrate surface, and the surface of the first gate filling structure 207 to form a sacrificial oxide layer, which is continuous with the shielded pad oxide layer 201; removing the sacrificial oxide layer and the shielded pad oxide layer 201 to obtain the voltage-resistant gate trench structure 206.

[0166] Specifically, the sacrificial oxide layer and the remaining pad oxide layer 201 can be removed together based on oxide layer etching to expose the surfaces of the SGT substrate region 101 and the BCD substrate region 102 , which is beneficial for the subsequent preparation of the control gate 211 and the control gate oxide layer 212 .

[0167] Next, refer to Figure 37 A continuous control gate oxide layer 212 can be formed on the exposed surface of the shield gate 210, the exposed surface of the deep trench wall, and the substrate surface based on a deposition process or thermal oxidation treatment. The control gate oxide layer 212 is a continuous oxide layer covering the exposed portion of the top of the shield gate 210, the exposed portion of the deep trench wall, the surface of the SGT substrate region 101, and the surface of the BCD substrate region 102, thereby protecting the substrate 100 and isolating the shield gate 210 from the substrate 100, as well as isolating the shield gate 210 from the deposited gate material. Then, referring to Figure 38 , the gate material is backfilled based on the deposition process to cover the control gate oxide layer 212 on the substrate surface to form a second filling layer 214, referring to Figure 39 The second filling layer 214 is thinned using a chemical mechanical polishing process until the control gate oxide layer 212 is exposed. The remaining portions of the second filling layer 214 in each deep trench 202 are isolated from each other to form the control gate 211. In this way, after forming the shield gate 210, the remaining pad oxide layer 201 is first removed to planarize the substrate surface, thereby forming a continuous and flat control gate oxide layer 212 on the substrate surface to serve as a thinning stop layer for the second filling layer 214. This facilitates thickness control during thinning of the second filling layer 214, avoids gate structure loss caused by oxide layer removal after forming the control gate 211, and improves gate performance.

[0168] In one embodiment, reference Figure 37The exposed shield gate 210, deep trench walls, and substrate surface are oxidized through a thermal oxidation process, thereby achieving in-situ oxidation at the aforementioned locations to form a continuous control gate oxide layer 212. It is understandable that due to the difference in gate material and substrate 100 material, the thickness of the control gate oxide layer 212 formed by thermal oxidation in the region located on the substrate 100 is thinner than that in the region located on the surface of the shield gate 210. This ensures the shield gate electric field control effect while improving the electrical isolation between the shield gate 210 and the control gate 211.

[0169] The thickness and material of the control gate oxide layer 212 formed in this embodiment are consistent with those in the previous embodiment and are not described in detail here.

[0170] Accordingly, refer to Figure 40 S14: forming an isolation oxide layer 215 covering at least the surface of the shielding gate trench structure 209 includes: performing surface oxidation treatment on the control gate 211 of the shielding gate trench structure 209 to form an isolation oxide layer 215 continuous with the control gate oxide layer 212 .

[0171] Specifically, in this embodiment, after the control gate 211 is formed, the substrate surface is covered with a continuous, flat, and uniformly thick control gate oxide layer 212. The exposed surface of the control gate 211 is oxidized in situ through a thermal oxidation process to form an isolation structure, thereby forming an isolation oxide layer 215 for protecting the gate structure. The top and / or bottom surfaces of the isolation structure are curved, forming a semi-ellipsoidal or ellipsoidal shape.

[0172] In some embodiments, reference Figure 22 , 34 and 41, after S14: forming an isolation oxide layer 215 that at least covers the surface of the shield gate trench structure 209, the preparation method further includes S15: forming a doping structure 401 in the SGT substrate region 101 and the BCD substrate region 102 based on an ion implantation process, and at least part of the doping structure 401 of the SGT substrate region 101 and at least part of the doping structure 401 of the BCD substrate region 102 are formed in the same ion implantation process.

[0173] Specifically, the same type of doping structure 401 in the SGT substrate region 101 and the BCD substrate region 102 can be formed in the same ion implantation process. This not only realizes the modular integration of the SGT device and the BCD device, but also integrates the similar process steps of the two devices to simplify the connection and improve the communication performance while simplifying the device manufacturing process and reducing the manufacturing cost. The doping structure 401 may include a well region and a source structure or a drain structure. For example, referring to Figure 41The P-well region in the active area of ​​the SGT device and the P-well region in the active area of ​​the BCD device can be formed in the same ion implantation process, and the N+ well region in the active area of ​​the SGT device and the N+ well region in the active area of ​​the BCD device can be formed in the same ion implantation process. In one embodiment, the ion implantation process includes at least an ion implantation process and an annealing process. The isolation oxide layer 215 not only prevents ion implantation of the gate structure but also reduces the risk of device damage during the annealing process.

[0174] In some embodiments, the SGT device formed in the SGT substrate region 101 is an SGT MOSFET, so as to further improve the performance of the semiconductor device, reduce the on-resistance, and improve the efficiency and reliability of the device circuit.

[0175] In summary, the present application utilizes a substrate 100 comprising a laterally arranged SGT substrate region 101 of a first conductivity type and a BCD substrate region 102 of a second conductivity type. Prior to fabricating the SGT device structure, a shallow trench isolation structure 302 is formed in the BCD substrate 100. This allows for a high-temperature annealing process for the trench isolation structure to be completed before the SGT device gate fabrication process, thereby reducing the risk of IGS leakage in the SGT device. Furthermore, the SGT device gate structure is fabricated prior to fabricating the BCD device's functional elements, further reducing the impact of high-temperature processes such as SGT annealing on the BCD device, thereby minimizing the cross-effects of SGT and BCD device integration. Furthermore, by forming a voltage-resistant gate trench structure 206 and a shielding gate trench structure 209 through a single trench etching and filling process extending to at least the SGT substrate region 101, the two devices achieve shared process integration without adding additional complex processes, thereby reducing fabrication costs. Furthermore, the technical solution of the present application is suitable for mass production of integrated devices, improves the process window, and addresses various device leakage issues.

[0176] The present application also provides an integrated semiconductor device, which is prepared based on the above-mentioned preparation method. Figure 21, 31, 33 and 40, the integrated semiconductor device specifically includes: a substrate 100, at least one shallow trench isolation structure 302, a voltage-resistant gate trench structure 206 located in the SGT substrate area 101; a shielding gate trench structure 209 and an isolation oxide layer 215 located in the SGT substrate area 101. The substrate 100 includes a laterally arranged SGT substrate region 101 of a first conductivity type and a BCD substrate region 102 of a second conductivity type; the shallow trench isolation structure 302 is located in the BCD substrate region 102; the shielding gate trench structure 209 includes a shielding gate 210, a control gate 211, a shielding gate oxide layer 208 and a control gate oxide layer 212, the shielding gate oxide layer 208 isolates the shielding gate 210 from the substrate 100, the control gate oxide layer 212 isolates the control gate 211 from the substrate 100, and isolates the shielding gate 210 from the control gate 211; the isolation oxide layer 215 covers at least the surface of the withstand voltage gate trench structure 206 and the surface of the shielding gate trench structure 209, and is continuous with the control gate oxide layer 212.

[0177] Specifically, at least one shallow trench isolation structure 302 is prepared before the deep trench 202 of the SGT device is formed.

[0178] In some embodiments, the thickness of at least a portion of the control gate oxide layer 212 does not exceed a predetermined thickness, which is 70-130 Å.

[0179] In some embodiments, the control gate 211 and the shielding gate 210 form a plug structure. The top diameter of the shielding gate 210 may be 2000-3000 Å, and the diameter of the control gate 211 may be 5000-8000 Å.

[0180] In some embodiments, the control gate oxide layer 212 is formed by performing surface oxidation treatment on at least the shield gate 210 and the trench wall of the shield gate trench structure 209 .

[0181] In some embodiments, the isolation oxide layer 215 is formed by performing a surface oxidation process on at least the control gate 211 .

[0182] Specifically, the shielding gate trench structure 209 and the voltage-resistant gate trench structure 206 are formed based on the gate filling structure 207 . The gate filling structure 207 is formed by filling the plurality of deep trenches 202 with a gate material.

[0183] In some embodiments, the shielding gate oxide layer 208, the control gate oxide layer 212 and the isolation oxide layer 215 are continuous, the shielding gate oxide layer 208 is located at the bottom and the lower end of the deep trench 202, at least part of the control gate oxide layer 212 is located at the upper end of the deep trench 202 and between the shielding gate 210 and the control gate 211, and at least part of the isolation oxide layer 215 is located on the top surface of the control gate 211 and / or the top surface of the voltage-resistant gate trench structure 206.

[0184] In one embodiment, reference Figure 31 Part of the control gate oxide layer 212 is located on the surface of the substrate 100, part of the control gate oxide layer 212 is located on the groove wall at the upper end of the deep trench 202, and between the shielding gate 210 and the control gate 211, and is continuous with the pad oxide layer 201, and the isolation oxide layer 215 is located on the surface of the control gate 211 and the voltage-resistant gate trench structure 206.

[0185] In another embodiment, referring to Figure 21 The control gate oxide layer 212 is located on the trench wall at the upper end of the deep trench 202 and between the shielding gate 210 and the control gate 211. The isolation oxide layer 215 is a continuous oxide layer covering the substrate surface, the control gate 211 and the surface of the voltage-resistant gate trench structure 206. The isolation oxide layer 215 at least covers the active area of ​​the SGT device in the SGT substrate area 101 and the active area of ​​the BCD device in the BCD substrate area 102.

[0186] In another embodiment, referring to Figure 40 The control gate oxide layer 212 is located between the shield gate 210 and the control gate 211, and extends along the upper end of the deep trench 202 to cover the substrate surface. The control gate oxide layer 212 covers at least the active area of ​​the SGT device in the SGT substrate region 101 and the active area of ​​the BCD device in the BCD substrate region 102. The isolation oxide layer 215 is located on the top surface of the control gate 211.

[0187] In some embodiments, there is an annular spacer 217 between the control gate oxide layer 212 on the shielding gate 210 and the control gate oxide layer 212 on the wall of the deep trench, and both are continuous with the shielding gate oxide layer 208 in the deep trench 202. The control gate 211 fills the top space of the shielding gate 210 in the deep trench 202 and the annular spacer 217, forming a plug structure with the shielding gate 210.

[0188] In some embodiments, the isolation oxide layer 215 is a deposited layer or an oxide layer formed based on a thermal oxidation process.

[0189] Specifically, the thickness of the isolation oxide layer 215 formed by thermal oxidation is greater than the thickness of the isolation oxide layer 215 on the substrate surface or the thickness of the control gate oxide layer 212 on the substrate surface. On the top surface of the control gate 211 or the top surface of the voltage-withstand gate trench structure 206, the top surface and / or bottom surface of the isolation oxide layer 215 formed by thermal oxidation is a curved surface, forming a convex semi-ellipsoidal or ellipsoidal shape.

[0190] In some embodiments, the integrated semiconductor device further includes a doping structure 401, referring to Figure 22 , 34 and 41, at least a portion of the doped structure 401 of the SGT substrate region 101 and at least a portion of the doped structure 401 of the BCD substrate region 102 are formed in the same ion implantation process.

[0191] It should be noted that the integrated semiconductor device embodiment of the present application is implemented based on the integrated semiconductor device manufacturing method embodiment, and both are based on the same inventive concept.

[0192] The embodiment of the present application further provides an electronic device, which includes the above-mentioned integrated semiconductor device. Specifically, the electronic device includes the integrated semiconductor device and an electronic component connected to the above-mentioned integrated semiconductor device.

[0193] The electronic device of the embodiment of the present application can be selected from any electronic product or device such as a mobile phone, a personal digital assistant (PDA), a tablet computer (pad), a laptop computer, a game console, a television, a video compact disc (VCD), a digital video disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a handheld game console (PlayStation Portable, PSP), etc., and can also be any intermediate product of an electronic device made of the above-mentioned integrated semiconductor device.

[0194] It should be noted that the order of the embodiments of the present application described above is for descriptive purposes only and does not represent the superiority or inferiority of the embodiments. The above description is of specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0195] The various embodiments described in the specification are intended to be exemplary only and the same are not to be taken in a limiting sense. Unless otherwise noted, structures described in this disclosure are not intended to be solely composed of elements as illustrated in the figures and described herein. Rather, unless otherwise specified, structures depicted herein are shown as simplified representations can be comprised of many elements including many elements not specifically shown or described in the figures and / or specification. Furthermore, unless otherwise specified, structures shown in the figures can be implemented with other structures not expressly shown or described. It will be apparent to those skilled in the art that numerous and various embodiments can be derived from the teachings described herein without departing from the scope of the present disclosure.

[0196] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0197] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing an integrated semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a SGT substrate region of a first conductivity type and a BCD substrate region of a second conductivity type arranged laterally; forming at least one shallow trench isolation structure in the BCD substrate region; forming a second mask layer spanning the SGT substrate region and the BCD substrate region, wherein the second mask layer is stacked on a pad oxide layer, the pad oxide layer being located on the substrate; the second mask layer comprises a hard mask layer stacked on the pad oxide layer and a mask oxide layer stacked on the hard mask layer; forming at least one second etching window located at least in the SGT base region on the second mask layer and the pad oxide layer based on a patterning process, and performing trench etching on the SGT base region based on the second etching window to obtain a plurality of deep trenches; performing a trench wall oxidation process on the plurality of deep trenches to form an initial oxide layer covering the trench walls of the deep trenches, wherein the initial oxide layer is continuous with the pad oxide layer; Filling the deep trench with a gate material to form a first filling layer that fills the deep trench and covers the second mask layer; Using the hard mask layer or the pad oxide layer as a stop layer, thinning the first filling layer to obtain at least one gate filling structure isolated from each other, the at least one gate filling structure including a first gate filling structure corresponding to the voltage-resistant gate trench structure and a second gate filling structure corresponding to the shielding gate trench structure; The voltage-resistant gate trench structure and the shielding gate trench structure are formed based on the at least one gate filling structure, the voltage-resistant gate trench structure of the SGT substrate region is adjacent to the BCD substrate region, the shielding gate trench structure includes a shielding gate, a control gate, a shielding gate oxide layer and a control gate oxide layer, the shielding gate oxide layer isolates the shielding gate from the substrate, the control gate oxide layer isolates the control gate from the substrate, and isolates the shielding gate from the control gate; An isolation oxide layer is formed to at least cover a surface of the shield gate trench structure, wherein the isolation oxide layer is continuous with the control gate oxide layer.

2. The preparation method according to claim 1, characterized in that The thickness of at least a portion of the control gate oxide layer does not exceed a preset thickness, and the preset thickness is 70-130 Å.

3. The preparation method according to claim 1, characterized in that The control gate oxide layer is formed by performing surface oxidation treatment on at least the shielding gate and the trench wall of the shielding gate trench structure.

4. The preparation method according to claim 1, characterized in that The preparation method further comprises: The isolation oxide layer is formed by performing surface oxidation treatment on at least the control gate.

5. The preparation method according to any one of claims 1 to 4, characterized in that The forming of at least one shallow trench isolation structure in the BCD substrate region comprises: forming a pad oxide layer covering the BCD substrate region and the SGT substrate region on the substrate, and a first mask layer stacked on the pad oxide layer; forming at least one first etching window located in the BCD base region on the first mask layer and the pad oxide layer based on a patterning process, and performing trench etching on the BCD base region based on the first etching window to obtain at least one shallow trench; Filling the shallow trench with an isolation material to form the at least one shallow trench isolation structure; The first mask layer is removed.

6. The preparation method according to any one of claims 1 to 4, characterized in that The forming of the voltage-resistant gate trench structure and the shielding gate trench structure based on the at least one gate filling structure includes: shielding the first gate filling structure; Performing back etching on the second gate filling structure to form the shielding gate; Removing the unmasked initial oxide layer and the pad oxide layer to expose the unmasked substrate surface, a portion of the deep trench wall and a portion of the shielding gate, and the initial oxide layer remaining in the exposed deep trench forms the shielding gate oxide layer; performing oxidation treatment on the exposed portion of the shielding gate, the exposed deep trench wall and the exposed substrate surface to form the control gate oxide layer, and removing the shielding layer; Depositing a gate material to backfill the back-etched deep trench to form a second filling layer filling the deep trench and covering the substrate; Using the hard mask layer or the pad oxide layer as a stop layer, thinning the second filling layer until the second filling layer is flush with the hard mask layer or flush with the pad oxide layer, thereby obtaining a thinned second filling layer; The thinned second filling layer and the exposed first gate filling structure are etched to expose the control gate oxide layer on the surface of the substrate, thereby obtaining the voltage-resistant gate trench structure and the control gate located above the shielding gate.

7. The preparation method according to claim 6, characterized in that The forming of the isolation oxide layer at least covering the surface of the shield gate trench structure comprises: removing a surface oxide layer of the substrate until the surface of the substrate is exposed; Surface oxidation treatment is performed on the surface of the substrate, the voltage-resistant gate trench structure, and the control gate of the shielding gate trench structure to obtain the isolation oxide layer.

8. The preparation method according to any one of claims 1 to 4, characterized in that The gate filling structure is formed by using the pad oxide layer as a stop layer, and the forming of the voltage-resistant gate trench structure and the shielding gate trench structure based on the at least one gate filling structure includes: shielding the first gate filling structure; Performing back etching on the second gate filling structure to form the shielding gate; Removing the unmasked initial oxide layer and the pad oxide layer to expose the unmasked substrate surface, a portion of the deep trench wall and a portion of the shielding gate, and the initial oxide layer remaining in the exposed deep trench forms the shielding gate oxide layer; removing the shielding layer and the shielded pad oxide layer, and forming the voltage-resistant gate trench structure; forming a control gate oxide layer covering the exposed portion of the shielding gate, the exposed deep trench wall, the surface of the voltage-resistant gate trench structure, and the surface of the substrate; Depositing a gate material to backfill the back-etched deep trench to form a second filling layer filling the deep trench and covering the control gate oxide layer; The control gate oxide layer is used as a stop layer, and the second filling layer is thinned until the second filling layer is flush with the control gate oxide layer, thereby obtaining the control gate located above the shielding gate.

9. The preparation method according to claim 8, characterized in that Forming an isolation oxide layer at least covering a surface of the shield gate trench structure includes: The control gate of the shielding gate trench structure is subjected to surface oxidation treatment to form an isolation oxide layer continuous with the control gate oxide layer.

10. The preparation method according to claim 8, characterized in that The removing of the shielding layer and the shielded pad oxide layer and forming the voltage-resistant gate trench structure includes: removing the shielding layer; performing oxidation treatment on the exposed portion of the shielding gate, the exposed deep trench wall, the exposed substrate surface, and the surface of the first gate filling structure to form a sacrificial oxide layer, wherein the sacrificial oxide layer is continuous with the shielded pad oxide layer; The sacrificial oxide layer and the shielded pad oxide layer are removed to obtain the voltage-resistant gate trench structure.

11. The preparation method according to any one of claims 1 to 4, characterized in that After forming the isolation oxide layer at least covering the surface of the shield gate trench structure, the preparation method further includes: Doping structures are formed in the SGT substrate region and the BCD substrate region based on an ion implantation process. At least a portion of the doping structure in the SGT substrate region and at least a portion of the doping structure in the BCD substrate region are formed in the same ion implantation process.

12. An integrated semiconductor device, prepared based on the preparation method according to any one of claims 1 to 11, characterized in that: include: A substrate including a SGT substrate region of a first conductivity type and a BCD substrate region of a second conductivity type arranged laterally; at least one shallow trench isolation structure located in the BCD substrate region; A voltage-resistant gate trench structure located in the SGT substrate region; A shield gate trench structure located in the SGT substrate region, comprising a shield gate, a control gate, a shield gate oxide layer and a control gate oxide layer, wherein the shield gate oxide layer isolates the shield gate from the substrate, the control gate oxide layer isolates the control gate from the substrate, and isolates the shield gate from the control gate; The isolation oxide layer at least covers the surface of the voltage-resistant gate trench structure and the surface of the shielding gate trench structure, and is continuous with the control gate oxide layer.

13. The integrated semiconductor device according to claim 12, wherein: The thickness of at least a portion of the control gate oxide layer does not exceed a preset thickness, and the preset thickness is 70-130 Å.

Images