Photovoltaic cell and manufacturing method thereof, laminated cell and photovoltaic module

Abstract

The embodiment of the invention relates to the photovoltaic field, and provides a photovoltaic cell and a manufacturing method thereof, a laminated cell and a photovoltaic module, and the photovoltaic cell comprises a substrate which is provided with a first surface side and a second surface side which are opposite to each other in a first direction; a tunneling layer on at least one of the first surface side and the second surface side; the doped semiconductor layer is doped with a doping element and is positioned on one side, far away from the substrate, of the tunneling layer; wherein one side, close to the doped semiconductor layer, of the tunneling layer is provided with a plurality of pits; the doping concentration of the doping element in the doped semiconductor layer is gradually increased in the direction from the substrate to the tunneling layer. According to the embodiment of the invention, the defect state density at the contact interface of the substrate and the tunneling layer can be reduced, and the tunneling efficiency of carriers in the tunneling layer can be improved.

Description

Technical Field

[0001] The present disclosure relates to the photovoltaic field, and in particular to a photovoltaic cell and a manufacturing method thereof, a laminated cell, and a photovoltaic module. Background Art

[0002] As fossil fuels gradually deplete, photovoltaic cells are becoming increasingly popular as a new energy alternative. Photovoltaic cells convert sunlight into electricity. They utilize the principle of photovoltaics to generate charge carriers, which are then extracted using electrodes, facilitating efficient use of the electrical energy.

[0003] Current photovoltaic cells primarily include BC cells (Back Contact), TOPCON (Tunnel Oxide Passivated Contact), PERC (Passivated Emitter and Real Cell), and heterojunction cells. To improve the photoelectric conversion efficiency of photovoltaic cells, different film layer configurations and functional limitations are employed.

[0004] However, in the current passivation contact structure of photovoltaic cells that includes a tunneling layer, it is difficult to balance the tunneling efficiency of carriers in the tunneling layer and the recombination loss of carriers, which requires further research. Summary of the Invention

[0005] The embodiments of the present disclosure provide a photovoltaic cell and a manufacturing method thereof, a stacked cell, and a photovoltaic module, which are at least beneficial in reducing the defect state density at the interface between the substrate and the tunneling layer, and improving the tunneling efficiency of carriers in the tunneling layer.

[0006] According to some embodiments of the present disclosure, on one hand, the embodiments of the present disclosure provide a photovoltaic cell, comprising: a substrate having a first surface side and a second surface side opposite to each other along a first direction; a tunneling layer located on at least one of the first surface side and the second surface side; a doped semiconductor layer doped with a doping element, located on a side of the tunneling layer away from the substrate; wherein the tunneling layer has a plurality of pits on a side close to the doped semiconductor layer; and the doping concentration of the doping element in the doped semiconductor layer gradually increases in a direction from the substrate to the tunneling layer.

[0007] In some embodiments, along the first direction, a ratio of the depth of the pit to the thickness of the tunnel layer is 20%-80%.

[0008] In some embodiments, the orthographic projection of the pit on the substrate is a circle, and the diameter of the circle is 5 nm to 10 nm; and / or the arrangement density of the pit in the tunneling layer is 1×10 9 pieces / cm 2 ~1×10 11 pieces / cm 2 .

[0009] In some embodiments, the tunneling layer includes a bottom facing the pit along the first direction, and the electric field strength formed by the bottom is 10 5 V / m~10 8 V / m.

[0010] In some embodiments, the tunneling layer includes a bottom facing the pit along the first direction, the bottom covers at least one of the first surface side and the second surface side, and along the first direction, the thickness of the bottom is 0.5nm~1.0nm.

[0011] In some embodiments, the tunneling layer includes: a first tunneling layer located on the first surface side, and a second tunneling layer located on the second surface side; the doped semiconductor layer includes: a first doped semiconductor layer located on the side of the first tunneling layer away from the substrate, and a second doped semiconductor layer located on the side of the second tunneling layer away from the substrate; wherein the doping element includes a first doping element and a second doping element of different conductivity types, the first doping semiconductor layer is doped with the first doping element, and the second doping semiconductor layer is doped with the second doping element; in the direction from the substrate to the first tunneling layer, the doping concentration of the first doping element in the first doped semiconductor layer gradually increases; in the direction from the substrate to the second tunneling layer, the doping concentration of the second doping element in the second doped semiconductor layer gradually increases.

[0012] In some embodiments, along the first direction, a thickness of the first doped semiconductor layer is less than a thickness of the second doped semiconductor layer.

[0013] In some embodiments, the doping concentration of the doping element in the doped semiconductor layer is from 1×10 19 atom / cm 3 Gradually increase to 1×10 21 atom / cm 3 .

[0014] In some embodiments, the photovoltaic cell further comprises: an electrode located at least on a side of the doped semiconductor layer away from the substrate, and the electrode comprises a tip embedded in the doped semiconductor layer.

[0015] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a photovoltaic cell, comprising: providing a substrate, the substrate having a first surface side and a second surface side opposite to each other along a first direction; forming a tunneling layer, the tunneling layer being located on at least one of the first surface side and the second surface side, and the tunneling layer having a plurality of pits on a side away from the substrate; forming a doped semiconductor layer doped with doping elements, the doped semiconductor layer being located on a side of the tunneling layer away from the substrate, and the pits being spaced between the doped semiconductor layer and the tunneling layer, and the doping concentration of the doping element in the doped semiconductor layer gradually increases in a direction from the substrate to the tunneling layer.

[0016] In some embodiments, the step of forming the tunneling layer includes: forming an initial tunneling layer on at least one of the first surface side and the second surface side; using a hydrofluoric acid vapor selective etching process to form a plurality of the pits on a side of the initial tunneling layer close to the doped semiconductor layer, and the remaining initial tunneling layer serves as the tunneling layer.

[0017] In some embodiments, in the step of performing the hydrofluoric acid vapor selective etching process, the concentration of the hydrofluoric acid is 50% to 80%; and / or the processing time of the hydrofluoric acid vapor selective etching process is 30s to 60s.

[0018] In some embodiments, the step of forming the doped semiconductor layer includes: providing a reaction chamber; in the reaction chamber, using a deposition process to deposit an initial semiconductor layer on the side of the tunneling layer away from the substrate, and in the step of performing the deposition process, introducing a doping source gas containing the doping element into the reaction chamber so that the initial semiconductor layer is doped with the doping element to form the doped semiconductor layer; wherein, as the deposition process proceeds, the flow rate of the doping source gas introduced into the reaction chamber is gradually increased, so that the doping concentration of the doping element in the doped semiconductor layer gradually increases in the direction from the substrate to the tunneling layer.

[0019] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a stacked cell, comprising: a bottom cell, which is a photovoltaic cell as described in any one of the above items, or a photovoltaic cell formed by the photovoltaic cell manufacturing method as described in any one of the above items; and a top cell, which is located on one side of the bottom cell.

[0020] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a photovoltaic assembly, comprising: a cell string, formed by electrically connecting a plurality of photovoltaic cells as described in any one of the above items, or electrically connecting a plurality of photovoltaic cells formed by the photovoltaic cell manufacturing method as described in any one of the above items, or electrically connecting a plurality of stacked cells as described above; a packaging film for covering the surface of the cell string; and a cover plate for covering the surface of the packaging film facing away from the cell string.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: On the one hand, it is beneficial to reduce the thickness of some areas in the tunneling layer by means of the pits to enhance the electric field strength formed in the area, thereby prompting more carriers to pass through the tunneling layer at a faster speed, so as to improve the tunneling efficiency of the carriers in the tunneling layer; on the other hand, based on the characteristic that the doping concentration of the doping element in the doped semiconductor layer gradually increases, the doping concentration of the doping element in the part of the doped semiconductor layer that is in contact with the tunneling layer is the lowest, so as to match the thickness of the tunneling layer with the pits. Even if the thickness of the tunneling layer with the pits is thinned, it is beneficial to reduce the risk of the doping element diffusing through the tunneling layer to the substrate, thereby effectively avoiding the substrate The defect state density at the interface in contact with the tunneling layer increases; on the other hand, the tunneling layer has multiple pits on the side close to the doped semiconductor layer, and the side of the tunneling layer close to the substrate can have a complete and continuous film layer to passivate the substrate, which is conducive to further reducing the defect state density at the interface between the substrate and the tunneling layer, thereby reducing carrier recombination losses; on the other hand, while minimizing the doping concentration of the doping element in the portion of the doped semiconductor layer in contact with the tunneling layer, the average doping concentration of the doping element in the doped semiconductor layer as a whole is still high, thereby reducing the transmission resistance of the doped semiconductor layer as a whole. In this way, based on the coordination of multiple aspects, it is conducive to allowing more carriers in the substrate to be quickly transmitted to the doped semiconductor layer based on the quantum tunneling effect, thereby improving the carrier collection efficiency of the photovoltaic cell, thereby improving the short-circuit current and open-circuit voltage of the photovoltaic cell, and thus improving its photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 A first cross-sectional schematic diagram of a photovoltaic cell provided in one embodiment of the present disclosure; Figure 2 for Figure 1 An enlarged cross-sectional schematic diagram of the photovoltaic cell at the dotted box A shown; Figure 3 for Figure 1 An enlarged cross-sectional schematic diagram of the photovoltaic cell at the dotted box B is shown; Figure 4 A second cross-sectional schematic diagram of a photovoltaic cell provided in one embodiment of the present disclosure; Figure 5 for Figure 4 An enlarged cross-sectional schematic diagram of the photovoltaic cell at the dotted box C shown; Figure 6 for Figure 4 An enlarged cross-sectional schematic diagram of the photovoltaic cell shown in the dashed box D; Figure 7 A third cross-sectional schematic diagram of a photovoltaic cell provided in one embodiment of the present disclosure; Figure 8 A schematic partial cross-sectional view after forming an initial tunneling layer in a method for manufacturing a photovoltaic cell provided by another embodiment of the present disclosure; Figure 9 A schematic partial cross-sectional view of a photovoltaic cell manufacturing method according to another embodiment of the present disclosure after an initial semiconductor layer is formed; Figure 10 A partial cross-sectional schematic diagram of a laminated battery provided in yet another embodiment of the present disclosure; Figure 11 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided by yet another embodiment of the present disclosure; Figure 12 A partial cross-sectional schematic diagram of a photovoltaic assembly provided in yet another embodiment of the present disclosure.

[0024] Description of reference numerals: 100. Substrate; 110. First surface side; 120. Second surface side; 101. Tunneling layer; 1011. First tunneling layer; 1012. Second tunneling layer; 111. Recess; 121. Bottom; 131. Top; 141. Initial tunneling layer; 1411. First initial tunneling layer; 1412. Second initial tunneling layer; 102. Doped semiconductor layer; 1021. First doped semiconductor layer; 1022. Second doped semiconductor layer; 112. Initial semiconductor layer; 1121. Initial first semiconductor layer; 1122. Initial second semiconductor layer; 103. Electrode; 113. Tip; 104. First anti-reflection layer; 105. Second anti-reflection layer; 106. Bottom cell; 107. Top cell; 40. Photovoltaic cell; 41. Encapsulation film; 42. Cover; 43. Conductive tape. DETAILED DESCRIPTION

[0025] As known from the background art, it is difficult to balance the tunneling efficiency of carriers in the tunneling layer and the recombination loss of carriers, which requires further research.

[0026] The embodiments of the present disclosure provide a photovoltaic cell and a manufacturing method thereof, a stacked cell, and a photovoltaic module. In the photovoltaic cell, on the one hand, the thickness of a part of the tunneling layer is reduced by means of the pits to enhance the electric field strength formed in the region, thereby prompting more carriers to pass through the tunneling layer at a faster speed, thereby improving the tunneling efficiency of the carriers in the tunneling layer; on the other hand, based on the characteristic that the doping concentration of the doping element in the doped semiconductor layer gradually increases, the doping concentration of the doping element in the part of the doped semiconductor layer that is in contact with the tunneling layer is the lowest, so as to match the thickness of the tunneling layer with the pits. Even if the thickness of the tunneling layer with the pits is reduced, it is beneficial to reduce the diffusion of the doping element through the tunneling layer. On the other hand, the risk of the doping element being dispersed into the substrate can be effectively avoided, thereby effectively avoiding the increase of the defect state density at the interface between the substrate and the tunneling layer; on the other hand, the tunneling layer has multiple pits on the side close to the doped semiconductor layer, and the side close to the substrate in the tunneling layer can have a complete and continuous film layer to passivate the substrate, which is conducive to further reducing the defect state density at the interface between the substrate and the tunneling layer, thereby reducing the recombination loss of carriers; on the other hand, while making the doping concentration of the doping element in the part of the doped semiconductor layer that is in contact with the tunneling layer the lowest, the average doping concentration of the doping element in the doped semiconductor layer as a whole is still high, thereby reducing the transmission resistance of the doped semiconductor layer as a whole. In this way, based on the coordination of multiple aspects, it is conducive to allowing more carriers in the substrate to be quickly transmitted to the doped semiconductor layer based on the quantum tunneling effect, thereby improving the carrier collection efficiency of the photovoltaic cell, thereby improving the short-circuit current and open-circuit voltage of the photovoltaic cell, and thus improving its photoelectric conversion efficiency.

[0027] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are used solely to distinguish between different objects and should not be understood to indicate or imply relative importance or to implicitly specify the quantity, specific order, or primary and secondary relationship of the technical features indicated. In the description of the embodiments of the present disclosure, "plurality" means more than two, unless otherwise specifically defined.

[0028] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0029] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0030] In the description of the embodiments of the present disclosure, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0031] In the description of the embodiments of the present disclosure, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the embodiments of the present disclosure.

[0032] In the description of the embodiments of the present disclosure, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and they can refer to internal connectivity between two components or interaction between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present disclosure based on specific circumstances.

[0033] In the accompanying drawings corresponding to the embodiments of the present disclosure, the thickness and area of ​​layers are exaggerated for better understanding and ease of description. When a component (such as a layer, film, region, or substrate) is described as being on or on the surface of another component, the component may be "directly" located on the surface of the other component, or a third component may be present between the two components. Conversely, when a component is described as being on the surface of another component, or as being formed or disposed on the surface of one component, it indicates that there is no third component between the two components. Furthermore, when a component is described as being "substantially" formed on another component, this means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a portion of the edge of the entire surface.

[0034] In the description of the embodiments of the present disclosure, when a component is referred to as "including" another component, unless otherwise specified, this does not exclude other components, and other components may further be included. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "on" another component, it may be "directly on" the other component (i.e., located on the surface of the other component with no other components between them) or another component may be present between them. Furthermore, when a component such as a layer, film, region, or plate is referred to as being "directly on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, this means that no other components are located between them.

[0035] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0036] The following detailed description of various embodiments of the present disclosure is provided in conjunction with the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the embodiments of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can be implemented.

[0037] An embodiment of the present disclosure provides a photovoltaic cell, which will be described in detail below with reference to the accompanying drawings.

[0038] Combined with reference Figures 1 to 3The photovoltaic cell includes: a substrate 100, the substrate 100 having a first surface side 110 and a second surface side 120 opposite to each other along a first direction X; a tunneling layer 101, located on at least one of the first surface side 110 and the second surface side 120; a doped semiconductor layer 102 doped with a doping element, located on a side of the tunneling layer 101 away from the substrate 100; wherein a side of the tunneling layer 101 close to the doped semiconductor layer 102 has a plurality of pits 111; the doping concentration of the doping element in the doped semiconductor layer 102 gradually increases along the direction from the substrate 100 to the tunneling layer 101.

[0039] It should be noted that Figure 1 A first cross-sectional schematic diagram of a photovoltaic cell provided in one embodiment of the present disclosure; Figure 2 for Figure 1 An enlarged cross-sectional schematic diagram of the photovoltaic cell at the dotted box A shown; Figure 3 for Figure 1 An enlarged cross-sectional view of the dotted box B in the photovoltaic cell shown. Figure 1 In the example, the tunneling layer 101 is located on both the first surface side 110 and the second surface side 120. In actual applications, the tunneling layer may be located only on the first surface side or only on the second surface side. Various situations will be described in detail later.

[0040] It is worth noting that the tunneling layer 101 can play a certain role in blocking the doping elements in the doped semiconductor layer 102, preventing excessive doping elements in the doped semiconductor layer 102 from diffusing through the tunneling layer 101 to the surface of the substrate 100, thereby avoiding the formation of numerous defects on the surface of the substrate 100. Moreover, the passivation effect of the tunneling layer 101 on the substrate 100 is also affected by the thickness of the tunneling layer 101 in the first direction X. Based on this, the thickness of the tunneling layer 101 in the first direction X should not be too thin. However, to ensure that a large number of carriers can pass through the tunneling layer 101 at a relatively fast rate by virtue of the quantum tunneling effect and be transmitted to the doped semiconductor layer 102, the thickness of the tunneling layer 101 in the first direction X should not be too thick.

[0041] On the basis of the above, the tunneling layer 101 and the doped semiconductor layer 102 are designed in coordination. On the one hand, it is beneficial to reduce the thickness of a part of the tunneling layer 101 by means of the multiple pits 111 on the side of the tunneling layer 101 close to the doped semiconductor layer 102 to enhance the electric field strength formed in the region, so that the tunneling layer 101 located in the region can have a stronger driving force for the carriers, prompting more carriers to pass through the tunneling layer 101 at a faster speed, so as to improve the tunneling efficiency of the carriers in the tunneling layer 101; at the same time, on the other hand, the design is such that the doping elements in the doped semiconductor layer 101 are arranged in a direction from the substrate 100 to the tunneling layer 101. The doping concentration in the layer 102 gradually increases, so that the doping concentration of the doping element in the part of the doped semiconductor layer 102 that is in contact with the tunnel layer 101 is the lowest, so as to match the thickness of the tunnel layer 101 with the pit 111. Even if the thickness of the tunnel layer 101 with the pit 111 is thinned, the reduction in the doping concentration of the doping element in the doped semiconductor layer 102 at the contact point with the tunnel layer 101 is beneficial to reducing the risk of the doping element diffusing through the tunnel layer 101 into the substrate 100, thereby effectively avoiding the increase in the defect state density at the interface between the substrate 100 and the tunnel layer 101 caused by the diffusion of the doping element. In other words, the design of thinning the thickness of the area with the pit 111 in the tunneling layer 101 can match the low doping concentration of the doping element at the contact point between the doped semiconductor layer 102 and the tunneling layer 101, thereby improving the tunneling efficiency of carriers in the tunneling layer 101 while reducing the risk of the doping element diffusing through the tunneling layer 101 into the substrate 100, thereby reducing the defect state density at the interface where the substrate 100 and the tunneling layer 101 contact, thereby effectively reducing the recombination loss of carriers before tunneling.

[0042] Moreover, on the other hand, when the tunneling layer 101 is designed to have a plurality of pits 111 on the side close to the doped semiconductor layer 102, the side of the tunneling layer 101 close to the substrate 100 can have a complete and continuous film layer, that is, the tunneling layer 101 can still cover the surface of the substrate 100 to passivate the substrate 100, so as to further reduce the defect state density at the interface where the substrate 100 and the tunneling layer 101 contact, so as to reduce the recombination loss of carriers; on the other hand, the design is to dope the doping elements in the doped semiconductor layer 102 in the direction from the substrate 100 to the tunneling layer 101. The concentration gradually increases, which makes the doping concentration of the doping element in the part of the doped semiconductor layer 102 that is in contact with the tunnel layer 101 as the lowest, and is also beneficial to make the average doping concentration of the doping element in the doped semiconductor layer 102 as a whole still relatively high, so as to reduce the overall transmission resistance of the doped semiconductor layer 102, and is beneficial to increase the doping concentration of the doping element in the part of the doped semiconductor layer 102 that is in contact with the subsequent electrode, so as to reduce the contact resistance between the doped semiconductor layer 102 and the subsequent electrode, and ultimately improve the collection efficiency of the subsequent electrode for carriers in the doped semiconductor layer 102.

[0043] In this way, based on the fact that the tunneling layer 101 has multiple pits 111 on one side close to the doped semiconductor layer 102, and the coordinated design that the doping concentration of the doping element in the doped semiconductor layer 102 gradually increases in the direction pointing from the substrate 100 to the tunneling layer 101, it is beneficial to enable more carriers in the substrate 100 to be quickly transmitted to the doped semiconductor layer 102 based on the quantum tunneling effect, and further quickly transmitted to the subsequent electrodes, thereby helping to improve the carrier collection efficiency of the photovoltaic cell, thereby improving the short-circuit current and open-circuit voltage of the photovoltaic cell, and thus improving its photoelectric conversion efficiency.

[0044] In some cases, the photoelectric conversion efficiency of the photovoltaic cell provided in an embodiment of the present disclosure can be increased to 26.5% or above, and the bifaciality of the photovoltaic cell can be increased to 85% or above.

[0045] In some cases, the design in which the doping concentration of the doping element in the doped semiconductor layer 102 gradually increases in the direction away from the substrate 100 is beneficial for reducing the carrier recombination velocity at the interface between the tunneling layer 101 and the doped semiconductor layer 102 to less than 10 cm / s.

[0046] The photovoltaic cell provided in one embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0047] In some embodiments, in conjunction with reference Figures 1 to 3Along the first direction X, the ratio of the depth of the pit 111 to the thickness of the tunnel layer 101 may be 20% to 80%. Preferably, the ratio of the depth of the pit 111 to the thickness of the tunnel layer 101 may be 30% to 50%, for example, 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, 45%, 46%, 47%, 48%, or 49%.

[0048] It is worth noting that if the ratio of the depth of the pit 111 to the thickness of the tunneling layer 101 is less than 20%, along the first direction X, the thickness of the portion of the tunneling layer 101 used to form the bottom surface of the pit 111 is less thinned than the thickness of the portion of the tunneling layer 101 without the pit, and the effect of improving the electric field strength of the portion of the tunneling layer 101 used to form the bottom surface of the pit 111 is limited, and the effect of promoting more carrier quantum tunneling is limited; if the depth of the pit 111 is less than 20%, the thickness of the portion of the tunneling layer 101 used to form the bottom surface of the pit 111 is less thinned than the thickness of the portion of the tunneling layer 101 without the pit. The ratio of the depth of the tunneling layer 101 to the thickness of the tunneling layer 101 is greater than 80%. Compared with the thickness of the portion of the tunneling layer 101 without the pit, the thickness of the portion of the tunneling layer 101 that forms the bottom surface of the pit 111 is thinned to a greater extent. Therefore, the thickness of the complete and continuous film layer of the tunneling layer 101 near the substrate 100 is relatively low. For example, the ratio of the thickness of the entire film layer to the thickness of the tunneling layer 101 is less than 20%, which is not conducive to ensuring that the tunneling layer 101 has a good passivation effect on the substrate 100. Therefore, the ratio of the depth of the pit 111 to the thickness of the tunneling layer 101 is designed to be 30% to 50%. This can control the depth of the pit 111 to be appropriate, thereby effectively improving the tunneling efficiency of carriers in the tunneling layer 101 through the pit 111 while ensuring that the tunneling layer 101 has a good passivation effect on the substrate 100, thereby reducing carrier recombination losses.

[0049] In some embodiments, in conjunction with reference Figures 1 to 3 The orthographic projection of the pit 111 on the substrate 100 may be a circle, and the diameter of the circle may be 5 nm to 10 nm, for example, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, or 9.5 nm. It is worth noting that the size of the pit 111 on the surface of the substrate 100 is at the nanometer level, which facilitates the layout of a large number of pits 111 on the surface of the tunnel layer with a limited layout area. This allows multiple regions in the tunnel layer 101 to form local electric fields with higher electric field strength based on the pits 111, so that carriers in the substrate 100 have multiple efficient transmission paths through the tunnel layer 101, thereby ensuring high tunneling efficiency of carriers in the tunnel layer 101.

[0050] It should be noted that the above-mentioned “tunneling layer surface” and the “tunneling layer surface” mentioned later all include the surface of the tunneling layer 101 away from the substrate 100 .

[0051] In some cases, due to the nanometer-scale size of the pits 111 on the surface of the substrate 100, when the doped semiconductor layer 102 is formed, the doped semiconductor layer 102 generally does not completely fill the pits 111. In other words, an air gap exists in the pits 111 between the doped semiconductor layer 102 and the tunneling layer 101. It is worth noting that during the process of forming the doped semiconductor layer 102 using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process, although the initial deposition of amorphous silicon by PECVD preferentially fills the pits from the perspective of the film growth mechanism, when the diameter of the pits 111 is less than 10 nm and the depth is relatively small, for example, less than 1 nm, the surface diffusion effect inhibits complete filling. In other words, the pits 111 are not completely filled by the doped semiconductor layer 102, resulting in an air gap in the pits 111 between the doped semiconductor layer 102 and the tunneling layer 101. In addition, the pit 111 can be regarded as a bowl-shaped pit rather than a vertical hole. The bowl-shaped pit hinders the nucleation of the precursor (such as silane) in the pit 111 , thereby inhibiting the formation of amorphous silicon in the pit 111 .

[0052] In some embodiments, in conjunction with reference Figures 1 to 3 The arrangement density of the pits 111 in the tunneling layer 101 can be 1×10 9 pieces / cm 2 ~1×10 11 pieces / cm 2 , for example, it can be 2×10 9 pieces / cm 2 , 5×10 9 pieces / cm 2 , 8×10 9 pieces / cm 2 , 9×10 9 pieces / cm 2 , 1×10 10 pieces / cm 2 , 3×10 10 pieces / cm 2 , 5×10 10 pieces / cm 2 , 7×10 10 pieces / cm 2 or 9×10 10 pieces / cm 2 wait.

[0053] It is worth noting that if the arrangement density of the pits 111 in the tunneling layer 101 is less than 1×10 9 pieces / cm 2 , the number of pits 111 arranged on the surface of the tunneling layer with a limited layout area is small, and the number of local high electric field strengths formed by the pits 111 in the tunneling layer 101 is small, so the driving effect on the tunneling of carriers is weakened; if the arrangement density of the pits 111 in the tunneling layer 101 is greater than 1×10 11 pieces / cm 2 , the number of pits 111 arranged on the surface of the tunneling layer with a limited layout area is large, which easily forms more defects on the surface of the tunneling layer 101 away from the substrate 100, thereby easily causing an increase in the defect state density at the interface between the tunneling layer 101 and the doped semiconductor layer 102. Therefore, the arrangement density of the pits 111 in the tunneling layer 101 is designed to be 1×10 9 pieces / cm 2 ~1×10 11 pieces / cm 2 , which is beneficial to controlling the number of pits 111 arranged on the surface of the tunnel layer with a limited layout area to be moderate, so that the carriers in the substrate 100 have multiple efficient transmission paths to pass through the tunnel layer 101, while avoiding the increase of the defect state density at the interface where the tunnel layer 101 and the doped semiconductor layer 102 contact, thereby ensuring lower carrier recombination losses.

[0054] In some embodiments, in conjunction with reference Figures 1 to 3 The tunneling layer 101 includes a bottom 121 facing the pit 111 along the first direction X. The electric field strength formed by the bottom 121 can be 10 5 V / m~10 8 V / m, for example, can be 2×10 5 V / m, 5×10 5 V / m, 8×10 5 V / m, 1×10 6 V / m, 2×10 6 V / m, 5×10 6 V / m, 8×10 6 V / m, 1×10 7 V / m, 3×10 7 V / m, 5×10 7 V / m or 8×10 7 V / m, etc.

[0055] It should be noted that the tunneling layer 101 includes not only the bottom 121 but also a portion other than the bottom 121, namely, the top 131. The bottom 121 and the top 131 are stacked along the first direction X. The bottom 121 can be regarded as the portion of the tunneling layer 101 without the pit 111, and the top 131 can be regarded as the portion of the tunneling layer 101 that accommodates the pit 111. Figure 2 and Figure 3 In the figures, the bottom 121 and the top 131 are divided by thicker dotted lines.

[0056] In some embodiments, in conjunction with reference Figures 1 to 3 The tunneling layer 101 includes a bottom 121 that is opposite to the pit 111 along the first direction X. The bottom 121 covers at least one of the first surface side 110 and the second surface side 120, and along the first direction X, the thickness of the bottom 121 is 0.5nm~1.0nm, for example, it can be 0.55nm, 0.6nm, 0.65nm, 0.7nm, 0.75nm, 0.8nm, 0.85nm, 0.9nm or 0.95nm, etc.

[0057] It is worth noting that, in the tunneling layer 101, except for the bottom 121, that is, when the thickness of the top 131 is constant, if the thickness of the bottom 121 is less than 0.5nm, the depth of the pit 111 enclosed by the top 131 and the bottom 121 is large. Although it can improve the tunneling efficiency of carriers, the bottom 121 with a thickness of less than 0.5nm has a poor passivation effect on the substrate 100; if the thickness of the bottom 121 is greater than 1.0nm, the depth of the pit 111 enclosed by the top 131 and the bottom 121 is small, and the effect of promoting more carrier quantum tunneling is limited. Based on this, the thickness of the bottom 121 is designed to be 0.5nm~1.0nm, which is conducive to ensuring that the bottom 121 also has a good passivation effect on the substrate 100, and can effectively improve the tunneling efficiency of carriers in the tunneling layer 101 with the help of the bottom 121.

[0058] In some embodiments, reference Figure 1The tunneling layer 101 may include: a first tunneling layer 1011 located on the first surface side 110, and a second tunneling layer 1012 located on the second surface side 120; the doped semiconductor layer 102 includes: a first doped semiconductor layer 1021 located on a side of the first tunneling layer 1011 away from the substrate 100, and a second doped semiconductor layer 1022 located on a side of the second tunneling layer 1012 away from the substrate 100; wherein the doping elements include a first doping element and a second doping element of different conductivity types, the first doping semiconductor layer 1021 is doped with the first doping element, and the second doping semiconductor layer 1022 is doped with the second doping element; in a direction from the substrate 100 to the first tunneling layer 1011, the doping concentration of the first doping element in the first doped semiconductor layer 1021 gradually increases; in a direction from the substrate 100 to the second tunneling layer 1012, the doping concentration of the second doping element in the second doped semiconductor layer 1022 gradually increases.

[0059] It is worth noting that the first tunneling layer 1011 and the first doped semiconductor layer 1021 can constitute a passivation contact structure located on the first surface side 110, and the second tunneling layer 1012 and the second doped semiconductor layer 1022 can constitute a passivation contact structure located on the second surface side 120, so that the passivation contact structure is provided on both the first surface side 110 and the second surface side 120, which is beneficial to improving the tunneling efficiency of the carriers collected on the first surface side 110 and the transmission efficiency in the first doped semiconductor layer 1021, and improving the tunneling efficiency of the carriers collected on the second surface side 120 and the transmission efficiency in the second doped semiconductor layer 1022, and reducing the recombination loss of carriers at the first surface side 110 and the second surface side 120, thereby helping to improve the bifaciality of the photovoltaic cell.

[0060] In some cases, one of the first doping element and the second doping element is an N-type doping element, and the other is a P-type doping element.

[0061] In some examples, the N-type doping element may be at least one of Group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As); the P-type semiconductor substrate is doped with a P-type element, and the P-type doping element may be at least one of Group III elements such as boron (B), aluminum (Al), gallium (Ga), or gallium (In).

[0062] It should be noted that Figure 1In this example, a first tunneling layer 1011 and a first doped semiconductor layer 1021 are stacked on the first surface side 110, and a second tunneling layer 1012 and a second doped semiconductor layer 1022 are stacked on the second surface side 120. In practical applications, the tunneling layer may be located only on the first surface side, i.e., the tunneling layer includes only the first tunneling layer and the doped semiconductor layer includes only the first doped semiconductor layer; or the tunneling layer may be located only on the second surface side, i.e., the tunneling layer includes only the second tunneling layer and the doped semiconductor layer includes only the second doped semiconductor layer. Based on this, the photovoltaic cell provided in one embodiment of the present disclosure can be either a TOPCON cell or a BC cell.

[0063] In some cases, in conjunction with reference Figures 1 to 3 , along the first direction X, the thickness of the first doped semiconductor layer 1021 is less than the thickness of the second doped semiconductor layer 1022. It is worth noting that, on the one hand, the thinning of the first doped semiconductor layer 1021 is beneficial for reducing the parasitic absorption of light by the thickness of the first doped semiconductor layer 1021, thereby improving the photoelectric conversion efficiency of the first surface side 110 by increasing the absorption utilization rate of light by the first surface side 110; on the other hand, compared with the thickness of the first doped semiconductor layer 1021, the thickness of the second doped semiconductor layer 1022 is greater, which is beneficial for improving the carrier collection efficiency of the second doped semiconductor layer 1022, thereby improving the photoelectric conversion efficiency of the second surface side 120, and thus facilitating the improvement of the bifaciality of the photovoltaic cell, for example, increasing the bifaciality of the photovoltaic cell to 85% or above.

[0064] In some examples, the photovoltaic cell can be a single-sided cell, that is, the first surface side 110 can serve as a light-receiving surface for receiving incident light, and the second surface side 120 can serve as a backlight surface; or, the photovoltaic cell can be a double-sided cell, in which case both the first surface side 110 and the second surface side 120 can serve as light-receiving surfaces, both of which can be used to receive incident light. It is understandable that the backlight surface described in one embodiment of the present disclosure can also receive incident light, but the degree of reception of the incident light is weaker than the degree of reception of the incident light by the light-receiving surface, and is therefore defined as a backlight surface. Based on this, along the first direction X, the thickness of the first doped semiconductor layer 1021 is designed to be less than the thickness of the second doped semiconductor layer 1022. By reducing the parasitic absorption of light by the thickness of the first doped semiconductor layer 1021, it is beneficial to maximize the absorption and utilization of light incident on the first surface side 110, so as to further improve the photoelectric conversion efficiency of the first surface side 110.

[0065] In some examples, along the first direction X, the thickness of the first doped semiconductor layer 1021 can be 80 nm, and the thickness of the second doped semiconductor layer 1022 can be 150 nm.

[0066] In some embodiments, in conjunction with reference Figures 1 to 3 , along the direction from the substrate 100 to the tunneling layer 101, the doping concentration of the doping element in the doped semiconductor layer 102 increases from 1×10 19 atom / cm 3 Gradually increase to 1×10 21 atom / cm 3 In this way, on the one hand, the doping concentration of the doping element at the interface between the doped semiconductor layer 102 and the tunneling layer 101 can be controlled to be as low as 1×10 19 atom / cm 3 , effectively reducing the defect state density at the interface between the doped semiconductor layer 102 and the tunneling layer 101 caused by the doping elements, thereby reducing the carrier recombination velocity at the interface between the doped semiconductor layer 102 and the tunneling layer 101 to less than 10 cm / s; on the other hand, the doping concentration of the doping element at the interface between the doped semiconductor layer 102 and the subsequent electrode can be controlled to be as high as 1×10 21 atom / cm 3 , effectively reducing the contact resistance at the interface between the doped semiconductor layer 102 and the subsequent electrode, thereby improving the carrier transmission efficiency in the doped semiconductor layer 102.

[0067] In some embodiments, in conjunction with reference Figures 4 to 6 The photovoltaic cell may further include: an electrode 103 , at least located on a side of the doped semiconductor layer 102 away from the substrate 100 , and the electrode 103 includes a tip 113 embedded in the doped semiconductor layer 102 .

[0068] in, Figure 4 A second cross-sectional schematic diagram of a photovoltaic cell provided in one embodiment of the present disclosure; Figure 5 for Figure 4 An enlarged cross-sectional schematic diagram of the photovoltaic cell at the dotted box C shown; Figure 6 for Figure 4 An enlarged cross-sectional schematic diagram of the dotted box D in the photovoltaic cell shown.

[0069] It is worth noting that, on the one hand, the size of the tip 113 embedded in the doped semiconductor layer 102 in the electrode 103 is at the nanometer level, and the doped semiconductor layer 102 still maintains a high degree of integrity to ensure the good electrical properties of the doped semiconductor layer 102 itself, such as ensuring that the doped semiconductor layer 102 has a good field passivation effect and reduces the carrier recombination loss at the contact between the electrode 103 and the doped semiconductor layer 102; on the other hand, it is beneficial to increase the contact area between the electrode 103 and the doped semiconductor layer 102 with the help of the tip 113, thereby further reducing the contact resistance at the contact between the electrode 103 and the doped semiconductor layer 102, so as to improve the carrier collection efficiency of the electrode 103.

[0070] It should be noted that the tip 113 of the electrode 103 only needs to be embedded in the doped semiconductor layer 102 and will not be embedded in the tunneling layer 101 .

[0071] In some cases, the material of electrode 103 may include at least one of silver, aluminum, or copper.

[0072] In some examples, the material of the electrode 103 may include silver and aluminum, and an Ag-Al-Si eutectic may be formed at the contact between the electrode 103 and the doped semiconductor layer 102 to improve the contact performance between the electrode 103 and the doped semiconductor layer 102; in addition, the tip 113 of the electrode 103 embedded in the doped semiconductor layer 102 is generated based on the enrichment of silver, and the silver content in the tip 113 can be further increased so that the tip 113 forms a conductive core, thereby improving the carrier collection efficiency of the electrode 103.

[0073] In some cases, compared to a doped semiconductor layer with non-gradient doping of doping elements, based on the design that the doping concentration of the doping element in the doped semiconductor layer 102 gradually increases in a direction away from the substrate 100, and the electrode 103 includes a tip 113 embedded in the doped semiconductor layer 102, the contact resistance between the electrode 103 and the doped semiconductor layer 102 can be reduced by about 40%.

[0074] In some examples, the interface resistance at the interface between the electrode 103 and the doped semiconductor layer 102 , ie, the contact resistance, may be less than 1 mΩ·cm², for example, less than or equal to 0.9 mΩ·cm².

[0075] In some embodiments, reference Figure 7 , Figure 7 This is a third cross-sectional schematic diagram of a photovoltaic cell provided in an embodiment of the present disclosure. The photovoltaic cell may further include: a first anti-reflection layer 104 located on the first surface side 110 ; and a second anti-reflection layer 105 located on the second surface side 120 .

[0076] In some cases, continue to refer to Figure 7 A first tunneling layer 1011 and a first doped semiconductor layer 1021 are provided between the first anti-reflection layer 104 and the first surface side 110 , and the electrode 103 is embedded in the first anti-reflection layer 104 to be in contact with the first doped semiconductor layer 1021 .

[0077] In some cases, continue to refer to Figure 7 A second tunneling layer 1012 and a second doped semiconductor layer 1022 are provided between the second anti-reflection layer 105 and the second surface side 120 , and the electrode 103 is embedded in the second anti-reflection layer 105 to be in contact with the second doped semiconductor layer 1022 .

[0078] In some cases, continue to refer to Figure 7 The materials of the first anti-reflection layer 104 and the second anti-reflection layer 105 can be at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0079] In some embodiments, reference Figures 1 to 7 The material of the tunneling layer 101 may include at least one of silicon oxide, aluminum oxide, hafnium oxide or amorphous silicon; the material of the doped semiconductor layer 102 may include polysilicon doped with doping elements.

[0080] In summary, the tunneling layer 101 and the doped semiconductor layer 102 are designed in a coordinated manner. On the one hand, it is beneficial to reduce the thickness of a part of the tunneling layer 101 by means of the pit 111 to enhance the electric field strength formed in the region, thereby prompting more carriers to pass through the tunneling layer 101 at a faster speed, thereby improving the tunneling efficiency of the carriers in the tunneling layer 101; on the other hand, based on the characteristic that the doping concentration of the doping element in the doped semiconductor layer 102 gradually increases, the doping concentration of the doping element in the part of the doped semiconductor layer 102 that is in contact with the tunneling layer 101 is the lowest, so as to match the thickness of the tunneling layer 101 with the pit 111. Even if the thickness of the tunneling layer 101 with the pit 111 is thinned, it is beneficial to reduce the diffusion of the doping element through the tunneling layer 101 into the substrate 100. On the other hand, the risk of defects is reduced, thereby effectively avoiding an increase in the defect state density at the interface where the substrate 100 and the tunneling layer 101 are in contact. On the other hand, the tunneling layer 101 has a plurality of pits 111 on one side close to the doped semiconductor layer 102, and the tunneling layer 101 has a complete and continuous film layer on one side close to the substrate 100 to passivate the substrate 100, which is beneficial to further reduce the defect state density at the interface where the substrate 100 and the tunneling layer 101 are in contact, so as to reduce the recombination loss of carriers. On the other hand, while making the doping concentration of the doping element in the part of the doped semiconductor layer 102 that is in contact with the tunneling layer 101 as low as possible, the average doping concentration of the doping element in the doped semiconductor layer 102 as a whole is still relatively high, so as to reduce the transmission resistance of the doped semiconductor layer 102 as a whole. In this way, based on multi-faceted coordination, it is beneficial to enable more carriers in the substrate 100 to be quickly transmitted to the doped semiconductor layer 102 based on the quantum tunneling effect, thereby helping to improve the carrier collection efficiency of the photovoltaic cell, thereby improving the short-circuit current and open-circuit voltage of the photovoltaic cell, and thus improving its photoelectric conversion efficiency.

[0081] Another embodiment of the present disclosure further provides a method for manufacturing a photovoltaic cell, which is used to prepare the photovoltaic cell provided in the aforementioned embodiment. The method for manufacturing a photovoltaic cell provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are identical or corresponding to the aforementioned embodiments are not described in detail here.

[0082] Combined with reference Figures 1 to 9The method for manufacturing a photovoltaic cell includes: providing a substrate 100, the substrate 100 having a first surface side 110 and a second surface side 120 opposite to each other along a first direction X; forming a tunneling layer 101, the tunneling layer 101 being located on at least one of the first surface side 110 and the second surface side 120, and having a plurality of pits 111 on a side of the tunneling layer 101 away from the substrate 100; forming a doped semiconductor layer 102 doped with a doping element, the doped semiconductor layer 102 being located on a side of the tunneling layer 101 away from the substrate 100, and having the pits 111 between the doped semiconductor layer 102 and the tunneling layer 101, and the doping concentration of the doping element in the doped semiconductor layer 102 gradually increases in a direction from the substrate 100 to the tunneling layer 101.

[0083] In this way, a plurality of pits 111 are formed on one side of the tunneling layer 101 close to the doped semiconductor layer 102, and a doped semiconductor layer 102 with a gradually increasing doping concentration of the doping element is formed along the direction of the substrate 100 pointing to the tunneling layer 101. This is beneficial for more carriers in the substrate 100 to be quickly transmitted to the doped semiconductor layer 102 based on the quantum tunneling effect, and further quickly transmitted to the subsequently formed electrode, thereby helping to improve the carrier collection efficiency of the photovoltaic cell, thereby improving the short-circuit current and open-circuit voltage of the photovoltaic cell, and thus improving its photoelectric conversion efficiency.

[0084] It is worth noting that after forming the tunneling layer 101 having the pit 111 , in the step of forming the doped semiconductor layer 102 , the doped semiconductor layer 102 will not fill the pit 111 , so that the pit 111 is separated between the finally formed doped semiconductor layer 102 and the tunneling layer 101 .

[0085] In some embodiments, the step of forming the tunneling layer may include: referring to Figure 8 , forming an initial tunneling layer 141 on at least one of the first surface side 110 and the second surface side 120; Figure 8 、 Figure 2 and Figure 3 A hydrofluoric acid vapor selective etching process is used to form a plurality of pits 111 on a side of the initial tunneling layer 141 close to the doped semiconductor layer 102 , and the remaining initial tunneling layer 141 serves as the tunneling layer 101 .

[0086] It should be noted that Figure 8 A partial cross-sectional schematic diagram of a photovoltaic cell manufacturing method after forming an initial tunneling layer in another embodiment of the present disclosure. In addition, Figure 8In the example, the initial tunneling layer 141 is formed on both the first surface side 110 and the second surface side 120. In actual applications, the initial tunneling layer can be formed only on the first surface side or only on the second surface side. The initial tunneling layer 141 located on the first surface side 110 is the first initial tunneling layer 1411, and the initial tunneling layer 141 located on the second surface side 120 is the second initial tunneling layer 1412.

[0087] In some cases, the process for forming the initial tunneling layer 141 may include an ALD (Atomic Layer Deposition) process, an LPCVD (Low Pressure Chemical Vapor Deposition) process, or a thermal oxidation process. The ALD and LPCVD processes both deposit an initial tunneling layer 141 on the original first surface 110 and / or second surface 120 , while the thermal oxidation process performs a high-temperature oxidation treatment on the first surface 110 and / or second surface 120 to convert a portion of the substrate 100 surface thickness into the initial tunneling layer 141 .

[0088] In some examples, in the ALD process, dichlorosilane and water may be used as precursors to form the initial tunneling layer 141 at a process temperature of 300° C.

[0089] In some examples, along the first direction X, the thickness of the initial tunneling layer 141 can be 1 nm to 2.0 nm, for example, 1.05 nm, 1.1 nm, 1.15 nm, 1.2 nm, 1.25 nm, 1.3 nm, 1.35 nm, 1.4 nm, 1.45 nm, 1.5 nm, 1.55 nm, 1.6 nm, 1.65 nm, 1.7 nm, 1.75 nm, 1.8 nm, 1.85 nm, 1.9 nm or 1.95 nm, etc.

[0090] In some cases, the substrate 100 is configured to receive incident light and generate photogenerated carriers.

[0091] In some examples, the material of substrate 100 can be an elemental semiconductor material. Optionally, the elemental semiconductor material is composed of a single element, such as silicon or germanium. The elemental semiconductor material can be single crystalline, polycrystalline, amorphous, or microcrystalline (a state that has both single crystalline and amorphous states is referred to as microcrystalline). For example, silicon can be at least one of single crystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. Based on this, the material of initial tunneling layer 141 formed using a thermal oxidation process can be silicon oxide.

[0092] In other examples, the substrate 100 may be made of a compound semiconductor material. Common compound semiconductor materials include, but are not limited to, silicon germanium, silicon carbide, gallium arsenide, indium gallium, perovskite, cadmium telluride, or copper indium selenide. In yet other examples, the substrate 100 may be a sapphire substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.

[0093] In some cases, during the hydrofluoric acid vapor selective etching process, the initial tunneling layer 141 grown by a deposition process, such as an ALD process, may be amorphous silicon oxide, in which oxygen dangling bonds (O - ) and silicon dangling bonds (Si + ), thereby forming a high-activity etching site in the tunneling layer 101. Based on the etching of the high-activity etching site by hydrofluoric acid vapor, a plurality of pits 111 are formed on the side of the initial tunneling layer 141 close to the doped semiconductor layer 102. The plurality of pits 111 finally formed can be irregularly arranged in the tunneling layer 101.

[0094] In addition, during the process of using the hydrofluoric acid vapor selective etching process, the semi-finished photovoltaic cell with the initial tunneling layer 141 is placed in a reaction chamber, and the hydrofluoric acid vapor is introduced into the reaction chamber in multiple cycles. By increasing the pulse time of the hydrofluoric acid vapor in the first and second cycles, the etching reaction between the hydrofluoric acid vapor and the initial tunneling layer 141 can be prolonged in the first and second cycles, thereby forming more initial pits in the initial tunneling layer 141 and increasing the density of the initial pits in the initial tunneling layer 141. In subsequent cycles, the initial pits can be gradually etched and expanded with the help of the hydrofluoric acid vapor to finally form the tunneling layer 101 having the pits 111. In some cases, during the step of performing the hydrofluoric acid vapor selective etching process, the concentration of the hydrofluoric acid can be 50% to 80%, for example, 52%, 55%, 57%, 60%, 63%, 65%, 68%, 70%, 72%, 75% or 77%, etc.

[0095] It is noteworthy that the concentration of hydrofluoric acid designed in the hydrofluoric acid vapor selective etching process is higher than the concentration of hydrofluoric acid in the hydrofluoric acid etchant conventionally used for etching the film layer, that is, the concentration of hydrofluoric acid in the hydrofluoric acid vapor is higher. In this way, on the one hand, the higher concentration of hydrofluoric acid enhances the etching selectivity of the interface between the tunneling layer 101 and the doped semiconductor layer 102, which is beneficial to retain the integrity of the tunneling layer 101 in the area not etched by the hydrofluoric acid vapor, so as to ensure that the tunneling layer 101 has a good passivation effect; on the other hand, the hydrogen radicals in the hydrofluoric acid vapor can in situ passivate the dangling bonds on the surface of the pit 111 to reduce the defect state density on the surface of the pit 111; on the other hand, a lower concentration of hydrofluoric acid, such as a hydrofluoric acid with a concentration of less than 40%, is prone to produce reaction byproducts, such as fluorosilicic acid. In the preparation method of the photovoltaic cell provided in another embodiment of the present disclosure, a higher concentration of hydrofluoric acid is used, which is beneficial to reduce the risk of producing reaction byproducts, thereby helping to avoid the risk of excessive reaction byproducts accumulating at the pit 111 and affecting the carrier tunneling efficiency.

[0096] In some cases, the processing time of the hydrofluoric acid vapor selective etching process can be 30s to 60s, for example, 32s, 35s, 37s, 40s, 43s, 45s, 48s, 50s, 52s, 55s or 57s, etc. In this way, it is beneficial to control the depth of the finally formed pit 111 in the first direction X by controlling the processing time of the hydrofluoric acid vapor selective etching process, so as to prevent the pit 111 from penetrating the tunnel layer 101 along the first direction X to expose the substrate 100.

[0097] In some embodiments, reference Figure 9 , Figure 9 A partial cross-sectional schematic diagram after the initial semiconductor layer is formed in the manufacturing method of the photovoltaic cell provided in another embodiment of the present disclosure, the step of forming the doped semiconductor layer 102 may include: providing a reaction chamber; in the reaction chamber, using a deposition process to deposit the initial semiconductor layer 112 on the side of the tunneling layer 101 away from the substrate 100, and in the step of performing the deposition process, introducing a doping source gas containing doping elements into the reaction chamber so that the initial semiconductor layer 112 is doped with the doping elements to form the doped semiconductor layer 102; wherein, as the deposition process proceeds, the flow rate of the doping source gas introduced into the reaction chamber is gradually increased, so that the doping concentration of the doping element in the doped semiconductor layer 102 gradually increases in the direction from the substrate 100 to the tunneling layer 101.

[0098] The following describes the process of forming the doped semiconductor layer 102 in detail, taking the example of forming the doped semiconductor layer 102 including forming the first doped semiconductor layer 1021 and the second doped semiconductor layer 1022. Thus, the initial semiconductor layer 112 includes the initial first semiconductor layer 1121 and the initial second semiconductor layer 1122.

[0099] Continue to refer Figure 9 , a PECVD process is used to deposit an initial second semiconductor layer 1122 on the side of the second tunneling layer 1012 away from the second surface side 120; and in the step of the deposition process, combined with reference Figure 9 and Figure 1 , a doping source gas containing a second doping element is introduced into the reaction chamber so that the second doping element is doped into the initial second semiconductor layer 1122 , thereby converting the initial second semiconductor layer 1122 into a second doped semiconductor layer 1022 .

[0100] In some cases, the doping source gas containing the second doping element can be phosphine, wherein as the deposition process progresses, the gas flow rate of phosphine introduced into the reaction chamber can be gradually increased from 10 sccm to 100 sccm, so that the doping concentration of the second doping element in the second doped semiconductor layer 1022 finally formed gradually increases in the direction along the substrate 100 pointing to the second tunneling layer 1012.

[0101] In some cases, the material of the initial second semiconductor layer 1122 can be amorphous silicon or polycrystalline silicon. In some cases, along the first direction X, the thickness of the initial second semiconductor layer 1122 can be 150 nm.

[0102] In one example, when the material of the initial second semiconductor layer 1122 is amorphous silicon, after the step of introducing a doping source gas containing the second doping element into the reaction chamber is completed, the initial second semiconductor layer 1122 doped with the second doping element is further subjected to an annealing and crystallization treatment to convert the amorphous silicon into polycrystalline silicon, thereby converting the initial second semiconductor layer 1122 into the second doped semiconductor layer 1022. The process temperature of the annealing and crystallization treatment can be 850° C. and the process time of the annealing and crystallization treatment can be 30 minutes. During the annealing and crystallization treatment, nitrogen gas is introduced into the reaction chamber to create an inert atmosphere.

[0103] Continue to refer Figure 9 , a PECVD process is used to deposit an initial first semiconductor layer 1121 on the side of the first tunneling layer 1011 away from the first surface side 110; and in the step of the deposition process, combined with reference Figure 9 and Figure 1, a doping source gas containing a first doping element is introduced into the reaction chamber so that the first doping element is doped into the initial first semiconductor layer 1121 to convert the initial first semiconductor layer 1121 into a first doped semiconductor layer 1021 .

[0104] In some cases, the doping source gas containing the first doping element can be borane, wherein, as the deposition process progresses, the gas flow rate of borane introduced into the reaction chamber can be gradually increased from 5 sccm to 50 sccm, so that the doping concentration of the first doping element in the first doped semiconductor layer 1021 finally formed gradually increases in the direction along the substrate 100 pointing to the tunneling layer 101.

[0105] In some cases, the material of the initial first semiconductor layer 1121 can be amorphous silicon or polycrystalline silicon. In some cases, along the first direction X, the thickness of the initial first semiconductor layer 1121 can be 80 nm.

[0106] In one example, when the material of the initial first semiconductor layer 1121 is amorphous silicon, after the step of introducing a doping source gas containing a first doping element into the reaction chamber is completed, the initial first semiconductor layer 1121 doped with the first doping element is further subjected to an annealing and crystallization treatment to convert the amorphous silicon into polycrystalline silicon, thereby converting the initial first semiconductor layer 1121 into the first doped semiconductor layer 1021. The process temperature of the annealing and crystallization treatment can be 850° C. and the process duration of the annealing and crystallization treatment can be 30 minutes. During the annealing and crystallization treatment step, nitrogen gas is introduced into the reaction chamber to create an inert atmosphere.

[0107] It should be noted that in actual applications, if the material of the initial first semiconductor layer and the material of the initial second semiconductor layer are both amorphous silicon, after forming the initial first semiconductor layer doped with the first doping element and the initial second semiconductor layer doped with the second doping element, an annealing crystallization treatment can be performed uniformly to simultaneously convert the initial first semiconductor layer into a first doped semiconductor layer and the initial second semiconductor layer into a second doped semiconductor layer.

[0108] In some embodiments, in conjunction with reference Figures 4 to 6 After forming the doped semiconductor layer 102 , the method for manufacturing a photovoltaic cell may further include: forming an electrode 103 , where the electrode 103 is at least located on a side of the doped semiconductor layer 102 away from the substrate 100 .

[0109] In some cases, in the step of forming electrode 103 , tip 113 embedded in doped semiconductor layer 102 is formed.

[0110] In some cases, the step of forming the electrode 103 may include: printing a paste on a side of the doped semiconductor layer 102 away from the substrate 100 , and sintering the paste to form the electrode 103 having the tip 113 .

[0111] In some examples, the paste is a silver-aluminum paste, so that during the sintering process, an Ag-Al-Si eutectic, rather than an Ag-Si eutectic, is formed between the silver-aluminum paste and the doped semiconductor layer 102. It is worth noting that the eutectic point of Ag-Si is approximately 835°C, and the eutectic point of Ag-Al-Si is approximately 600°C. Therefore, the addition of aluminum to the silver-aluminum paste can reduce the process temperature of the sintering process, that is, the process temperature of the sintering process can be reduced to 600°C. Compared with the process temperature of more than 700°C in conventional sintering processes, the method for preparing a photovoltaic cell provided in another embodiment of the present disclosure is conducive to lowering the temperature of the sintering process, thereby helping to reduce thermal damage to the photovoltaic cell during the manufacturing process and reducing the risk of warping of the photovoltaic cell. Therefore, the method for preparing a photovoltaic cell provided in another embodiment of the present disclosure can accommodate ultra-thin silicon wafers of 130μm.

[0112] It is worth noting that in the sintering step, at a process temperature of 600°C, the aluminum in the silver-aluminum paste preferentially reacts with the silicon in the doped semiconductor layer 102 to form an Al-Si liquid phase (the eutectic point of Al-Si is approximately 577°C), and the local corrosion of the doped semiconductor layer 102 promotes the formation of the initial tip. Furthermore, the silver in the silver-aluminum paste migrates in the Al-Si liquid phase and is eventually enriched at the initial tip, thereby ultimately forming a tip 113 embedded in the doped semiconductor layer 102.

[0113] In some examples, the ratio of the silver content to the aluminum content in the silver-aluminum paste may be 9.

[0114] In some embodiments, reference Figure 7 After forming the doped semiconductor layer 102 and before forming the electrode 103, the method for manufacturing the photovoltaic cell may further include: forming a first anti-reflection layer 104 on a side of the first doped semiconductor layer 1021 away from the first tunneling layer 1011; forming a second anti-reflection layer 105 on a side of the second doped semiconductor layer 1022 away from the second tunneling layer 1012; in the subsequent step of forming the electrode 103, the electrode 103 located on the first surface side 110 will be embedded in the first anti-reflection layer 104 to contact and connect with the first doped semiconductor layer 1021, and the electrode 103 located on the second surface side 120 will be embedded in the second anti-reflection layer 105 to contact and connect with the second doped semiconductor layer 1022.

[0115] Another embodiment of the present disclosure provides a laminated cell, comprising the photovoltaic cell provided in the preceding embodiments, or a photovoltaic cell formed by the photovoltaic cell manufacturing method provided in the preceding embodiments. The laminated cell provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that parts identical or corresponding to the preceding embodiments will not be repeated here.

[0116] refer to Figure 10 , Figure 10 A partial cross-sectional schematic diagram of a laminated solar cell provided in yet another embodiment of the present disclosure includes: a bottom cell 106, which is the photovoltaic cell provided in the aforementioned embodiment, or a photovoltaic cell formed by the photovoltaic cell manufacturing method provided in the aforementioned embodiment; and a top cell 107, which is located on one side of the bottom cell 106.

[0117] In some embodiments, the top cell 107 may be one of a perovskite solar cell, a donor-acceptor cell, a cadmium telluride (CdTe) photovoltaic cell, a copper indium gallium selenide (CIGS) photovoltaic cell, or a gallium arsenide (GaAs) photovoltaic cell.

[0118] In some embodiments, the top cell 107 may include: a stacked first transmission layer, a perovskite substrate, a second transmission layer, a transparent conductive layer, and an anti-reflection layer, wherein the first transmission layer faces the bottom cell 106 .

[0119] In some examples, the first transport layer may be one of an electron transport layer and a hole transport layer, and the second transport layer may be the other of the electron transport layer and the hole transport layer.

[0120] In some embodiments, the band gap width of the top cell 107 is wider than that of the bottom cell 106. Therefore, stacking the top cell 107 on the bottom cell 106 can enable the stacked cell to have a wider spectral response range, thereby maximizing the use of solar energy and improving the efficiency of the photovoltaic cell.

[0121] In some embodiments, the back-contact stacked cell may further include an intermediate connecting layer (not shown in the figure), which is connected between the bottom cell 106 and the top cell 107 .

[0122] In some cases, the intermediate connecting layer is typically a tunnel junction or a very thin metal or transparent electrode composite layer. Alternatively, the intermediate connecting layer can be a transparent conductive oxide, which has excellent optoelectronic properties, high photon transmittance and high conductivity, thereby maintaining good ohmic contact between the top cell 107 and the bottom cell 106.

[0123] In other cases, the back fine grid, back main grid, front fine grid and front main grid in the photovoltaic cell serving as the bottom cell 106 can also be used as an intermediate connection layer to achieve electrical connection with the top cell 107. Figures 4 to 7 At least one of the back fine grid, the back main grid, the front fine grid and the front main grid can be regarded as the electrode 103.

[0124] Another embodiment of the present disclosure provides a photovoltaic assembly, comprising a plurality of photovoltaic cells as provided in the preceding embodiments, or a plurality of photovoltaic cells formed by the methods for manufacturing photovoltaic cells as provided in the preceding embodiments, or a plurality of connected laminated cells as provided in the preceding embodiments, the photovoltaic assembly being configured to convert received light energy into electrical energy. It should be noted that for portions identical or corresponding to the preceding embodiments, reference may be made to the corresponding descriptions of the preceding embodiments and will not be repeated below.

[0125] Combined with reference Figure 11 、 Figure 12 as well as Figures 1 to 10 The photovoltaic module includes: a cell string, which is formed by electrically connecting multiple photovoltaic cells 40 provided by the aforementioned embodiments, or electrically connecting multiple photovoltaic cells 40 formed by the photovoltaic cell manufacturing method provided by the aforementioned embodiments, or electrically connecting multiple laminated cells provided by the aforementioned embodiments; an encapsulation film 41, which is used to cover the surface of the cell string; and a cover plate 42, which is used to cover the surface of the encapsulation film 41 facing away from the cell string.

[0126] in, Figure 11 A partial three-dimensional schematic diagram of a cell string in a photovoltaic module provided by yet another embodiment of the present disclosure; Figure 12 A partial cross-sectional schematic diagram of a photovoltaic assembly provided in yet another embodiment of the present disclosure.

[0127] In some embodiments, the photovoltaic cell 40 is electrically connected in a whole cell or multiple slices to form multiple cell strings, and the multiple cell strings are electrically connected in series and / or parallel. The photovoltaic cell 40 can be a whole cell or a sliced ​​cell. A sliced ​​cell refers to a cell formed by cutting a complete whole cell.

[0128] In some embodiments, in conjunction with reference Figure 11 and Figure 12 , multiple photovoltaic cells 40 can be electrically connected through conductive tapes 43. Figure 11 and Figure 12Only one positional relationship between the photovoltaic cells 40 is illustrated, i.e., the gridlines of the photovoltaic cells 40 having the same polarity are arranged in the same direction, or the gridlines of each photovoltaic cell 40 having the positive polarity are arranged toward the same side, so that the conductive ribbons 43 connect different sides of two adjacent photovoltaic cells 40. In other embodiments, the photovoltaic cells may also have electrodes of different polarities facing the same side, i.e., the electrodes of multiple adjacent photovoltaic cells may be arranged in the order of first polarity, second polarity, and first polarity, respectively, so that the conductive ribbons connect two adjacent photovoltaic cells on the same side.

[0129] In some embodiments, the encapsulation film 41 includes a first encapsulation layer and a second encapsulation layer, wherein the first encapsulation layer covers one of the front and back sides of the photovoltaic cell 40, and the second encapsulation layer covers the other of the front and back sides of the photovoltaic cell 40. Specifically, at least one of the first encapsulation layer or the second encapsulation layer can be an organic encapsulation film such as polyvinyl butyral (PVB) film, ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene co-elastomer (POE) film, or polyethylene terephthalate (PET) film, or at least one of the first encapsulation layer or the second encapsulation layer can also be an EP film, EPE film, or PVP film. Among them, EP film refers to a co-extruded film composed of stacked EVA film and POE film, EPE film refers to a co-extruded film formed by stacking EVA film + POE film + EVA film in sequence, and PVP film refers to a co-extruded film formed by stacking POE film + EVA film + POE film. Co-extruded films can be prepared by sequentially extruding one or more raw materials onto another already manufactured film during the film processing process, or by bonding different types of already manufactured films together.

[0130] In some cases, there is a boundary line between the first encapsulation layer and the second encapsulation layer before lamination. After the lamination process, the photovoltaic module is formed and there is no longer the concept of the first encapsulation layer and the second encapsulation layer, that is, the first encapsulation layer and the second encapsulation layer have formed an integral encapsulation film 41.

[0131] In some embodiments, the cover plate 42 may be a light-transmitting cover plate such as a glass cover plate or a plastic cover plate. Specifically, the surface of the cover plate 42 facing the encapsulation film 41 may have a concave-convex surface or a velvet surface including multiple raised structures, thereby increasing the utilization of incident light. The cover plate 42 includes a first cover plate and a second cover plate. The first cover plate faces the first encapsulation layer, and the second cover plate faces the second encapsulation layer.

[0132] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A photovoltaic cell, characterized in that: include: a substrate having a first surface side and a second surface side opposite to each other in a first direction; a tunneling layer on at least one of the first surface side and the second surface side; a doped semiconductor layer doped with a doping element, located on a side of the tunneling layer away from the substrate; Wherein, a side of the tunneling layer close to the doped semiconductor layer has a plurality of pits; In a direction from the substrate to the tunneling layer, the doping concentration of the doping element in the doped semiconductor layer gradually increases.

2. The photovoltaic cell according to claim 1, characterized in that Along the first direction, a ratio of the depth of the pit to the thickness of the tunnel layer is 20% to 80%.

3. The photovoltaic cell according to claim 1 or 2, characterized in that: The orthographic projection of the pit on the substrate is a circle, and the diameter of the circle is 5 nm to 10 nm; and / or the arrangement density of the pit in the tunneling layer is 1×10 9 pieces / cm 2 ~1×10 11 pieces / cm 2 .

4. The photovoltaic cell according to claim 1, characterized in that The tunneling layer includes a bottom facing the pit along the first direction, and the electric field strength formed by the bottom is 10 5 V / m~10 8 V / m.

5. The photovoltaic cell according to claim 1, characterized in that The tunneling layer includes a bottom facing the pit along the first direction, the bottom covers at least one of the first surface side and the second surface side, and a thickness of the bottom along the first direction is 0.5 nm to 1.0 nm.

6. The photovoltaic cell according to claim 1, characterized in that The tunneling layer includes: a first tunneling layer located on the first surface side, and a second tunneling layer located on the second surface side; The doped semiconductor layer includes: a first doped semiconductor layer located on a side of the first tunnel layer away from the substrate, and a second doped semiconductor layer located on a side of the second tunnel layer away from the substrate; In which, the doping elements include a first doping element and a second doping element with different conductivity types, the first doping element is doped in the first doping semiconductor layer, and the second doping element is doped in the second doping semiconductor layer; along the direction from the substrate to the first tunneling layer, the doping concentration of the first doping element in the first doping semiconductor layer gradually increases; along the direction from the substrate to the second tunneling layer, the doping concentration of the second doping element in the second doping semiconductor layer gradually increases.

7. The photovoltaic cell according to claim 6, characterized in that Along the first direction, the thickness of the first doped semiconductor layer is less than the thickness of the second doped semiconductor layer.

8. The photovoltaic cell according to claim 1 or 6, characterized in that: Along the direction from the substrate to the tunneling layer, the doping concentration of the doping element in the doped semiconductor layer is from 1×10 19 atom / cm 3 Gradually increase to 1×10 21 atom / cm 3 .

9. The photovoltaic cell according to claim 1, characterized in that Also includes: The electrode is located at least on a side of the doped semiconductor layer away from the substrate, and the electrode includes a tip embedded in the doped semiconductor layer.

10. A method for manufacturing a photovoltaic cell, characterized in that: include: providing a substrate having a first surface side and a second surface side opposite to each other in a first direction; forming a tunneling layer, wherein the tunneling layer is located on at least one of the first surface side and the second surface side, and a side of the tunneling layer away from the substrate has a plurality of pits; A doped semiconductor layer doped with a doping element is formed, the doped semiconductor layer is located on a side of the tunneling layer away from the substrate, and the pit is separated from the doped semiconductor layer and the tunneling layer. The doping concentration of the doping element in the doped semiconductor layer gradually increases in a direction from the substrate to the tunneling layer.

11. The method for manufacturing a photovoltaic cell according to claim 10, wherein: The step of forming the tunneling layer includes: forming an initial tunneling layer on at least one of the first surface side and the second surface side; A hydrofluoric acid vapor selective etching process is adopted to form a plurality of the pits on a side of the initial tunneling layer close to the doped semiconductor layer, and the remaining initial tunneling layer serves as the tunneling layer.

12. The method for manufacturing a photovoltaic cell according to claim 11, wherein: In the step of performing the hydrofluoric acid vapor selective etching process, the concentration of the hydrofluoric acid is 50% to 80%; and / or the processing time of the hydrofluoric acid vapor selective etching process is 30s to 60s.

13. The method for manufacturing a photovoltaic cell according to claim 10, wherein: The step of forming the doped semiconductor layer comprises: providing a reaction chamber; In the reaction chamber, a deposition process is used to deposit an initial semiconductor layer on a side of the tunnel layer away from the substrate, and during the deposition process, a doping source gas containing the doping element is introduced into the reaction chamber to dope the initial semiconductor layer with the doping element to form the doped semiconductor layer; As the deposition process proceeds, the flow rate of the doping source gas introduced into the reaction chamber is gradually increased, so that the doping concentration of the doping element in the doped semiconductor layer gradually increases in the direction from the substrate to the tunneling layer.

14. A stacked battery, characterized in that: include: A bottom cell, wherein the bottom cell is the photovoltaic cell according to any one of claims 1 to 9, or a photovoltaic cell formed by the method for manufacturing a photovoltaic cell according to any one of claims 10 to 13; A top cell is located on one side of the bottom cell.

15. A photovoltaic module, characterized in that: include: A cell string, formed by electrically connecting a plurality of photovoltaic cells according to any one of claims 1 to 9, or by electrically connecting a plurality of photovoltaic cells formed by the method for manufacturing a photovoltaic cell according to any one of claims 10 to 13, or by electrically connecting a plurality of stacked cells according to claim 14; A packaging film, used to cover the surface of the battery string; A cover plate is used to cover the surface of the packaging film facing away from the battery string.

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