Solar cell and photovoltaic module

Abstract

The invention provides a solar cell and a photovoltaic module, and the solar cell comprises a semiconductor substrate which is provided with a first surface and a second surface which are opposite to each other; the doped semiconductor layer is arranged on the first surface of the semiconductor substrate; the dielectric layer is arranged on one side, deviating from the semiconductor substrate, of the doped semiconductor layer; the dielectric layer comprises a plurality of openings, the openings expose a partial region of the doped semiconductor layer, and pores are formed between the dielectric layer at the edges of the openings and the doped semiconductor layer below the dielectric layer; the electrode is arranged on the side, away from the semiconductor substrate, of the dielectric layer, and the electrode penetrates through the opening in the dielectric layer to be electrically connected with the doped semiconductor layer. According to the invention, the risk of film explosion in the laser mold opening process is reduced, and the passivation effect of the solar cell is ensured.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Solar cells are increasingly being used as a new energy alternative. Photovoltaic solar cells convert sunlight into electricity. Specifically, they utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, facilitating efficient use of the electrical energy.

[0003] The traditional high-temperature metallization process involves sintering a high-temperature silver paste on a dielectric layer such as silicon nitride. The paste can penetrate the silicon nitride interface and form good metal contact with the underlying doped semiconductor layer. However, due to the high cost of high-temperature silver paste, the industry has been actively researching other metallization processes in recent years. Summary of the Invention

[0004] The present application provides a solar cell and a photovoltaic module, which are used to reduce the cost of the metallization process, alleviate or avoid the film explosion problem during laser mold opening, reduce the damage caused by laser mold opening, and effectively ensure the passivation effect of the solar cell.

[0005] According to one aspect of the present application, there is provided a solar cell, comprising:

[0006] a semiconductor substrate having a first side and a second side opposite to each other;

[0007] a doped semiconductor layer, disposed on the first surface of the semiconductor substrate;

[0008] a dielectric layer disposed on a side of the doped semiconductor layer facing away from the semiconductor substrate; the dielectric layer comprising a plurality of openings, the openings exposing a portion of the doped semiconductor layer, and a gap formed between the dielectric layer at edges of the openings and the doped semiconductor layer below;

[0009] The electrode is arranged on a side of the dielectric layer away from the semiconductor substrate, and the electrode passes through an opening on the dielectric layer and is electrically connected to the doped semiconductor layer.

[0010] This application adopts the above-mentioned technical solution. Compared with directly forming electrodes through a high-temperature sintering process, this application can form electrodes at the opening using a low-temperature metallization process, thereby reducing the cost of the metallization process. In addition, a pore is formed between the dielectric layer and the underlying doped semiconductor layer at the edge of the opening. The pore provides space for hydrogen to escape during the laser mold opening process, thereby alleviating or avoiding the film explosion of the dielectric layer in the non-opening area caused by the laser mold opening, facilitating the precise control of the size of the opening area, and reducing the damage caused by the laser mold opening to the doped semiconductor layer in the non-opening area, thereby effectively ensuring the passivation effect of the solar cell.

[0011] In some embodiments, the length of the pores distributed from the edge of the opening of the dielectric layer along a direction parallel to the semiconductor substrate is greater than 0 μm and less than or equal to 5 μm.

[0012] Considering that if the length of the distributed pores is too large, for example, 10μm, 20μm or 30μm or larger, the dielectric layer will easily break and fall off, thereby affecting the passivation effect of the solar cell, thereby increasing the recombination loss of the doped semiconductor layer, the embodiment of the present application has a length of the distributed pores of less than or equal to 5μm starting from the edge of the opening of the dielectric layer along a direction parallel to the semiconductor substrate.

[0013] Furthermore, if the length of the distributed pores is too small, hydrogen will escape during the laser mold opening process, and insufficient space will be provided for hydrogen escape, resulting in the risk of film explosion. Therefore, in some examples, the length of the distributed pores is greater than or equal to 0.01 μm starting from the edge of the opening in the dielectric layer in a direction parallel to the semiconductor substrate.

[0014] The above-mentioned length range of distributed pores provided in the present application can provide a reasonable space for the escape of hydrogen in the dielectric layer during the laser mold opening process, which can effectively alleviate or avoid the film explosion of the dielectric layer in the non-opening area caused by laser mold opening, which is conducive to accurately controlling the size of the opening area and reducing the damage caused by laser mold opening to the doped semiconductor layer in the non-opening area. It can also prevent the dielectric layer from being broken and falling off due to the excessive length of the distributed pores, which is conducive to avoiding the breakage and falling off of the dielectric layer affecting the passivation effect of the solar cell, thereby reducing the damage caused by laser mold opening and ensuring the passivation effect of the solar cell.

[0015] In some embodiments, a portion of the dielectric layer adjacent to the opening is warped in a direction away from the doped semiconductor layer.

[0016] By adopting the above technical solution, since the portion of the dielectric layer close to the opening is warped in the direction away from the doped semiconductor layer, a space is formed between the dielectric layer and the underlying doped semiconductor layer in the portion of the dielectric layer close to the opening, which can further provide space for the escape of hydrogen generated by the dielectric layer under the action of the laser during the laser mold opening process, thereby helping to alleviate or avoid film explosion, reduce the damage caused by laser mold opening, avoid the dielectric layer from cracking and falling off, and affect the passivation effect of the solar cell, thereby ensuring the passivation effect of the solar cell.

[0017] In some embodiments, a portion of the dielectric layer adjacent to the opening is warped in a direction away from the doped semiconductor layer at an angle greater than 0° and less than or equal to 20°.

[0018] Using the above technical solution, considering that if the angle of warping of the portion of the dielectric layer near the opening away from the doped semiconductor layer is too large, for example, 30°, 40°, or other larger angles, the dielectric layer is easily broken, affecting the passivation effect of the solar cell and causing recombination loss of the doped semiconductor layer, the angle of warping of the portion of the dielectric layer near the opening away from the doped semiconductor layer in the embodiment of the present application is less than or equal to 20°.

[0019] Furthermore, considering that if the angle at which the portion of the dielectric layer close to the opening is warped away from the doped semiconductor layer is too small, it will not be conducive to providing space for the escape of hydrogen during the laser mold opening process, and will cause the dielectric layer in the non-laser opening area to have the risk of film explosion, therefore, in some examples, the angle at which the portion of the dielectric layer close to the opening is warped away from the doped semiconductor layer is greater than or equal to 0.001°.

[0020] The angle range in which the portion of the dielectric layer close to the opening provided in the embodiment of the present application is warped in a direction away from the doped semiconductor layer can provide a reasonable space for hydrogen in the dielectric layer to escape during the laser mold opening process, can alleviate or avoid the dielectric layer explosion in the non-opening area caused by the laser mold opening, and can reduce the damage caused by the laser mold opening to the doped semiconductor layer in the non-opening area, and can prevent the dielectric layer from cracking and falling off due to excessive warping angles. Therefore, the above-mentioned angle range can ensure the passivation effect of the solar cell, reduce the damage caused by the laser mold opening, and avoid the rupture of the dielectric layer affecting the passivation effect of the solar cell.

[0021] In some embodiments, the portion of the doped semiconductor layer exposed in the opening on a side facing away from the semiconductor substrate includes a plurality of holes.

[0022] The above technical solution helps increase the surface roughness of the doped semiconductor layer at the opening, thereby increasing the contact area between the doped semiconductor layer exposed at the opening and the electrode. This helps to increase the bonding force between the electrode and the doped semiconductor layer, strengthen the connection strength between the two, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural reliability of the solar cell. In addition, because the contact area between the portion of the doped semiconductor layer exposed at the opening and the electrode is increased, the contact resistance between the doped semiconductor layer and the electrode can be reduced, improving contact performance and further increasing the photoelectric conversion efficiency of the solar cell.

[0023] In some embodiments, a ring-shaped protrusion is formed on the edge of the hole.

[0024] By adopting the above technical solution, the part of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate can have an uneven surface feature, which is beneficial to increase the surface roughness and specific surface area of ​​the doped semiconductor layer at the opening. Based on this, since the electrode of the solar cell provided by the present application is formed on the doped semiconductor layer with an uneven surface, the contact area between the part of the doped semiconductor layer exposed in the opening and the electrode is increased, which is beneficial to increase the bonding force between the electrode and the doped semiconductor layer, enhance the connection strength between the two, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural reliability of the solar cell. In addition, since the contact area between the part of the doped semiconductor layer exposed in the opening and the electrode is increased, the contact resistance between the doped semiconductor layer and the electrode can be reduced, the contact performance can be improved, and the photoelectric conversion efficiency of the solar cell can be further improved.

[0025] In some embodiments, a portion of the doped semiconductor layer exposed in the opening further has a plurality of discontinuous protrusions formed on a side facing away from the semiconductor substrate.

[0026] By adopting the above technical solution, the discontinuous protrusions are beneficial to increasing the surface roughness of the doped semiconductor layer located at the opening, thereby further increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0027] In some embodiments, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon disposed on a side of the doped polysilicon layer exposed in the opening away from the semiconductor substrate.

[0028] With the above technical solution, after the dielectric layer is opened, an etching solution is used to remove any residue. Because amorphous silicon has good corrosion resistance, amorphous silicon is distributed on the side of the doped semiconductor layer exposed in the opening, facing away from the semiconductor substrate. This protects the underlying doped polysilicon layer, preventing it from being severely damaged by the etching solution and potentially causing serious recombination. Furthermore, amorphous silicon has a good passivation effect, which helps reduce recombination caused by direct contact between the doped polysilicon layer and the electrode.

[0029] In some embodiments, the pores include at least one metallic material in the electrode.

[0030] The present application adopts the above-mentioned solution, and the pores include at least one metal material in the electrode, which can increase the contact area between the electrode and the doped semiconductor layer. In this way, the contact resistance between the electrode and the doped semiconductor layer can be reduced, and the bonding force between the electrode and the doped semiconductor layer can be increased, thereby reducing the risk of the electrode detaching from the doped semiconductor layer and improving the structural reliability of the solar cell.

[0031] In some embodiments, the metal material includes one or more of nickel, copper, silver, or tin.

[0032] The present application adopts the above-mentioned solution, and these metal materials are filled into the pores, thereby increasing the contact area between the electrode and the doped semiconductor layer, reducing the contact resistance between the electrode and the doped semiconductor layer, and increasing the bonding force between the electrode and the doped semiconductor layer, thereby enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell. In addition, these metals can also block deep energy level impurities or other metals from diffusing into the doped semiconductor layer and the semiconductor substrate, thereby reducing the recombination of the doped semiconductor layer and the semiconductor substrate, and reducing the recombination loss.

[0033] In some embodiments, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon located at the edge of the opening of the dielectric layer, below the dielectric layer, and arranged on a side of the doped polysilicon layer away from the semiconductor substrate.

[0034] The present application adopts the above-mentioned technical solution. After the dielectric layer is opened, it is necessary to use an etching liquid to etch and remove the residue. When the etching liquid is used to etch and remove the residue, the edge of the opening of the dielectric layer and the portion located below the dielectric layer will also be side-etched. In this case, since amorphous silicon has good corrosion resistance, amorphous silicon is distributed at the edge of the opening of the dielectric layer and below the dielectric layer, on the side of the doped polysilicon layer facing away from the semiconductor substrate. In this way, the amorphous silicon can protect the doped polysilicon layer below it, preventing the doped polysilicon layer below the amorphous silicon from being severely damaged by the etching liquid, thereby causing serious recombination. In addition, amorphous silicon has a good passivation effect, which is beneficial to reducing the recombination loss caused by direct contact between the doped polysilicon layer and the electrode.

[0035] In some embodiments, the length of the amorphous silicon distributed from the edge of the opening of the dielectric layer along a direction parallel to the semiconductor substrate is greater than 0 μm and less than or equal to 6 μm.

[0036] Considering that if the length range of the amorphous silicon is too large, since the lateral transmission resistance of amorphous silicon is larger than that of polycrystalline silicon, it is not conducive to the lateral transmission of carriers, which will reduce the photoelectric conversion efficiency of the solar cell. In addition, considering that if the length range of the amorphous silicon is too large, a large amount of heat will be required when forming an opening on the dielectric layer, and the large amount of heat will cause excessive damage to the doped semiconductor layer when forming the opening in the dielectric layer, resulting in poor passivation effect of the doped semiconductor layer. Therefore, in this application, the length of the amorphous silicon distributed from the edge of the opening of the dielectric layer in a direction parallel to the semiconductor substrate is less than or equal to 6μm.

[0037] Furthermore, considering that if the length range of the distributed amorphous silicon is too small, in the case of severe side etching, the amorphous silicon cannot effectively prevent corrosion, and the passivation effect is not obvious, therefore in some examples, the length of the distributed amorphous silicon is greater than or equal to 0.001 μm from the edge of the opening of the dielectric layer along a direction parallel to the semiconductor substrate.

[0038] In some embodiments, starting from the edge of the opening of the dielectric layer and in a direction parallel to the semiconductor substrate, a length where the amorphous silicon is distributed is greater than a length where the pores are distributed.

[0039] The present application adopts the above-mentioned technical solution. After the dielectric layer is opened, it is necessary to use an etching liquid to remove the residue. During the process of using the etching liquid to remove the residue, the etching liquid is more likely to remain in the pores and is not easy to flow out. In order to prevent the etching liquid from corroding the doped polysilicon in the pores and causing damage to the doped polysilicon, in some embodiments of the present application, amorphous silicon is formed on the side of the doped polysilicon layer away from the semiconductor substrate at the edge of the opening of the dielectric layer and below the dielectric layer, and the length of the amorphous silicon is greater than the length of the pores.

[0040] In some embodiments, the portion of the doped semiconductor layer exposed in the opening has a first surface roughness on a side facing away from the semiconductor substrate, and the portion of the doped semiconductor layer not exposed in the opening has a second surface roughness on a side facing away from the semiconductor substrate, and the first surface roughness is greater than the second surface roughness.

[0041] The present application adopts the above-mentioned technical solution, and the surface roughness of the part of the doped semiconductor layer exposed in the opening is relatively large, which can increase the contact area between the doped semiconductor layer and the electrode, which is beneficial to reducing the contact resistance between the electrode and the doped semiconductor layer, and is beneficial to increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell. The roughness of the second surface is relatively small, which can ensure the film formation quality of the formed doped semiconductor layer.

[0042] In some embodiments, a portion of the doped semiconductor layer exposed in the opening has a first thickness, and a portion of the doped semiconductor layer not exposed in the opening has a second thickness, wherein the first thickness is less than the second thickness.

[0043] The present application adopts the above-mentioned technical solution, and the thickness of the doped semiconductor layer at the opening is less than the thickness at the non-opening, so that the transmission distance of the carriers from the semiconductor substrate to the electrode is reduced, and the longitudinal transmission resistance is reduced. Especially for non-sintered electrodes, the thickness of the doped semiconductor layer can be made smaller, thereby reducing the longitudinal transmission resistance, ensuring that the doped semiconductor layer has a higher carrier shunting ability, reducing the carrier recombination rate, and further improving the photoelectric conversion efficiency of the solar cell.

[0044] In some embodiments, silicon oxide is formed on a side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate.

[0045] With the above technical solution, after the dielectric layer is opened, an etching solution is required to remove the residue. During this process, because the silicon oxide is located above the doped semiconductor layer, the etching solution preferentially reacts with the silicon oxide, minimizing corrosion of the next layer, the doped semiconductor layer, and thus reducing mold opening damage. Furthermore, silicon oxide has a good passivation effect, passivating the surface of the doped semiconductor layer, which helps reduce recombination losses caused by direct contact between the doped semiconductor layer and the electrode.

[0046] In some embodiments, the dielectric layer includes aluminum oxide, and the portion of the doped semiconductor layer exposed in the opening on a side facing away from the semiconductor substrate includes aluminum.

[0047] By adopting the above technical solution, since aluminum is a metal element, when there is residual aluminum element on the side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate, the contact resistance between the electrode and the doped semiconductor layer can be reduced, which is more conducive to the shunting of carriers, reduces the carrier recombination rate, and further improves the photoelectric conversion efficiency of the solar cell.

[0048] According to a second aspect of the present application, a photovoltaic assembly is provided, comprising a plurality of cell strings, the cell strings comprising a plurality of solar cells and a plurality of interconnecting members, the interconnecting members being used to connect the plurality of solar cells in series; the solar cells comprising any of the solar cells described in the first aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0050] Figure 1 A schematic cross-sectional view of a first structure of a solar cell provided in an embodiment of the present application;

[0051] Figure 2 A schematic cross-sectional view of a second structure of a solar cell provided in an embodiment of the present application;

[0052] Figure 3 A schematic diagram of the opening of a solar cell after laser mold opening provided in an embodiment of the present application;

[0053] Figure 4 A cross-sectional structural diagram of a solar cell provided in an embodiment of the present application;

[0054] Figure 5 A scanning electron microscope topography image of the doped semiconductor layer at the opening of the solar cell provided in an embodiment of the present application;

[0055] Figure 6 This is a schematic cross-sectional view of the third structure of the solar cell provided in an embodiment of the present application.

[0056] Figure numerals: 11 is a semiconductor substrate, 12 is a doped semiconductor layer, 13 is a dielectric layer, 14 is an opening, 15 is a hole, 16 is an annular protrusion, 17 is an electrode, 17-1 is a connecting electrode, 17-2 is a conductive contact layer, 19 is a second passivation layer, 20 is a first passivation layer, 21 is a discontinuous protrusion, and 22 is a pore. DETAILED DESCRIPTION

[0057] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present application. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion in the concepts of the present application.

[0058] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present application. These figures are not drawn to scale, and for the purpose of clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0059] In the context of this application, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects to be solved by this application more clearly understood, the application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely intended to explain this application and are not intended to limit this application.

[0060] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0061] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0062] Existing solar cells typically include a semiconductor substrate, a doped semiconductor layer, a dielectric layer, and electrodes. The doped semiconductor layer is formed on the light-facing and / or light-reflecting surfaces of the semiconductor substrate. The dielectric layer is formed on the side of the doped semiconductor layer facing away from the semiconductor substrate and serves as a surface passivation layer and / or anti-reflection layer. The surface passivation layer is used to passivate surface defects on the side of the doped semiconductor layer facing away from the semiconductor substrate, thereby reducing the carrier recombination efficiency of the doped semiconductor layer. The anti-reflection layer is used to reduce the reflection of incident light and increase the light absorption rate of the semiconductor substrate. The electrode at least partially penetrates the dielectric layer and is in electrical contact with the doped semiconductor layer to conduct the carriers collected by the doped semiconductor layer to form a photocurrent.

[0063] In actual applications, the electrodes can be formed using processes such as screen printing, electroplating, or physical vapor deposition. Currently, screen printing is commonly used to form electrodes, using high-temperature silver paste as the material for manufacturing the electrodes. However, the high cost of high-temperature silver paste makes the manufacturing cost of the electrodes very high in the overall manufacturing cost of solar cells, in addition to the cost of the semiconductor substrate itself. Therefore, reducing the cost of electrode manufacturing has become an urgent problem that needs to be solved in the current industry.

[0064] To address this issue, the industry performs mold opening at the interface of dielectric layers, such as silicon nitride, to remove part of the dielectric layer to form a contact window for the exposed doped semiconductor layer, and uses a low-temperature metallization process to make electrodes, such as using a low-temperature paste instead of a high-temperature silver paste, or using an electroplating process to form electrodes. However, the bonding strength between the electrodes formed by the current low-temperature metallization process and the doped semiconductor layer is lower than the bonding strength provided by the fusion crystal formed by the glass body inside the silver paste and the silicon interface in the manufacture of high-temperature silver paste. This leads to a higher risk of the electrode detaching from the doped semiconductor layer, reducing the structural reliability of the solar cell.

[0065] In order to solve the above technical problems, the embodiments of the present application provide a solar cell. In terms of the type of cell, the solar cell provided by the embodiments of the present application includes but is not limited to any of the following photovoltaic cells that can convert light energy into electrical energy. For example, the solar cell provided by the embodiments of the present application can be any of the following solar cells: a tunneling oxide passivated contact cell (Topcon), a doped polycrystalline silicon full back contact cell (TBC), a composite passivated back contact cell (HPBC), a bifacial hybrid cell, etc.

[0066] In terms of the position of the electrodes, the solar cell provided in the embodiment of the present application may be a back contact cell, such as Figure 1 As shown in , the positive electrode and negative electrode of the solar cell are both formed on the backlight side of the semiconductor substrate. Alternatively, the solar cell provided in the embodiment of the present application can also be a double-sided contact cell, such as Figure 2As shown in , the positive electrode and the negative electrode of the solar cell are respectively formed on the light-facing side and the backlight-facing side of the semiconductor substrate.

[0067] Reference Figure 1-Figure 3 The solar cell provided in the embodiment of the present application includes: a semiconductor substrate 11 , a doped semiconductor layer 12 , a dielectric layer 13 and an electrode 17 .

[0068] Here, the semiconductor substrate 11 has a first surface and a second surface that are opposite to each other. The first surface of the semiconductor substrate 11 may correspond to the backlight surface of the solar cell, and the second surface of the semiconductor substrate 11 may correspond to the light-facing surface of the solar cell. The embodiment of the present application does not specifically limit the surface morphology of the first surface and the second surface of the semiconductor substrate 11. For example Figure 2 As shown in FIG, the first surface and the second surface of the semiconductor substrate 11 are both planes. Figure 1 As shown, the second surface of the semiconductor substrate 11 may also be a velvet surface, and the first surface of the semiconductor substrate 11 may be at least partially flat. For another example, both the first surface and the second surface of the semiconductor substrate 11 may be a velvet surface.

[0069] In one embodiment, the semiconductor substrate 11 may be a silicon substrate. The conductivity type of the semiconductor substrate 11 may be N-type or P-type, or the semiconductor substrate 11 may be close to the intrinsic conductivity type, and the crystal type may be single crystal or polycrystalline.

[0070] The doped semiconductor layer 12 may be provided on the first surface of the semiconductor substrate 11. It is understood that the doped semiconductor layer 12 may also be provided on the second surface of the semiconductor substrate 11, or the doped semiconductor layer may be provided on both the first surface and the second surface of the semiconductor substrate 11. Figure 2 As shown in .

[0071] The formation position of the doped semiconductor layer 12 on the semiconductor substrate 11 can be determined according to the type of solar cell. It should be noted that the doped semiconductor layer 12 in the embodiment of the present application refers to a semiconductor layer with a hole formed on the side of the opening of the dielectric layer away from the semiconductor substrate, which can also be called a first doped semiconductor layer; in some examples, the doped semiconductor layer 12 in the embodiment of the present application can also refer to a semiconductor layer with a hole formed on the side of the opening of the dielectric layer away from the semiconductor substrate, and a ring-shaped protrusion is formed on the edge of the hole. The third doped semiconductor layer described below, unlike the doped semiconductor layer (i.e., the first doped semiconductor layer), refers to a semiconductor layer without a hole.

[0072] For example, when the solar cell provided in the embodiment of the present application is a double-sided contact cell, the doped semiconductor layer 12 may be formed only on one side of the first surface or the second surface of the semiconductor substrate 11. In this case, the conductivity type of the doped semiconductor layer 12 may be opposite to the conductivity type of the semiconductor substrate 11. In this case, the solar cell further includes a third doped semiconductor layer formed on the side of the semiconductor substrate 11 away from the doped semiconductor layer 12 and having the same conductivity type as the semiconductor substrate. Alternatively, when the doped semiconductor layer is formed only on one side of the first surface or the second surface of the semiconductor substrate 11, the conductivity type of the doped semiconductor layer may also be the same as the conductivity type of the semiconductor substrate 11, and the solar cell further includes a third doped semiconductor layer formed on the side of the semiconductor substrate away from the doped semiconductor layer, and the conductivity type of the third doped semiconductor layer is opposite to that of the semiconductor substrate. Of course, when the solar cell provided in the embodiment of the present application is a double-sided contact cell, the solar cell may also not include the above-mentioned third doped semiconductor layer.

[0073] Alternatively, the doped semiconductor layer 12 may also be formed on both the first and second surfaces of the semiconductor substrate 11 . In this case, the two doped semiconductor layers 12 located on the first and second surfaces of the semiconductor substrate 11 have opposite conductivity types.

[0074] When the solar cell provided in the embodiment of the present application is a double-sided contact cell, the doped semiconductor layer 12 can be arranged on the entire surface of the first surface and / or the second surface of the semiconductor substrate 11, or can be arranged in a local area of ​​the first surface and / or the second surface of the semiconductor substrate 11.

[0075] Specifically, the conductivity type of the doped semiconductor layer 12 can be determined according to actual application scenarios and is not specifically limited here.

[0076] For another example, when the solar cell provided in the embodiment of the present application is a back-contact cell, the doped semiconductor layer 12 is formed on one side of the first surface of the semiconductor substrate 11. The conductivity type of the doped semiconductor layer 12 may be the same as that of the semiconductor substrate 11. In this case, the solar cell further includes a third doped semiconductor layer formed on the first surface of the semiconductor substrate 11 and alternating with the doped semiconductor layer 12. The conductivity type of the third doped semiconductor layer is opposite to that of the semiconductor substrate 11. Alternatively, the conductivity type of the doped semiconductor layer 12 may be opposite to that of the semiconductor substrate 11. In this case, the solar cell may include a third doped semiconductor layer formed on the first surface of the semiconductor substrate 11 and alternating with the doped semiconductor layer 12. The conductivity type of the third doped semiconductor layer is the same as that of the semiconductor substrate 11. Of course, when the solar cell provided in the embodiment of the present application is a back-contact cell, the solar cell may also not include the third doped semiconductor layer. Alternatively, the conductivity types of the doped semiconductor layers 12 located in different regions on the first surface of the semiconductor substrate 11 are opposite, and the different doped semiconductor layers 12 of opposite conductivity types are alternately distributed.

[0077] When the solar cell further includes a third doped semiconductor layer, the conductivity type of the third doped semiconductor layer can be determined based on actual needs, as long as the conductivity type of the doped semiconductor layer 12 is opposite to that of the third doped semiconductor layer. For example, the materials of the doped semiconductor layer 12 and the third doped semiconductor layer can be semiconductor materials such as silicon, germanium, silicon carbide, or gallium arsenide. In terms of the internal arrangement of the materials, they can be amorphous, microcrystalline, single crystal, nanocrystalline, or polycrystalline. The materials of the doped semiconductor layer 12 and the third doped semiconductor layer can be the same or different.

[0078] The dielectric layer 13 is disposed on the side of the doped semiconductor layer 12 facing away from the semiconductor substrate 11. A plurality of openings 14 are defined through the dielectric layer 13, exposing at least a portion of the doped semiconductor layer 12. A plurality of holes 15 are formed in the portion of the doped semiconductor layer 12 exposed in the openings 14, on the side facing away from the semiconductor substrate 11. In some examples, the edges of the holes 15 are formed with an annular raised portion 16.

[0079] The dielectric layer 13 can passivate the surface of the doped semiconductor layer 12 and reduce the carrier recombination rate. Because the dielectric layer 13 is a non-conductive insulating layer, an opening 14 is provided through the dielectric layer 13. The opening 14 in the present application may be a circular, square, or elliptical shape. The opening 14 exposes at least a portion of the doped semiconductor layer 12. In addition, a plurality of holes 15 are formed on the side of the doped semiconductor layer 12 exposed in the opening 14 that faces away from the semiconductor substrate 11. This method allows electrodes to be formed at the opening 14 using a low-temperature metallization process, which can reduce the cost of the metallization process. In addition, because a plurality of holes 15 are formed on the side of the doped semiconductor layer 12 exposed in the opening 14 that faces away from the semiconductor substrate 11, the side of the doped semiconductor layer 12 exposed in the opening 14 that faces away from the semiconductor substrate 11 has an uneven surface feature, which helps to increase the surface roughness and specific surface area of ​​the doped semiconductor layer 12 located at the opening. Based on this, compared with the existing solar cell in which the electrode 17 is formed on the doped semiconductor layer with a relatively flat surface, the solar cell provided in the embodiment of the present application has the electrode 17 formed on the doped semiconductor layer 12 with an uneven surface. The contact area between the portion of the doped semiconductor layer 12 exposed in the opening 14 and the electrode 17 is larger, which is beneficial to increasing the bonding force between the electrode 17 and the doped semiconductor layer 12, enhancing the connection strength between the two, reducing the risk of the electrode 17 detaching from the doped semiconductor layer 12, and improving the structural reliability of the solar cell; at the same time, due to the large contact area, the contact resistance between the electrode 17 and the doped semiconductor layer 12 can also be reduced, the contact performance can be improved, and the photoelectric conversion efficiency of the solar cell can be further improved.

[0080] The material of dielectric layer 13 is an insulating material. For example, the material of dielectric layer 13 may include at least one of silicon nitride, silicon oxynitride, silicon carbide, and aluminum oxide. In some examples, the material of dielectric layer 13 includes silicon nitride. In this case, because silicon nitride has a high resistivity, when the material of dielectric layer 13 includes silicon nitride, the insulating properties of dielectric layer 13 are improved, and a good passivation effect is achieved. Therefore, dielectric layer 13 including silicon nitride passivates the surface of doped semiconductor layer 12, which helps reduce the carrier recombination rate. In addition, because silicon nitride also has a good anti-reflection effect, the photoelectric conversion efficiency of the solar cell can be improved.

[0081] The dielectric layer 13 can be a single-layer structure or a multi-layer structure. In some examples, the dielectric layer 13 can include a passivation layer, and can also include other possible layers such as an anti-reflection layer, or include a passivation layer and an anti-reflection layer arranged in a stacked manner. The embodiment of the present application does not specifically limit the structure of the dielectric layer 13, and it can be arranged according to the needs of the solar cell. For example, for a TBC cell, the dielectric layer 13 on the backlight side can include a passivation layer and an anti-reflection layer arranged in a stacked manner; for a Topcon cell, the dielectric layer 13 on the backlight side can include an anti-reflection layer, and can also include a passivation layer and an anti-reflection layer arranged in a stacked manner; the dielectric layer on the light-facing side of both the TBC cell and the Topcon cell can include a passivation layer and an anti-reflection layer arranged in a stacked manner.

[0082] The thickness of the dielectric layer 13 can be determined based on the actual application scenario and is not specifically limited here. Secondly, regarding the openings provided in the dielectric layer 13, since the electrodes need to pass through the dielectric layer 13 through the openings and be electrically connected to the doped semiconductor layer 12, the distribution and size of the openings in the dielectric layer 13 can be determined based on the contact range between the electrode 17 and the doped semiconductor layer 12 in the actual application scenario.

[0083] In some embodiments, the solar cell may further include a first passivation layer 20 located between the semiconductor substrate 11 and the doped semiconductor layer 12. The first passivation layer 20 may passivate at least the corresponding surfaces of the semiconductor substrate 11 and the doped semiconductor layer 12, thereby reducing the rate at which carriers recombine on the surface of the semiconductor substrate 11. Furthermore, the doped semiconductor layer 12 formed on the first passivation layer 20 can selectively collect carriers of the corresponding conductivity type within the semiconductor substrate 11, thereby further improving the photoelectric conversion efficiency of the solar cell provided by the embodiments of the present application.

[0084] The first passivation layer 20 can be a single layer or multiple layers, or can be composed of different materials in different regions. The material of the first passivation layer 20 can be determined based on the material of the doped semiconductor layer 12. For example, when the material of the doped semiconductor layer 12 includes one or more of doped amorphous silicon, doped microcrystalline silicon, or doped nanocrystalline silicon, the first passivation layer 20 can be an intrinsic amorphous silicon layer, an intrinsic microcrystalline silicon layer, an intrinsic nanocrystalline silicon layer, or a mixed layer of at least two of the three. In this case, the doped semiconductor layer 12 and the first passivation layer 20 can form a heterogeneous contact structure.

[0085] For another example, when the doped semiconductor layer 12 is a doped polysilicon layer, the first passivation layer 20 may be a tunneling passivation layer. In this case, the doped semiconductor layer 12 and the first passivation layer 20 may form a tunneling passivation contact structure. Furthermore, the material of the tunneling passivation layer may include any dielectric material having a tunneling passivation effect. For example, the material of the tunneling passivation layer may include one or more of silicon oxide, aluminum oxide, titanium oxide, hafnium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride.

[0086] In some embodiments, the doped semiconductor layer 12 is formed only on one side of the first surface or the second surface of the semiconductor substrate 11. The solar cell may further include a second passivation layer 19 formed on the side of the semiconductor substrate 11 away from the doped semiconductor layer 12, which can passivate the side of the semiconductor substrate 11 away from the doped semiconductor layer 12, thereby reducing the rate of carrier recombination on the surface of the semiconductor substrate 11 and further improving the photoelectric conversion efficiency of the solar cell. Specifically, the embodiment of the present application does not specifically limit the material and thickness of the second passivation layer 19, which can refer to the material of the above-mentioned dielectric layer. For example, the material of the second passivation layer 19 may include any one or more insulating materials such as silicon oxide, aluminum oxide, silicon nitride, etc.

[0087] Typically, hydrogen is formed in the dielectric layer during its formation. For example, when the dielectric layer's material includes aluminum oxide, excess hydrogen is produced during the deposition of aluminum oxide due to the presence of water in the reaction. Another example is when depositing silicon nitride, residual nitrogen-hydrogen bonds are present. At high temperatures, these bonds break and recombine to produce hydrogen. Because the dielectric layer contains hydrogen, heat can cause hydrogen to escape from the dielectric layer during laser opening. This hydrogen escape can cause film cracking in areas outside the opening, damaging the dielectric layer and the doped semiconductor layer, thereby affecting the passivation performance of the solar cell.

[0088] The embodiment of the present application proposes a solution to the problem that hydrogen escape during the laser mold opening process causes the dielectric layer in the non-opening area to explode, causing damage to the dielectric layer and the doped semiconductor layer. Figure 4As shown in , specifically, in the solar cell of the embodiment of the present application, a pore 22 is formed between the dielectric layer 13 and the doped semiconductor layer 12 below, at the edge of the opening of the dielectric layer 13. The pore 22 can provide space for hydrogen to escape during the laser mold opening process, thereby alleviating or avoiding the dielectric layer explosion in the non-opening area caused by the laser mold opening, and is conducive to accurately controlling the size of the opening area, and reducing the damage caused by the laser mold opening to the doped semiconductor layer in the non-opening area, thereby effectively ensuring the passivation effect of the solar cell. In addition, compared with directly using a high-temperature sintering process to form electrodes, the present application can form electrodes at the opening using a low-temperature metallization process, which can reduce the cost of the metallization process.

[0089] Reference Figure 4 and Figure 5 The solar cell provided in the embodiments of the present application may also have any one or more of the following features.

[0090] Exemplarily, the length of the pores 22 distributed from the edge of the opening of the dielectric layer in a direction parallel to the semiconductor substrate is greater than 0 μm and less than or equal to 5 μm. Exemplarily, the length of the distributed pores is calculated as the length from the edge of the opening of the dielectric layer, in a direction parallel to the semiconductor substrate and away from the edge of the opening, to the farthest pore. Here, the direction parallel to the semiconductor substrate is perpendicular to the thickness direction of the semiconductor substrate. Considering that if the length of the distributed pores 22 is too large, for example, 10 μm, 20 μm or 30 μm or more, the dielectric layer is prone to cracking and falling off, resulting in affecting the passivation effect of the solar cell, thereby increasing the recombination loss of the doped semiconductor layer, the embodiment of the present application has a length of the pores distributed from the edge of the opening of the dielectric layer in a direction parallel to the semiconductor substrate of less than or equal to 5 μm.

[0091] Furthermore, if the length of the distributed pores 22 is too small, hydrogen will escape during the laser mold opening process, and insufficient space will be provided for hydrogen escape, and the dielectric layer in the non-opening area will still be at risk of film explosion. Therefore, in some examples, the length of the distributed pores is greater than or equal to 0.01 μm starting from the edge of the opening of the dielectric layer in a direction parallel to the semiconductor substrate.

[0092] The length of the pores distributed from the edge of the opening of the dielectric layer along a direction parallel to the semiconductor substrate may be, for example, 0.01 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 2 μm, 3 μm or 5 μm.

[0093] The above-mentioned length range of distributed pores provided in the present application can provide a reasonable space for the escape of hydrogen in the dielectric layer during the laser mold opening process, which can effectively alleviate or avoid the film explosion of the dielectric layer in the non-opening area caused by laser mold opening, which is conducive to accurately controlling the size of the opening area and reducing the damage caused by laser mold opening to the doped semiconductor layer in the non-opening area. It can also prevent the dielectric layer from being broken and falling off due to the excessive length of the distributed pores, which is conducive to avoiding the breakage and falling off of the dielectric layer affecting the passivation effect of the solar cell, thereby reducing the damage caused by laser mold opening and ensuring the passivation effect of the solar cell.

[0094] For example, the portion of the dielectric layer close to the opening is warped in a direction away from the doped semiconductor layer. Figure 4 At the position indicated by the middle arrow, since the portion of the dielectric layer close to the opening is warped in the direction away from the doped semiconductor layer, a space is formed between the dielectric layer and the underlying doped semiconductor layer in the portion of the dielectric layer close to the opening, which can further provide space for the escape of hydrogen generated in the dielectric layer under the action of the laser during the laser mold opening process, thereby helping to alleviate or avoid film explosion, reduce the damage caused by laser mold opening, and help avoid the dielectric layer from cracking and falling off, affecting the passivation effect of the solar cell, thereby helping to ensure the passivation effect of the solar cell.

[0095] For example, the angle of the dielectric layer near the opening that is bent away from the doped semiconductor layer is greater than 0° and less than or equal to 20°. Figure 4 The angle α shown in . Exemplarily, the angle is the angle formed by the surface of the portion of the dielectric layer near the opening facing the doped semiconductor layer relative to the first surface of the semiconductor substrate. One side of the angle corresponds to the first surface of the semiconductor substrate and is parallel to the direction of the first surface of the semiconductor substrate, and the other side corresponds to the surface of the portion of the dielectric layer near the opening facing the doped semiconductor layer. Considering that if the angle of warping of the portion of the dielectric layer near the opening away from the doped semiconductor layer is too large, for example, 30°, 40° or other larger angles, the dielectric layer is likely to crack and fall off, affecting the passivation effect of the solar cell and causing recombination loss of the doped semiconductor layer, the angle of warping of the portion of the dielectric layer near the opening away from the doped semiconductor layer in the embodiment of the present application is less than or equal to 20°.

[0096] Furthermore, considering that if the angle at which the portion of the dielectric layer close to the opening is warped away from the doped semiconductor layer is too small, it will not be conducive to providing space for the escape of hydrogen during the laser mold opening process, and will cause the dielectric layer in the non-opening area of ​​the laser mold opening to have the risk of film explosion, therefore, in some examples, the angle at which the portion of the dielectric layer close to the opening is warped away from the doped semiconductor layer is greater than or equal to 0.001°.

[0097] The angle at which the portion of the dielectric layer near the opening is warped away from the doped semiconductor layer may be, for example, 0.001°, 0.005°, 0.01°, 0.05°, 0.09°, 1°, 6°, 9°, 10°, 12°, 15°, 18° or 20°.

[0098] The angle range in which the portion of the dielectric layer close to the opening provided in the embodiment of the present application is warped in a direction away from the doped semiconductor layer can provide a reasonable space for hydrogen in the dielectric layer to escape during the laser mold opening process, can alleviate or avoid the dielectric layer explosion in the non-opening area caused by the laser mold opening, and can reduce the damage caused by the laser mold opening to the doped semiconductor layer in the non-opening area, and can prevent the dielectric layer from cracking and falling off due to excessive warping angles. Therefore, the above-mentioned angle range can ensure the passivation effect of the solar cell, reduce the damage caused by the laser mold opening, and avoid the rupture of the dielectric layer affecting the passivation effect of the solar cell.

[0099] For example, the portion of the doped semiconductor layer exposed in the opening and facing away from the semiconductor substrate includes a plurality of holes 15. Figure 5 As shown in FIG, the circular (or quasi-circular) area surrounded by the bright circle in the figure is the hole 15.

[0100] It should be noted that in the embodiment of the present application, the hole does not penetrate the doped semiconductor layer and is a blind hole.

[0101] The above technical solution helps increase the surface roughness of the doped semiconductor layer at the opening, thereby increasing the contact area between the doped semiconductor layer exposed at the opening and the electrode. This helps to increase the bonding force between the electrode and the doped semiconductor layer, strengthen the connection strength between the two, reduce the risk of the electrode detaching from the doped semiconductor layer, and improve the structural reliability of the solar cell. In addition, because the contact area between the portion of the doped semiconductor layer exposed at the opening and the electrode is increased, the contact resistance between the doped semiconductor layer and the electrode can be reduced, improving contact performance and further increasing the photoelectric conversion efficiency of the solar cell.

[0102] For example, the hole 15 may be a quasi-hemispherical hole. The quasi-hemispherical hole may be a strictly hemispherical hole or an approximately hemispherical hole, that is, it may have some small deformation relative to the hemispherical hole, for example, a deformation within an allowable tolerance range (e.g., within 5% or 10%) relative to the hemispherical hole.

[0103] Exemplarily, the maximum radial dimension of the holes 15 is greater than 0 μm and less than or equal to 3 μm. Considering that if the maximum radial dimension of the holes 15 is too large, for example, 4 μm, 5 μm, or 10 μm or greater, the number of holes 15 will decrease, which will reduce the specific surface area of ​​the doped semiconductor layer exposed to the opening portion, thereby reducing the contact area between the doped semiconductor layer and the electrode, and reducing the bonding force between the electrode and the doped semiconductor layer, therefore, the maximum radial dimension of the holes 15 in the present application is less than or equal to 3 μm.

[0104] Furthermore, considering that if the maximum radial dimension of the hole 15 is too small, the surface roughness of the doped semiconductor layer will be small, and when forming an electrode on the doped semiconductor layer, it will be difficult to fill the small hole 15 with the conductive material used to manufacture the electrode, and the connection strength and contact performance between the electrode and the doped semiconductor layer cannot be ensured, in some examples, the maximum radial dimension of the hole is greater than or equal to 0.02 μm. Optionally, the maximum radial dimension of the hole is greater than or equal to 0.02 μm and less than or equal to 0.1 μm.

[0105] The maximum radial dimension of the hole 15 may be, for example, 0.02 μm, 0.03 μm, 0.04 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.4 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 1.5 μm, 2 μm or 3 μm.

[0106] The present application adopts the above-mentioned maximum radial size range of the hole 15, which is beneficial to increasing the surface roughness of the doped semiconductor layer, increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, and reducing the risk of the electrode detaching from the doped semiconductor layer, thereby helping to improve the structural reliability of the solar cell.

[0107] For example, the edge of the hole 15 is formed with a ring-shaped protrusion 16. Figure 5 As shown in FIG, the bright circle is an annular raised portion 16 formed at the edge of the hole 15. In some examples, the annular raised portion 16 can be formed by melting and then solidifying the material of the doped semiconductor layer, similar to the form of a circular crater. The annular raised portion 16 is raised relative to the area inside and / or outside the hole 15. It will be understood that since the annular raised portion 16 is formed by melting and then solidifying the doped semiconductor layer, when the doped semiconductor layer is a doped polysilicon layer, the material of the annular raised portion includes silicon.

[0108] By adopting the above technical solution, the portion of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate can have uneven surface features, which is beneficial to increasing the surface roughness and specific surface area of ​​the doped semiconductor layer at the opening.

[0109] Exemplarily, the width of the annular raised portion 16 is greater than 0 μm and less than or equal to 0.3 μm. Considering that if the width of the annular raised portion 16 is too large, for example, 0.4 μm, 0.7 μm, or 1 μm or more, the specific surface area of ​​the doped semiconductor layer will not increase significantly, thereby reducing the surface roughness of the doped semiconductor layer and not being conducive to increasing the contact area between the electrode and the doped semiconductor layer, the width of the annular raised portion of the present application is less than or equal to 0.3 μm.

[0110] Furthermore, considering that if the width of the annular protrusion 16 is too small, the annular protrusion 16 is easily broken, resulting in no contribution to increasing the contact area between the electrode and the doped semiconductor layer, and the silicon in the annular protrusion 16 (i.e., the silicon in the doped semiconductor layer) is easily pulled off by the electrode, which is not conducive to increasing the adhesion between the electrode and the doped semiconductor layer, in some examples, the width of the annular protrusion is greater than or equal to 0.05 μm.

[0111] The width of the annular protrusion 16 may be, for example, 0.05 μm, 0.07 μm, 0.09 μm, 0.1 μm, 0.15 μm, 0.2 μm or 0.3 μm.

[0112] The width range of the above-mentioned annular protrusion 16 is beneficial to increasing the surface roughness of the doped semiconductor layer, thereby increasing the contact area between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0113] Exemplarily, the height of the annular protrusion 16 is greater than 0 μm and less than or equal to 0.5 μm. Considering that if the height of the annular protrusion 16 is too high, for example, 0.6 μm, 0.8 μm, 1 μm or more, the annular protrusion 16 is easily broken, resulting in no contribution to increasing the contact area between the electrode and the doped semiconductor layer, and the annular protrusion 16 is easily broken by the electrode, thus reducing the tension between the electrode and the doped semiconductor layer, which is not conducive to increasing the bonding strength between the electrode and the doped semiconductor layer, the height of the annular protrusion of the present application is less than or equal to 0.5 μm.

[0114] Furthermore, considering that if the height of the annular protrusion 16 is too low, it will not be conducive to increasing the surface roughness of the doped semiconductor layer, in some examples, the height of the annular protrusion 16 is greater than or equal to 0.001 μm.

[0115] The height of the annular protrusion may be, for example, 0.001 μm, 0.005 μm, 0.008 μm, 0.01 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.2 μm, 0.3 μm or 0.5 μm.

[0116] Exemplarily, the ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 is less than or equal to 60. Considering that if this ratio is too large, for example, 80, 90, or 100 or more, that is, the maximum radial dimension of the hole 15 is large and the width of the annular protrusion 16 is small, and the maximum radial dimension of the hole 15 is large, the number of holes 15 will be reduced, and the width of the annular protrusion 16 is small, which will cause the specific surface area of ​​the doped semiconductor layer at the opening to decrease, thereby reducing the surface roughness of the doped semiconductor layer at the opening, and is not conducive to increasing the contact area between the electrode and the doped semiconductor layer. Therefore, in the present application, the ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 is less than or equal to 60.

[0117] Furthermore, if this ratio is too small, that is, if the width of the annular protrusion 16 is large and the maximum radial dimension of the hole 15 is small, the specific surface area of ​​the doped semiconductor layer will be reduced, thereby reducing the surface roughness of the doped semiconductor layer and hindering the increase in the contact area between the electrode and the doped semiconductor layer. Furthermore, a small maximum radial dimension of the hole 15 results in a smaller surface roughness of the doped semiconductor layer. Furthermore, when forming an electrode on the doped semiconductor layer, it is difficult to fill the small hole 15 with the conductive material used to manufacture the electrode, thus failing to ensure the connection strength and contact performance between the electrode and the doped semiconductor layer. Therefore, in some examples, the ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 is greater than or equal to 0.06.

[0118] The ratio of the maximum radial dimension of the hole 15 to the width of the annular protrusion 16 may be, for example, 0.06, 0.08, 0.1, 0.2, 0.3, 1, 10, 15, 18, 20, 30, 35, 40 or 60.

[0119] For example, a plurality of discontinuous protrusions 21 are formed on the side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate. The discontinuous protrusions 21 may include dot-shaped protrusions (such as Figure 5 Bright spots within the circle mark in Figure 5 The linear protrusion may be a straight line protrusion, a curved line protrusion, an unclosed loop protrusion, etc.

[0120] The discontinuous raised portions 21 can be located at any location on the side of the doped semiconductor layer exposed in the opening that faces away from the semiconductor substrate. The discontinuous raised portions 21 help increase the surface roughness of the doped semiconductor layer at the opening, thereby further increasing the contact area between the electrode and the doped semiconductor layer, enhancing the bonding force between the electrode and the doped semiconductor layer, and strengthening the connection between the two. This reduces the risk of the electrode detaching from the doped semiconductor layer, thereby improving the structural reliability of the solar cell.

[0121] Exemplarily, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon disposed on a side of the doped polysilicon layer exposed in the opening and facing away from the semiconductor substrate.

[0122] After the dielectric layer is opened, it is necessary to use an etching solution to remove the residue. Since amorphous silicon has good corrosion resistance, amorphous silicon is distributed on the side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate. In this way, the amorphous silicon can protect the doped polycrystalline silicon layer below it, preventing the doped polycrystalline silicon layer below the amorphous silicon from being severely damaged by the etching solution, thereby causing serious recombination. In addition, amorphous silicon has a good passivation effect, which is beneficial to reducing the recombination caused by direct contact between the doped polycrystalline silicon layer and the electrode.

[0123] Optionally, when the doped semiconductor layer is a doped polycrystalline silicon layer, the portion of the doped semiconductor layer exposed in the opening on a side facing away from the semiconductor substrate may further include at least one of microcrystalline silicon and nanocrystalline silicon. The beneficial effects of microcrystalline silicon and / or nanocrystalline silicon are similar to those of amorphous silicon, and reference may be made to the above description, which will not be further elaborated here.

[0124] Exemplarily, the pores 22 contain at least one metal material from the electrode. The electrode may include a single metal layer, or multiple metal layers. When the electrode includes multiple metal layers, the pores 22 may contain at least one metal material from the bottom layer or layers. The inclusion of at least one metal material from the electrode in the pores can increase the contact area between the electrode and the doped semiconductor layer, thereby reducing the contact resistance between the electrode and the doped semiconductor layer, increasing the bonding strength between the electrode and the doped semiconductor layer, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell.

[0125] Exemplary metal materials include one or more of nickel, copper, silver, or tin. These metal materials are filled into the pores, thereby increasing the contact area between the electrode and the doped semiconductor layer, reducing the contact resistance between the electrode and the doped semiconductor layer, increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell. In addition, these metals can also block deep energy level impurities or other metals from diffusing into the doped semiconductor layer and the semiconductor substrate, thereby reducing recombination between the doped semiconductor layer and the semiconductor substrate and reducing recombination losses.

[0126] Exemplarily, the doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon located at the edge of the opening in the dielectric layer, located below the dielectric layer, and disposed on a side of the doped polysilicon layer facing away from the semiconductor substrate. After the dielectric layer is opened, an etching solution is required to remove the residue. When the etching solution is used to remove the residue, the edge of the opening in the dielectric layer and the portion located below the dielectric layer will also be undercut. In this case, due to the good corrosion resistance of amorphous silicon, amorphous silicon is distributed at the edge of the opening in the dielectric layer, located below the dielectric layer, and on a side of the doped polysilicon layer facing away from the semiconductor substrate. In this way, the amorphous silicon can protect the doped polysilicon layer below it, preventing the doped polysilicon layer below the amorphous silicon from being severely damaged by the etching solution, thereby causing serious recombination. In addition, the amorphous silicon has a good passivation effect, which is conducive to reducing recombination losses caused by direct contact between the doped polysilicon layer and the electrode.

[0127] Exemplarily, the length of the amorphous silicon distributed along a direction parallel to the semiconductor substrate from the edge of the opening of the dielectric layer is greater than 0 μm and less than or equal to 6 μm. Here, the length of the amorphous silicon distributed is calculated as the length from the edge of the opening of the dielectric layer, along a direction parallel to the semiconductor substrate and away from the edge of the opening, to the farthest amorphous silicon. Here, the direction parallel to the semiconductor substrate is perpendicular to the thickness direction of the semiconductor substrate.

[0128] Based on the role of amorphous silicon described above, it can be seen that if the length range of the amorphous silicon is too large, since the lateral transmission resistance of amorphous silicon is larger than that of polycrystalline silicon, it is not conducive to the lateral transmission of carriers, which will reduce the photoelectric conversion efficiency of the solar cell. In addition, considering that if the length range of the amorphous silicon is large, a large amount of heat is required when forming an opening in the dielectric layer, and the large amount of heat will cause excessive damage to the doped semiconductor layer when forming the opening in the dielectric layer, resulting in poor passivation effect of the doped semiconductor layer. Therefore, in this application, the length of the amorphous silicon distributed from the edge of the opening in the dielectric layer along the direction parallel to the semiconductor substrate is less than or equal to 6μm.

[0129] Furthermore, considering that if the length range of the distributed amorphous silicon is too small, in the case of severe side etching, the amorphous silicon cannot effectively prevent corrosion, and the passivation effect is not obvious, therefore in some examples, the length of the distributed amorphous silicon is greater than or equal to 0.001 μm from the edge of the opening of the dielectric layer along a direction parallel to the semiconductor substrate.

[0130] The length of the amorphous silicon distribution may be, for example, 0.001 μm, 0.007 μm, 0.01 μm, 0.07 μm, 0.09 μm, 0.1 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 2 μm, 3 μm, 5 μm or 6 μm.

[0131] Exemplarily, along the thickness direction of the semiconductor substrate, the depth of the amorphous silicon ranges from greater than 0 nm to less than or equal to 350 nm.

[0132] In some embodiments, the depth of the amorphous silicon at the location where the portion of the doped semiconductor layer exposed at the opening facing away from the semiconductor substrate and where a protrusion (e.g., a ring-shaped protrusion or a discontinuous protrusion) is distributed is greater than the depth of the amorphous silicon at the location without the protrusion. Exemplarily, the depth of the amorphous silicon at the location where the portion of the doped semiconductor layer exposed at the opening facing away from the semiconductor substrate and where the protrusion is distributed is greater than 0 nm and less than or equal to 350 nm, while the depth of the amorphous silicon at the location without the protrusion is greater than 0 nm and less than or equal to 50 nm. Since the protrusion is formed by melting and resolidifying the material of the doped semiconductor layer in most cases, when the doped semiconductor layer is a doped polycrystalline silicon layer, the material of the protrusion is mainly amorphous silicon, and therefore the depth of the amorphous silicon at the protrusion is greater than the depth of the amorphous silicon at the non-protrusion.

[0133] In the above technical solution, considering that if the depth of amorphous silicon is too large, the carrier transmission resistance will increase and the photoelectric conversion efficiency of the solar cell will be affected, the depth of amorphous silicon is less than or equal to 350nm.

[0134] Furthermore, considering that if the depth range of amorphous silicon is too small, it cannot protect the underlying doped semiconductor layer and prevent the underlying doped semiconductor layer from being damaged by the corrosive liquid, and cannot effectively passivate the surface of the doped polysilicon, therefore, in some examples, the depth of amorphous silicon is greater than or equal to 0.001nm.

[0135] The depth of the amorphous silicon along the thickness direction of the semiconductor substrate may be, for example, 0.001 nm, 0.005 nm, 0.009 nm, 0.01 nm, 0.05 nm, 0.1 nm, 0.8 nm, 1 nm, 6 nm, 10 nm, 50 nm, 100 nm, 200 nm or 350 nm.

[0136] Exemplarily, the length of the amorphous silicon distributed along a direction parallel to the semiconductor substrate from the edge of the opening of the dielectric layer is greater than the length of the pores distributed. After the dielectric layer is molded, an etching liquid needs to be used to remove the residue. During the process of removing the residue with the etching liquid, the etching liquid is more likely to remain in the pores and is not easy to flow out. In order to prevent the etching liquid from corroding the doped polycrystalline silicon in the pores and causing damage to the doped polycrystalline silicon, in some embodiments of the present application, amorphous silicon is formed on the side of the doped polycrystalline silicon layer facing away from the semiconductor substrate at the edge of the opening of the dielectric layer and below the dielectric layer, and the length of the amorphous silicon distributed is greater than the length of the pores.

[0137] Exemplarily, the portion of the doped semiconductor layer exposed in the opening has a first surface roughness on the side facing away from the semiconductor substrate, and the portion of the doped semiconductor layer not exposed in the opening has a second surface roughness on the side facing away from the semiconductor substrate, and the first surface roughness is greater than the second surface roughness. Exemplarily, the first surface roughness is in the range of 0 to 0.5 μm, the optional first surface roughness range is 0.3 μm to 0.5 μm, and the second surface roughness is in the range of 0 to 100 nm. The surface roughness of the portion of the doped semiconductor layer exposed in the opening is relatively large, which can increase the contact area between the doped semiconductor layer and the electrode, which is beneficial to reducing the contact resistance between the electrode and the doped semiconductor layer, and is beneficial to increasing the bonding force between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell. The roughness of the second surface is relatively small, which can ensure the film formation quality of the doped semiconductor layer formed.

[0138] Exemplarily, the portion of the doped semiconductor layer exposed in the opening has a first surface roughness on a side facing away from the semiconductor substrate, and the unexposed portion of the doped semiconductor layer not exposed in the opening includes the first unexposed portion at the edge of the dielectric layer opening and the remaining unexposed portion excluding the first unexposed portion, the first unexposed portion has a third surface roughness on a side facing away from the semiconductor substrate, and the remaining unexposed portion has a fourth surface roughness on a side facing away from the semiconductor substrate, wherein the first surface roughness > the third surface roughness > the fourth surface roughness. The greater surface roughness of the portion of the doped semiconductor layer exposed in the opening can increase the contact area between the doped semiconductor layer and the electrode, facilitating reduction of contact resistance between the electrode and the doped semiconductor layer, and can also increase the bonding strength between the electrode and the doped semiconductor layer, enhancing the connection strength between the two, reducing the risk of the electrode detaching from the doped semiconductor layer, and improving the structural reliability of the solar cell. Furthermore, during electrode formation, electrode material may be formed on the first unexposed portion. Therefore, the third surface roughness of the first unexposed portion is greater than the fourth surface roughness, further enhancing the bonding strength between the electrode and the doped semiconductor layer, facilitating reduction of the risk of the electrode detaching from the doped semiconductor layer, and thereby improving the structural stability of the solar cell.

[0139] In the embodiments of the present application, surface roughness may refer to the arithmetic mean deviation Ra of the profile of the targeted surface, specifically the arithmetic mean of the absolute values ​​of the profile peaks and valleys (relative to the average line) of the surface within the sampling length Lr of the targeted surface. In actual measurement, the more measuring points there are, the more accurate Ra is. Alternatively, surface roughness may also refer to the maximum height Rz of the profile of the targeted surface, specifically the distance between the peak top line and the valley bottom line of the profile of the targeted surface. It is understood that when the roughness of different surface areas is involved, for example, when the first surface roughness, the second surface roughness, the third surface roughness, and the fourth surface roughness are involved, the same roughness measurement standard is used.

[0140] For example, refer to Figure 3 As shown in FIG, the portion of the doped semiconductor layer exposed at the opening has a first thickness d1, and the portion of the doped semiconductor layer not exposed at the opening has a second thickness d2, where the first thickness d1 is less than the second thickness d2. The thickness of the doped semiconductor layer at the opening is less than the thickness at the non-opening portion, thereby reducing the distance carriers travel from the semiconductor substrate to the electrode and lowering the longitudinal transmission resistance. In particular, for non-sintered electrodes, the thickness of the doped semiconductor layer can be made smaller, thereby reducing the longitudinal transmission resistance, ensuring that the doped semiconductor layer has a high carrier shunting capability, reducing the carrier recombination rate, and further improving the photoelectric conversion efficiency of the solar cell.

[0141] Exemplarily, the portion of the doped semiconductor layer exposed in the opening has a first thickness, and for the unexposed portion of the doped semiconductor layer not exposed in the opening: it includes a first unexposed portion at the opening edge of the dielectric layer and a remaining unexposed portion other than the first unexposed portion, the first unexposed portion has a third thickness, and the remaining unexposed portion has a fourth thickness, wherein the fourth thickness>the third thickness>the first thickness.

[0142] Exemplarily, silicon oxide is formed on the side of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate. In one embodiment, the thickness of the silicon oxide formed on the annular protrusion 16 is relatively thick. Furthermore, the silicon oxide distribution in the peripheral area of ​​the annular protrusion 16 (for the hole 15, the side facing away from the hole) is relatively concentrated, and the silicon oxide in the peripheral area of ​​the annular protrusion 16 is thicker than the silicon oxide in the hole 15. It is understandable that after the dielectric layer is opened, it is necessary to use an etching solution to remove the residue. When using the etching solution to remove the residue, since the silicon oxide is located above the doped semiconductor layer, the etching solution preferentially reacts with the silicon oxide, which can reduce the etching solution's corrosion of the next layer, i.e., the doped semiconductor layer, thereby reducing mold opening damage. In addition, silicon oxide has a good passivation effect. Silicon oxide can passivate the surface of the doped semiconductor layer, which is beneficial to reduce the recombination loss caused by direct contact between the doped semiconductor layer and the electrode.

[0143] For example, when the dielectric layer is made of aluminum oxide, the side of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate includes aluminum. Since aluminum is a metallic element, if there is residual aluminum on the side of the doped semiconductor layer exposed in the opening facing away from the semiconductor substrate, the contact resistance between the electrode and the doped semiconductor layer can be reduced, which is more conducive to carrier shunting and further improves the photoelectric conversion efficiency of the solar cell.

[0144] In this embodiment, the electrode 17 may be a single-layer structure, for example Figure 1 and Figure 2 As shown in ; It can also be a stacked multi-layer structure, such as Figure 6 As shown, the electrode 17 includes a two-layer structure, which are a stacked conductive contact layer 17 - 2 and a connecting electrode 17 - 1 .

[0145] The conductive contact layer 17 - 2 is located on a side of the electrode 17 close to the doped semiconductor layer 12 , and the connecting electrode 17 - 1 is electrically connected to the doped semiconductor layer 12 through the conductive contact layer 17 - 2 .

[0146] When the electrode 17 is a single-layer structure, the electrode 17 can be formed by screen printing, electroplating, etc. When the electrode 17 comprises a stacked multi-layer structure, each film layer can be formed by electroplating, chemical plating, screen printing, etc.

[0147] The material of electrode 17 can be a metal material such as Ag, Cu, Al, Ni, Au, Zn, Sn, Pb, etc.; it can also be a metal oxide, including various types of TCO, such as ITO, AZO, IWO, etc.; it can also be a metal nitride such as TiN, etc.; it can also be a metal carbide such as TiC, etc.; it can also be a metal sulfide, etc., as well as other conductive connecting materials such as graphene, etc., or various combinations of the above materials. The material of conductive contact layer 17-2 and connecting electrode 17-1 can also be any of the above electrode materials or a suitable combination thereof.

[0148] It should be noted that if the electrode 17 includes a conductive contact layer 17-2 and a connecting electrode 17-1, the material of the conductive contact layer 17-2 and the material of the connecting electrode 17-1 may be the same or different. The material and thickness of the conductive contact layer 17-2 can be determined according to the conductivity type of the doped semiconductor layer and the actual application scenario, and are not specifically limited here. In one possible implementation, the conductive contact layer 17-2 is formed by electroplating or chemical plating, and the material may be, for example, one or more of Ag, Ni, and Sn. The connecting electrode 17-1 is formed by silk screen printing, and the material may be, for example, silver paste, copper paste, or silver-coated copper paste.

[0149] It is understood that when electrode 17 comprises a multi-layer structure, since the bottommost conductive contact layer 17-2 is formed on the surface of the doped semiconductor layer 12 having an uneven surface, this helps to increase the bonding strength between the conductive contact layer 17-2 and the doped semiconductor layer 12, reducing the risk of the conductive contact layer 17-2 detaching from the doped semiconductor layer 12. In other words, the risk of the electrode 17 detaching from the doped semiconductor layer 12 is reduced, thereby improving the structural reliability of the solar cell. Here, when the conductive contact layer 17-2 is formed on the surface of the doped semiconductor layer 12 having an uneven surface, the surface of the conductive contact layer 17-2 facing away from the semiconductor substrate can be flat or uneven. When the surface of the conductive contact layer 17-2 facing away from the semiconductor substrate also has an uneven surface feature, the formation of the connecting electrode 17-1 is beneficial for increasing the contact area between the conductive contact layer 17-2 and the connecting electrode 17-1, thereby improving the bonding strength between the conductive contact layer 17-2 and the connecting electrode 17-1. This further increases the bonding strength between the electrode 17 and the doped semiconductor layer 12, further reducing the risk of the electrode 17 detaching from the doped semiconductor layer 12. When the electrode 17 has a single-layer structure, the electrode 17 is formed on the surface of the doped semiconductor layer 12 with an uneven surface, which helps to increase the bonding strength between the electrode 17 and the doped semiconductor layer 12, reduce the risk of the electrode 17 detaching from the doped semiconductor layer 12, and improve the structural reliability of the solar cell.

[0150] An embodiment of the present application further provides a photovoltaic module, comprising a plurality of cell strings, wherein the plurality of cell strings can be connected together in series and / or in parallel. Each cell string comprises a plurality of solar cells and a plurality of interconnecting members, wherein the interconnecting members are used to connect the plurality of solar cells in series. It is understood that the interconnecting members are electrically connected to the electrodes of the plurality of solar cells, thereby connecting the plurality of solar cells in series. Here, the solar cell includes the solar cell of any of the above embodiments.

[0151] In addition, the above-mentioned interconnection member may be, for example, a soldering tape, a metal wire, a conductive tape, etc.

[0152] While the above description does not provide detailed explanations of the technical details of patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be used to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that are not identical or completely different from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0153] The above describes the embodiments of the present application. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this application. The scope of this application is defined by the appended claims and their equivalents. Without departing from the scope of this application, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of this application.

Claims

1. A solar cell, characterized in that: include: a semiconductor substrate having a first side and a second side opposite to each other; a doped semiconductor layer, disposed on the first surface of the semiconductor substrate; a dielectric layer, disposed on a side of the doped semiconductor layer facing away from the semiconductor substrate; The dielectric layer includes a plurality of openings, wherein the openings expose a portion of the doped semiconductor layer, and a gap is formed between the dielectric layer at the edge of the opening and the doped semiconductor layer below; The electrode is arranged on a side of the dielectric layer away from the semiconductor substrate, and the electrode passes through an opening on the dielectric layer and is electrically connected to the doped semiconductor layer.

2. The solar cell according to claim 1, wherein The length of the pores distributed from the edge of the opening of the dielectric layer along a direction parallel to the semiconductor substrate is greater than 0 μm and less than or equal to 5 μm.

3. The solar cell according to claim 1, wherein The pores include at least one metal material in the electrode.

4. The solar cell according to claim 3, characterized in that The metal material includes one or more of nickel, copper, silver or tin.

5. The solar cell according to claim 1, wherein A portion of the dielectric layer close to the opening is warped in a direction away from the doped semiconductor layer.

6. The solar cell according to claim 5, characterized in that The angle of the warping of the portion of the dielectric layer close to the opening in a direction away from the doped semiconductor layer is greater than 0° and less than or equal to 20°.

7. The solar cell according to claim 1, wherein The portion of the doped semiconductor layer exposed in the opening includes a plurality of holes on a side facing away from the semiconductor substrate.

8. The solar cell according to claim 7, characterized in that A ring-shaped protrusion is formed on the edge of the hole.

9. The solar cell according to claim 1, wherein A plurality of discontinuous protrusions are formed on a side of the doped semiconductor layer exposed in the opening away from the semiconductor substrate.

10. The solar cell according to claim 1, wherein The doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon disposed on a side of the doped polysilicon layer exposed in the opening away from the semiconductor substrate.

11. The solar cell according to claim 1, wherein The doped semiconductor layer includes a doped polysilicon layer, and the doped semiconductor layer further includes: amorphous silicon located at the edge of the opening of the dielectric layer, below the dielectric layer, and on a side of the doped polysilicon layer away from the semiconductor substrate.

12. The solar cell according to claim 11, characterized in that The length of the amorphous silicon distributed from the edge of the opening of the dielectric layer along a direction parallel to the semiconductor substrate is greater than 0 μm and less than or equal to 6 μm.

13. The solar cell according to claim 11 or 12, characterized in that: Starting from the edge of the opening of the dielectric layer and along a direction parallel to the semiconductor substrate, a length where the amorphous silicon is distributed is greater than a length where the pores are distributed.

14. The solar cell according to claim 1, wherein The portion of the doped semiconductor layer exposed in the opening has a first surface roughness on a side facing away from the semiconductor substrate, and the portion of the doped semiconductor layer not exposed in the opening has a second surface roughness on a side facing away from the semiconductor substrate, wherein the first surface roughness is greater than the second surface roughness.

15. The solar cell according to claim 1, wherein The portion of the doped semiconductor layer exposed in the opening has a first thickness, and the portion of the doped semiconductor layer not exposed in the opening has a second thickness, wherein the first thickness is less than the second thickness.

16. A photovoltaic module, characterized in that: The battery string comprises a plurality of solar cells and a plurality of interconnecting members, wherein the interconnecting members are used to connect the plurality of solar cells in series; Wherein, the solar cell is the solar cell according to any one of claims 1 to 15.

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