Display panel and display device including same

Abstract

Disclosed are a display panel having an improved aperture ratio per pixel and a display device including the same. To this end, the display panel includes: a first pixel; and a second pixel adjacent to the first pixel in a first direction, in which two light emitting regions that respectively emit light of different colors and are adjacent to each other in a second direction intersecting the first direction are disposed between two gate lines among the plurality of gate lines, in which the two gate lines are connected to each other, wherein each of the scan lines is disposed between two light emitting regions that respectively emit light of different colors and are adjacent to each other in a second direction, and each of the scan lines is disposed between two gate lines connected to each other, wherein the scan line is configured to drive only the sensor transistor of each of the first pixel and the second pixel.

Description

Technical Field

[0001] The present disclosure relates to a display panel and a display device, and more particularly, for example, but not limited to, to a display panel having an improved aperture ratio per pixel and a display device including the display panel. Background Art

[0002] Organic light-emitting display devices include self-luminous organic light-emitting diodes (OLEDs) and offer advantages such as fast response speed, high luminous efficiency, high brightness, and a wide viewing angle. These features not only include fast response speed, excellent luminous efficiency, high brightness, and a wide viewing angle, but also excellent contrast and color gamut because they can produce a perfect black grayscale.

[0003] Various studies are underway to ensure the aperture ratio of organic light-emitting display devices. However, due to the large amount of wiring required to drive the pixels, achieving a design that improves the aperture ratio is difficult. Furthermore, ensuring the aperture ratio is even more difficult when each pixel is composed of sub-pixels that emit four colors of light: red, green, blue, and white.

[0004] The description of related art should not be assumed to be prior art simply because it is mentioned in or associated with this section. The description of related art includes information describing one or more aspects of the subject technology, and the description in this section does not limit the present invention. Summary of the Invention

[0005] The inventors of the present disclosure have recognized the problems and needs of the related art, conducted extensive research and experiments, and invented a display panel in which a separate scan line for driving only the sensor transistor of each pixel is provided between existing gate lines, and a display device including the display panel. One or more aspects of the present disclosure are directed to devices that substantially overcome one or more problems due to the limitations and disadvantages of the related art.

[0006] One or more aspects of the present disclosure are to provide a display panel in which two gate lines sandwich two light-emitting areas that emit light of different colors respectively and are connected to each other, and each of the scan lines used only to drive the sensor transistor of each pixel is arranged between the two light-emitting areas that emit light of different colors respectively and between the two gate lines connected to each other.

[0007] One or more aspects of the present disclosure are to provide a display device including the display panel defined above.

[0008] The aspects of the present disclosure are not limited to the above aspects. Other aspects and advantages not mentioned according to the present disclosure can be understood based on the following description and can be more clearly understood based on the embodiments of the present disclosure. In addition, it will be readily understood that the aspects and advantages according to the present disclosure can be achieved using the means and combinations thereof shown in the claims.

[0009] One or more aspects of the present disclosure provide a display panel including: a first pixel; and a second pixel adjacent to the first pixel in a first direction, wherein the first pixel and the second pixel each include a first subpixel, a second subpixel, and a third subpixel for respectively emitting light of different colors, wherein the first pixel and the second pixel share a plurality of white subpixels, wherein each of the first subpixels includes a first pixel circuit and a first light-emitting region connected to the first pixel circuit, wherein each of the second subpixels includes a second pixel circuit and a second light-emitting region connected to the second pixel circuit, wherein each of the third subpixels includes a third pixel circuit and a third light-emitting region connected to the third pixel circuit, wherein each of the white subpixels includes a fourth pixel circuit and a fourth light-emitting region connected to the fourth pixel circuit, wherein a plurality of gate lines extend along the first direction and are arranged in a second direction intersecting the first direction, wherein two light-emitting regions for respectively emitting light of different colors and adjacent to each other in the second direction are provided between two of the plurality of gate lines, wherein the two gate lines are connected to each other, wherein each of scan lines is provided between the two light-emitting regions for respectively emitting light of different colors and adjacent to each other in the second direction, wherein each of the scan lines is configured to drive only the sensor transistors of each of the first pixel and the second pixel.

[0010] One or more aspects of the present disclosure provide a display device comprising: a display panel comprising a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixels; a data driver configured to convert pixel data into a data voltage and supply the data voltage to the data lines; a gate driver configured to sequentially supply a gate pulse to the gate lines; and a timing controller configured to transmit the pixel data to the data driver and control the data driver and the gate driver, wherein the plurality of pixels comprise: a first pixel; and a second pixel adjacent to the first pixel in a first direction, wherein the first pixel and the second pixel each comprise a first sub-pixel, a second sub-pixel, and a third sub-pixel for respectively emitting light of different colors, wherein the first pixel and the second pixel share a plurality of white sub-pixels, wherein each of the first sub-pixels comprises a first pixel circuit and a third sub-pixel circuit. a first light-emitting area connected to the first pixel circuit, wherein each of the second sub-pixels includes a second pixel circuit and a second light-emitting area connected to the second pixel circuit, wherein each of the third sub-pixels includes a third pixel circuit and a third light-emitting area connected to the third pixel circuit, wherein each of the white sub-pixels includes a fourth pixel circuit and a fourth light-emitting area connected to the fourth pixel circuit, wherein the plurality of gate lines extend along the first direction and are arranged in a second direction intersecting with the first direction, wherein two light-emitting areas for respectively emitting light of different colors and adjacent to each other in the second direction are set between two gate lines of the plurality of gate lines, wherein the two gate lines are connected to each other, wherein each of the scan lines is set between the two light-emitting areas for respectively emitting light of different colors and adjacent to each other in the second direction, wherein each of the scan lines is configured to drive only the sensor transistors of each of the first pixel and the second pixel.

[0011] According to an embodiment of the present disclosure, a scan line for driving only a sensor transistor of each pixel may be provided between sub-pixels where no existing gate line for driving the scan transistor exists.

[0012] According to an embodiment of the present disclosure, conventional pixel drive voltage (EVDD) lines and reference voltage (Vref) lines are swapped to form an effective dual-scan architecture. Each sensor transistor is placed between each pixel drive voltage (EVDD) line and the reference voltage (Vref) line.

[0013] According to an embodiment of the present disclosure, the area of ​​the white sub-pixel can be increased, so that a 2-scan structure capable of driving 4 sub-pixels (normal 4 sub-pixels) in a DRD (double rate drive) manner can be formed.

[0014] Furthermore, according to the embodiments of the present disclosure, 4-sub-pixel operation can be used to achieve high-efficiency and high-brightness pixel operation, allowing the display panel to operate at a low power level.

[0015] Furthermore, according to the embodiments of the present disclosure, a display panel having an improved aperture ratio and convenient repair design can be provided.

[0016] Furthermore, according to an embodiment of the present disclosure, since the light emitting region generating white light is not continuous but disconnected, an image can be reproduced on a display panel without white horizontal or vertical stripes, thereby improving display quality.

[0017] Furthermore, according to an embodiment of the present disclosure, adjacent pixels may be operated alternately with each other in a 4-subpixel manner and a 3-subpixel manner to increase the brightness of an image reproduced on a display panel and improve a color gamut.

[0018] Furthermore, according to the embodiments of the present disclosure, the light emitting area of ​​the white sub-pixel can be increased without bending the wiring pattern.

[0019] Furthermore, according to an embodiment of the present disclosure, pixel circuits for driving sub-pixels emitting light of the same color are adjacent to each other in the horizontal direction without a light emitting region therebetween, thereby preventing a reduction in aperture ratio due to a repair pattern disposed therebetween.

[0020] Furthermore, according to the embodiments of the present disclosure, the color gamut can be improved, thereby enhancing the display quality and preventing the life of the display panel from being shortened.

[0021] Furthermore, according to embodiments of the present disclosure, improved display quality may lead to reduced power consumption and increased lifespan.

[0022] Furthermore, according to the embodiments of the present disclosure, reduced power consumption may lead to improved lifespan, thereby providing a long-life display device.

[0023] The display device according to the present disclosure can reduce power consumption to prevent the lifespan of the display panel from being reduced, and improve the display quality of the display device.

[0024] Effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art through the following description.

[0025] In addition to the above-described effects, while describing specific details for implementing the present disclosure, specific effects of the present disclosure are also described together.

[0026] Additional features, advantages, and aspects of the present disclosure are set forth in part in the following description and in part will become apparent from the present disclosure or may be learned by practicing the inventive concepts provided herein. Other features, advantages, and aspects of the present disclosure may be recognized and obtained through the description provided in the present disclosure, or may be derived from the description provided in the present disclosure, its claims, and the accompanying drawings. It is intended that all such features, advantages, and aspects be included in this description, be included within the scope of the present disclosure, and be protected by the appended claims. This section should not be construed as limiting the claims. Further aspects and advantages are discussed below in conjunction with the embodiments of the present disclosure.

[0027] It is to be understood that both the foregoing description and the following description of the present disclosure are examples, and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this disclosure, illustrate aspects and embodiments of the disclosure and together with the description serve to explain principles and examples of the disclosure.

[0029] Figure 1 is a diagram schematically illustrating a configuration of a display device according to an embodiment of the present disclosure.

[0030] Figure 2 is a diagram schematically illustrating a first pixel and a second pixel according to an embodiment of the present disclosure.

[0031] Figure 3 It is shown in detail as Figure 2 : An equivalent circuit diagram of an example of a pixel circuit shown in .

[0032] Figure 4 is a circuit diagram showing an example of a unit pixel circuit.

[0033] Figure 5 is a diagram showing light emitting areas of four pixels.

[0034] Figure 6 is a diagram illustrating an example of a hybrid driving method.

[0035] Figure 7 is a diagram illustrating an example in which gate lines are configured to form a dual scanning structure in a display panel according to an embodiment of the present disclosure.

[0036] Figure 8A 1 is a diagram illustrating an example in which the second power wiring RL and the first power wiring VL are interchanged in position with each other in the display panel according to the embodiment of the present disclosure.

[0037] Figure 8B is a diagram illustrating an example in which the width of the first power wiring VL is greater than the width of the second power wiring RL in the display panel according to the embodiment of the present disclosure.

[0038] Figure 9A is a diagram illustrating an example of arrangement of first scan lines and second scan lines in a display panel according to an embodiment of the present disclosure.

[0039] Figure 9B In the display panel according to an embodiment of the present disclosure, Figure 9A Magnified view of area A in FIG.

[0040] Figure 9C In the display panel according to an embodiment of the present disclosure, Figure 9B Magnified view of area B in FIG.

[0041] Figure 10 1 is a diagram illustrating an example of arrangement of gate lines and scan lines in the third light emitting region ER in the display panel according to an embodiment of the present disclosure.

[0042] Figure 11 is a display panel according to an embodiment of the present disclosure, along Figure 10 A cross-sectional view taken along line AA' in FIG.

[0043] Figure 12A is a diagram illustrating an example of arrangement of gate lines and scan lines in a display panel according to an embodiment of the present disclosure.

[0044] Figure 12B is a display panel according to an embodiment of the present disclosure, along Figure 12A Cross-sectional view taken along the BB' cutting line.

[0045] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The size, length, and thickness of layers, regions, and elements, as well as their descriptions, may be exaggerated for clarity, illustration, and / or convenience. DETAILED DESCRIPTION

[0046] The advantages and features of the present disclosure and the methods for achieving these advantages and features will be described with reference to the following and accompanying drawings. Figure 1 The embodiments described in detail below will become apparent. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in a variety of different forms. Therefore, these embodiments are set forth only to make the present disclosure complete and to fully inform those of ordinary skill in the art to which the present disclosure belongs, and the scope of the present disclosure is limited only by the scope of the claims.

[0047] For simplicity and clarity of explanation, the elements in the accompanying drawings are not necessarily drawn to scale. The same reference numerals in different figures represent the same or similar elements and therefore perform similar functions. In addition, in order to simplify the description, the description and details of well-known steps and elements are omitted. In addition, in the following detailed description of the present disclosure, many specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it should be understood that the present disclosure can be practiced without these specific details. In other cases, well-known methods, steps, components and circuits are not described in detail to avoid making various aspects of the present disclosure unnecessarily vague. Examples of various embodiments are further explained and described below. It will be understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present disclosure defined by the appended claims.

[0048] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing the embodiments of the present disclosure are exemplary, and the present disclosure is not limited thereto.

[0049] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one" and "an" are also intended to include plural forms, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprise", "include" and "contain" are used in this application, the existence of the features, integers, operations, elements and / or parts described is specified, but the existence or addition of one or more other features, integers, operations, elements, parts and / or parts thereof is not excluded. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. When an expression such as "at least one" is adjacent to a series of elements, the expression can modify the elements of the entire series and does not modify the individual elements in the series. When explaining a numerical value, even if it is not clearly described, errors or tolerances may occur therein.

[0050] Furthermore, it will be understood that when a first element or layer is referred to as being “on” a second element or layer, the first element or layer can be directly disposed on the second element or layer or can be indirectly disposed on the second element or layer with a third element or layer between the first and second elements or layers. It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, the element or layer can be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers can also be present. It will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers can also be present.

[0051] Furthermore, as used herein, when a layer, film, region, plate, etc. is disposed “on” or “on top of” another layer, film, region, plate, etc., the former may be in direct contact with the latter, or one or more layers, films, regions, plates, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly “on” or “on top of” another layer, film, region, plate, etc., the former is in direct contact with the latter and no further layer, film, region, plate, etc. is disposed between the former and the latter. Furthermore, as used herein, when a layer, film, region, plate, etc. is disposed “under” or “beneath” another layer, film, region, plate, etc., the former may be in direct contact with the latter, or another layer, film, region, plate, etc. may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, etc. is disposed directly “under” or “beneath” another layer, film, region, plate, etc., the former is in direct contact with the latter and no further layer, film, region, plate, etc. is disposed between the former and the latter.

[0052] When describing a temporal relationship, for example, a temporal precedence relationship between two events such as "after," "after," "before," etc., another event may occur between them unless "directly after," "directly after," or "directly before" is indicated.

[0053] When a certain embodiment can be implemented differently, the functions or operations specified in a particular block may occur in an order different from the order specified in the flow chart. For example, depending on the functions or operations involved, two consecutive blocks may actually be executed roughly simultaneously, or the two blocks may be executed in reverse order.

[0054] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section described below may be referred to as a second element, component, region, layer, or section without departing from the spirit and scope of the present disclosure.

[0055] The features of the various embodiments of the present disclosure can be combined with each other in part or in whole, and can be technically associated with each other or operate with each other. These embodiments can be implemented independently of each other, or can be implemented together in an associated relationship.

[0056] When interpreting numerical values, unless otherwise expressly stated, the values ​​are interpreted as including the error range.

[0057] It will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. Additionally, it will be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0058] Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present inventive concept belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0059] As used herein, "embodiments," "examples," "aspects," and the like should not be construed to render any described aspect or design preferred or advantageous over other aspects or designs. An embodiment is an example embodiment. An aspect is an example aspect. Unless otherwise indicated, an embodiment, an example, an example embodiment, an aspect, and the like may refer to one or more embodiments, one or more examples, one or more example embodiments, one or more aspects, and the like. Furthermore, the term "may" includes all meanings of the term "can."

[0060] Furthermore, the term “or” refers to an inclusive or rather than an exclusive or. For example, unless stated otherwise or clear from the context, the expression 'x employs a or b' refers to any of the natural inclusive permutations.

[0061] The terms used in the following description have been selected to be general and commonly used in the relevant technical fields. However, other terms may exist in accordance with the development and / or changes in technology, conventions, preferences of technicians, etc. Therefore, the terms used in the following description should not be understood as limiting the technical concept, but should be understood as examples of terms used to describe the embodiments.

[0062] In addition, in certain cases, the applicant may arbitrarily select terms, and in such cases, their detailed meanings will be described in the corresponding description section. Therefore, the terms used in the following description should not be simply understood based on the names of the terms, but should be understood based on the meanings of the terms and the content of the entire detailed description.

[0063] In the description of a signal flow, for example, when a signal is transmitted from node A to node B, unless the phrase “immediately transmitted” or “directly transmitted” is used, this may include a case where the signal is transmitted from node A to node B via another node.

[0064] Throughout this disclosure, unless otherwise specified, “A and / or B” means A, B, or A and B, and unless otherwise specified, “C to D” means C inclusive to D inclusive.

[0065] “At least one” should be understood to include any combination of one or more of the listed components. For example, at least one of the first component, the second component, and the third component refers not only to the first component, the second component, or the third component, but also to all combinations of two or more of the first component, the second component, and the third component.

[0066] Hereinafter, embodiments of the present disclosure will be described using the accompanying drawings. For ease of explanation, the proportions of each component shown in the accompanying drawings are different from their actual proportions, and therefore, the present disclosure is not limited to the proportions shown in the accompanying drawings.

[0067] Hereinafter, a display panel having an improved aperture ratio per pixel and a display device including the same according to some embodiments of the present disclosure will be described.

[0068] Figure 1 is a diagram schematically illustrating a configuration of a display device according to an embodiment of the present disclosure.

[0069] Reference Figure 1 A display device according to an embodiment of the present disclosure may include: a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driving circuit.

[0070] The display panel 100 may include a display area (active area) AA and a non-display (non-active area) NA.

[0071] The display panel 10 may include a substrate and a plurality of sub-pixels disposed on the substrate. In addition, the display panel 100 may further include various types of signal lines for driving the plurality of sub-pixels.

[0072] The display area AA may include a plurality of data lines DL transmitting data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL transmitting gate signals (also referred to as scan signals).

[0073] The plurality of data lines and the plurality of gate lines may intersect each other. Each of the plurality of data lines may extend in a second direction (Y direction). Each of the plurality of gate lines may extend in a first direction (X direction). In this regard, the first direction may be a row direction, and the second direction may be a column direction. Alternatively, the first direction may be a column direction, and the second direction may be a row direction.

[0074] The non-display area NA may be an area outside the display area AA and may include a frame area. All or a portion of the non-display area NA may be visible to a viewer in front of the display device, or may be an area that is curved backward and therefore not visible to a viewer in front of the display device.

[0075] The display panel 100 may be a panel having a rectangular structure having a length in the X-axis direction or the first direction, a width in the Y-axis direction or the second direction, and a thickness in the Z-axis direction or the third direction. The X-axis and the Y-axis may be linear axes orthogonal to each other and may define an XY plane. The display area AA of the display panel 100 includes a pixel array that displays an input image. The pixel array includes a plurality of data lines DL, a plurality of gate lines GL that intersect the data lines DL, and pixels arranged in a matrix form. The display panel 100 includes a power supply line commonly connected to the pixels. The power supply line may be connected to a constant voltage node of a pixel circuit and provide the pixel PXL with a constant voltage required to drive the pixel PXL. The power supply line may be implemented as a strip or grid wiring and may be commonly connected to the pixels of the display panel 100.

[0076] Each pixel PXL includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel for emitting light of different colors, respectively, for color display. The arrangement of the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel for emitting light of different colors, respectively, can be changed. The first sub-pixel can be a blue (B) sub-pixel, the second sub-pixel can be a green (G) sub-pixel, the third sub-pixel can be a red (R) sub-pixel, and the fourth sub-pixel can be a white (W) sub-pixel. However, the embodiments of the present disclosure are not limited to this. Each sub-pixel includes a pixel circuit for driving a light-emitting element. Each pixel circuit is connected to a data line, a gate line, and a power line. The area of ​​each sub-pixel can be divided into a circuit area and a light-emitting area. The pixel circuit is arranged in the circuit area. The light-emitting area is an area where light is emitted from a light-emitting element electrically connected to the pixel circuit.

[0077] The pixel array includes a plurality of pixel rows L1 to LN. Each pixel row L1 to LN includes a row of pixels arranged along the row direction (X-axis direction) of the pixel array of the display panel 100. The pixels arranged in a pixel row share the same gate line GL. Subpixels arranged in the column direction Y along the data line direction share the same data line DL. One horizontal period is equivalent to one frame period divided by the total number of pixel rows L1 to LN.

[0078] The power supply 140 uses a DC-DC converter to output voltages required to drive the pixels of the display panel 100 and the display panel driving circuit. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, and the like.

[0079] The display panel driving circuit writes pixel data of an input image into pixels of the display panel 100 under the control of the timing controller 130. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0080] The display panel driver circuit can drive pixels using a DRD (Double Rate Drive) scheme. In a display panel operating with the DRD scheme, data lines DL can be connected to adjacent sub-pixels in the left-right direction, thereby reducing the number of channels in the data driver 110 and the number of data lines DL. This helps ensure the pixel aperture ratio.

[0081] The display panel driving circuit may further include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted in FIG. The data driver 110 and the touch sensor driver may be integrated into one source driver IC (Integrated Circuit).

[0082] The data driver 110 receives pixel data of an input image as a digital signal from the timing controller 130 and outputs data voltages based on the pixel data. The data driver 110 may convert the pixel data of the input image into gamma-compensated data voltages using a DAC (digital-to-analog converter) and output the gamma-compensated data voltages during each frame period. The gamma-compensated data voltages are output from each channel of the data driver 110 via an output buffer.

[0083] The gate driver 120 and the TFT array and wiring of the pixel array may be formed in the display panel 100. The gate driver 120 may be disposed in the non-display area NA of the display panel 100, or at least a portion of the gate driver 120 may be disposed in the display area AA reproducing an input image.

[0084] The gate driver 120 may be disposed in a non-display area NA on each of opposite sides of the display panel 100, with the display area AA of the display panel 100 disposed between the gate drivers 120. The gate driver 120 may also be disposed at opposite ends of the gate lines GL, thereby supplying gate pulses to the gate lines GL using a dual-feed scheme. In another embodiment, the gate driver 120 may be disposed in either the left or right non-display area NA of the display panel 100 and may supply gate signals to the gate lines GL using a single-feed scheme. Under the control of the timing controller 130, the gate driver 120 sequentially outputs gate signal pulses to the gate lines. The gate driver 120 may sequentially supply gate signals to the gate lines GL by shifting the gate signal pulses (hereinafter referred to as gate pulses) using a shift register. The gate driver 120 may include a plurality of shift registers that output gate signal pulses.

[0085] The timing controller 130 receives digital video data of an input image and timing signals synchronized with the digital video data from the host system 200. Timing signals may include vertical synchronization signals, horizontal synchronization signals, a clock, and a data enable signal. Since the vertical and horizontal periods can be determined by counting the data enable signal, the vertical and horizontal synchronization signals may be omitted. The data enable signal has a duration of one horizontal period (1H). Based on the timing signals received from the host system 200, the timing controller 130 generates data timing control signals for controlling the operation timing of the data driver 110 and gate timing control signals for controlling the operation timing of the gate driver 120.

[0086] The timing controller 130 may add white data to the three-primary color pixel data RGB input from the host system to obtain four sub-color data RGBW, and transmit the four sub-color data RGBW to the data driver 110. A method for converting the three-primary color pixel data RGB into four sub-color data RGBW including white data may include a known color conversion algorithm. For example, the timing controller 130 may generate W data for the first pixel data based on the minimum grayscale value among the grayscale values ​​of the R data, G data, and B data by mixing the R data, G data, and B data of the first pixel data received as input image data, and may convert the primary color pixel data RGB into four sub-color data RGBW based on the generated W data. Furthermore, the timing controller 130 may generate W data for the second pixel data received as input image data by mixing the R data, G data, and B data of the second pixel data received as input image data, and may convert the primary color pixel data RGB into four sub-color data RGBW based on the generated W data. Therefore, in each of the first pixel data and the second pixel data, the grayscale values ​​of the R, G, and B data may be lowered by the grayscale value of the W data. In this regard, the R data may be data to be written to the red sub-pixel, the G data may be data to be written to the green sub-pixel, the B data may be data to be written to the blue sub-pixel, and the W data may be data to be written to the white sub-pixel.

[0087] The level shifter 150 may receive a gate timing control signal from the timing controller 130, generate a start pulse and a shift clock based on the gate timing control signal, and provide the start pulse and the shift clock to the gate driver 120. The start pulse and the shift clock output from the level shifter 150 swing between a gate high voltage and a gate low voltage.

[0088] The host system 200 may include a mainboard of any one of a TV system, a set-top box, a navigation system, a personal computer (PC), a vehicle system, a mobile terminal, and a wearable terminal. The host system may scale the image signal from the video source to match the resolution of the display panel 100 and transmit the scaled image signal along with a timing signal to the timing controller 130.

[0089] The display device according to some embodiments of the present disclosure may be a liquid crystal display device, etc., or may be a self-luminous display device including a self-luminous display panel 100. When the display device according to some embodiments of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels may include a light-emitting element.

[0090] For example, the display device according to some embodiments of the present disclosure may be an organic light-emitting display device in which the light-emitting elements are implemented as organic light-emitting diodes (OLEDs). In another example, the display device 100 according to some embodiments of the present disclosure may be an inorganic light-emitting display device in which the light-emitting elements are implemented as inorganic-based light-emitting diodes. In yet another example, the display device 100 according to some embodiments of the present disclosure may be a quantum dot display device in which the light-emitting elements are implemented as quantum dots, which are self-luminous semiconductor crystals.

[0091] The structure of each of the plurality of sub-pixels may vary depending on the type of display device. For example, when the display device 100 is a self-luminous display device in which the sub-pixels themselves emit light, each sub-pixel may include a self-luminous element, one or more transistors, and one or more capacitors.

[0092] For not only image display function but also touch sensing function, the display device according to some embodiments of the present disclosure may include: a touch sensor for sensing a touch of a touch panel by a touch object such as a finger or a pen; and a touch sensing circuit configured to detect the presence or absence of a touch, or a touch position based on a sensing result from the touch sensor.

[0093] The touch sensing circuit may include a touch driving circuit that drives the touch sensor to generate and output touch sensing data, and a touch controller that may detect a touch occurrence or a touch position using the touch sensing data.

[0094] The touch sensor may include a plurality of touch electrodes and may further include a plurality of touch lines to electrically connect the plurality of touch electrodes and the touch driving circuit.

[0095] The touch sensor may be provided in the form of a touch panel, and may be provided outside the display panel 100 , or may be provided inside the display panel 100 .

[0096] When a touch sensor is provided in the form of a panel outside the display panel 100, the touch sensor may be referred to as an external touch sensor. When the touch sensor is implemented as an external touch sensor, the touch panel and the display panel 100 may be manufactured separately and may be combined with each other during the assembly process. The external touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0097] When the touch sensor exists inside the display panel 100 , the touch sensor and signal lines and electrodes related to display driving may be formed on the substrate SUB during a manufacturing process of the display panel 100 .

[0098] The touch driving circuit may supply a touch driving signal to at least one of the plurality of touch electrodes to sense a touch on the touch panel to generate touch sensing data and may receive the touch sensing data therefrom.

[0099] The touch sensing circuit may perform touch sensing using a self-capacitance sensing scheme or a mutual-capacitance sensing scheme.

[0100] When the touch sensing circuit performs touch sensing using a self-capacitance sensing scheme, the touch sensing circuit may perform touch sensing based on capacitance between each touch electrode and a touch object such as a finger or a touch pen.

[0101] According to the self-capacitance sensing scheme, each of the multiple touch electrodes can serve as a driving touch electrode and a sensing touch electrode. The touch driving circuit can drive all or some of the multiple touch electrodes and can receive touch sensing data from all or some of the multiple touch electrodes.

[0102] When the touch sensing circuit performs touch sensing using a mutual capacitance sensing scheme, the touch sensing circuit may perform touch sensing based on capacitance between touch electrodes.

[0103] According to the mutual capacitance sensing scheme, a plurality of touch electrodes can be divided into driving touch electrodes and sensing touch electrodes. A touch driving circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0104] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate components or may be integrated into a single component. In addition, the touch driving circuit and the data driver 110 may be implemented as separate components or may be integrated into a single component.

[0105] The display device according to some embodiments of the present disclosure may be included in a mobile terminal device, such as a smart phone and a tablet computer, or a display or television of various sizes. However, the embodiments of the present disclosure are not limited thereto. The display device according to some embodiments of the present disclosure may be of various types and sizes capable of displaying information or images.

[0106] Figure 2 2 is a diagram schematically illustrating a first pixel and a second pixel according to an embodiment of the present disclosure. Pixels of a display panel may be arranged such that the first pixel and the second pixel are repeatedly arranged.

[0107] Reference Figure 2 The display panel 100 may include first and second pixels PXL1 and PXL2 that are arranged in a mirror-symmetrical structure around the Y axis and are adjacent to each other in the X axis direction as a first direction.

[0108] Each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel, a second sub-pixel, and a third sub-pixel for emitting light of different colors, respectively.

[0109] The first pixel PXL1 and the second pixel PXL2 may share a plurality of white sub-pixels.

[0110] The display panel 100 includes: a first data line pair DL10 arranged on the left side of the first pixel PXL1 and extending in the Y-axis direction; a second data line pair DL20 arranged between the first pixel PXL1 and the second pixel PXL1 and extending in the Y-axis direction; a third data line pair DL30 arranged on the right side of the second pixel PXL2 and extending in the Y-axis direction; a first power line PL10 arranged between the first data line pair DL10 and the second data line pair DL20 and extending in the Y-axis direction; and a second power line PL20 arranged between the second data line pair DL20 and the third data line pair DL30 and extending in the Y-axis direction.

[0111] Each of the first power lines PL10 and the second power lines PL20 may include a plurality of first power lines VL to which a pixel drive voltage EVDD is applied, and a second power line RL to which a reference voltage Vref is applied. The plurality of first power lines VL may be disposed on opposite sides of the second power line RL and connected to each other. Each of the plurality of first power lines VL may be wider than the second power line RL.

[0112] exist Figure 2In the embodiment, the first vertical reference line VR1 is an imaginary line parallel to the Y-axis direction and disposed between the first data line pair DL10 and the first power line PL10. The second vertical reference line VR2 is an imaginary line parallel to the Y-axis direction and disposed between the first power line PL10 and the second data line pair DL20. The third vertical reference line VR3 is an imaginary line parallel to the Y-axis direction and disposed between the second data line pair DL20 and the second power line PL20. The fourth vertical reference line VR4 is an imaginary line parallel to the Y-axis direction and disposed between the second power line PL20 and the third data line pair DL30.

[0113] First pixel PXL1 includes a blue subpixel, a green subpixel, and a red subpixel arranged along the Y-axis, such that a virtual first vertical reference line VR1 and a virtual second vertical reference line VR2 extend through the blue, green, and red subpixels. Second pixel PXL2 includes a blue subpixel, a green subpixel, and a red subpixel arranged along the Y-axis, such that a virtual third vertical reference line VR3 and a virtual fourth vertical reference line VR4 extend through the blue, green, and red subpixels. The blue subpixels of first pixel PXL1 and second pixel PXL2 are separated and spaced apart from each other. The green subpixels of first pixel PXL1 and second pixel PXL2 are separated and spaced apart from each other. The red subpixels of first pixel PXL1 and second pixel PXL2 are separated and spaced apart from each other. Independent R data can be written separately to first pixel PXL1 and second pixel PXL2. Independent G data can be written separately to first pixel PXL1 and second pixel PXL2. Independent B data can be written separately to first pixel PXL1 and second pixel PXL2.

[0114] The first pixel PXL1 and the second pixel PXL2 share a white sub-pixel, and the emission area EW of the white sub-pixel includes an area where the second and third vertical reference lines VR2 and VR3 intersect with a virtual fourth horizontal reference line HR4 .

[0115] Each of the first pixel PXL1 and the second pixel PXL2 can be operated in a 4-subpixel mode or a 3-subpixel mode. In the 4-subpixel mode, the 4 subpixels include a red subpixel, a green subpixel, a blue subpixel, and a shared white subpixel. In the 3-subpixel mode, the 3 subpixels include a red subpixel, a green subpixel, and a blue subpixel, but do not include a white subpixel.

[0116] When the first pixel PXL1 operates in a 4-subpixel mode, W data generated based on the R, G, and B data of the first pixel PXL1 is written to the white subpixel. When the second pixel PXL2 operates in a 4-subpixel mode, W data generated based on the R, G, and B data of the second pixel PXL2 is written to the white subpixel.

[0117] Each of the first pixel PXL1 and the second pixel PXL2 can operate in a hybrid mode. For example, when the first pixel PXL1 operates in a 4-subpixel mode, the second pixel PXL2 can operate in a 3-subpixel mode. When the second pixel PXL2 operates in a 4-subpixel mode, the first pixel PXL1 can operate in a 3-subpixel mode.

[0118] The timing controller 130 can analyze whether the input image is based on a pure color or analyze the saturation of the input image. When the saturation is greater than or equal to a predetermined reference value, the timing controller 130 can control the first pixel PXL1 and the second pixel PXL2 to operate simultaneously in a three-subpixel manner. In this case, the white subpixel does not operate.

[0119] The blue subpixel includes a first pixel circuit CB and a first light-emitting region EB connected to the first pixel circuit CB and emitting blue light. The green subpixel includes a second pixel circuit CG and a second light-emitting region EG connected to the second pixel circuit CG and emitting green light. The red subpixel includes a third pixel circuit CR and a third light-emitting region ER connected to the third pixel circuit CR and emitting red light. The white subpixel includes fourth pixel circuits CW1 and CW2, respectively disposed in the first and second pixels, and fourth light-emitting regions EW1 and EW2, respectively disposed in the first and second pixels and connected to the fourth pixel circuits CW1 and CW2, and emitting white light. The anode electrode of the light-emitting element EL may be disposed in each of the light-emitting regions EB, EG, ER, EW1, and EW2. Each of the pixel circuits CB, CG, CR, CW1, and CW2 may be connected to the anode electrode of a corresponding one of the light-emitting regions EB, EG, ER, EW1, and EW2. When current is generated by the driver element of the pixel circuit, the light-emitting region may emit light. The 4-1st light-emitting region EW1 is connected to the 4-1st pixel circuit CW1. The 4-2 th light emitting region EW2 is connected to the 4-2 th pixel circuit CW2 .

[0120] In the white sub-pixel, the fourth light emitting regions EW1 and EW2 may be operated under the control of two fourth pixel circuits CW1 and CW2, respectively. Figure 3 As shown in , the 4-1st pixel circuit CW1 and the 4-2nd pixel circuit CW2 may be connected to different gate lines, may sequentially receive gate pulses, and may drive light emitting elements of white sub-pixels.

[0121] In this regard, the fourth light emitting region EW may be formed as follows. Figure 2At this point, the fourth light emitting region EW includes fourth light emitting regions EW1 and EW2, and the fourth light emitting regions EW1 and EW2 include a 4-1st light emitting region EW1 and a 4-2nd light emitting region EW2 located in the first pixel PXL1 and the second pixel PLX2, respectively.

[0122] However, the embodiments of the present disclosure are not limited thereto. Figure 5 As shown in FIG, only one fourth light emitting region EW may be provided in the combination of the first pixel PXL1 and the second pixel PLX2. Only one fourth light emitting region EW may be provided in the combination of the third pixel PXL3 and the fourth pixel PXL4.

[0123] Or, as Figure 6 As shown in FIG, only one fourth light emitting region EW may be provided in only one of the first pixel PXL1 and the second pixel PLX2. Only one fourth light emitting region EW may be provided in only one of the third pixel PXL3 and the fourth pixel PXL4.

[0124] In the first pixel PXL1, the first pixel circuit CB, the left portion of the first emission region EB, the left portion of the second emission region EG, the second pixel circuit CG, and the left portion of the third emission region ER are arranged in this order along the first vertical reference line VR1.

[0125] In the first pixel PXL1, the 4-1st pixel circuit CW1, the right portion of the first light-emitting region EB, the right portion of the second light-emitting region EG, the third pixel circuit CR, the right portion of the third light-emitting region ER, and the 4-1st light-emitting region EW1 are arranged in this order along the second vertical reference line VR2.

[0126] In the second pixel PXL2, the 4-2nd pixel circuit CW2, the left portion of the first light-emitting region EB, the left portion of the second light-emitting region EG, the third pixel circuit CR, the left portion of the third light-emitting region ER, and the 4-2nd light-emitting region EW2 are arranged in this order along the third vertical reference line VR3.

[0127] In the second pixel PXL2, the first pixel circuit CB, the right portion of the first emission region EB, the right portion of the second emission region EG, the second pixel circuit CG, and the right portion of the third emission region ER are arranged in this order along the fourth vertical reference line VR4.

[0128] The arrangement of the different-colored light-emitting regions in first pixel PXL1 along the Y-axis direction can be similar to the arrangement of the different-colored light-emitting regions in second pixel PXL2 along the Y-axis direction. The light-emitting regions of the same color in first pixel PXL1 and second pixel PXL2 are arranged along the X-axis direction. For example, the first light-emitting regions EB of first pixel PXL1 and second pixel PXL2 are arranged along and overlap with a virtual first horizontal reference line HR1 parallel to the X-axis direction. The second light-emitting regions EG of first pixel PXL1 and second pixel PXL2 are arranged along and overlap with a virtual second horizontal reference line HR2 below the first light-emitting region EB in the Y-axis direction and parallel to the X-axis direction. The upper portions of the third light-emitting regions ER of first pixel PXL1 and second pixel PXL2 are arranged along and overlap with a virtual third horizontal reference line HR3 below the second light-emitting region EG in the Y-axis direction and parallel to the X-axis direction. The lower portions of the third emission regions ER of the first and second pixels PXL1 and PXL2, as well as the fourth emission regions EW1 and EW2, are arranged along a virtual fourth horizontal reference line HR4 below the third horizontal reference line HR3 in the Y-axis direction. In this regard, the first to fourth horizontal reference lines HR1 to HR4 are arranged in this order along the Y-axis direction. To improve the color gamut, the size of the third emission region ER, which generates red light, may be larger than each of the first and second emission regions EB and EG.

[0129] The fourth light emitting area EW generating white light is not continuous in the display panel 100 and is therefore provided in a disconnected or discontinuous manner on a pixel basis. This prevents white horizontal or vertical stripes from being visible to viewers when the entire display area AA of the display panel 100 displays a single color or a specific grayscale.

[0130] The third light-emitting region ER may be an L-shaped region with a quarter corner removed from the rectangle. The upper portion of the third light-emitting region ER in the column direction includes a smaller portion 20 adjacent to the upper end of the fourth light-emitting region EW in the column direction. The fourth light-emitting region EW is located within an area defined by removing a portion of the lower portion of the third light-emitting region ER of the first pixel PXL1 (overlapping with portion 20 in the column direction) and a portion of the lower portion of the third light-emitting region ER of the second pixel PXL1 (overlapping with portion 20 in the column direction), which are arranged in a mirror-symmetrical manner around the second data line pair DL20. In a plan view, the upper, left, and right sides of the combined fourth light-emitting regions EW1 and EW2 are surrounded by the third light-emitting regions ER of the first and second pixels PXL1 and PXL2. The third and fourth pixels PXL3 and PXL4 are arranged along the X-axis. The third and first pixels PXL1 are arranged along the Y-axis. The fourth and second pixels PXL4 are arranged along the Y-axis. That is, the first emission regions EB of the third pixel PXL3 and the fourth pixel PXL4 are respectively disposed below the fourth emission regions EW1 and EW2 of the first pixel PXL1 and the second pixel PXL2. The third pixel PXL3 and the fourth pixel PXL4 are adjacent to each other in the X-axis direction. Therefore, the fourth emission regions EW1 and EW2 of the first pixel PXL1 and the second pixel PXL2 are not adjacent to the fourth emission regions EW1 and EW2 of the third pixel PXL3 and the fourth pixel PXL4.

[0131] Power lines PL10 and PL20 can supply the constant voltage required to drive pixels PXL1 and PX2 to the pixel circuits CB, CG, CR, CW1, and CW2. The pixel drive voltage can be applied to the EVDD power line VL, and the reference voltage can be applied to the REF power line RL. The REF power line RL is arranged between the EVDD power lines VL, which have a relatively large width. The EVDD power line VL is connected to the adjacent pixel circuits CB, CG, CR, CW1, and CW2 and supplies the pixel drive voltage to the pixel circuits CB, CG, CR, CW1, and CW2. The REF power line RL can be arranged in the non-display area NA. The REF power line RL can be connected to the adjacent pixel circuits CB, CG, CR, CW1, and CW2 and supplies the pixel drive voltage to the pixel circuits CB, CG, CR, CW1, and CW2.

[0132] In each of the first pixel PXL1 and the second pixel PXL2, the power lines VL and RL may extend across the first light-emitting region EB, the second light-emitting region EG, and the third light-emitting region ER in a manner overlapping the first light-emitting region EB, the second light-emitting region EG, and the third light-emitting region ER. The power lines VL and RL may bypass the fourth light-emitting regions EW1 and EW2 and not overlap with the fourth light-emitting regions EW1 and EW2.

[0133] The first data line pair DL10 includes a first data line DLB1 to which a data voltage for B data is applied, and a second data line DLG1 to which a data voltage for G data is applied. The first data line DLB1 is positioned between the first pixel PXL1 and a pixel adjacent to it in the X-axis direction, and is commonly connected to the first pixel circuits CB of the first pixel PXL1 and the adjacent pixel. The first data line DLB1 supplies the data voltage for B data to the first pixel PXL1 and the adjacent pixel. The second data line DLG1 is positioned between the first pixel PXL1 and a pixel adjacent to it in the X-axis direction, and is commonly connected to the second pixel circuits CG of the first pixel PXL1 and the adjacent pixel. The second data line DLG1 supplies the data voltage for G data to the first pixel PXL1 and the adjacent pixel.

[0134] The first data line DLB1 is connected to a plurality of first pixel circuits CB arranged along the Y-axis direction. The first data line DLB1 transmits the data voltage for the B data to be written from the data driver 110 to the first pixel circuit CB. Only the data voltage for the B data is applied to the first data line DLB1. The second data line DLG1 is connected to a plurality of second pixel circuits CG arranged along the Y-axis direction. The second data line DLG1 transmits the data voltage for the G data to be written from the data driver 110 to the second pixel circuit CG. Only the data voltage for the G data is applied to the second data line DLG1.

[0135] The second data line pair DL20 includes a third data line DLR to which a data voltage of R data is applied, and a fourth data line DLW to which a data voltage of W data is applied. While the third data line DLR is disposed between the pixels PXL1 and PXL2, the third data line DLR is commonly connected to the third pixel circuits CR of the first pixel PXL1 and the second pixel PXL2 adjacent thereto in the X-axis direction, and while the third data line DLR is disposed between the pixels PXL1 and PXL2, the third data line DLR transmits the data voltage of R data to the third pixel circuits CR of the first pixel PXL1 and the second pixel PXL2 adjacent thereto in the X-axis direction. While the fourth data line DLW is disposed between the pixels PXL1 and PXL2, the fourth data line DLW is commonly connected to the fourth pixel circuits CW1 and CW2 of the first pixel PXL1 and the second pixel PXL2 adjacent thereto in the X-axis direction, and while the fourth data line DLW is disposed between the pixels PXL1 and PXL2, the fourth data line DLW transmits the data voltage of the W data to the fourth pixel circuits CW1 and CW2 of the first pixel PXL1 and the second pixel PXL2 adjacent thereto in the X-axis direction.

[0136] The third data line DLR is connected to a plurality of third pixel circuits CR arranged along the Y-axis direction. The third data line DLR transmits the data voltage for R data to be written from the data driver 110 to the third pixel circuits CR. Only the data voltage for R data is applied to the third data line DLR. The fourth data line DLW is connected to a plurality of fourth pixel circuits CW1 and CW2 arranged along the Y-axis direction. The fourth data line DLW transmits the data voltage for W data to be written from the data driver 110 to the fourth pixel circuits CW1 and CW2 for white subpixels. Only the data voltage for W data is applied to the fourth data line DLW.

[0137] The second data line pair DL20 extends through and overlaps the fourth emission region EW. The second data line pair DL20 may bypass other emission regions EB, EG, and ER and all pixel circuits CB, CG, CR, CW1, and CW2 so as not to overlap therewith.

[0138] The third data line pair DL30 includes a fifth data line DLB2 to which a data voltage for B data is applied, and a sixth data line DLG2 to which a data voltage for G data is applied. The fifth data line DLB2 receives only the data voltage for B data supplied from the data driver 110 to the blue subpixel. The sixth data line DLG2 receives only the data voltage for G data supplied from the data driver 110 to the green subpixel. While the fifth data line DLB2 is disposed between the second pixel PXL2 and a pixel adjacent thereto in the X-axis direction, the fifth data line DLB2 is commonly connected to the first pixel circuit CB of the second pixel PXL2 and the adjacent pixel. Furthermore, while the fifth data line DLB2 is disposed between the second pixel PXL2 and a pixel adjacent thereto in the X-axis direction, the fifth data line DLB2 supplies the data voltage for B data to the second pixel PXL2 and the first pixel circuit CB of the adjacent pixel. While the sixth data line DLG2 is arranged between the second pixel PXL2 and the pixel adjacent to it in the X-axis direction, the sixth data line DLG2 is commonly connected to the second pixel PXL2 and the second pixel circuit CG of the adjacent pixel, and while the sixth data line DLG2 is arranged between the second pixel PXL2 and the pixel adjacent to it in the X-axis direction, the sixth data line DLG2 supplies the data voltage of G data to the second pixel PXL2 and the second pixel circuit CG of the adjacent pixel.

[0139] A plurality of gate lines may extend along the first direction or the X-axis direction. Two gate lines sandwiching two light emitting regions (EB and EG or ER and EW) that respectively emit light of different colors and are adjacent to each other in the second direction Y may be connected to each other.

[0140] Each of the gate lines may extend along each pixel circuit row, and two gate lines adjacent to each other in the second direction Y may be commonly connected to a single output terminal of the gate driver 120. Figure 2 and Figure 3 As shown in , two gate lines sandwiching two light emitting areas that respectively emit light of different colors and are adjacent to each other in the second direction Y may be connected to each other and to a single output terminal of the gate driver 120. Therefore, a gate pulse may be applied to two pixel circuit rows at the same time. The n-th gate line GLn may simultaneously apply a gate pulse to the pixel circuits CB, CG, CR, CW1, and CW2 distributed on the two pixel circuit rows. Figure 2 , the connection between the pixel circuit CW2 and the n-th gate line GLn is omitted. Gate pulses may be sequentially applied to the gate lines GLn-1 to GLn+2 in the following order: GLn-1, GLn, GLn+1, and GLn+2.

[0141] Each of the scan lines SCn and SCn+1 for driving only the sensor transistor T2 of each of the first pixel PXL1 and the second pixel PXL2 may be disposed between two light emitting regions (EB and EG or ER and EW) that respectively emit light of different colors and between two gate lines GLn connected to each other.

[0142] That is, the nth scan line SCn may be disposed between the first and second emission regions EB and EG, respectively emitting light of different colors. The n+1th scan line SCn+1 may be disposed between the third and fourth emission regions ER and EW1 and EW2, respectively emitting light of different colors.

[0143] For example, in each of the first pixel PXL1 and the second pixel PXL2, the nth scan line SCn may be disposed between a first light emitting region EB and a second light emitting region EG that respectively emit light of different colors arranged along the Y-axis direction, and may be disposed between two gate lines of the nth gate line GLn extending in the first direction.

[0144] In addition, in each of the first pixel PXL1 and the second pixel PXL2, the n+1th scan line SCn+1 can be set between the third light-emitting region ER and the fourth light-emitting regions EW1 and EW2, which respectively emit light of different colors arranged along the Y-axis direction, and can be set between the two gate lines of the n+1th gate line GLn+1 extending in the first direction.

[0145] The first to third light emitting regions EB, EG, and ER of the first pixel PXL1 and the first to third light emitting regions EB, EG, and ER of the second pixel PXL2 may be arranged around the second data line pair DL20 in a mirror-symmetrical manner to each other.

[0146] The fourth emission regions EW1 and EW2 may be disposed between the third emission region ER of the first pixel PXL1 and the third emission region ER of the second pixel PXL2 arranged along the first direction X. The third emission region ER may constitute a third subpixel, and the fourth emission regions EW1 and EW2 may constitute a white subpixel.

[0147] The size of the light-emitting area of ​​each sub-pixel emitting light of different colors can be appropriately set based on the color gamut and high brightness. For example, in an image model or display model that prioritizes high brightness over color gamut, the size of the light-emitting area of ​​the fourth light-emitting area EW can be larger, and the driving voltage of each of the three sub-pixels except the white sub-pixel can be increased. Figure 2The structure of the third and fourth light-emitting regions ER and EW shown in the figure makes it easy to expand or reduce the size of the fourth light-emitting region EW in an elongated manner extending parallel to a horizontal reference line. Therefore, without changing the wiring shape, the sizes of the third and fourth light-emitting regions ER and EW can be easily controlled. In a display model that prioritizes pure colors (i.e., color gamut over high brightness), the size of the fourth light-emitting region EW can be reduced. To increase brightness, the size of the fourth light-emitting region EW can be increased.

[0148] Figure 3 It is shown in detail as Figure 2 : An equivalent circuit diagram of an example of a pixel circuit shown in . Figure 4 is a circuit diagram showing a unit pixel circuit.

[0149] Reference Figure 3 and Figure 4 Each of the pixel circuits CB, CG, CR, CW1 and CW2 is connected to a data line DL to which a data voltage Vdata of pixel data is applied, a gate line GL to which a gate pulse SCAN is applied, a power line VL to which a pixel driving voltage EVDD is applied, a power line to which a cathode voltage EVSS is applied, and a REF power line RL to which a reference voltage Vref is applied.

[0150] In the display panel 100 , a plurality of gate lines extend along a first direction, and two gate lines sandwiching two light emitting regions that respectively emit light of different colors and are adjacent to each other in a second direction Y may be connected to each other.

[0151] The display panel 100 has an nth scan line SCn and an n+1th scan line SCn+1, the nth scan line SCn is arranged between a first light-emitting region EB and a second light-emitting region EG, which respectively emit light of different colors and are adjacent to each other in the second direction Y, and the n+1th scan line SCn+1 is arranged between a third light-emitting region ER and fourth light-emitting regions EW1 and EW2, which respectively emit light of different colors and are adjacent to each other in the second direction Y.

[0152] Each of the nth scan line SCn and the (n+1)th scan line SCn+1 may be configured to apply a scan signal SCAN to drive only the sensor transistor T2 of each of the first pixel PXL1 and the second pixel PXL2 .

[0153] Each of the pixel circuits CB, CG, CR, CW1, and CW2 includes: a plurality of transistors DT, T1, and T2; and a capacitor C.

[0154] Each light-emitting region may include a light-emitting element EL, which may be implemented as an organic light-emitting diode (OLED) or an inorganic light-emitting element such as a Micro LED. The light-emitting element EL may include, but is not limited to, a red light-emitting element, a green light-emitting element, and a blue light-emitting element. The anode electrode of the light-emitting element EL is connected to the driving element DT and is disposed in the corresponding light-emitting region of each pixel. The light-emitting element EL operates based on the current generated by the driving element DT to emit light. Thus, light is guided out of the display panel 100 through the light-emitting region.

[0155] The driving element DT generates a current at a gate-source voltage to drive the light-emitting element EL. The driving element DT includes a gate electrode connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. A capacitor C is connected to the first node N1 and the third node N3 and is disposed between the first node N1 and the third node N3. The second node N2 is connected to an EVDD power supply line VL. The third node N3 is connected to the anode electrode of the light-emitting element EL. The cathode electrode of the light-emitting element EL is connected to a power supply line to which a cathode voltage EVSS is applied.

[0156] The first switching element T1 is connected to the data line DL and the first node N1 and is disposed between the data line DL and the first node N1. The first switching element T1 can be, for example, a scan transistor. The first switching element T1 is turned on in response to a gate pulse SCAN. When the first switching element T1 is turned on, a data voltage Vdata of the pixel data is applied to the first node N1, so that the pixel data is written to the subpixel. The first switching element T1 includes a gate electrode connected to the gate line GL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1.

[0157] The second switching element T2 is connected to the third node N3 and the REF power line RL and is disposed between the third node N3 and the REF power line RL. The second switching element T2 may be, for example, a sensor transistor. The second switching element T2 is turned on in response to a gate pulse SCAN. When the second switching element T2 is turned on, the third node N3 is connected to the REF power line RL. The second switching element T2 includes a gate electrode connected to each of the scan lines SCn and SCn+1, a first electrode connected to the third node N3, and a second electrode connected to the REF power line RL.

[0158] The driving elements DT of all sub-pixels should have consistent electrical characteristics. However, due to process variations and component characteristic variations, the electrical characteristics of the driving elements DT of the sub-pixels may differ. These differences may increase as the operating time of each sub-pixel increases. To compensate for the differences in the electrical characteristics of the driving elements DT of the sub-pixels, an external compensation circuit may be applied to the display panel driver circuit.

[0159] exist Figure 3 For example, the nth scan line SCn may be connected to the gate electrode of the sensor transistor T2 of the first pixel circuit CB. The driving element DT may be connected to the first electrode of the sensor transistor T2 of the first pixel circuit CB. The REF power line RL may be connected to the second electrode of the sensor transistor T2 of the first pixel circuit CB.

[0160] In addition, the (n+1)th scan line SCn+1 is connected to the gate electrode of the sensor transistor T2 of the second pixel circuit CG. The driving element DT can be connected to the first electrode of the sensor transistor T2 of the second pixel circuit CG. The REF power line RL can be connected to the second electrode of the sensor transistor T2 of the second pixel circuit CG.

[0161] The external compensation circuit senses the electrical characteristics of the driving element DT in real time and compensates for the electrical characteristics of the driving element DT based on the sensing results in a sensing mode. The sensing mode may include a sensing mode before product shipment and a sensing mode after product shipment. In the sensing mode before product shipment, the external compensation circuit senses the electrical characteristics of the driving element DT in each sub-pixel via the REF power line RL connected to each sub-pixel and compensates for differences in the electrical characteristics of the driving element DT in each sub-pixel based on the sensing results.

[0162] The sensing mode after product shipment may include an ON RF mode performed in a power-up sequence, an RT mode performed during a vertical blank period of a display driving period, and an OFF RS mode performed in a power-down sequence.

[0163] In ON RF mode, when the display device is powered on, the external compensation circuit senses the mobility of the driver element DT, which drives the light-emitting element, via the REF power line RL in each subpixel. The external compensation circuit compares the mobility sensing result with the mobility compensation value of the driver element in each subpixel measured before product shipment, and updates the mobility compensation value based on the comparison result. In the pre-product sensing mode, the threshold voltage and mobility of the driver element DT in each subpixel are sensed, and the threshold voltage compensation value and mobility compensation value for the driver element are set in a lookup table. The external compensation circuit compensates the mobility of the driver element in each subpixel using the mobility compensation value based on the mobility sensing result of the driver element in each subpixel.

[0164] In RT mode, during the vertical blank period VB of each frame period during the display drive period in which an image is displayed, the external compensation circuit senses the mobility of the driving element DT of each subpixel in real time through the REF power line RL, and updates the mobility compensation value in each subpixel based on the mobility sensing result. The vertical blank period is a period between the active period of the N-1th frame period and the active period of the Nth frame period, during which no data is input to the timing controller 130.

[0165] In the OFF RS mode, when the display device is powered off, the external compensation circuit senses the threshold voltage of the driving element DT in each subpixel via the REF power line RL and updates the threshold voltage compensation value of the driving element DT in each subpixel based on the threshold voltage sensing result. In the OFF RS mode, the display panel drive circuit and the external compensation circuit operate for a preset delay time before power is completely turned off. The external compensation circuit senses the threshold voltage of the driving element DT in each subpixel and updates the threshold voltage compensation value of the driving element DT in each subpixel based on the threshold voltage sensing result.

[0166] The external compensation circuit includes an analog-to-digital converter (ADC) electrically connected to the REF power line (RL) and a compensation circuit for compensating the ADC data. The compensation circuit's lookup table stores compensation values ​​for compensating the threshold voltage and mobility of the driver element driving the light-emitting element in each subpixel. The compensation circuit inputs sensing data output from the ADC into the lookup table and adds or multiplies the compensation value output from the lookup table with the pixel data of the input image to modulate the pixel data to compensate for variations in the electrical characteristics of the driver element. The ADC can be provided in each sensing channel group in the data driver 110 integrated with the source driver IC. The compensation circuit can be implemented as a logic circuit in the timing controller 130.

[0167] Figure 5 is a diagram showing light emitting areas of four pixels. Figure 6 is a diagram illustrating an example of a hybrid driving method.

[0168] Reference Figure 5 and Figure 6 The third pixel PXL3 and the fourth pixel PXL4 having substantially the same structure as the first pixel PXL1 and the second pixel PXL2 are arranged in the Y-axis direction with the first pixel PXL1 and the second pixel PXL2, respectively.

[0169] like Figure 6 As shown in FIG, the first to fourth pixels PXL1 to PXL4 may be operated in a mixed manner. The first to fourth pixels PXL1 to PXL4 may be operated alternately with each other in a 4-subpixel and a 3-subpixel manner on a predetermined time basis. For example, Figure 6As shown in FIG, during the odd frame period FRodd, each of the first pixel PXL1 and the fourth pixel PXL4 may operate in a 4-subpixel manner, and each of the second pixel PXL2 and the third pixel PXL3 may operate in a 3-subpixel manner. Figure 6 As shown in FIG, during an even frame period FReven, each of the first pixel PXL1 and the fourth pixel PXL4 can operate in a 3-subpixel mode, and each of the second pixel PXL2 and the third pixel PXL3 can operate in a 4-subpixel mode. When the first pixel PXL1 operates in a 4-subpixel mode, W data written to the white subpixel can be generated based on the R, G, and B data of the first pixel PXL1. When the second pixel PXL2 operates in a 4-subpixel mode, W data written to the white subpixel can be generated based on the R, G, and B data of the second pixel PXL2. When the third pixel PXL3 operates in a 4-subpixel mode, W data written to the white subpixel can be generated based on the R, G, and B data of the third pixel PXL3. When the fourth pixel PXL4 operates in a 4-subpixel mode, W data written to the white subpixel can be generated based on the R, G, and B data of the fourth pixel PXL4.

[0170] Figure 7 is a diagram illustrating an example in which gate lines are configured to form a dual scanning structure in a display panel according to an embodiment of the present disclosure.

[0171] Reference Figure 7 In the display panel 100 according to an embodiment of the present disclosure, a plurality of gate lines extend along the first direction. Two gate lines sandwiching two light-emitting regions EB and EG, or ER and EW, which emit light of different colors and are adjacent to each other in the second direction Y, may be connected to each other, thereby forming a dual scanning structure.

[0172] In this regard, the power supply line may include a first power supply wiring VL to which the pixel driving voltage EVDD is applied, and a plurality of second power supply wirings RL respectively provided on opposite sides of the first power supply wiring VL.

[0173] In this regard, the width of the first power wiring VL may be greater than the width of each of the plurality of second power wirings RL.

[0174] In the display panel 100 according to an embodiment of the present disclosure, in each of the first pixel PXL1 and the second pixel PXL2, the nth scan line SCn may be arranged between a first light-emitting region EB and a second light-emitting region EG, which respectively emit light of different colors, arranged along the Y-axis direction, and between two gate lines of the nth gate line GLn extending in the first direction.

[0175] In addition, in each of the first pixel PXL1 and the second pixel PXL2, the n+1th scan line SCn+1 can be set between the third light-emitting region ER and the fourth light-emitting regions EW1 and EW2, which are arranged along the Y-axis direction and emit light of different colors, respectively, and set between the two gate lines of the n+1th gate line GLn+1 extending in the first direction.

[0176] That is, the display panel 100 may have the n-th scan line SCn and the (n+1)-th scan line SCn+1 for driving only the sensor transistor T2 of each of the first pixel PXL1 and the second pixel PXL2 .

[0177] Figure 8A 1 is a diagram illustrating an example in which the second power wiring RL and the first power wiring VL are interchanged in position with each other in the display panel according to the embodiment of the present disclosure. Figure 8B is a diagram illustrating an example in which the width of the first power wiring VL is greater than the width of the second power wiring RL in the display panel according to the embodiment of the present disclosure.

[0178] Reference Figure 8A In the display panel 100 according to an embodiment of the present disclosure, a plurality of first power wirings VL to which the pixel driving voltage EVDD is applied may be respectively provided on opposite sides of a second power wiring RL to which the reference voltage Vref is applied.

[0179] The plurality of first power wirings VL may be respectively provided on opposite sides of the second power wiring RL and may be connected to each other.

[0180] Reference Figure 8B , the width of each of the plurality of first power wirings VL may be greater than the width of the second power wiring RL.

[0181] In this regard, in the display panel 100 , two gate lines sandwiching two light emitting regions EB and EG or ER and EW respectively emitting light of different colors and adjacent to each other in the second direction Y may be connected to each other, thereby forming a dual scanning structure.

[0182] However, in the display panel 100 , since a wiring for driving the sensor transistor T2 must pass through the opening area, a reduction in aperture ratio may occur.

[0183] Therefore, to compensate for this disadvantage, the display panel 100 may have an arrangement in which the second power wiring RL and the first power wiring VL are interchanged in position, so that a plurality of first power wirings VL may be respectively disposed on opposite sides of the second power wiring RL.

[0184] Therefore, each sensor transistor T2 can be provided between each of the first power wirings VL and the second power wiring RL. Therefore, the result obtained by operating each sensor transistor T2 can be transmitted to the common second power wiring RL.

[0185] Figure 9A is a diagram illustrating an example of arrangement of first scan lines and second scan lines in a display panel according to an embodiment of the present disclosure. Figure 9B In the display panel according to an embodiment of the present disclosure, Figure 9A Magnified view of area A in FIG. Figure 9C In the display panel according to an embodiment of the present disclosure, Figure 9B Magnified view of area B in FIG.

[0186] Reference Figure 9A According to an embodiment of the present disclosure, the display panel 100 has an nth scan line SCn arranged between a first light-emitting region EB and a second light-emitting region EG, which respectively emit light of different colors and are adjacent to each other in the second direction Y, and an n+1th scan line SCn+1 arranged between a third light-emitting region ER and fourth light-emitting regions EW1 and EW2, which respectively emit light of different colors and are adjacent to each other in the second direction Y.

[0187] For example, in each of the first pixel PXL1 and the second pixel PXL2, the nth scan line SCn may be disposed between the first light-emitting region EB and the second light-emitting region EG, which respectively emit light of different colors, arranged along the Y-axis direction, and may be disposed between two gate lines of the nth gate line GLn extending in the first direction.

[0188] In addition, in each of the first pixel PXL1 and the second pixel PXL2, the n+1th scan line SCn+1 can be set between the third light-emitting region ER and the fourth light-emitting regions EW1 and EW2 arranged along the Y-axis direction, which respectively emit light of different colors, and can be set between the two gate lines of the n+1th gate line GLn+1 extending in the first direction.

[0189] In addition, the n+1th scan line SCn+1, which is arranged between the third light-emitting region ER and the fourth light-emitting regions EW1 and EW2, which respectively emit light of different colors and are adjacent to each other in the second direction Y, can be divided into two parts extending to surround the contact hole overlapping with the second power wiring RL in the area between the first pixel PXL1 and the second pixel PXL2.

[0190] Reference Figure 9BIn the region A, the n-th scan line SCn, which is disposed between the first light-emitting region EB and the second light-emitting region EG, which respectively emit light of different colors and are adjacent to each other in the second direction Y, may be divided into two portions extending to surround the contact hole overlapping with the second power wiring RL to which the reference voltage Vref is applied, in the region B between the first pixel PXL1 and the second pixel PXL2. Then, the two portions of the n-th scan line SCn divided in the region B between the first pixel PXL1 and the second pixel PXL2 are merged into one scan line in the second pixel PXL2, which extends in the first direction X while being disposed between the first light-emitting region EB and the second light-emitting region EG of the second pixel PXL2.

[0191] Reference Figure 9B , a connecting line in region B may be directed toward one side in the second direction Y ( Figure 9B The upper side thereof extends from the first sub-pixel EB and may be connected to a source node 910 of the driving transistor DT of the first sub-pixel B in the first emission region EB.

[0192] In addition, another connection line in the region B may be directed toward the other side in the second direction Y ( Figure 9B The transistor DT extends from the lower side of the third sub-pixel R in the third emission region ER and may be connected to the source node 920 of the driving transistor DT of the third sub-pixel R in the third emission region ER.

[0193] Reference Figure 9C , the two parts of the n-th scan line SCn divided in the region B between the first pixel PXL1 and the second pixel PXL2 may include two opposite parts in the second direction Y. At this point, one of the two opposite parts in the second direction Y ( Figure 9C The upper portion in the middle) may overlap with the sensor transistor 912 of the first sub-pixel B in the first light-emitting region EB and the second power wiring RL.

[0194] In addition, the other of the two opposing portions in the second direction Y ( Figure 9C The lower portion in the third sub-pixel (the lower portion in the third light emitting region ER) may overlap with the sensor transistor 922 of the third sub-pixel R and the second power wiring RL.

[0195] Figure 10 1 is a diagram illustrating an example of arrangement of gate lines and scan lines in the third light emitting region ER in the display panel according to an embodiment of the present disclosure. Figure 11 is a display panel according to an embodiment of the present disclosure, along Figure 10 A cross-sectional view taken along line AA' in FIG.

[0196] Reference Figure 10 and Figure 11In the display panel 100 according to an embodiment of the present disclosure, the nth gate line GLn extends in the first direction X and is disposed on one of the two opposite sides of the third light emitting region ER in the second direction Y ( Figure 10 The n+1th scan line SCn+1 extends in the first direction X and is disposed on the other of the two opposite sides in the second direction Y of the third light emitting region ER ( Figure 10 on the lower side of the center).

[0197] In this regard, the display panel 100 may include a light shielding layer 103 on a substrate 101 , a buffer layer 105 disposed on the substrate 101 and the light shielding layer 103 , and a gate insulating layer GI and a semiconductor layer ACT disposed on the buffer layer 105 .

[0198] The semiconductor layer ACT may be a semiconductor layer of the driving transistor DT, and may be implemented as an oxide semiconductor layer made of IGZO.

[0199] The light shielding layer 103 may vertically overlap the semiconductor layer 153 or the channel region of the driving transistor DT. The light shielding layer 103 may be made of a metal such as copper (Cu) and not only blocks external light but also connects to other electrodes or circuits and serves as an electrode constituting a capacitor.

[0200] The portion of semiconductor layer 153 corresponding to each of the source and drain regions, excluding the portion corresponding to the channel region, may be made conductive and serve as metal electrode 111 or wiring (metallization). The process of making the source / drain regions conductive may use O2 plasma or an etching process. However, embodiments of the present disclosure are not limited thereto.

[0201] A metal electrode (e.g., made of MoTi) 109 may be provided on the semiconductor layer ACT. A gate insulating layer GI (e.g., made of SiO 2 ) may be provided on the metal electrode 109, and a gate metal GM may be provided on the gate insulating layer GI. The gate metal GM may be made of a metal such as copper (Cu).

[0202] An insulating layer 107 may be disposed on the gate metal GM. A red pigment corresponding to the third light emitting region ER and an overcoat layer OC may be disposed on the insulating layer 107. The overcoat layer OC may include an organic material.

[0203] The anode electrode AE ​​may be disposed on the overcoat layer OC and connected to the gate metal GM via a contact hole. The anode electrode AE ​​may include ITO (Indium Tin Oxide).

[0204] The light emitting layer OLED may be disposed on the anode electrode AE. The cathode electrode CE may be disposed on the light emitting layer OLED. The cathode electrode CE may include a metal such as aluminum (Al).

[0205] Figure 12A is a diagram showing an example of arrangement of gate lines and scan lines in a display panel according to an embodiment of the present disclosure, and Figure 12B is a display panel according to an embodiment of the present disclosure, along Figure 12A Cross-sectional view taken along the BB' cutting line.

[0206] Reference Figure 12A and Figure 12B The display panel 100 according to an embodiment of the present disclosure includes a light shielding layer 103 disposed on a substrate 101 and a buffer layer 105 disposed on the light shielding layer 103 .

[0207] An electrode region 111 and a semiconductor region ACT constituting the drive transistor DT may be disposed on the buffer layer 105, and a gate insulating layer GI may be disposed on the electrode region 111 and the semiconductor region ACT. A metal electrode (e.g., made of MoTi) 109 may be disposed on the electrode region 111. The metal electrode 109 may be a source electrode or a drain electrode.

[0208] The semiconductor region ACT may be the semiconductor region of the drive transistor DT and may be implemented as an oxide semiconductor layer made of IGZO. Portions corresponding to each of the source and drain regions adjacent to the semiconductor region ACT may be made conductive and serve as the metal region 111 or wiring (metallization). The process of making the source and drain regions conductive may use O2 plasma or an etching process. However, embodiments of the present disclosure are not limited thereto.

[0209] The driving transistor DT may be disposed on a portion of the gate insulating layer GI overlapping the semiconductor region ACT.

[0210] On the remaining portion of the gate insulating layer GI, an nth gate line GLn, an nth scan line SCn, an n-1th gate line GLn-1, and a gate metal GM may be disposed.

[0211] An insulating layer 107 may be disposed on the driving transistor DT, the nth gate line GLn, the nth scan line SCn, the (n-1)th gate line GLn-1, and the gate metal GM.

[0212] A first light emitting region EB and a second light emitting region EG may be disposed on the insulating layer 107. The first light emitting region EB and the second light emitting region EG may be adjacent to each other.

[0213] An overcoat layer OC may be disposed on the first and second light emitting regions EB and EG.

[0214] An anode electrode AE ​​may be provided on the overcoat layer OC. The anode electrode AE ​​may include ITO (indium tin oxide). A plurality of anode electrodes AE may be provided on the overcoat layer OC in a manner corresponding to the first light emitting region EB and the second light emitting region EG, respectively.

[0215] A bank layer BK may be disposed on the overcoat layer OC and a portion of the anode electrode AE.

[0216] The light emitting layer OLED may be disposed on the anode electrode AE ​​and the bank layer BK. The cathode electrode CE may be disposed on the light emitting layer OLED. The cathode electrode CE may include a metal such as aluminum (Al).

[0217] As described above, according to an embodiment of the present disclosure, a display panel can be provided, in which two gate lines sandwich two light-emitting areas that emit light of different colors respectively and the two gate lines are connected to each other, and each scanning line used only to drive the sensor transistor of each pixel is arranged between the two light-emitting areas that emit light of different colors respectively and between the two gate lines connected to each other.

[0218] Furthermore, according to an embodiment of the present disclosure, a display device including the above-mentioned display panel may be provided.

[0219] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments, but can be implemented in various different forms. It will be understood by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or essential features of the present disclosure. Therefore, it should be understood that the above-described embodiments are not restrictive in all aspects, but illustrative. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical features within their equivalent scope should be interpreted as included within the scope of the present disclosure.

Claims

1. A display panel, comprising: First pixel; as well as a second pixel, the second pixel being adjacent to the first pixel in a first direction, wherein the first pixel and the second pixel each include a first sub-pixel, a second sub-pixel, and a third sub-pixel for respectively emitting light of different colors, wherein the first pixel and the second pixel share a plurality of white sub-pixels, Each of the first sub-pixels includes a first pixel circuit and a first light emitting region connected to the first pixel circuit, wherein each of the second sub-pixels includes a second pixel circuit and a second light emitting region connected to the second pixel circuit, wherein each of the third sub-pixels includes a third pixel circuit and a third light emitting region connected to the third pixel circuit, Each of the white sub-pixels includes a fourth pixel circuit and a fourth light emitting region connected to the fourth pixel circuit. wherein a plurality of gate lines extend along the first direction and are arranged in a second direction intersecting the first direction, wherein two light emitting regions for respectively emitting light of different colors and adjacent to each other in the second direction are arranged between two gate lines of the plurality of gate lines, wherein the two gate lines are connected to each other, Each of the scan lines is provided between two light emitting regions for respectively emitting light of different colors and adjacent to each other in the second direction, wherein each of the scan lines is configured to drive only the sensor transistors of each of the first pixel and the second pixel.

2. The display panel according to claim 1, wherein the scan lines include an nth scan line arranged between the first light-emitting area and the second light-emitting area for respectively emitting light of different colors, and an n+1th scan line arranged between the third light-emitting area and the fourth light-emitting area for respectively emitting light of different colors.

3. The display panel according to claim 1 , wherein the first to third light emitting regions of the first pixel are arranged in a mirror-symmetrical manner with the first to third light emitting regions of the second pixel, and The fourth light emitting region arranged along the first direction is disposed between the third light emitting region of the first pixel and the third light emitting region of the second pixel arranged along the first direction.

4. The display panel according to claim 1 , wherein the display panel further comprises a power supply line for supplying a constant voltage to the first to fourth pixel circuits, Each of the power lines extends along the second direction to overlap with a corresponding first light emitting area, a corresponding second light emitting area, and a corresponding third light emitting area.

5. The display panel according to claim 4 , wherein each of the power lines comprises: a plurality of first power supply wirings for receiving pixel driving voltages; and a second power supply wiring for receiving a reference voltage, wherein the plurality of first power supply wirings are provided on opposite sides of the second power supply wiring and are connected to each other, wherein a width of each of the plurality of first power wirings is greater than a width of the second power wiring.

6. The display panel according to claim 4 , wherein the display panel further comprises a plurality of data line pairs for supplying data voltages of pixel data to the first to fourth pixel circuits, wherein the plurality of data line pairs include a first data line pair and a second data line pair, The first data line pair includes: a first data line extending in the second direction and connected to a plurality of first pixel circuits arranged along the second direction; and a second data line extending in the second direction and connected to a plurality of second pixel circuits arranged along the second direction, The second data line pair includes: a third data line extending in the second direction and connected to a plurality of third pixel circuits arranged along the second direction; and A fourth data line extends in the second direction and is connected to a plurality of fourth pixel circuits arranged along the second direction. 7 . The display panel of claim 6 , wherein the second data line pair extends to overlap an area between the fourth light emitting areas.

8. The display panel according to claim 1, wherein the fourth light emitting area comprises: a 4-1st light-emitting region, the 4-1st light-emitting region being adjacent to the third light-emitting region in the first pixel in the second direction; and The 4-2 luminous region is adjacent to the third luminous region in the second pixel in the second direction.

9. The display panel according to claim 8, wherein the fourth pixel circuit comprises: a 4-1st pixel circuit, the 4-1st pixel circuit being connected to the 4-1st light emitting region; and The 4-2 pixel circuit is connected to the 4-2 light-emitting area. 10 . The display panel of claim 9 , wherein the 4 - 1st pixel circuit and the 4 - 2nd pixel circuit are connected to different gate lines and are configured to sequentially receive gate pulses from the different gate lines.

11. The display panel according to claim 8, wherein the 4-1st light emitting area has two opposite sides in the first direction and two opposite sides in the second direction, wherein the 4-2 luminous region has two opposite sides in the first direction and two opposite sides in the second direction, wherein one of the two opposite sides of the 4-1st light emitting region in the first direction and one of the two opposite sides in the second direction are connected to each other and are surrounded by the third light emitting region in the first pixel, One of two opposite sides of the 4-2 light emitting region in the first direction and one of two opposite sides in the second direction are connected to each other, and are surrounded by the third light emitting region in the second pixel. 12 . The display panel of claim 1 , wherein the first sub-pixel is a blue sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a red sub-pixel.

13. A display device comprising: A display panel comprising a plurality of data lines, a plurality of gate lines, a plurality of power lines and a plurality of pixels; a data driver configured to convert pixel data into a data voltage and supply the data voltage to the data line; a gate driver configured to sequentially supply gate pulses to the gate lines; as well as a timing controller configured to transmit the pixel data to the data driver and control the data driver and the gate driver, The plurality of pixels include: First pixel; as well as a second pixel, the second pixel being adjacent to the first pixel in a first direction, wherein the first pixel and the second pixel each include a first sub-pixel, a second sub-pixel, and a third sub-pixel for emitting light of different colors, respectively; wherein the first pixel and the second pixel share a plurality of white sub-pixels, Each of the first sub-pixels includes a first pixel circuit and a first light emitting region connected to the first pixel circuit, wherein each of the second sub-pixels includes a second pixel circuit and a second light emitting region connected to the second pixel circuit, wherein each of the third sub-pixels includes a third pixel circuit and a third light emitting region connected to the third pixel circuit, Each of the white sub-pixels includes a fourth pixel circuit and a fourth light emitting region connected to the fourth pixel circuit. wherein the plurality of gate lines extend along the first direction and are arranged in a second direction intersecting the first direction, wherein two light emitting regions for respectively emitting light of different colors and adjacent to each other in the second direction are arranged between two gate lines of the plurality of gate lines, wherein the two gate lines are connected to each other, Each of the scan lines is provided between two light emitting regions for respectively emitting light of different colors and adjacent to each other in the second direction, wherein each of the scan lines is configured to drive only the sensor transistors of each of the first pixel and the second pixel.

14. The display device according to claim 13, wherein the scan lines include an nth scan line and an (n+1)th scan line, wherein the n-th scan line is provided between the first light emitting region and the second light emitting region, which respectively emit light of different colors and are adjacent to each other in the second direction, and the n-th scan line is divided into two portions, in the region between the first pixel and the second pixel, extending so as to surround a contact hole overlapping with a second power wiring for applying a reference voltage among the plurality of power lines, wherein the n+1th scan line is arranged between the third light-emitting area and the fourth light-emitting area, which are respectively used to emit light of different colors and are adjacent to each other in the second direction, and the n+1th scan line is divided into two parts extending to surround the contact hole overlapping with the second power wiring in the area between the first pixel and the second pixel.

15. The display device according to claim 14 , wherein a plurality of first power wirings for applying pixel driving voltages among the plurality of power wirings are respectively provided on opposite sides of the second power wiring and connected to each other, wherein the width of each of the plurality of first power wirings is greater than the width of the second power wiring, Each of the plurality of first power supply wirings has a narrow width in a region between the first pixel and the second pixel, and overlaps with two divided portions of each of the nth scan line and the (n+1)th scan line.

Images