Display device

Abstract

The display device includes: a display panel including a plurality of first row output pads and a plurality of second row output pads; and a driving chip including a plurality of first row output bumps and a plurality of second row output bumps. Each of the first row of output pads and the second row of output pads includes a plurality of first output pads and a plurality of second output pads alternately arranged with the first output pads. Each of the first row of output bumps and the second row of output bumps includes a plurality of first output bumps and a plurality of second output bumps, the second output pads are disposed shifted by a predetermined distance from the first output pads in the second direction, and the second output bumps are disposed shifted by the predetermined distance from the first output bumps in the second direction.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device having a driver chip mounted on a substrate. Background Art

[0002] Various display devices have been developed for use in multimedia devices such as televisions, mobile phones, tablet computers, navigation systems, and game consoles. These display devices include multiple electronic components. These components may include display panels, driver chips, and circuit boards. These electronic components are electrically connected using various methods. Summary of the Invention

[0003] An object of the present invention is to provide a display device including a driver chip that does not cause cracks or damage on a substrate during installation.

[0004] According to one embodiment of the present invention, a display device is provided, comprising: a display panel including a plurality of first-row output pads and a plurality of second-row output pads, the plurality of first-row output pads being arranged along a first direction, and the plurality of second-row output pads being spaced apart from the plurality of first-row output pads by a first distance in a second direction intersecting the first direction; and a driver chip including a plurality of first-row output bumps and a plurality of second-row output bumps, the plurality of first-row output bumps being arranged along the first direction and connected to the first-row output pads, and the plurality of second-row output bumps being spaced apart from the plurality of first-row output bumps in the second direction and connected to the second-row output pads, the second distance being greater than or equal to the first distance. Each of the first-row output pads and the second-row output pads comprises: a plurality of first output pads aligned along the first direction; and a plurality of second output pads aligned along the first direction, arranged alternately with the first output pads along the first direction, and shifted from the first output pads by a fourth distance in the second direction. Each of the first row of output bumps and the second row of output bumps includes: a plurality of first output bumps aligned along the first direction and connected to the first output pads respectively; and a plurality of second output bumps aligned along the first direction and connected to the second output pads respectively, and configured to be shifted a third distance from the first output bumps in the second direction.

[0005] A display device may be provided in which the fourth distance is smaller than the first distance.

[0006] A display device may be provided in which the third distance is smaller than the second distance.

[0007] A display device may be provided in which the fourth distance is equal to or smaller than the third distance.

[0008] A display device may be provided, wherein the first output pad of the first row of output pads is aligned with the first output pad of the second row of output pads in the second direction, and the second output pad of the first row of output pads is aligned with the second output pad of the second row of output pads in the second direction.

[0009] A display device may be provided, wherein the display panel further includes: a plurality of pixels; and a plurality of signal lines connecting the pixels to the first row of output pads and the second row of output pads. The signal lines include: a first signal line group arranged between adjacent first and second output pads in the same row; and a second signal line group separated from the first signal line group by the second output pad in the first direction. Each of the first and second signal line groups includes: a first signal line connected to one of the first and second output pads; and a second signal line electrically insulated from the first signal line.

[0010] A display device may be provided, wherein each of the plurality of signal lines includes: a first line portion parallel to the second direction; a second line portion parallel to the second direction and spaced apart from the first line portion in the second direction; and a connecting portion connecting the first line portion and the second line portion and inclined relative to the first direction and the second direction, wherein the second line portion is displaced from the first line portion in the first direction.

[0011] A display device may be provided in which the connection portions of the signal lines of the first signal line group and the connection portions of the signal lines of the second signal line group are aligned along the first direction.

[0012] A display device may be provided, wherein each of the plurality of pixels includes: a first transistor including a first gate; and a second transistor including a second gate configured on a different layer from the first gate. The first signal line and the first gate are configured on the same layer, and the second signal line and the second gate are configured on the same layer.

[0013] A display device can be provided in which the first signal line does not overlap with the second signal line in a plane.

[0014] A display device may be provided, further comprising a contact portion, the contact portion penetrating the insulating layer disposed on the first output pad and connected to the first output pad, the first output bump being electrically connected to the first output pad via the contact portion.

[0015] A display device may be provided, wherein each of the first and second signal line groups further includes a third signal line electrically insulated from the second signal line and separated from the first signal line via the second signal line. Each of the first to third signal lines includes the first line portion, the second line portion, and the connecting portion, the second line portion being displaced from the first line portion in the first direction. The first line portion or the second line portion of the third signal line further includes an inclined portion displaced from the connecting portion of the third signal line in the first direction.

[0016] A display device may be provided, wherein the connecting portions of the first signal line to the third signal line are aligned in the first direction, and the fourth distance is greater than or equal to the first distance.

[0017] A display device may be provided, wherein the display panel further includes a plurality of input pads spaced apart from the second row of output pads in the second direction and arranged along the first direction, and the driver chip further includes a plurality of input bumps spaced apart from the second row of output bumps in the second direction and connected to the input pads. The input bumps include: a plurality of first input bumps aligned along the first direction; and a plurality of second input bumps aligned along the first direction, alternately arranged with the first input bumps along the first direction, and displaced from the first input bumps in the second direction by a fifth distance.

[0018] A display device may be provided, wherein the input pads include: a plurality of first input pads aligned along the first direction and electrically connected to the first input bumps; and a plurality of second input pads aligned along the first direction and electrically connected to the second input bumps, wherein the second input pads are arranged to be shifted from the first input pads by a sixth distance in the second direction.

[0019] A display device may be provided in which the sixth distance is less than or equal to the fifth distance.

[0020] According to one embodiment of the present invention, a display device is provided, which includes: a display panel, including a plurality of first-row output pads, a plurality of second-row output pads and a plurality of input pads, the plurality of first-row output pads are respectively arranged along a first direction, the plurality of second-row output pads are respectively separated from the plurality of first-row output pads by a first distance in a second direction intersecting the first direction, and the plurality of input pads are separated from the second-row output pads in the second direction and arranged along the first direction; and a driving chip, including a plurality of first-row output bumps, a plurality of second-row output bumps and a plurality of input bumps, the plurality of first-row output bumps are arranged along the first direction and connected to the first-row output pads, the plurality of second-row output bumps are separated from the plurality of first-row output bumps in the second direction by a second distance and connected to the second-row output pads, the second distance is greater than or equal to the first distance, and the plurality of input bumps are separated from the plurality of second-row output bumps in the second direction and connected to the input pads. Each of the first row of output bumps and the second row of output bumps includes: a plurality of first output bumps aligned along the first direction; and a plurality of second output bumps aligned along the first direction, alternately arranged with the first output bumps along the first direction, and displaced from the first output bumps by a third distance in the second direction. The input bumps include: a plurality of first input bumps aligned along the first direction; and a plurality of second input bumps aligned along the first direction, alternately arranged with the first input bumps along the first direction, and displaced from the first input bumps in the second direction.

[0021] A display device may be provided, wherein each of the first row of output pads and the second row of output pads includes: a plurality of first output pads aligned along the first direction and electrically connected to the first output bump; and a plurality of second output pads aligned along the first direction, alternately arranged with the first output pads along the first direction, and electrically connected to the second output bump. The second output pads are arranged to be shifted from the first output pads by a fourth distance in the second direction.

[0022] A display device may be provided, wherein the input pads include: a plurality of first input pads aligned along the first direction and electrically connected to the first input bumps; and a plurality of second input pads aligned along the first direction and electrically connected to the second input bumps, wherein the second input pads are arranged to be shifted from the first input pads in the second direction.

[0023] (Effects of the Invention)

[0024] According to the display device of one embodiment of the present invention, the driving chip is safely mounted on the substrate without causing cracks or damage on the substrate.

[0025] According to an embodiment of the present invention, the display device can be miniaturized and manufacturing costs can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1A FIG. 1 is a perspective view of a display device according to an embodiment of the present invention.

[0027] Figure 1B It is an exploded perspective view of a display device according to an embodiment of the present invention.

[0028] Figure 2A and Figure 2B is a cross-sectional view of a display device according to an embodiment of the present invention.

[0029] Figure 3A FIG. 1 is a top view of a display panel according to an embodiment of the present invention.

[0030] Figure 3B FIG. 4 is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0031] Figure 4 FIG. 1 is an exploded perspective view of a bonding region of a display device according to an embodiment of the present invention.

[0032] Figure 5 FIG. 1 is a top view of a chip region of a display device according to an embodiment of the present invention.

[0033] Figure 6A and Figure 6B This is a schematic diagram showing an enlarged portion of a chip region of a display device according to an embodiment of the present invention.

[0034] Figure 7 This is a schematic diagram showing an enlarged portion of a chip region of a display device according to an embodiment of the present invention.

[0035] Figures 8A to 8C FIG. 1 is an enlarged plan view of a portion of a pad region of a display device according to an embodiment of the present invention.

[0036] Figure 8D and Figure 8E This is an enlarged cross-sectional view of a portion of a pad region of a display device according to an embodiment of the present invention.

[0037] Figures 9A to 9C FIG. 1 is an enlarged plan view of a portion of a pad region of a display device according to an embodiment of the present invention.

[0038] Figure 10FIG. 1 is an enlarged plan view of a portion of a pad region of a display device according to an embodiment of the present invention.

[0039] Figure 11 FIG. 1 is a top view of a chip region of a display device according to an embodiment of the present invention.

[0040] Figure 12A and Figure 12B FIG. 1 is an enlarged plan view of a portion of a pad region of a display device according to an embodiment of the present invention.

[0041] Figure 13 FIG. 1 is a top view of a chip region of a display device according to an embodiment of the present invention.

[0042] Description of Reference Signs

[0043] DD: display device; DP: display panel; DC: driver chip; PD: pad; PB:

[0044] Bump; OPD: output pad; IPD: input pad; OPB: output bump; IPB: input bump; SGL: signal line DETAILED DESCRIPTION

[0045] In this specification, when it is mentioned that a certain structural element (or region, layer, part, etc.) is "above" another structural element, "connected" or "combined with" another structural element, it means that the certain structural element can be directly configured / connected / combined above the other structural element, or a third structural element can be configured between them.

[0046] The same reference numerals denote the same structural elements. Furthermore, in the accompanying drawings, the thicknesses, ratios, and sizes of the structural elements are exaggerated for effective illustration of the technical content. "And / or" includes all combinations of more than one possible combination of related structural elements.

[0047] Terms such as first and second can be used to describe various structural elements, but the structural elements are not limited to the terms. The terms are used only to distinguish one structural element from other structural elements. For example, within the scope of the claims of the present invention, a first structural element may be referred to as a second structural element, and similarly, a second structural element may be referred to as a first structural element. Unless the context clearly indicates a different meaning, a singular expression includes a plural expression.

[0048] Furthermore, terms such as “below,” “lower side,” “above,” and “upper side” are used to describe the relationship between components shown in the drawings. These terms are relative and are described based on the directions shown in the drawings.

[0049] Terms such as “including” or “having” should be understood as intending to specify the existence of the features, numbers, steps, actions, structural elements, parts or their combinations recorded in the specification, and are not intended to preclude the existence or additional possibilities of one or more other features, numbers, steps, actions, structural elements, parts or their combinations.

[0050] Unless defined differently, all terms (including technical and scientific terms) used in this specification have the same meanings as those commonly understood by those skilled in the art to which the present invention pertains. Furthermore, terms that are the same as those defined in commonly used dictionaries should be interpreted as having meanings consistent with those in the context of the relevant technology, and unless explicitly defined, should not be interpreted as having overly idealized or overly formalized meanings.

[0051] Hereinafter, a display panel and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0052] Figure 1A is a perspective view of a display device according to an embodiment of the present invention, Figure 1B It is an exploded perspective view of a display device according to an embodiment of the present invention.

[0053] In this specification, a mobile phone terminal is illustrated as an example of a display device DD. The display device DD of the present invention is applicable not only to large electronic devices such as televisions and monitors, but also to small and medium-sized electronic devices such as tablet PCs, car navigation systems, game consoles, and smart watches.

[0054] Reference Figure 1A and Figure 1B The display device DD can display an image IM via its display surface DD-IS. An example of the image IM is an icon image. The display surface DD-IS can be parallel to a plane defined by the first direction DR1 and the second direction DR2. The normal direction of the display surface DD-IS and the thickness direction of the display device DD can be parallel to the third direction DR3.

[0055] The display surface DD-IS may include a display area DD-DA for displaying an image IM and a non-display area DD-NDA adjacent to the display area DD-DA. The non-display area DD-NDA may be an area where no image is displayed. However, this is not limiting, and the non-display area DD-NDA may be adjacent to a side of the display area DD-DA or may be omitted.

[0056] In this specification, "when viewed from a plane or on a plane" may refer to viewing from a third direction DR3. The front (or upper) and back (or lower) surfaces of each layer or unit described below may be distinguished by the third direction DR3. However, this is not limiting, and the combination of the first to third directions DR1, DR2, and DR3 may be changed to other combinations.

[0057] Furthermore, the display device DD may include a window WM, a display module DM, and a receiving member BC. Although not shown, the display device DD may further include an optical member disposed between the window WM and the display module DM. The optical member may include a polarizer.

[0058] The window WM can be positioned above the display module DM and allows the image provided by the display module DM to be transmitted externally. The window WM can include a transmissive area TA and a non-transmissive area NTA. The transmissive area TA can overlap with the display area DD-DA and have a shape corresponding to the display area DD-DA. The window WM can include a base layer and functional layers disposed on the base layer. The functional layers can include a protective layer, an anti-fingerprint layer, etc. The base layer of the window WM can be made of glass, sapphire, or plastic.

[0059] The non-transmission area NTA may overlap with the non-display area DD-NDA and may have a shape corresponding to the non-display area DD-NDA. The non-transmission area NTA may be a region having a relatively low light transmittance compared to the transmissive area TA. The non-transmission area NTA may be defined by configuring a frame pattern on a portion of the base layer of the window WM, and the region not configured with the frame pattern may be defined as the transmissive area TA. However, the technical concept of the present invention is not limited to this, and the non-transmission area NTA may be omitted.

[0060] According to an embodiment of the present invention, the display panel DP may be one of a liquid crystal display panel, an electrophoretic display panel, a microelectromechanical system display panel, an electrowetting display panel, an organic light emitting display panel, an inorganic light emitting display panel, and a quantum dot light emitting display panel, without particular limitation. Hereinafter, the display panel DP may be described as an organic light emitting display panel.

[0061] The input sensor ISU may include a capacitive sensor, an optical sensor, an ultrasonic sensor, or an electromagnetic induction sensor. The input sensor ISU may be formed on the display panel DP through a continuous process, or may be manufactured separately and then attached to the upper side of the display panel DP via an adhesive layer. The embodiment is not limited to one embodiment.

[0062] Figure 2A and Figure 2B is a cross-sectional view of a display device according to an embodiment of the present invention.

[0063] Reference Figure 2A In one embodiment, a display device DD may include a driver chip DC and a circuit board CF. While the driver chip DC is shown as being mounted on a display panel DP, the present invention is not limited thereto. The driver chip DC may generate driving signals required for the operation of the display panel DP based on control signals transmitted from the circuit board CF.

[0064] The circuit board CF electrically bonded to the display panel DP may be disposed on the back of the display panel DP. Figure 1B ) can accommodate the display device DD and is associated with the window WM (see Figure 1B ) combined. The circuit board CF can be disposed at one end of the base substrate SUB and electrically connected to the circuit component layer DP-CL. Although not shown, the electronic device may further include a mainboard, an electronic module mounted on the mainboard, a camera module, a power module, etc.

[0065] The display panel DP of an embodiment may include: a curved area BA; a first non-curved area NBA1 and a second non-curved area NBA2 spaced apart from each other in a third direction DR3 with the curved area BA interposed therebetween.

[0066] The bending area BA may be defined as an area where the display panel DP is bent along a virtual bending axis BX extending in the first direction DR1. The first non-bending area NBA1 may be defined as an area adjacent to the transmissive area TA (refer to FIG. 1 ). Figure 1B ) overlapping area, the second non-bending area NBA2 can be defined as an area connected to the circuit board CF.

[0067] When the bending area BA is bent about the bending axis BX, the circuit board CF and the driver chip DC can be bent toward the back surface of the display panel DP and disposed on the back surface of the display panel DP. When the bending area BA is bent about the bending axis BX, the first non-bending area NBA1 and the second non-bending area NBA2 can be spaced apart in the third direction DR3.

[0068] Although not shown, an additional structure may be provided to compensate for a step generated between the circuit board CF and the back surface of the display panel DP due to the bent area BA.

[0069] According to an embodiment of the present invention, the width of the first non-bending area NBA1 in the first direction DR1 may be greater than the widths of the bending area BA and the second non-bending area NBA2. However, this is not limited to this. The width of the bending area BA in the first direction DR1 may be configured such that the width gradually narrows as it moves from the first non-bending area NBA1 to the second non-bending area NBA2, but this is not limited to a single embodiment.

[0070] Reference Figure 2B The display panel DP may include a base substrate SUB, a circuit element layer DP-CL disposed on the base substrate SUB, a display element layer DP-ED, and an upper insulating layer TFL. The input sensor ISU may be disposed on the upper insulating layer TFL.

[0071] Figure 2B The above Figure 2A The curved area BA and the area corresponding to the second non-curved area NBA2 in the display panel DP.

[0072] The display panel DP may include a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP may be Figure 1A The display area DD-DA shown (refer to Figure 1A )or Figure 1B The transmissive area TA shown (see Figure 1B ) corresponds to the non-display area DP-NDA and Figure 1A The non-display area DD-NDA shown (refer to Figure 1A )or Figure 1B The non-transmissive area NTA shown (refer to Figure 1B )correspond.

[0073] The base substrate SUB may include at least one plastic film. The base substrate SUB is a flexible substrate, which may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0074] The display element layer DP-ED includes a plurality of organic light-emitting diodes. The display element layer DP-ED may further include an organic layer such as a pixel definition film. The upper insulating layer TFL seals the display element layer DP-ED. As an example, the upper insulating layer TFL may include a thin film encapsulation layer. The thin film encapsulation layer may include a laminated structure of an inorganic layer / organic layer / inorganic layer. The upper insulating layer TFL protects the display element layer DP-ED from foreign matter such as moisture, oxygen, and dust particles. However, this is not limiting, and the upper insulating layer TFL may further include additional insulating layers in addition to the thin film encapsulation layer. For example, it may further include an optical insulating layer for controlling the refractive index.

[0075] In one embodiment of the present invention, a packaging substrate can be provided in place of the upper insulating layer TFL. In this case, the packaging substrate can be positioned on the display element layer DP-ED, facing the base substrate SUB. Compared to the upper insulating layer TFL, the packaging substrate is more rigid. The packaging substrate can seal the display element layer DP-ED while also protecting it from external impacts.

[0076] The input sensor ISU can be directly configured on the display panel DP. In this specification, "structure A is directly configured on structure B" means that no adhesive layer is provided between structure A and structure B. In this embodiment, the input sensor ISU and the display panel DP can be manufactured through a continuous process. However, the technical concept of the present invention is not limited to this. The input sensor ISU can be provided as a separate panel and bonded to the display panel DP via an adhesive layer. As another example, the input sensor ISU can be omitted.

[0077] Figure 3A is a top view of a display panel according to an embodiment of the present invention, Figure 3B FIG. 4 is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0078] Reference Figure 3A The display panel DP may include a plurality of pixels PX, a gate driving circuit GDC, a plurality of signal lines SGL, and a plurality of display pads DP-PD and DP-CPD.

[0079] Pixels PX are arranged in the display area DP-DA. Each pixel PX includes an organic light-emitting diode (OLED) and a pixel driver circuit connected thereto. Furthermore, the display area DP-DA can essentially be the area where the OLED is arranged. Therefore, the pixel driver circuit can be arranged in either the display area DP-DA or the non-display area DP-NDA. As long as the pixel driver circuit can be electrically connected to the OLED, it can be arranged in various locations and is not limited to a specific embodiment.

[0080] The gate drive circuit GDC sequentially outputs gate signals to the plurality of gate lines GL. The gate drive circuit GDC may include a plurality of thin film transistors formed using the same process as the driver circuit of the pixel PX, such as a low-temperature polycrystalline silicon (LTPS) process or a low-temperature polycrystalline oxide (LTPO) process. The display panel DP may also include another drive circuit that provides light emission control signals to the pixel PX.

[0081] In addition, although the gate driver circuit GDC is shown as being disposed in the non-display area DP-NDA in this embodiment, this is not limiting. For example, at least a portion of the gate driver circuit GDC may be disposed so as to overlap with the display area DP-DA in a planar manner. Furthermore, although a single gate driver circuit GDC is shown in this embodiment, multiple gate driver circuits may be provided. As long as the gate driver circuit GDC can be electrically connected to the pixel PX, it may be disposed in various locations and provided in various numbers, and is not limited to a single embodiment.

[0082] The signal lines SGL include gate lines GL, data lines DL, power lines PL, and control signal lines CSL. The gate lines GL are connected to corresponding pixels PX, while the data lines DL are connected to corresponding pixels PX. The power lines PL are connected to the pixels PX. The control signal lines CSL can provide control signals to the scan drive circuit.

[0083] The signal line SGL overlaps the display area DP-DA and the non-display area DP-NDA.

[0084] The display panel DP may include display pads. The display pads may include first display pads DP-PD and second display pads DP-CPD. According to an embodiment of the present invention, the first display pads DP-PD and the second display pads DP-CPD may be disposed on the second non-bending area NBA2.

[0085] The non-display area DP-NDA may define a chip area DCA and a first pad area PCA1 that are separated from each other. The chip area DCA is connected to the driver chip DC (see Figure 2A ) is connected to the driving chip DC (refer to the first display pad DP-PD). The first display pad area PCA1 is the area connected to the circuit board CF. It can be the area where the second display pad DP-CPD is configured. Figure 2A ) is electrically connected and transmits the electrical signal received from the driving chip DC to the signal line SGL.

[0086] The first display pads DP-PD include: a first row of display pads DP-PD1, arranged along the first direction DR1; and the second to x-th rows of display pads DP-PD2 to DP-PDx (x is a natural number greater than 3), arranged along the first direction DR1, and arranged in sequence with the first row of display pads DP-PD1 in the second direction DR2 and separated from the first row of display pads DP-PD1 in sequence along the second direction DR2 by specified intervals.

[0087] Second display pads DP-CPD may be disposed in the first pad area PCA1. The second display pads DP-CPD may be arranged along the first direction DR1. The first display pads DP-PD may be connected to corresponding ones of the second display pads DP-CPD via bridge signal lines S-CL.

[0088] The second display pads DP-CPD may also include row display pads arranged along the first direction DR1 , similarly to the first display pads DP-PD.

[0089] The circuit board CF may include circuit pads CF-PD arranged along the first direction DR1. The circuit pads CF-PD may be disposed in a second pad area PCA2 defined on the circuit board CF. The circuit pads CF-PD may be pads connected to the display panel DP.

[0090] Furthermore, when the second display pads DP-CPD are arranged in a row of pads aligned in the first direction DR1, the circuit pads CF-PD included in the circuit board CF may also be arranged in a 1:1 correspondence with the second display pads DP-CPD, but this is not limited to a particular embodiment. A second pad area PCA2 of the circuit board CF may be configured on the first pad area PCA1. The second display pads DP-CPD are electrically connected to the circuit pads CF-PD included in the circuit board CF to transmit electrical signals received from the circuit board CF to the first display pads DP-PD. The circuit board CF may be rigid or flexible. For example, if the circuit board CF is flexible, it may be provided as a flexible printed circuit board (FPCB).

[0091] The circuit board CF may include a timing control circuit for controlling the operation of the display panel DP. The timing control circuit may be mounted on the circuit board CF in the form of an integrated chip. Furthermore, although not shown, the circuit board CF may include an input sensing circuit for controlling the input sensor ISU.

[0092] In addition, although the display panel DP is described as including Figure 2A The driver chip DC shown (refer to Figure 2A ) is mounted on the first display pad DP-PD structure, but is not limited to this. The driving chip DC (refer to Figure 2A ) can be mounted on the circuit board CF, in which case the first display pad DP-PD can be omitted.

[0093] Figure 3B The display device DD is shown as an example. Figure 3A A certain pixel PX ( Figure 3A The display device DD includes a display panel DP and an input sensor ISU (see Figure 2B ), the display panel DP includes a base layer BS, a circuit layer DP-CL, a display element layer DP-ED and an encapsulation layer TFE. In addition, a certain pixel PX ( Figure 3A ) can have an equivalent circuit including multiple transistors, a capacitor and a light-emitting element, and the equivalent circuit diagram of the pixel can be deformed into various shapes. Figure 3B Pixel PX ( Figure 3A ) includes a transistor TR and a light emitting element LD.

[0094] The display panel DP according to an embodiment may include a plurality of insulating layers, transistors, conductive patterns, signal wirings, and the like.

[0095] Multiple inorganic films, multiple organic films, semiconductor layers, and conductive layers can be formed by coating, deposition, and other methods. Subsequently, the inorganic films, organic films, semiconductor layers, and conductive layers can be selectively patterned by photolithography. This method can form: multiple insulating layers formed from the inorganic and organic films; transistors TR including semiconductor patterns formed from the semiconductor layers; and circuit layers DP-CL including conductive patterns and signal wiring formed from the conductive layers.

[0096] Subsequently, a display element layer DP-ED including a light emitting element LD including a conductive pattern and the like may be formed on the circuit layer DP-CL, and an encapsulation layer TFE may be formed covering the display element layer DP-ED.

[0097] Reference Figure 3B The circuit layer DP-CL may include a shielding electrode BML, a buffer layer BFL, a plurality of insulating layers IOL1, IOL2, IOL3, IOL4 including inorganic films and a plurality of insulating layers OML1, OML2 including organic films, a transistor TR, connection electrodes CNE1, CNE2, a signal wiring SCL, and the like.

[0098] The shielding electrode BML may be disposed on the base layer BS. The shielding electrode BML may overlap with the transistor TR. Furthermore, in one embodiment, a shielding electrode BML may also be disposed below the signal wiring SCL. The shielding electrode BML may block light entering from the bottom of the display panel DP toward the transistor TR or the signal wiring SCL, thereby protecting the semiconductor pattern or conductive pattern of the transistor TR and the signal wiring SCL. The shielding electrode BML may include a conductive material. In one embodiment, the shielding electrode BML may overlap with the power line PL ( Figure 3A ) is connected and a voltage is applied to the shield electrode BML. When a voltage is applied to the shield electrode BML, the threshold voltage of the transistor TR configured on the shield electrode BML can be maintained. However, this is not limited to this, and the shield electrode BML can be a floating electrode. In one embodiment, the shield electrode BML can also be omitted.

[0099] A buffer layer (BFL) may be disposed on the base layer (BS) and cover the shield electrode (BML). The buffer layer (BFL) may improve the bonding strength between the semiconductor pattern or conductive pattern disposed on the buffer layer (BFL) and the base layer (BS). Furthermore, the buffer layer (BFL) may prevent metal atoms or impurities from diffusing from the base layer (BS) into the semiconductor pattern or conductive pattern.

[0100] The buffer layer BFL may be an inorganic film. The buffer layer BFL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. For example, the buffer layer BFL may include a structure in which silicon oxide layers and silicon nitride layers are alternately stacked.

[0101] The transistor TR may include a source electrode SE, a channel AC, a drain electrode DE, and a gate electrode GT. The source electrode SE, the channel AC, and the drain electrode DE of the transistor TR may be formed from a semiconductor pattern. In a cross section, the source electrode SE and the drain electrode DE may extend from the channel AC in opposite directions to each other. Figure 3B A portion of the signal wiring SCL formed from the semiconductor pattern is shown in . Although not shown separately, the signal wiring SCL can be connected to the drain DE of the transistor TR on a plane.

[0102] The semiconductor pattern of the transistor TR may include polysilicon, amorphous silicon, or metal oxide, and is not limited to any one material as long as it has semiconductor properties.

[0103] The semiconductor pattern may include multiple regions divided according to the strength of the conductivity. The region doped with a dopant or reduced with a metal oxide in the semiconductor pattern may have a strong conductivity and may essentially function as the source electrode and drain electrode of the transistor TR. The region with a strong conductivity in the semiconductor pattern may correspond to the source SE and drain DE of the transistor TR. The region that is undoped or doped with a low concentration or has a weak conductivity due to the unreduced metal oxide may correspond to the channel AC (or active) of the transistor TR.

[0104] The first insulating layer IOL1 may cover the semiconductor pattern of the transistor TR and be disposed on the buffer layer BFL. The gate GT of the transistor TR may be disposed on the first insulating layer IOL1. The gate GT may overlap with the channel AC of the transistor TR. In one embodiment, the gate GT may serve as a mask during the doping process of the semiconductor pattern of the transistor TR.

[0105] The gate GT may include titanium (Ti), silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not particularly limited thereto.

[0106] The first insulating layer 1OL1 may include an inorganic film. The first insulating layer 1OL1 may also be referred to as a first inorganic film. For example, the first insulating layer 1OL1 may be an inorganic film comprising at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first insulating layer 1OL1 may have a single-layer or multi-layer structure. The first insulating layer 1OL1 may have a structure in which multiple inorganic films are stacked. When the first insulating layer 1OL1 has a structure in which multiple layers are stacked, the first insulating layer 1OL1 may further include a buffer inorganic film disposed directly below the inorganic film and having a relatively higher O content than adjacent inorganic films. The buffer inorganic film may have physical properties similar to those of the buffer insulating layer of the input sensor described above.

[0107] Furthermore, in one embodiment, the first insulating layer 101 may include an organic film in addition to the inorganic film. If the first insulating layer 101 comprises a stacked structure of inorganic and organic films, the first insulating layer 101 may further include a buffer inorganic film disposed between adjacent inorganic and organic films. In this case, the buffer inorganic film may have similar physical properties to the buffer insulating layer of the input sensor described above. For example, the buffer inorganic film may contain a relatively high content of O and C compared to adjacent inorganic films.

[0108] Furthermore, the multilayer structure described for the first insulating layer IOL1 can also be incorporated into the second to fourth insulating layers IOL2, IOL3, IOL4, etc., which will be described later. Thus, the stacked structure of the insulating layers of the multilayer structure, the structure of the buffer inorganic film within the multilayer structure, and the like can also be applied to the second to fourth insulating layers IOL2, IOL3, IOL4, etc., which will be described later.

[0109] The second insulating layer IOL2 may be disposed on the first insulating layer IOL1 and cover the gate electrode GT. The second insulating layer IOL2 may overlap the pixel in a shared manner. The second insulating layer IOL2 may include an inorganic film. The second insulating layer IOL2 may also be referred to as a second inorganic film. For example, the second insulating layer IOL2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second insulating layer IOL2 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. In one embodiment, the second insulating layer IOL2 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0110] The third insulating layer 10L3 may be disposed on the second insulating layer 10L2. The third insulating layer 10L3 may include an inorganic film. The third insulating layer 10L3 may also be referred to as a third inorganic film. The third insulating layer 10L3 may have a single-layer or multi-layer structure. For example, the third insulating layer 10L3 may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

[0111] The first connection electrode CNE1 may be disposed on the third insulating layer IOL3 and connected to the signal line SCL through a first contact hole CH-1 that penetrates the first, second, and third insulating layers IOL1, IOL2, and IOL3.

[0112] The fourth insulating layer IOL4 may be disposed on the third insulating layer IOL3. The fourth insulating layer IOL4 may include an inorganic film, and may also be referred to as a fourth inorganic film. The fourth insulating layer IOL4 may be a single silicon oxide layer.

[0113] The fifth insulating layer OML1 may be disposed on the fourth insulating layer IOL4. The fifth insulating layer OML1 may include an organic film. The fifth insulating layer OML1 may be referred to as a first organic film. The first organic film may further include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin.

[0114] The second connection electrode CNE2 may be disposed on the fifth insulating layer OML1 and connected to the first connection electrode CNE1 through a second contact hole CH-2 that penetrates the fourth insulating layer IOL4 and the fifth insulating layer OML1.

[0115] The sixth insulating layer OML2 may be disposed on the fifth insulating layer OML1 and cover the second connection electrode CNE2. The sixth insulating layer OML2 may include an organic film. The sixth insulating layer OML2 may be referred to as a second organic film. The second organic film may further include at least one of an acrylic resin, a methacrylic resin, polyisoprene, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin.

[0116] In addition, although not Figure 3B As shown in the figure, the circuit layer may further include a plurality of transistors and may further include signal wiring electrically connected to the plurality of transistors. The signal wiring may extend and be connected to the non-display area NDA ( Figure 3A ) is connected to the first display pad DP-PD of the non-sensing area. In addition, the signal wiring can be extended and connected to the sensing pad of the non-sensing area.

[0117] The display element layer DP-ED is disposed on the circuit layer DP-CL. The display element layer DP-ED may include a pixel definition layer PDL and a light emitting element LD. The light emitting element LD may include a first electrode AE, a light emitting layer EL, and a second electrode CE.

[0118] The first electrode AE ​​may be disposed on the sixth insulating layer OML2 and connected to the second connection electrode CNE2 via a third contact hole CH-3 penetrating the sixth insulating layer OML2. The first electrode AE ​​may be electrically connected to the drain DE of the transistor TR via the first and second connection electrodes CNE1 and CNE2.

[0119] The first electrode AE ​​may be referred to as a pixel electrode. The first electrode AE ​​may be formed of a metal material, a metal alloy, or a conductive compound. The first electrode AE ​​may be an anode or a cathode. The first electrode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. When the first electrode AE ​​is a transmissive electrode, the first electrode AE ​​may include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. When the first electrode AE ​​is a semi-transmissive electrode or a reflective electrode, the first electrode AE ​​may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, or a compound or mixture thereof (e.g., a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al. Alternatively, the first electrode AE ​​may have a multilayer structure including a reflective film or a semi-transparent film formed from the aforementioned substances and a transparent conductive film formed from ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), or the like. For example, the first electrode AE ​​may have a three-layer structure of ITO / Ag / ITO, but is not limited thereto. Furthermore, the embodiment is not limited thereto, and the first electrode AE ​​may include the aforementioned metal materials, a combination of two or more metal materials selected from the aforementioned metal materials, or oxides of the aforementioned metal materials.

[0120] The pixel definition film PDL can be configured on the sixth insulating layer OML2. In one embodiment, the pixel definition film PDL can be formed by a polymer resin. For example, the pixel definition film PDL can be formed by including a polyacrylate resin or a polyimide resin. In addition, the pixel definition film PDL can also be formed by including an inorganic substance in addition to the polymer resin. In addition, the pixel definition film PDL can be formed by including a light absorbing substance, or by including a black pigment or a black dye. The pixel definition film PDL formed by including a black pigment or a black dye can realize a black pixel definition film. When forming the pixel definition film PDL, carbon black or the like can be used as the black pigment or the black dye, but the embodiment is not limited thereto.

[0121] Furthermore, the pixel definition layer PDL may be formed of an inorganic material. For example, the pixel definition layer PDL may be formed including silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0122] The pixel definition film PDL may define a pixel opening PX-OP that exposes a portion of the first electrode AE. In a display device DD according to one embodiment, the pixel definition film PDL may define a light-emitting area PXA. The display device DD includes the light-emitting area PXA and a non-light-emitting area NPXA. The non-light-emitting area NPXA may be a portion overlapping the pixel definition film PDL. The portion of the first electrode AE ​​exposed through the pixel opening PX-OP may be defined as the light-emitting area PXA.

[0123] In the light emitting element LD, the light emitting layer EL may be disposed on the first electrode AE. In this embodiment, the light emitting layer EL may emit light of at least one color of blue, red, and green. In addition, in one embodiment, the entire display area DP-DA ( Figure 3A ) in which the light-emitting layer EL can provide blue light.

[0124] The second electrode CE may be disposed on the light emitting layer EL. The second electrode CE may have an integral shape and be disposed in a common manner on a plurality of pixels PX ( Figure 3A ). The second electrode CE may be referred to as a common electrode. The second electrode CE may be a cathode or an anode. For example, when the first electrode AE ​​is an anode, the second electrode CE may be a cathode, and when the first electrode AE ​​is a cathode, the second electrode CE may be an anode.

[0125] The second electrode CE may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. When the second electrode CE is a transmissive electrode, the second electrode CE may be made of a transparent metal oxide, such as ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), or the like. Furthermore, the second electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, or a compound or mixture thereof (e.g., a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al.

[0126] Although not shown, a hole control layer may be provided between the first electrode AE ​​and the light-emitting layer EL. The hole control layer may include a hole transport layer and may further include a hole injection layer. An electron control layer may be provided between the light-emitting layer EL and the second electrode CE. The electron control layer may include an electron transport layer and may further include an electron injection layer. The hole control layer and the electron control layer may be formed together in the plurality of pixels PX ( Figure 3A ).

[0127] The encapsulation layer TFE may be disposed on the display element layer DP-ED. The encapsulation layer TFE may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 stacked in sequence. However, the layers constituting the encapsulation layer TFE are not limited thereto.

[0128] The inorganic layers IL1 and IL2 protect the display element layer DP-ED from moisture and oxygen, while the organic layer OL protects the display element layer DP-ED from foreign matter such as dust particles. The inorganic layers IL1 and IL2 may include at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. The organic layer OL may include an acrylic organic material. However, the materials comprising the inorganic layers IL1 and IL2 and the organic layer OL are not limited thereto.

[0129] An input sensor ISU may be disposed on the encapsulation layer TFE. The input sensor ISU may be referred to as a sensor layer, input sensing layer, or input sensing panel. The input sensor ISU may include multiple sensor insulation layers ISL and multiple sensor conductive layers MTL. A portion of the multiple sensor insulation layers ISL, a portion ISL-B, may be disposed directly on the display panel DP. For example, in one embodiment, the input sensor ISU may include a first sensor insulation layer ISL-B, a first sensor conductive layer MTL1, a second sensor insulation layer ISL-C, a second sensor conductive layer MTL2, and a third sensor insulation layer ISL-T, which are sequentially stacked on the display panel DP in the third direction DR3.

[0130] The first sensor insulation layer ISL-B may include a base insulation layer. Furthermore, the first sensor insulation layer may include a buffer insulation layer. That is, the input sensor ISU may have a single-layer structure consisting solely of a base insulation layer or a buffer insulation layer, or a stacked structure including a buffer insulation layer and a base insulation layer, but this is not limited to any particular embodiment.

[0131] The first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may have a multi-layer structure. A multi-layer sensor conductive layer may include two or more layers stacked together, including a transparent conductive layer and / or a metal layer. For example, a multi-layer sensor conductive layer may include a stacked structure of a transparent conductive layer and a metal layer, or a stacked structure of metal layers including different metals.

[0132] For example, the transparent conductive layer included in the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may include ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), PEDOT, metal nanowires, or graphene. The metal layer included in the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof.

[0133] The first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may include sensing electrodes of the input sensor ISU and may further include sensing wirings.

[0134] The second sensor insulating layer ISL-C may be disposed on the first sensor conductive layer MTL1. The third sensor insulating layer ISL-T may be disposed on the second sensor conductive layer MTL2. Each of the second sensor insulating layer ISL-C and the third sensor insulating layer ISL-T may include an inorganic film. Furthermore, each of the second sensor insulating layer ISL-C and the third sensor insulating layer ISL-T may further include an organic film.

[0135] Each of the first, second, and third sensor insulating layers ISL-B, ISL-C, and ISL-T may include at least one of silicon nitride (SiNx) and silicon oxynitride (SiOXNY). Furthermore, the first, second, and third sensor insulating layers ISL-B, ISL-C, and ISL-T may include silicon oxide (SiOX). Furthermore, the first, second, and third sensor insulating layers ISL-B, ISL-C, and ISL-T may further include at least one of aluminum oxide, titanium oxide, zirconium oxide, and hafnium oxide as an inorganic film. In the expressions for silicon nitride (SiNx), silicon oxynitride (SiOXNY), and silicon oxide (SiOX), X and Y may each be greater than 0.

[0136] When the first sensor insulating layer ISL-B, the second sensor insulating layer ISL-C, and the third sensor insulating layer ISL-T include organic films, the organic films may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, silicone resin, polyimide resin, polyamide resin, and perylene resin.

[0137] In addition, although Figure 3B The input sensor ISU is shown as including a stacked first sensor conductive layer MTL1 and a second sensor conductive layer MTL2, but embodiments are not limited thereto. For example, in one embodiment, the input sensor ISU may include a sensor conductive layer MTL disposed on a first sensor insulating layer ISL-B. In this case, one of the second sensor insulating layer ISL-C and the third sensor insulating layer ISL-T may be omitted.

[0138] In addition, although Figure 3B In order to schematically illustrate the stacked structure, each of the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 is shown as a single layer superimposed on the entire display panel DP, but the embodiment is not limited thereto. Each of the first sensor conductive layer MTL1 and the second sensor conductive layer MTL2 may be formed by patterning.

[0139] According to one embodiment, the display device DD may include an optical layer. In one embodiment, the optical layer AF may be directly disposed on the third sensor insulation layer ISL-T. However, this is not limited to this embodiment. An adhesive layer or the like may be included between the optical layer AF and the input sensor ISU. This is not limited to a particular embodiment.

[0140] Figure 4 FIG. 1 is an exploded perspective view of a bonding region of a display device according to an embodiment of the present invention.

[0141] Reference Figure 4 The display panel DP includes a first adhesive layer AF-C disposed between the circuit board CF and the base substrate SUB; and a second adhesive layer AF-D disposed between the driver chip DC and the base substrate SUB. The first adhesive layer AF-C connects the circuit board CF and the display panel DP, while the second adhesive layer AF-D connects the driver chip DC and the display panel DP. Each of the first and second adhesive layers AF-C and AF-D may have insulating properties. The first and second adhesive layers AF-C and AF-D physically bond the circuit board CF and driver chip DC, respectively, to the display panel DP.

[0142] The circuit board CF includes an upper surface CF-US and a lower surface CF-DS. The lower surface CF-DS of the circuit board CF may be the surface opposite the display panel DP. A plurality of substrate pads CF-PD may be disposed on the lower surface CF-DS of the circuit board CF and electrically connected to a plurality of second display pads DP-CPD of the display panel DP.

[0143] The driver chip DC includes an upper surface DC-US and a lower surface DC-DS. The lower surface DC-DS of the driver chip DC may be opposite the display panel DP. The driver chip DC includes chip pads DC-PD disposed on the lower surface DC-DS. The plurality of chip pads DC-PD are electrically connected to a plurality of first display pads DP-PD disposed on the base substrate SUB.

[0144] The plurality of chip pads DC-PD may include: a first row of chip pads DC-PD1 arranged along a first direction DR1; a second row of chip pads DC-PD2 arranged along the first direction DR1 and spaced apart from the first row of chip pads DC-PD1 in a second direction DR2; and an nth row of chip pads (n being a natural number greater than or equal to 3) arranged along the first direction DR1 and spaced apart from the second row of chip pads DC-PD2 in the second direction DR2. The first row of chip pads DC-PD1 and the second row of chip pads DC-PD2 may be shaped to be exposed to the outside from the bottom surface of the driver chip DC.

[0145] Although Figure 4 The chip pads DC-PD are described as being arranged in four rows, but the present invention is not limited thereto. The chip pads DC-PD may be arranged in more than five rows based on the arrangement structure of the first display pads DP-PD.

[0146] Although the connection between the circuit board CF and the display panel DP is exemplarily illustrated below, the connection structure between the circuit board CF and the display panel DP described later may also be applied to the connection between the driving chip DC and the display panel DP.

[0147] Furthermore, the pad PD described below (refer to Figure 5 ) can be connected to the aforementioned first display pad DP-PD ( Figure 4 ) corresponds to the bump PB (refer to Figure 5 ) corresponds to the aforementioned chip pad DC-PD.

[0148] Figure 5 FIG. 1 is a top view of a chip region of a display device according to an embodiment of the present invention.

[0149] Reference Figure 5 The display panel DP may include a chip region DCA. The chip region DCA may include a pad region PDR configured with pads PD of each of an input pad portion IPDR, a side pad portion SPDR, and an output pad portion OPDR; and a circuit region CR configured with circuits.

[0150] Each of the input pad portion IPDR, the side pad portion SPDR, and the output pad portion OPDR may include a plurality of pads PD.

[0151] The output pad portion OPDR includes a plurality of output pads OPD, the input pad portion IPDR includes a plurality of input pads IPD, and the side pad portion SPDR includes a plurality of side pads SPD.

[0152] The aforementioned driver chip DC (refer to Figure 4 ) may include a plurality of output bumps OPB corresponding to the output pads OPD, a plurality of input bumps IPB corresponding to the input pads IPD, and side bumps SPB corresponding to the side pads SPD. The output bumps OPB may overlap with the output pads OPD, the input bumps IPB may overlap with the input pads IPD, and the side bumps SPB may overlap with the side pads SPD.

[0153] A plurality of input pads IPD may be arranged along the first direction DR1 to form a row. A plurality of side pads SPD may be arranged along the second direction DR2 to form a column. Each input pad IPD may be correspondingly configured with an input bump IPB, and each side pad SPD may be correspondingly configured with a side bump SPB.

[0154] The arrangement of the input pads IPD and the side pads SPD shown in the drawings is only an example and is not limited to what is shown in the drawings. The arrangement of the input pads IPD and the side pads SPD may be different depending on the design of the display panel DP or the driver chip DC and is not limited to a certain embodiment.

[0155] The input pad portion IPDR and the side pad portion SPDR may provide a display device DD (refer to Figure 1B The various signals may be provided to the driving chip DC through a plurality of input bumps IPB configured corresponding to the input pad portion IPDR and a plurality of side bumps SPB configured corresponding to the side pad portion SPDR.

[0156] The output pad portion OPDR may include a plurality of output pads OPD. The plurality of output pads OPD may be arranged along a first direction DR1 and a second direction DR2. The plurality of output pads OPD arranged along the first direction DR1 may be defined as output pad rows. The output pad rows OPD_R1, OPD_R2, OPD_R3, and OPD_R4 may be arranged along the second direction DR2.

[0157] Although the output pad portion OPDR is shown in the drawings as a structure including only the first to fourth output pad rows OPD_R1, OPD_R2, OPD_R3, and OPD_R4, it is not limited thereto and may include more than five output pad rows, and is not limited to a certain embodiment.

[0158] The output pad portion OPDR can receive the power from the driver chip DC (see FIG. Figure 4 ) output various signals. The various signals provided to the output pad portion OPDR can be provided to each pixel configured in the display area through a plurality of lines connected to the output pad portion OPDR.

[0159] The output pads OPD may be arranged at a predetermined distance from each other in the first direction DR1. The signal lines SGL described above may be arranged in the spaces between the output pads in the first direction DR1 (see FIG. Figure 3A ).

[0160] The output pad portion OPDR may include a greater number of output pads OPD than the number of input pads IPD of the input pad portion IPDR or the number of side pads SPD of the side pad portion SPDR, corresponding to the number of pixels PX.

[0161] The output pads OPD included in each of the output pad rows OPD_R1 , OPD_R2 , OPD_R3 , and OPD_R4 may have the same shape and may be arranged side by side with each other.

[0162] The output pads OPD arranged in the same row can be arranged in a zigzag pattern in the first direction DR1. That is, the output pads OPD arranged in the same row and adjacent to each other can be shifted a predetermined distance in the second direction DR2 so that a portion of the pads are staggered. In this case, the predetermined shift distance can be smaller than the distance between adjacent rows.

[0163] In this case, by arranging the output pads OPD in a zigzag pattern, the density of the output pads OPD within the same area can be increased, and the display panel DP (see FIG. Figure 4 Specifically, since the area of ​​the output pad OPD in the second direction DR2 can be reduced, the display panel DP (see FIG. Figure 4 Furthermore, by arranging the output bumps OPB in a zigzag manner, the density of the output bumps OPB within the same area can be increased, thereby promoting the display device DD (see Figure 2A ) is ultra-miniaturized.

[0164] Furthermore, since the output pads OPD are arranged in a zigzag pattern, when the output pads OPD and the output bumps OPB are electrically connected to the driver chip DC (see FIG. Figure 4 ) when heat and pressure are applied, it is possible to prevent deformation or cracks caused by the pressure (or stress) being concentrated on the area adjacent to the output pad OPD. That is, when pressure (or stress) is applied to the area adjacent to the output pad OPD, by preventing the area to which the pressure (or stress) is applied from being arranged regularly in a specific direction (for example, the first direction DR1), it is possible to prevent the pressure (or stress) from being distributed uniformly over the entire display panel DP (refer to FIG. Figure 4 ) is evenly distributed within the range of . Thus, it is possible to prevent the Figure 4 ) and the local deformation in the entire display panel DP (refer to Figure 4 ) causes deformation.

[0165] Each of the output bumps OPB arranged corresponding to the output pad portion OPDR may be configured to have a specific pattern. Specifically, the output bumps OPB may include output bump rows OPB_R1, OPB_R2, OPB_R3, and OPB_R4 in which a plurality of output bumps OPB are arranged along the first direction DR1.

[0166] The output bumps OPB included in each of the output bump rows OPB_R1 , OPB_R2 , OPB_R3 , and OPB_R4 may have the same shape and may have a partially symmetrical shape, but this is not limited to a certain embodiment.

[0167] According to one embodiment of the present invention, the output bumps OPB arranged in the same row may be arranged in a zigzag pattern in the first direction DR1. That is, the output bumps OPB arranged in the same row and adjacent to each other may be shifted a predetermined distance in the second direction DR2 so that a portion of the output bumps OPB are staggered. In this case, the predetermined shift distance may be smaller than the distance between adjacent rows.

[0168] By arranging the output pads OPD configured in a zigzag manner and / or arranging the output bumps OPB in a zigzag arrangement, cracks or breakage that may occur when mounting the driving chip DC can be minimized.

[0169] In the case of an embodiment of the present invention in which the output pads OPD and the output bumps OPB are arranged in a zigzag manner, the pressure (or stress) applied to the area adjacent to the output pads OPD can be reduced by 8% to 13% compared to the case in which neither the output pads OPD nor the output bumps OPB are arranged in a zigzag manner (comparative example).

[0170] Furthermore, in the case of the embodiment of the present invention, the deformation amount of the display panel in the thickness direction can be reduced by about 22% to 66% compared with the aforementioned comparative example.

[0171] Figure 6A and Figure 6B This is a schematic diagram showing an enlarged portion of a chip region of a display device according to an embodiment of the present invention. Figure 6A It will Figure 5 The output pad portion OPDR is enlarged in the top view. Figure 6B It will Figure 5 A magnified top view of the F6B.

[0172] Reference Figure 6A and Figure 6B Each output pad row OPD_R may include a plurality of first output pads OPD1 and a plurality of second output pads OPD2. The plurality of first output pads OPD1 may be arranged along a first direction DR1. The plurality of second output pads OPD2 may be arranged alternately with the first output pads OPD1 along the first direction DR1.

[0173] Each output pad row OPD_R may be spaced apart from each other by a first distance D1. Each output bump row OPB_R may be spaced apart from each other by a second distance D2. The second distance D2 may be greater than or equal to the first distance D1. By adjusting the difference between the first distance D1 and the second distance D2, the area occupied by the output pads OPD and the output bumps OPB in the chip area DCA can be adjusted.

[0174] The second output pads OPD2 may be arranged shifted from the first output pads OPD1 in the second direction DR2 by a fourth distance D4. Specifically, when the first output pads OPD1 are arranged in the first direction DR1 with the first alignment line AGL1 as a reference, and the second output pads OPD2 are arranged in the second direction DR2 with the second alignment line AGL2 as a reference, the distance between the first alignment line AGL1 and the second alignment line AGL2 in the second direction DR2 may be the fourth distance D4. One end of the first output pads OPD1 and the second output pads OPD2 in the first direction DR1 may be aligned with the third alignment line AGL3.

[0175] According to an embodiment, the first distance D1 may be greater than or equal to the fourth distance D4. However, the present invention is not limited thereto, and the first distance D1 may be less than the fourth distance D4. This is not limited to a particular embodiment.

[0176] According to an embodiment of the present invention, the output pads OPD located in different output pad rows OPD_R may be aligned with each other in the second direction DR2.

[0177] The first output pads OPD1 of the first output pad row OPD_R1 and the second output pads OPD2 of the second output pad row OPD_R2 may be aligned with each other in the second direction DR2.

[0178] The first output pad OPD1 of the second output pad row OPD_R2 may be aligned with the first output pad OPD1 of the third output pad row OPD_R3 in the second direction DR2. The second output pad OPD2 of the second output pad row OPD_R2 may be aligned with the second output pad OPD2 of the third output pad row OPD_R3 in the second direction DR2.

[0179] Since the first output pads OPD1 and the second output pads OPD2 of the first to fourth output pad rows OPD_R are aligned in the second direction DR2, the density of the output pads OPD can be increased, and ultra-miniaturization of the display panel DP can be facilitated.

[0180] Although the first output pads OPD1 and the second output pads OPD2 of the first to fourth output pad rows OPD_R are shown in the drawings as being aligned in the second direction DR2, the present invention is not limited thereto. Only a portion of the first output pads OPD1 may be aligned in the second direction, and the present invention is not limited to a particular embodiment. Also, only a portion of the second output pads OPD2 may be aligned in the second direction DR2, and the present invention is not limited to a particular embodiment.

[0181] The output bump section may include first to fourth output bump rows OPB_R. Although the drawings illustrate that the intervals between adjacent output bump rows OPB_R are the same, this is not limiting and may have some differences. This is not limited to a particular embodiment.

[0182] Each output bump row OPB_R may include a plurality of first output bumps OPB1 and a plurality of second output bumps OPB2 .

[0183] The plurality of first output bumps OPB1 may be arranged along the first direction DR1, and the plurality of second output bumps OPB2 may be arranged alternately with the first output bumps OPB1 along the first direction DR1.

[0184] The second output bump OPB2 can be arranged offset from the first output bump OPB1 by a third distance D3 in the second direction DR2. The third distance D3 can be less than the second distance D2. However, this is not limiting and the third distance D3 can be equal to the second distance D2. Furthermore, the third distance D3 can be greater than or equal to the fourth distance D4. By making the third distance D3 greater than or equal to the fourth distance D4, the reliability of the connection between the output bump OPB and the output pad OPD can be improved.

[0185] The first output bumps OPB1 and the second output bumps OPB2 of the first to fourth output bump rows OPB_R may be connected to the first output pads OPD1 and the second output pads OPD2 of the corresponding first to fourth output pad rows OPD_R, ​​respectively. Specifically, the arrangement relationship of the first output bumps OPB1 and the second output bumps OPB2 of the first output bump row OPB_R1 may correspond to the first output pads OPD1 and the second output pads OPD2 of the first output pad row OPD_R1, and the arrangement relationship of the first output bumps OPB1 and the second output bumps OPB2 of the second output bump row OPB_R2 may correspond to the first output pads OPD1 and the second output pads OPD2 of the second output pad row OPD_R2. The same applies to the third output bump row OPB_R3 and the fourth output bump row OPB_R4.

[0186] As an example, the first output bump OPB1 of the first output bump row OPB_R1 may be aligned with the first output bump OPB1 of the second output bump row OPB_R2 along the second direction DR2, and the second output bump OPB2 of the first output bump row OPB_R1 may be aligned with the second output bump OPB2 of the second output bump row OPB_R2 along the second direction DR2.

[0187] That is, according to an embodiment of the present invention, the output pads OPD of each output pad row OPD_R may be arranged in a zigzag manner along the first direction DR1 , and the output bumps OPB of each output bump row OPB_R may be arranged in a zigzag manner along the first direction DR1 corresponding to the output pads OPD.

[0188] Furthermore, since the second output pad OPD2 can be displaced by a fourth distance D4 relative to the first output pad OPD1 in the second direction DR2, and the second output bump OPB2 can be displaced by a third distance D3 relative to the first output bump OPB1 in the second direction DR2, the area of ​​the region where the second output bump OPB2 and the second output pad OPD2 overlap can be maintained constant, while the area of ​​the region where the output bump OPB does not overlap with the output pad OPD can be reduced. Consequently, the size of the display device DD can be reduced to ultra-miniaturization.

[0189] Figure 7 This is a schematic diagram showing an enlarged portion of a chip region of a display device according to an embodiment of the present invention.

[0190] Reference Figure 7 When the first output pads OPD1 and the second output pads OPD2 of each of the first to fourth output pad rows OPD_R are arranged in a zigzag manner along the first direction DR1, the first output bumps OPB1 and the second output bumps OPB2 of the first to fourth output bump rows OPB_R can also be aligned along the first direction DR1.

[0191] In this case, the first output pads OPD1 and the second output pads OPD2 of each of the first to fourth output pad rows OPD_R may also be arranged in a zigzag pattern along the first direction DR1.

[0192] Figures 8A to 8C FIG. 1 is an enlarged top view of a portion of a pad region of a display device according to an embodiment of the present invention. Figure 8D and Figure 8E This is an enlarged cross-sectional view of a portion of a pad region of a display device according to an embodiment of the present invention.

[0193] Figures 8A to 8C , a plurality of signal lines SGL, a plurality of output pads OPD, and a plurality of output bumps OPB are shown.

[0194] The output pad OPD of one embodiment of the present invention can be aligned with the output bump OPB and the contact portion CNP (see FIG. Figure 8D ) overlap with each other, and the output pads OPD, output bumps OPB, and contacts CNP overlap with each other (refer to Figure 8D ) can constitute various patterns.

[0195] A plurality of patterns may be aligned along the arrangement direction of the output pads OPD of the first output pad row OPD_R1. The first pattern PDG1, the second pattern PDG2, the third pattern PDG3, and the fourth pattern PDG4 may be arranged in a zigzag manner along the arrangement direction of the output pads OPD of the first output pad row OPD_R1. The same may apply to the second output pad row OPD_R2, the third output pad row OPD_R3, and the fourth output pad row OPD_R4.

[0196] A plurality of signal lines SGL can connect the pixels PX (refer to Figure 3A ) and the first output pad OPD1 (refer to Figure 6A ) and the second output pad OPD2 (refer to Figure 6B ) are connected. The signal line SGL can be arranged between the first pattern PDG1 and the second pattern PDG2, between the second pattern PDG2 and the third pattern PDG3, and between the third pattern PDG3 and the fourth pattern PDG4. The signal line SGL can be defined as a plurality of signal line groups SGL-G1, SGL-G2, SGL-G3, and SGL-G4. The signal line groups SGL-G1, SGL-G2, SGL-G3, and SGL-G4 can each include a plurality of signal lines SGL.

[0197] The first signal line group SGL-G1 may be disposed between the first pattern PDG1 and the second pattern PDG2, the second signal line group SGL-G2 may be disposed between the second pattern PDG2 and the third pattern PDG3, and the third signal line group SGL-G3 may be disposed between the third pattern PDG3 and the fourth pattern PDG4. That is, the first signal line group SGL-G1 may be disposed between the first pad PD1 and the second pad PD2, and the second signal line group SGL-G2 may be separated from the first signal line group SGL-G1 via the second pattern PDG2.

[0198] A portion of the signal lines SGL in each of the signal line groups SGL-G1, SGL-G2, SGL-G3, and SGL-G4 can be electrically connected to a pattern. Each signal line SGL can electrically connect a pad PD located in a different output pad row OPD_R. For example, a portion of the signal lines in the first signal line group SGL-G1 can be electrically connected to an output pad OPD in the second output pad row OPD_R2, while another portion of the signal lines in the first signal line group SGL-G1 can be electrically connected to an output pad OPD in the third output pad row OPD_R3.

[0199] A portion of the signal line SGL may extend in the second direction DR2 , and another portion may be inclined with respect to the first direction DR1 and the second direction DR2 .

[0200] Although only the first to fourth signal line groups SGL-G1, SGL-G2, SGL-G3, and SGL-G4 are shown in the drawings, the present invention is not limited thereto and may be additionally provided corresponding to the number of output pad rows OPD_R. The present invention is not limited to a certain embodiment.

[0201] Reference Figure 8B , the first output pad row OPD_R1 (refer to Figure 8A ) may have a first width W1, and the interval between the first output pad OPD1-1 and the second output pad OPD2-1 of the first output pad row OPD_R1 may be a second width W2. According to an embodiment of the present invention, the second width W2 may be greater than the first width W1. The second width W2 may be configured to a degree that allows the signal lines SGL corresponding to the number of pad groups to be spaced apart from each other. Figure 8C As shown, when there are four output pad rows OPD_R (refer to Figure 8A ), the second width W2 may have a value sufficient to accommodate at least four or five signal lines SGL.

[0202] The width of each signal line SGL can be 2 microns or less, and the interval between each signal line SGL can be 1 micron or more and 1.5 microns or less. As an example, when the width of each signal line SGL is 2 microns and the interval between each signal line SGL is 1 micron, the second width W2 can be 13 microns or more, preferably 16 microns. In this case, the first width W1 can be 8 microns.

[0203] However, if the second width W2 is too large, the overall size of the base substrate SUB will be increased. Therefore, the second width W2 cannot be above a specific range.

[0204] At this time, each output pad row OPD_R (refer to Figure 8A ) may have the same shape and may have a first width W1 and a second width W2 of the same value, respectively.

[0205] According to an embodiment of the present invention, the aforementioned fourth distance D4 may be less than or equal to the first distance D1. In the second direction DR2, the distance between the first output pad OPD1-1 of the first output pad row OPD_R1 and the first output pad OPD1-2 of the second output pad row OPD_R2 may be the first distance D1. In the second direction DR2, the distance between the second output pad OPD2-1 of the first output pad row OPD_R1 and the second output pad OPD2-2 of the second output pad row OPD_R2 may be the first distance D1. The same applies to the first output pads OPD1 or second output pads OPD2 between adjacent output pad rows OPD_R.

[0206] The second output pads OPD2 may be shifted from the first output pads OPD1 in the second direction DR2 by a fourth distance D4. That is, the shifted distance of the second output pads OPD2 may be smaller than the interval between the second output pads OPD2 in different output pad rows OPD_R in the second direction DR2.

[0207] Reference Figure 8C and Figure 8A Each output pad OPD may be connected to each signal line SGL, and a plurality of signal lines SGL may be arranged between adjacent output pads in each output pad row OPD_R.

[0208] The first signal line group SGL-G1 may include a first signal line SL1-1, a second signal line SL2-1, a third signal line SL3-1, and a fourth signal line SL4-1. The first to fourth signal lines SL1-1, SL2-1, SL3-1, and SL4-1 may be arranged at intervals in the first direction DR1.

[0209] The first to fourth signal lines SL1-1, SL2-1, SL3-1, and SL4-1 of the first signal line group SGL-G1 can be electrically connected to the first output pad OPD1 located in a different output pad row OPD_R. Furthermore, the first to fourth signal lines SL1-1, SL2-1, SL3-1, and SL4-1 of the first signal line group SGL-G1 can be electrically connected to the second output pad OPD2 located in a different output pad row OPD_R. That is, one side of the first to fourth signal lines SL1-1, SL2-1, SL3-1, and SL4-1 can be connected to the first output pad OPD1, and the other side can be connected to the second output pad OPD2. However, this is not limited to this, and some of the first to fourth signal lines SL1-1, SL2-1, SL3-1, and SL4-1 can be connected to pixels, but this is not limited to a certain embodiment.

[0210] As an example, the first signal line SL1-1 of the first signal line group SGL-G1 can be electrically connected to the first output pad OPD1-2. In this case, the first signal line SL1-1 and the second signal line SL2-1 can be arranged on different layers, and the third signal line SL3-1 and the fourth signal line SL4-1 can be arranged on different layers. In this case, the first signal line SL1-1 and the second signal line SL2-1 can be electrically insulated, and the third signal line SL3-1 and the fourth signal line SL4-1 can be electrically insulated. Furthermore, the first signal line SL1-1 does not need to overlap with the second signal line SL2-1 in a planar manner.

[0211] The first signal line group SGL-G1 may include a fifth signal line SL5-1. The fifth signal line SL5-1 of the first signal line group SGL-G1 may be electrically connected to a second output pad OPD2-1 adjacent to the fourth signal line SL4-1. Furthermore, the fifth signal line SL5-1 may be electrically connected to a first output pad OPD1 located in a different output pad row OPD_R than the first to fourth signal lines SL1-1, SL2-1, SL3-1, and SL4-1.

[0212] The second signal line group SGL-G2 may include a first signal line SL1-2, a second signal line SL2-2, a third signal line SL3-2, and a fourth signal line SL4-2. The first to fourth signal lines SL1-2, SL2-2, SL3-2, and SL4-2 may be arranged at intervals from each other in the first direction DR1.

[0213] The first to fourth signal lines SL1-2, SL2-2, SL3-2, and SL4-2 of the second signal line group SGL-G2 can be electrically connected to the first output pad OPD1 located in a different output pad row ODP_R. Furthermore, the first to fourth signal lines SL1-2, SL2-2, SL3-2, and SL4-2 of the second signal line group SGL-G2 can be electrically connected to the second output pad OPD2 located in a different output pad row OPD_R. That is, one side of the first to fourth signal lines SL1-2, SL2-2, SL3-2, and SL4-2 can be connected to the first output pad OPD1, and the other side can be connected to the second output pad OPD2. However, this is not limited to this, and some of the first to fourth signal lines SL1-2, SL2-2, SL3-2, and SL4-2 can be connected to pixels, and this is not limited to a certain embodiment.

[0214] The second signal line group SGL-G2 may include a fifth signal line SL5-2. The fifth signal line SL5-2 of the second signal line group SGL-G2 may be electrically connected to a first output pad OPD1-1 adjacent to the fourth signal line SL4-2. Furthermore, the fifth signal line SL5-2 may be electrically connected to a second output pad OPD2 located in a different output pad row OPD_R than the first to fourth signal lines SL1-2, SL2-2, SL3-2, and SL4-2.

[0215] The first to fifth signal lines SL1-1, SL2-1, SL3-1, SL4-1, and SL5-1 of the first signal line group SGL-G1 may include first line portions SLA1, SLA2, SLA3, SLA4, and SLA5, second line portions SLB1, SLB2, SLB3, SLB4, and SLB5, and connecting portions SLC1, SLC2, SLC3, SLC4, and SLC5. The first line portions SLA1, SLA2, SLA3, SLA4, and SLA5 may extend in a second direction DR2. The second line portions SLB1, SLB2, SLB3, SLB4, and SLB5 may extend in the second direction DR2 and may be spaced apart from the first line portions SLA1, SLA2, SLA3, SLA4, and SLA5 in the second direction DR2. The connection portions SLC1 , SLC2 , SLC3 , SLC4 , and SLC5 may respectively connect the first line portions SLA1 , SLA2 , SLA3 , SLA4 , and SLA5 and the second line portions SLB1 , SLB2 , SLB3 , SLB4 , and SLB5 , and be inclined with respect to the first direction DR1 and the second direction DR2 .

[0216] In the direction viewed from the second direction DR2, the connection portions SLC1, SLC2, SLC3, SLC4, and SLC5 may partially overlap with the electrically insulated output pad OPD. Referring to the drawings, in the direction viewed from the second direction DR2, the fifth signal line SL5-1 of the first signal line group SGL-G1 may partially overlap with the second output pad OPD2-2.

[0217] According to one embodiment of the present invention, the second line portions SLB1, SLB2, SLB3, SLB4, and SLB5 can be displaced from the first line portions SLA1, SLA2, SLA3, SLA4, and SLA5 in the first direction DR1. Since the second line portions SLB1, SLB2, SLB3, SLB4, and SLB5 are displaced from the first line portions SLA1, SLA2, SLA3, SLA4, and SLA5 and connected to the first line portions SLA1, SLA2, SLA3, SLA4, and SLA5 via the connecting portions SLC1, SLC2, SLC3, SLC4, and SLC5, the area occupied by the signal lines SGL can be reduced. Consequently, a display device can be miniaturized.

[0218] The present invention is not limited thereto. Depending on the direction in which the fifth signal line SL5 - 1 comes out of the pad PD, the second line portions SLB1 , SLB2 , SLB3 , SLB4 , and SLB5 may be shifted to different degrees and in different directions. The present invention is not limited to a certain embodiment.

[0219] The shapes and arrangement relationships described above may also be applied to the signal lines SL1 - 2 , SL2 - 2 , SL3 - 2 , SL4 - 2 , and SL5 - 2 of the second signal line group SGL-G2 .

[0220] The line portions SLA1-5 and SLB1-5 of each of the first to fifth signal lines SL1-1, SL2-1, SL3-1, SL4-1, and SL5-1 can extend in the same direction. The connecting portions SLC1-5 of the signal lines SL1-1, SL2-1, SL3-1, SL4-1, and SL5-1 of the first signal line group SGL-G1 or the connecting portions of the first to fifth signal lines SL1-2, SL2-2, SL3-2, SL4-2, and SL5-2 of the second signal line group SGL-G2 can be aligned in the first direction DR1. The regular arrangement of the line portions and connecting portions can reduce the area occupied by the signal lines SGL.

[0221] However, this is not limited to this, and the connecting parts SLC1~5 of the signal lines SL1-1, SL2-1, SL3-1, SL4-1, and SL5-1 of the first signal line group SGL-G1 and the connecting parts SLC1~5 of the signal lines SL1-2, SL2-2, SL3-2, SL4-2, and SL5-2 of the second signal line group SGL-G2 can also be aligned in the first direction DR1, and are not limited to a certain embodiment.

[0222] Figure 8D A partial cross-sectional view of the display device of the present invention taken along a direction parallel to the first direction DR1 is shown. Figure 8D Show Figure 8C The cross-sectional plane II-II' is shown. Figure 8E A partial cross-sectional view of the display device of the present invention taken along a direction parallel to the second direction DR2 is shown.

[0223] Figure 8D As an example, the first output pad row OPD_R (refer to Figure 8A In this case, the first signal line SL1-1 and the second signal line SL2-1 may be arranged in different layers.

[0224] The first to third layers L1, L2, L3 may be sequentially arranged in the third direction DR3. The first to third layers L1, L2, L3 may be insulating layers, respectively.

[0225] A first output pad OPD1-1 and a first signal line SL1-1 may be disposed on the first layer L1. The first output pad OPD1-1 and the first signal line SL1-1 may be formed using the same process. A second output pad OPD2-1 and a second signal line SL2-1 may be disposed on the second layer L2. The second output pad OPD2-1 and the second signal line SL2-1 may be formed using the same process.

[0226] The first output pad OPD1-1 and the second output pad OPD2-1 may be disposed on different layers. The first signal line SL1-1 and the second signal line SL2-1 may be disposed on different layers. The first output pad OPD1-1 and the second output pad OPD2-1 may be disposed on different layers from the first signal line SL1-1 and the second signal line SL2-1 and may be insulated from each other.

[0227] Furthermore, the first output pad OPD1-1 and the first signal line SL1-1 may not overlap with the second output pad OPD2-1 and the second signal line SL2-1, respectively, in a plane, thereby preventing coupling between the signal lines SGL.

[0228] Although not shown, the first output pads OPD1-1 of the first output pad row OPD_R1 and the first output pads OPD1-2 of the second output pad row OPD_R2 can be arranged on different layers. The first output pads OPD1-1 of the first output pad row OPD_R1 and the second output pads OPD2-2 of the second output pad row OPD_R2 can be arranged on the same layer. However, this is not limiting, and the output pads of each output pad row can be arranged on the same layer, and this is not limited to a particular embodiment.

[0229] According to an embodiment of the present invention, the display device may further include a contact portion CNP. A plurality of contact portions CNP may be provided, and the number of the contact portions CNP may be configured to correspond to the number of the output pads OPD. Figure 8D , contact parts CNP corresponding to the output pads OPD of the first output pad row OPD_R1 are shown.

[0230] Among the plurality of contact portions CNP, the first contact portion CNP1-1 may overlap with the first output pad OPD1-1. The first contact portion CNP1-1 may penetrate the insulating layer disposed on the first output pad OPD1-1 and be connected to the first output pad OPD1-1. The first output bump OPB1-1 may be electrically connected to the first output pad OPD1-1 through the first contact portion CNP1-1.

[0231] Among the plurality of contact portions CNP, the second contact portion CNP2-1 may overlap with the second output pad OPD2-1. The second contact portion CNP2-1 may penetrate the insulating layer disposed on the second output pad OPD2-1 and be connected to the second output pad OPD2-1. The second output bump OPB2-1 may be electrically connected to the second output pad OPD2-1 through the second contact portion CNP2-1.

[0232] The reliability of the electrical connection between the output bump OPB and the output pad OPD can be ensured by the contact portion CNP. However, the contact portion CNP may be omitted and is not limited to a certain embodiment.

[0233] Although not shown, a plurality of conductive balls are provided on the second adhesive layer AF-D, thereby further improving the reliability of the electrical connection between the output bumps OPB and the output pads OPD.

[0234] Reference Figure 8E , the first gate G1 of the first transistor T1 and the second gate G2 of the second transistor T2 may be configured in different layers.

[0235] The first transistor T1 and the second transistor T2 may respectively overlap the display area, and the first output pad OPD1 - 1 and the second output pad OPD2 - 1 may respectively overlap the non-display area.

[0236] The first output pad OPD1-1 may be disposed on the same layer as the first gate G1. Specifically, the first output pad OPD1-1 may be disposed on the first layer L1. Furthermore, the first output pad OPD1-1 may overlap with the second layer L2 in cross section. The second output pad OPD2-1 may be disposed on the same layer as the second gate G2. Specifically, the second output pad OPD2-1 may overlap with the third layer L3 in cross section.

[0237] The first gate G1 and the first output pad OPD1-1 of the first transistor T1 can be formed in the same process. As previously described, the first signal line SL1-1, which is configured on the same layer as the first output pad OPD1-1, can also be formed in the same process as the first gate G1. The second gate G2 and the second output pad OPD2-1 of the second transistor T2 can also be formed in the same process. As previously described, the second signal line SL2-1, which is configured on the same layer as the second output pad OPD2-1, can also be formed in the same process as the second gate G2.

[0238] This applies not only to the first signal line group SGL-G1 (see Figure 8C ) of the first signal line SL1-1 (see Figure 8C ) and the second signal line SL2-1 (refer to Figure 8C), and can also be applied to the second signal line group SGL-G2 (refer to Figure 8C ) of the first signal line SL1-2 (refer to Figure 8C ) and the second signal line SL2-2 (refer to Figure 8C ), and the same applies to the first signal line group SGL-G1 (refer to Figure 8C ) and the second signal line group SGL-G2 (refer to Figure 8C ) other signal lines, and are not limited to a certain embodiment.

[0239] Although the drawings show that one layer is disposed between the first gate G1 of the first transistor T1 and the second gate G2 of the second transistor T2, the present invention is not limited thereto. Multiple layers may be disposed between the first gate G1 and the second gate G2. This is not limited to a particular embodiment.

[0240] Furthermore, although only the first gate G1 of the first transistor T1 and the second gate G2 of the second transistor T2 are shown in the drawings, it is not limited to this. The third gate of the third transistor may be configured on a different layer from the first gate G1 and the second gate G2, and the first output pad OPD1-1 or the second output pad OPD2-1 may be configured on the same layer as the third gate, and is not limited to a certain embodiment.

[0241] Although Figure 8E For the first output pad row OPD_R1 (refer to Figure 8A ) is illustrated in the figure, but this can also be similarly applied to the second to fourth output pad rows OPD_R2, OPD_R3, OPD_R4 (see Figure 8A ). And, in the second output pad row OPD_R2 (refer to Figure 8A ), the first output pad OPD1-2 (refer to Figure 8B ) can be configured on the same layer as the second gate G2, and the second output pad OPD2-2 (refer to Figure 8B ) can be configured on the same layer as the first gate G1.

[0242] Figures 9A to 9C FIG. 1 is an enlarged plan view of a portion of a pad region of a display device according to an embodiment of the present invention.

[0243] and Figures 8A to 8C Compared with the second output pad OPD2 of one embodiment of the present invention, Figures 9A to 9C The second output pad OPD2a of an embodiment of the present invention may be further shifted in the second direction DR2.

[0244] at this time, Figures 9A to 9CThe interval between the first output pad OPD1a and the second output pad OPD2a of the embodiment may be substantially the same as Figures 8A to 8C The interval between the first output pad OPD1 and the second output pad OPD2 is the same, but is not limited thereto, and may be greater or less than Figures 8A to 8C The aforementioned interval is not limited to a certain embodiment.

[0245] Hereinafter, the same reference numerals will be given to the same structures as those of the embodiment of the present invention described in the above drawings, and detailed description will be omitted.

[0246] Reference Figure 9A and Figure 9B ,and Figures 8A to 8C Compared to the embodiment of the present invention shown in FIG. 1 , the shift degree of the second output pads OPD2a of the plurality of output pad rows OPD_Ra in the second direction DR2 and in the extending direction of the signal line SGLa may be partially different. The first pattern PDG1a, the second pattern PDG2a, the third pattern PDG3a, and the fourth pattern PDG4a may be arranged in a zigzag manner along the arrangement direction of the output pads OPD of the first output pad row OPD_R1a.

[0247] According to one embodiment of the present invention, the fourth distance D4 (see Figure 7 That is, in the second direction DR2, the distance by which the second output pad OPD2a is shifted may be greater than or equal to the interval between the first output pad OPD1a of one output pad row and the first output pad OPD1a of another output pad row.

[0248] Reference Figure 9C , signal line SGLa (refer to Figure 9A ) may include a first signal line group SGL-G1a and a second signal line group SGL-G2a. One of the first line portion SLA5 and the second line portion SLB5 of the fifth signal line SL5-1a of the first signal line group SGL-G1a may include a slanted portion SLD. The slanted portion SLD may be inclined relative to the first direction DR1 and the second direction DR2. The slanted portion SLD may be displaced from the connection portion SLC5 in the first direction DR1. Furthermore, the line portions on one side and the other side of the slanted portion SLD may be displaced relative to each other in the first direction DR1.

[0249] The inclined portion SLD may not be aligned with the connection portion SLC5 of the fifth signal line SL5-1a in the first direction DR1. However, the inclined portions SLD and the connection portions of different signal line groups may be aligned in the first direction DR1 without being limited to a certain embodiment.

[0250] The inclined portion SLD may partially overlap the electrically insulated pad as viewed in the second direction DR2. Referring to the drawings, the fifth signal line SL5-1a of the first signal line group SGL-G1a may partially overlap the first pad PD1a as viewed in the second direction DR2.

[0251] By providing the inclined portion SLD as described above, even at the second distance D2 (refer to Figure 9B ) is greater than or equal to the first distance D1 (refer to Figure 9B ) can also be configured so that each signal line SGLa (refer to Figure 9A ) are separated from each other by a predetermined interval. According to this, the scalability of the pad position design can be increased.

[0252] Furthermore, by making each signal line SGLa (refer to Figure 9A ) are arranged at a predetermined interval, which can prevent the signal line SGLa (refer to Figure 9A ) between the signal lines SGLa (see Figure 9A ) overlap each other on the plane to prevent coupling.

[0253] Each signal line SGLa (refer to Figure 9A ) can be less than 2 microns, and each signal line SGLa (refer to Figure 9A ) can be spaced less than 1 micron. Preferably, each signal line SGLa (refer to Figure 9A ) can be 1 micron wide, and each signal line SGLa (refer to Figure 9A ) can be 0.5 microns. Figure 9A ) is set to less than 0.5 microns, which can improve the output pad OPDa (reference Figure 9B ) in the area between the signal line SGLa (refer to Figure 9A Furthermore, it is possible to prevent the signal line SGLa (see Figure 9A ) density is reduced.

[0254] Figure 10 FIG. 1 is an enlarged plan view of a portion of a pad region of a display device according to an embodiment of the present invention.

[0255] Hereinafter, the same reference numerals will be given to the same components as those of the embodiment of the present invention described in the aforementioned drawings, and detailed description thereof will be omitted.

[0256] Reference Figure 10The output pads OPD1-1c, OPD2-1c, OPD1-2c, and OPD2-2c of the present invention may have shapes other than rectangles. As an example, the output pads OPD1-1c, OPD2-1c, OPD1-2c, and OPD2-2c of the present invention may have shapes with partially cut corners. This increases the area through which the signal lines SGL-1 and SGL-2 pass. Providing such an area allows for design freedom regarding the spacing between the output pads OPD1-1c, OPD2-1c, OPD1-2c, and OPD2-2c, as well as the extended or tilted shape of the signal lines SGL-1 and SGL-2.

[0257] Figure 11 FIG. 1 is a top view of a chip region of a display device according to an embodiment of the present invention.

[0258] Reference Figure 11 , the input pad portion IPDR may include a plurality of input pads IPD.

[0259] The input pads IPD may have the same shape as each other and may be arranged side by side with each other.

[0260] Driver chip DC (refer to Figure 4 ) may include a plurality of input bumps IPB connected to the plurality of input pads IPD. The input bumps IPB may overlap with the input pads IPD on a plane.

[0261] The input bumps IPB may have the same shape. Also, the input bumps IPB may have a partially symmetrical shape, but this is not limited to a certain embodiment.

[0262] According to an embodiment of the present invention, the input bumps IPB arranged in the same row may be arranged in a zigzag pattern in the first direction DR1 , that is, adjacent input bumps IPB may be shifted by a predetermined distance in the second direction DR2 so as to be partially staggered.

[0263] Since the input bumps IPB are arranged in a zigzag pattern, when the input pads IPD and the input bumps IPB are electrically connected to the driver chip DC (see Figure 4 ) when heat and pressure are applied, it is possible to prevent deformation or cracks caused by the pressure (or stress) being concentrated on the area adjacent to the input pad IPD. That is, when pressure (or stress) is applied to the area adjacent to the input pad IPD, by preventing the areas to which pressure (or stress) is applied from being arranged regularly in a specific direction (for example, the first direction DR1), it is possible to prevent the pressure (or stress) from being distributed uniformly over the entire display panel DP (refer to FIG. Figure 4 ) is evenly distributed within the range of . Thus, it is possible to prevent the Figure 4 ) and the local deformation in the entire display panel DP (refer to Figure 4 ) causes deformation.

[0264] In the embodiment of the present invention where the input bumps IPB are arranged in a zigzag manner, the pressure (or stress) applied to the area adjacent to the input pad IPD can be reduced by 8% to 13% compared to the case where the input bumps IPB are not arranged in a zigzag manner (comparative example).

[0265] Furthermore, in the case of the embodiment of the present invention, the deformation amount of the display panel in the thickness direction can be reduced by about 16% to 17% compared with the aforementioned comparative example.

[0266] Figure 12A and Figure 12B FIG. 1 is an enlarged plan view of a portion of a pad region of a display device according to an embodiment of the present invention. Figure 12A It will Figure 11 The input pad portion IPDR is shown in an enlarged top view. Figure 12B is shown with Figure 12A FIG. 1 is a top view of an input pad portion IPDRa according to another embodiment of the present invention that is different from the embodiment of the present invention.

[0267] Reference Figure 12A The input bumps IPB may include a plurality of first input bumps IPB1 and a plurality of second input bumps IPB2. The input bumps IPB1 and IPB2 may be arranged in a zigzag pattern in the first direction DR1. That is, adjacent input bumps IPB may be shifted a predetermined distance in the second direction DR2 so that a portion of the adjacent input bumps IPB are staggered.

[0268] Referring to the drawings, the second input bump IPB2 may be configured to be shifted from the first input bump IPB1 by a fifth distance D5 in the second direction DR2 .

[0269] Reference Figure 12B , the input pads IPD may include a plurality of first input pads IPD1 and a plurality of second input pads IPD2.

[0270] The first input pads IPD1 may be arranged along the first direction DR1. The second input pads IPD2 may be arranged alternately with the first input pads IPD1 along the first direction DR1. The second input pads IPD2 may be arranged shifted from the first input pads IPD1 by a predetermined distance in the second direction DR2.

[0271] Referring to the drawings, the second input bump IPB2 may be shifted from the first input bump IPB1 by a fifth distance D5 in the second direction DR2 , and the second input pad IPD2 may be shifted from the first input pad IPD1 by a sixth distance D6 in the second direction.

[0272] The sixth distance D6 may be less than or equal to the fifth distance D5. By adjusting the difference between the fifth distance D5 and the sixth distance D6, the areas occupied by the input pads IPD and the input bumps IPB in the chip area DCA may be adjusted.

[0273] By arranging the input pads IPD1 and IPD2 in a zigzag manner and / or arranging the input bumps IPB1 and IPB2 in a zigzag manner, it is possible to install the driver chip DC (refer to Figure 4 ) to minimize cracks or breakage that may occur.

[0274] Figure 13 FIG. 1 is a top view of a chip region of a display device according to an embodiment of the present invention.

[0275] exist Figure 13 In the chip area of ​​the display device shown, the Figure 5 As shown, the output pads OPD and the output bumps OPB may be arranged in a zigzag manner along the first direction DR1 .

[0276] Moreover, with the aforementioned Figure 12A and Figure 12B Similarly, the input bumps IPB may be arranged in a zigzag manner along the first direction DR1 , but the arrangement is not limited thereto. The input pads IPD may also be arranged in a zigzag manner along the first direction DR1 , and the arrangement is not limited to a particular embodiment.

[0277] Although the above description is based on the preferred embodiments of the present invention, it will be understood by those skilled in the art or those of ordinary skill in the art that various modifications and variations may be made to the present invention without departing from the spirit and technical scope of the present invention as described in the appended claims. Therefore, the technical scope of the present invention should not be limited to the details described in the specific embodiments of the specification, but should be defined by the appended claims.

Claims

1. A display device, in, include: The display panel includes a plurality of first-row output pads and a plurality of second-row output pads, wherein the plurality of first-row output pads are arranged along a first direction, and the plurality of second-row output pads are spaced apart from the plurality of first-row output pads by a first distance in a second direction intersecting the first direction. a driver chip comprising a plurality of first-row output bumps and a plurality of second-row output bumps, wherein the plurality of first-row output bumps are arranged along the first direction and connected to the first-row output pads, and the plurality of second-row output bumps are separated from the plurality of first-row output bumps by a second distance in the second direction and connected to the second-row output pads, wherein the second distance is greater than or equal to the first distance; Each of the first row of output pads and the second row of output pads includes: a plurality of first output pads aligned along the first direction, and a plurality of second output pads aligned along the first direction, arranged alternately with the first output pads along the first direction, and shifted from the first output pads by a fourth distance in the second direction; Each of the first row of output bumps and the second row of output bumps comprises: a plurality of first output bumps aligned along the first direction and connected to the first output pads respectively; and A plurality of second output bumps are aligned along the first direction and connected to the second output pads respectively, and are arranged to be shifted from the first output bumps by a third distance in the second direction.

2. The display device according to claim 1, wherein The fourth distance is smaller than the first distance.

3. The display device according to claim 1, wherein The third distance is smaller than the second distance.

4. The display device according to claim 1, wherein The fourth distance is equal to or smaller than the third distance.

5. The display device according to claim 1, wherein The first output pad of the first row of output pads is aligned with the first output pad of the second row of output pads in the second direction, The second output pad of the first row of output pads is aligned with the second output pad of the second row of output pads in the second direction. The display device according to claim 1 , wherein: The display panel further includes: multiple pixels, and a plurality of signal lines connecting the pixels with the first row of output pads and the second row of output pads; The signal line includes: a first signal line group arranged between the first output pad and the second output pad adjacent to each other in the same row; and a second signal line group separated from the first signal line group by the second output pad in the first direction; Each of the first signal line group and the second signal line group includes: a first signal line connected to one of the first output pad and the second output pad; and The second signal line is electrically insulated from the first signal line.

7. The display device according to claim 6, wherein: Each of the plurality of signal lines includes: a first line portion parallel to the second direction, a second line portion parallel to the second direction and spaced apart from the first line portion in the second direction, and a connecting portion connecting the first line portion and the second line portion and inclined relative to the first direction and the second direction; The second line portion is displaced from the first line portion in the first direction.

8. The display device according to claim 7, wherein: The connection portions of the signal lines of the first signal line group and the connection portions of the signal lines of the second signal line group are aligned along the first direction.

9. The display device according to claim 6, wherein: Each of the plurality of pixels comprises: a first transistor including a first gate, and a second transistor comprising a second gate configured at a different layer from the first gate; The first signal line and the first gate are arranged on the same layer, The second signal line and the second gate are arranged on the same layer.

10. The display device according to claim 9, wherein The first signal line does not overlap with the second signal line in a plane.

11. The display device according to claim 9, wherein It also includes a contact portion, the contact portion penetrates the insulating layer configured on the first output pad and is connected to the first output pad, The first output bump is electrically connected to the first output pad through the contact portion.

12. The display device according to claim 7, wherein: Each of the first signal line group and the second signal line group further includes: a third signal line electrically insulated from the second signal line and separated from the first signal line via the second signal line; Each of the first to third signal lines includes the first line portion, the second line portion, and the connecting portion, the second line portion being shifted from the first line portion in the first direction; The first line portion or the second line portion of the third signal line further includes an inclined portion shifted from the connection portion of the third signal line in the first direction.

13. The display device according to claim 12, wherein: The connecting portions of the first signal line to the third signal line are aligned in the first direction, The fourth distance is greater than or equal to the first distance.

14. The display device according to claim 1, wherein The display panel further includes a plurality of input pads, which are spaced apart from the second row of output pads in the second direction and arranged along the first direction. The driver chip further includes a plurality of input bumps, which are spaced apart from the second row of output bumps in the second direction and connected to the input pads. The input bump comprises: a plurality of first input bumps aligned along the first direction, and A plurality of second input bumps are aligned along the first direction, arranged alternately with the first input bumps along the first direction, and are shifted from the first input bumps by a fifth distance in the second direction.

15. The display device according to claim 14, wherein The input pad includes: a plurality of first input pads aligned along the first direction and electrically connected to the first input bumps, and a plurality of second input pads aligned along the first direction and electrically connected to the second input bumps; The second input pad is arranged to be shifted from the first input pad by a sixth distance in the second direction.

16. The display device according to claim 15, wherein The sixth distance is less than or equal to the fifth distance.

17. A display device, in, include: A display panel includes a plurality of first-row output pads, a plurality of second-row output pads, and a plurality of input pads, wherein the plurality of first-row output pads are arranged along a first direction, the plurality of second-row output pads are spaced apart from the plurality of first-row output pads by a first distance in a second direction intersecting the first direction, and the plurality of input pads are spaced apart from the second-row output pads in the second direction and arranged along the first direction; a driver chip comprising a plurality of first-row output bumps, a plurality of second-row output bumps, and a plurality of input bumps, wherein the plurality of first-row output bumps are arranged along the first direction and connected to the first-row output pads, the plurality of second-row output bumps are spaced apart from the plurality of first-row output bumps by a second distance in the second direction and connected to the second-row output pads, the second distance being greater than or equal to the first distance, and the plurality of input bumps are spaced apart from the plurality of second-row output bumps by an interval in the second direction and connected to the input pads; Each of the first row of output bumps and the second row of output bumps comprises: a plurality of first output bumps aligned along the first direction, and a plurality of second output bumps aligned along the first direction, arranged alternately with the first output bumps along the first direction, and displaced from the first output bumps by a third distance in the second direction; The input bump comprises: a plurality of first input bumps aligned along the first direction, and A plurality of second input bumps are aligned along the first direction, arranged alternately with the first input bumps along the first direction, and arranged to be shifted from the first input bumps in the second direction.

18. The display device according to claim 17, wherein: Each of the first row of output pads and the second row of output pads includes: a plurality of first output pads aligned along the first direction and electrically connected to the first output bumps, and a plurality of second output pads aligned along the first direction, arranged alternately with the first output pads along the first direction, and electrically connected to the second output bumps; The second output pad is arranged to be shifted from the first output pad by a fourth distance in the second direction.

19. The display device according to claim 17, wherein: The input pad includes: a plurality of first input pads aligned along the first direction and electrically connected to the first input bumps, and a plurality of second input pads aligned along the first direction and electrically connected to the second input bumps; The second input pad is arranged to be shifted from the first input pad in the second direction.

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