Stability monitoring circuit for LDO output voltage

Abstract

The embodiment of the invention provides an LDO output voltage stability monitoring circuit, which comprises an LDO main circuit, a voltage division circuit, a first voltage generation circuit, a second voltage generation circuit, a comparison circuit and a logic circuit, and is characterized in that the voltage division circuit is coupled with the LDO main circuit and is configured to divide the output voltage of the LDO main circuit through a resistor to obtain a first divided voltage; the first voltage generation circuit is configured to perform half-wave rectification on the first partial voltage and charge the capacitor to obtain a first voltage; a second voltage generation circuit configured to generate a second voltage; a comparison circuit configured to compare the first voltage and the second voltage and output a voltage comparison signal; the logic circuit is configured to jointly control the LDO main circuit to be turned on and turned off through the voltage comparison signal and an enable signal of the LDO main circuit. The stability of the output voltage in the use process of the LDO is better guaranteed, and the risk of a post-stage circuit is reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of power supply technology, and in particular, to a stability monitoring circuit for an LDO output voltage. Background Art

[0002] Low Dropout Regulator (LDO) is a common power supply chip with the characteristics of simple structure, low cost, and small output voltage ripple. It is widely used in the electronics / automotive / aerospace fields.

[0003] If the output voltage of an LDO is unstable during operation, it may exceed the set voltage, potentially damaging downstream circuitry. Causes of LDO output voltage instability include: 1. Disconnection of the external large capacitor used with the LDO, causing system instability and output voltage instability; 2. Output voltage oscillation can also occur if the external large capacitor's capacitance drifts (e.g., too small) or if internal LDO device parameters drift during LDO operation. A common solution for the first issue is to check the external capacitor's connection during the LDO chip's power-up phase. If the connection is good, the LDO can be powered on normally; if there's a problem, the LDO is shut down. However, this approach only checks the connection at power-up and cannot prevent the possibility of the external capacitor suddenly becoming improperly connected during operation after the LDO has finished powering on, thus posing a certain application risk. For the second issue, since the oscillation amplitude is small, it's more likely to fall within the system's overvoltage (OVUV) protection range. However, persistent small-amplitude oscillations can still affect downstream circuitry.

[0004] In summary, how to better ensure the stability of the output voltage during the use of LDO and reduce the risk of the subsequent circuit is an urgent problem to be solved. Summary of the Invention

[0005] The embodiments described in this disclosure provide a stability monitoring circuit for an LDO output voltage, in order to better ensure the stability of the output voltage during the use of the LDO and reduce the risk of subsequent circuits.

[0006] According to a first aspect of the present disclosure, a circuit for monitoring the stability of an LDO output voltage is provided. The circuit comprises: an LDO main circuit, a voltage divider circuit, a first voltage generating circuit, a second voltage generating circuit, a comparison circuit, and a logic circuit. The LDO main circuit is configured to adjust the conduction state of a first transistor coupled to an input voltage based on an error signal between a feedback signal of the output voltage and a first reference voltage to maintain the output voltage stable. The voltage divider circuit is coupled to the output voltage and configured to divide the output voltage by a resistor to obtain a first divided voltage. The first voltage generating circuit is configured to perform half-wave rectification on the first divided voltage obtained by the voltage divider circuit and charge a capacitor to obtain a first voltage. The second voltage generating circuit is configured to generate a second voltage, which is related to the first voltage. The comparison circuit is coupled to the first and second voltage generating circuits and configured to receive the first and second voltages and output a voltage comparison signal after comparison. The logic circuit is configured to use the voltage comparison signal and an enable signal of the LDO main circuit to control the on / off of the LDO main circuit.

[0007] Optionally, the first voltage generating circuit includes: a diode, a first resistor, and a first capacitor, wherein the positive electrode of the diode is coupled to the first divided voltage output by the voltage divider circuit, and the negative electrode of the diode is coupled to one end of the first resistor and one end of the first capacitor respectively; the other end of the first resistor and the other end of the first capacitor are both coupled to the ground end; the voltage at one end of the first capacitor is the first voltage.

[0008] Optionally, the second voltage generating circuit is coupled to the first voltage generating circuit, and the second voltage generating circuit includes: k low-pass filtering circuits, k is a positive integer, wherein the k low-pass filtering circuits are connected in series in sequence, the input end of the first low-pass filtering circuit is coupled to the first voltage generated by the first voltage generating circuit, and the output end of the kth low-pass filtering circuit outputs the second voltage.

[0009] Optionally, the low-pass filter circuit includes: a filter resistor and a filter capacitor, wherein one end of the filter resistor serves as the input end of the low-pass filter circuit, and the other end of the filter resistor serves as the output end of the low-pass filter circuit; one end of the filter capacitor is coupled to the other end of the filter resistor, and the other end of the filter capacitor is coupled to the ground end.

[0010] Optionally, the second voltage generating circuit provides a second reference voltage as the second voltage, and the value of the second reference voltage is equal to the DC component of the first divided voltage minus the conduction voltage of the diode.

[0011] Optionally, the comparison circuit includes a comparator, wherein a positive input terminal of the comparator is coupled to the second voltage, a negative input terminal of the comparator is coupled to the first voltage, and an output terminal of the comparator outputs the voltage comparison signal.

[0012] Optionally, the logic circuit includes: an AND gate, wherein a first input terminal of the AND gate is coupled to the voltage comparison signal output by the comparison circuit, a second input terminal of the AND gate is coupled to the enable signal of the LDO main circuit, and an output terminal of the AND gate is coupled to the enable terminal of the error amplifier in the LDO main circuit.

[0013] Optionally, the voltage divider circuit includes a second resistor and a third resistor, wherein one end of the second resistor is coupled to the output voltage of the LDO main circuit, and the other end of the second resistor is coupled to one end of the third resistor; the other end of the third resistor is coupled to the ground end, and the node between the second resistor and the third resistor outputs the first divided voltage.

[0014] Optionally, the comparison speed of the comparison circuit is positively correlated with the number k of low-pass filter circuits in the second voltage generating circuit.

[0015] Optionally, the LDO main circuit includes: the first transistor, an error amplifier, a fourth resistor, a fifth resistor, and an output capacitor, wherein the first electrode of the first transistor is coupled to the input voltage, the second electrode of the first transistor serves as the output end of the LDO main circuit, outputting the output voltage, and the control electrode of the first transistor is coupled to the output end of the error amplifier; one end of the fourth resistor is coupled to the output end, the other end of the fourth resistor is coupled to one end of the fifth resistor, and the other end of the fifth resistor is coupled to the ground end; one end of the output capacitor is coupled to the output end, and the other end of the output capacitor is coupled to the ground end; the positive input end of the error amplifier is coupled to the first reference voltage, the negative input end of the error amplifier is coupled to the node between the fourth resistor and the fifth resistor, and the enable end of the error amplifier is coupled to the output end of the logic circuit.

[0016] In the LDO output voltage stability monitoring circuit of the embodiment of the present disclosure, the output voltage of the LDO is divided by a resistor to obtain a first divided voltage through a voltage divider circuit, and the first divided voltage is half-wave rectified and charged to a capacitor to obtain a first voltage; the first voltage and the second voltage (the second voltage is a voltage associated with the first voltage) are compared to output a voltage comparison signal, and the LDO main circuit is controlled to be turned on and off according to the voltage comparison signal and the enable signal of the LDO main circuit. For the monitoring circuit in the embodiment of the present disclosure, when the output voltage of the LDO is unstable and the waveform of the output voltage oscillates, the output voltage is divided to obtain a first divided voltage, and the first divided voltage is charged to the capacitor after half-wave rectification to increase the capacitor voltage (i.e., the first voltage), and the first voltage and the second voltage are input to the comparison circuit. When the comparison circuit output voltage comparison signal becomes low, the LDO main circuit can be controlled to be turned off by the logic circuit to avoid affecting the subsequent circuit. The monitoring circuit of the embodiment of the present disclosure can monitor the high-frequency large oscillation of the output voltage due to the disconnection of the external large capacitor, and can also monitor the small oscillation due to the offset of the device parameters. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0018] Figure 1 A schematic block diagram of a LDO output voltage stability monitoring circuit according to an embodiment of the present disclosure is shown;

[0019] Figure 2 An exemplary circuit diagram of an LDO output voltage stability monitoring circuit according to an embodiment of the present disclosure is shown;

[0020] Figure 3 An exemplary circuit diagram showing another LDO output voltage stability monitoring circuit according to an embodiment of the present disclosure;

[0021] Figure 4-5 Shown Figure 2 Schematic diagram of the waveform of the key signals corresponding to the LDO output voltage stability monitoring circuit under different conditions;

[0022] Elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0024] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant technology, and will not be interpreted in an idealized or overly formal form unless otherwise clearly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together should refer to the parts being directly combined together or combined through one or more intermediate components. In addition, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0025] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the directions of the conduction current between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as the control terminal, and the remaining two terminals of the MOS transistor are referred to as the first terminal and the second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0026] In order to better ensure the stability of the output voltage during the use of LDO and reduce the risk of the subsequent circuit, a LDO output voltage stability monitoring circuit is proposed. The LDO output voltage stability monitoring circuit of the embodiment of the present disclosure can perform real-time monitoring during the startup phase and the entire operation of the LDO. When the output voltage is unstable for more than a certain time (this time is mainly related to the amplitude of the output oscillation and the set offset voltage), the LDO main circuit will be automatically shut down. The following is a detailed description of the LDO output voltage stability monitoring circuit disclosed in the present disclosure.

[0027] like Figure 1As shown, an embodiment of the present disclosure provides a schematic block diagram of a LDO output voltage stability monitoring circuit 100, wherein the LDO output voltage oscillation monitoring circuit 100 includes an LDO main circuit 110, a voltage divider circuit 120, a first voltage generating circuit 130, a second voltage generating circuit 140, a comparison circuit 150, and a logic circuit 160.

[0028] The LDO main circuit 110 is configured to adjust the first transistor M1 ( M1 ) coupled to the input voltage Vin based on an error signal between a feedback signal of the output voltage Vout and a first reference voltage. Figure 1 The LDO main circuit 110 is a general circuit structure of an existing low voltage drop linear regulator. Figure 2 As shown, a circuit structure example diagram of an LDO main circuit 110 is provided, including a first transistor M1, an error amplifier EA, a fourth resistor R4, a fifth resistor R5, and an output capacitor Cout. A first electrode of the first transistor M1 is coupled to the input voltage Vin, a second electrode of the first transistor M1 serves as an output terminal of the LDO main circuit 110, outputting the output voltage Vout, and a control electrode of the first transistor M1 is coupled to the output terminal of the error amplifier EA. One end of the fourth resistor R4 is coupled to the output terminal (Vout terminal), the other end of the fourth resistor R4 is coupled to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is coupled to ground. One end of the output capacitor Cout is coupled to the output terminal, and the other end of the output capacitor Cout is coupled to ground. A positive input terminal of the error amplifier EA is coupled to the first reference voltage Vref1, a negative input terminal of the error amplifier EA is coupled to a node between the fourth resistor R4 and the fifth resistor R5 (i.e., a feedback voltage VFB output terminal), and an enable terminal EN of the error amplifier EA is coupled to the output terminal of the logic circuit 160. Figure 2 Where VFB is the feedback signal of the output voltage Vout. The error amplifier EA compares VFB with the first reference voltage Vref1 to generate an error signal. The conduction degree of M1 is controlled according to the error signal, so that the output voltage Vout is maintained at a stable value. When the output voltage Vout increases, the error signal output by the error amplifier EA decreases, the conduction degree of M1 decreases, and the output voltage Vout decreases; conversely, when the output voltage Vout decreases, the error signal output by the error amplifier EA increases, the conduction degree of M1 increases, and the output voltage Vout increases.

[0029] The voltage divider circuit 120 is coupled to the output voltage Vout and is configured to divide the output voltage Vout by resistors to obtain a first divided voltage Vd. The voltage divider circuit 120 is composed of resistors connected in series. The voltage divider circuit 120 can obtain a suitable feedback voltage by designing the ratio of the resistors in the voltage divider circuit 120 according to the parameters of the desired comparator, which is very flexible. For example, if the selected comparator is to compare at a DC voltage point of 0.6V, a feedback voltage with a DC divided voltage of 0.6V can be obtained through the voltage divider circuit 120 to adapt to the selected comparator; if the selected comparator is to compare at a DC voltage point of 2V, a feedback voltage with a DC divided voltage of 2V can be obtained through the voltage divider circuit 120 to adapt to the selected comparator.

[0030] The first voltage generating circuit 130 is configured to perform half-wave rectification on the first divided voltage Vd obtained by the voltage divider circuit 120, and charge the capacitor to obtain a first voltage V1. The embodiment of the present disclosure utilizes the unidirectional conduction characteristic of the diode D to perform rectification, removing half a cycle and leaving half a cycle. When the LDO output voltage Vout is unstable, the waveform of Vout will oscillate, which is equivalent to alternating current. After passing through the diode D, the alternating current can be converted into direct current. The direct current rectified by the diode D is charged to the capacitor, so that a first voltage V1 can be formed on the capacitor. As the output voltage Vout continues to oscillate, the first voltage V1 will continue to rise.

[0031] The second voltage generating circuit 140 is configured to generate a second voltage V2, which is related to the first voltage V1. Specifically, the second voltage V2 can be obtained by passing the first voltage V1 through one or more low-pass filters, or can be directly designed based on the DC voltage portion of the first voltage V1. Specifically, Figure 2 and 3 The two circuit schematic diagrams for obtaining the second voltage V2 are shown respectively. Figure 2 Corresponding to the first embodiment described above, the second voltage generating circuit 140 includes k low-pass filter circuits 141, where k is a positive integer. The k low-pass filter circuits 141 are connected in series, with the input of the first low-pass filter circuit 141 coupled to the first voltage V1 generated by the first voltage generating circuit 130, and the output of the k-th low-pass filter circuit 141 outputting the second voltage V2. When k=1, the second voltage generating circuit 140 includes one low-pass filter circuit 141. Figure 2It is just a schematic diagram, and does not mean that the second voltage generating circuit 140 must include two or more low-pass filter circuits 141. The comparison speed of the comparison circuit 150 is positively correlated with the number k of the low-pass filter circuits 141, that is, the more low-pass filter circuits 141 there are, the faster the comparison circuit 150 can compare the results, because the higher the number of low-pass filter levels, the more stable the second voltage V2 obtained after the first voltage V1 (the first voltage V1 has the largest AC amount before filtering) is low-pass filtered, and the shorter the time it takes for the comparison circuit 150 to compare the results, so the results can be compared faster. In addition, the more low-pass filter circuits 141 there are, the more resources are consumed. Therefore, in actual applications, an appropriate k value can be set according to actual needs. If the comparison time requirement is not high, a small number of low-pass filter circuits 141 can be selected. For each low-pass filter circuit 141, Figure 2 A circuit example diagram is also shown, including: a filter resistor R0 and a filter capacitor C0, wherein one end of the filter resistor R0 serves as the input end of the low-pass filter circuit 141, and the other end of the filter resistor R0 serves as the output end of the low-pass filter circuit 141; one end of the filter capacitor C0 is coupled to the other end of the filter resistor R0, and the other end of the filter capacitor C0 is coupled to the ground end. Figure 2 The figure is an example. In actual applications, the low-pass filter circuit 141 can also be other circuit structures as long as it can achieve the low-pass filtering effect.

[0032] Figure 3 Corresponding to the second method mentioned above, that is, directly providing a second reference voltage (DC voltage) as the second voltage V2, the value of the second reference voltage is equal to the DC component of the first divided voltage Vd minus the conduction voltage of the diode D. It can be seen that the DC component of the first divided voltage Vd minus the conduction voltage of the diode D is related to the first voltage. Compared with Figure 2 The first method has the advantage of faster comparison results. However, it has the disadvantage that the second voltage generating circuit 140 does not obtain the second voltage V2 by direct coupling with the first voltage V1, so there may be some inaccuracies. In addition, the Vd voltage needs to be detected and then calculated with the conduction voltage of the diode D, which is more troublesome.

[0033] The comparison circuit 150 is coupled to the first voltage generating circuit 130 and the second voltage generating circuit 140, and is configured to receive the first voltage V1 and the second voltage V2, and output a voltage comparison signal System_OK after comparison; the comparison circuit 150 is composed of a comparator A0 with a fixed offset voltage Vos. Figure 2As shown in FIG3 , the positive input of comparator A0 is coupled to the second voltage V2, and the negative input of comparator A0 is coupled to the first voltage V1. The actual comparison is between V1 and V2 + Vos. The output of comparator A0 outputs the voltage comparison signal System_OK. This voltage comparison signal System_OK is used to indicate whether the output voltage Vout of the LDO main circuit 110 is stable. If the voltage comparison signal System_OK is high, the output voltage Vout is stable. If the voltage comparison signal System_OK is low, the output voltage Vout is unstable.

[0034] The logic circuit 160 is configured to use the voltage comparison signal System_OK and the LDO main circuit enable signal EN_LDO to control the on / off state of the LDO main circuit 110. Specifically, the control logic of the logic circuit 160 is such that when both the LDO main circuit enable signal EN_LDO and the voltage comparison signal System_OK are high, the LDO main circuit 110 can be turned on to ensure stable output; if either signal is low, the LDO main circuit 110 must be turned off.

[0035] As can be seen from the above description, in the LDO output voltage stability monitoring circuit 100 according to the embodiment of the present disclosure, the LDO output voltage Vout is divided by a resistor through the voltage divider circuit 120 to obtain a first divided voltage Vd, the first divided voltage Vd is then half-wave rectified, and a capacitor is charged to obtain a first voltage V1; the first voltage V1 is compared with a second voltage V2 (the second voltage V2 is a voltage associated with the first voltage V1) to output a voltage comparison signal System_OK, and the LDO main circuit 110 is controlled to be turned on and off according to the voltage comparison signal System_OK and the enable signal EN_LDO of the LDO main circuit. For the monitoring circuit in the embodiment of the present disclosure, when the output voltage Vout of the LDO is unstable, the waveform of the output voltage Vout will oscillate. After the output voltage Vout is divided, a first divided voltage Vd is obtained. The first divided voltage Vd is charged to the capacitor after half-wave rectification, which can increase the capacitor voltage (i.e., the first voltage V1). The first voltage V1 and the second voltage V2 are input into the comparison circuit. When the output voltage comparison signal System_OK of the comparison circuit becomes low, the logic circuit 160 can control the shutdown of the LDO main circuit 110 to avoid affecting the subsequent circuit.

[0036] Furthermore, as shown in 2 or 3, the first voltage generating circuit 130 includes: a diode D, a first resistor R1, and a first capacitor C1. The anode of the diode D is coupled to the first divided voltage Vd output by the voltage divider circuit 120, and the cathode of the diode D is coupled to one end of the first resistor R1 and one end of the first capacitor C1, respectively. The other ends of the first resistor R1 and the first capacitor C1 are both coupled to ground. The voltage at one end of the first capacitor C1 is the first voltage V1. The first resistor R1 is provided to discharge the first voltage V1, preventing it from being accumulated by normal AC variations in the output voltage Vout, thereby making the first voltage V1 more stable.

[0037] Furthermore, as shown in Figures 2 and 3, the voltage divider circuit 120 includes a second resistor R2 and a third resistor R3, wherein one end of the second resistor R2 is coupled to the output voltage Vout of the LDO main circuit 110, and the other end of the second resistor R2 is coupled to one end of the third resistor R3; the other end of the third resistor R3 is coupled to the ground, and the node between the second resistor R2 and the third resistor R3 outputs the first divided voltage Vd; the ratio between the second resistor R2 and the third resistor R3 is adjusted according to the DC voltage comparison point of the comparator A0 in the comparison circuit 150.

[0038] Furthermore, as shown in 2 and 3, the logic circuit 160 includes: an AND gate AND, wherein a first input terminal of the AND gate AND is coupled to the voltage comparison signal System_OK output by the comparison circuit 150, a second input terminal of the AND gate AND is coupled to the enable signal EN_LDO of the LDO main circuit, and an output terminal of the AND gate AND is coupled to the enable terminal of the error amplifier EA in the LDO main circuit 110.

[0039] Combine Figure 2The working principle of the monitoring circuit 100 for the stability of the LDO output voltage Vout in the embodiment of the present disclosure is explained as follows: When the system has an external capacitor and the output is stable, the voltage value of V1 is equal to Vd-Vov (the conduction voltage of the diode D), and the voltage value of V2 is approximately equal to V1, so the output System_OK is a high level. At this time, the level of EN_LDO determines the opening and closing of the LDO main circuit 110. When there is no external capacitor (the external capacitor is disconnected), Vout will oscillate above and below the normal output value (the voltage value in steady state), and the oscillation frequency is generally above tens of kHz. The maximum oscillation amplitude will exceed the OUT_OV value (the maximum output value that the system can accept, which is also the value of the system over voltage protection). In order to avoid false flipping, the normal OVUV comparator A0 of the LDO system is generally set with a hysteresis of several us to tens of us, so it is impossible to detect the output of such high-frequency oscillation. Furthermore, if the LDO main circuit 110 becomes unstable due to special circumstances such as the external large capacitor having a low capacitance or LDO internal device parameter deviation during use, the Vout voltage will also begin to oscillate. The oscillation amplitude is smaller than when the external large capacitor is not present. The oscillation frequency is related to the system bandwidth and is likely within the system's OVUV protection range, making it undetectable by the system. However, in the disclosed embodiment, both high-frequency, large-amplitude oscillations and small-amplitude oscillations can be monitored. The specific monitoring principle is as follows: When Vout is unstable, the Vout waveform oscillates. Vout is divided by R2 and R3 to obtain Vd. Diode D performs half-wave rectification on Vd. The positive AC voltage on Vd charges C1, causing the V1 voltage to rise. When Vout is unstable, the V1 voltage gradually increases. For large oscillation amplitudes, V1 increases quickly, while for small amplitudes, V1 increases slowly. When the V1 voltage exceeds V2 + Vos, the System_OK signal goes low. A "logical AND" operation is performed on System_OK and EN_LDO to produce a low-level signal, which causes the EN terminal of the error amplifier EA controlling the LDO main circuit 110 to be low, thereby shutting down the LDO main circuit 110. In the absence of a large external capacitor, the relatively large amplitude causes V1 to rise quickly, allowing the resulting output instability to be quickly detected and the LDO main circuit to be quickly shut down. In the aforementioned small-amplitude case, because V1 rises slowly, it takes a relatively long time to detect the resulting output instability. However, as long as the oscillation persists, it can be detected. This small oscillation has a relatively small impact on the system in the short period of time after it occurs, so monitoring it over a relatively long period of time is sufficient for practical applications. Furthermore, after the Vout oscillation disappears, the LDO main circuit can be reopened with EN_LDO at a high level.

[0040] for Figure 3 The monitoring circuit 200 of the LDO output voltage Vout stability is Figure 2 The difference is that the input of comparator A0 is the size of V1 and Vref2. When the voltage of V1 gradually increases to be greater than Vref2+Vos, the System_OK signal will become low level, turning off the LDO main circuit 110. In addition to the above differences, Figure 3 and Figure 2 The rest of the work is the same.

[0041] Furthermore, in order to illustrate the monitoring effect of the embodiment of the present disclosure, a waveform diagram of key signals is provided. Figure 4-5 Shown is Figure 2 Corresponding key signals: waveform diagram of output voltage Vout, first voltage V1, second voltage V2, voltage comparison signal System_OK, from Figure 4 As can be seen in FIG, when Vout starts to oscillate, V1 starts to increase. When Vout continues to oscillate and V1 is greater than V2+Vos, System_OK changes from high to low, thereby shutting down the LDO main circuit 110. After shutdown, Vout immediately drops and V1 gradually drops. Figure 5 In the embodiment, when Vout starts to oscillate, V1 starts to increase, but before V1 becomes greater than V2+Vos, Vout returns to stability. In this case, System_OK is always high and the LDO main circuit 110 will not be shut down. Figure 5 The waveform diagram in the figure is to illustrate that the monitoring circuit of the embodiment of the present disclosure can also avoid some false triggering that only oscillates a few times and then recovers to stability but does not affect the stability of the system, which has important practical significance. Figure 3 The waveform diagram of the key signals corresponding to the circuit is the same as the following except that V2 is replaced by Vref2. Figure 4-5 They are the same and will not be repeated here.

[0042] In summary, the LDO output voltage stability monitoring circuit of the disclosed embodiment can process the AC waveform of the output voltage oscillation when the LDO is unstable, rectify it with a diode, and then charge the capacitor. The stability of VOUT is determined by the increase in the voltage on the charged capacitor exceeding a certain threshold. The logic circuit then automatically controls the switching of the LDO main circuit, thereby achieving real-time monitoring of the LDO output voltage stability. The monitoring circuit of the disclosed embodiment can not only detect oscillations in the case of capacitor disconnection; it can also detect small oscillations caused by internal component offsets after the LDO circuit has been used for a long time.

[0043] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it follows a group of terms, "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0044] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present disclosure can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended to be illustrative only and are not intended to limit the scope of the present disclosure.

[0045] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A LDO output voltage stability monitoring circuit, characterized in that: The monitoring circuit includes: an LDO main circuit, a voltage dividing circuit, a first voltage generating circuit, a second voltage generating circuit, a comparison circuit, and a logic circuit. The LDO main circuit is configured to adjust the conduction state of a first transistor coupled to the input voltage based on an error signal between a feedback signal of the output voltage and a first reference voltage, so as to keep the output voltage stable. The voltage divider circuit is coupled to the output voltage and is configured to divide the output voltage by resistors to obtain a first divided voltage; The first voltage generating circuit is configured to perform half-wave rectification on the first divided voltage obtained by the voltage divider circuit and charge the capacitor to obtain a first voltage; The second voltage generating circuit is configured to generate a second voltage, wherein the second voltage is related to the first voltage; The comparison circuit is coupled to the first voltage generating circuit and the second voltage generating circuit, and is configured to receive the first voltage and the second voltage and output a voltage comparison signal after comparison; The logic circuit is configured to use the voltage comparison signal and the enable signal of the LDO main circuit to control the turning on and off of the LDO main circuit.

2. The LDO output voltage stability monitoring circuit according to claim 1, wherein: The first voltage generating circuit includes: a diode, a first resistor, and a first capacitor. The anode of the diode is coupled to the first divided voltage output by the voltage divider circuit, and the cathode of the diode is coupled to one end of the first resistor and one end of the first capacitor respectively; The other end of the first resistor and the other end of the first capacitor are both coupled to the ground; The voltage at one end of the first capacitor is the first voltage.

3. The LDO output voltage stability monitoring circuit according to claim 1, wherein: The second voltage generating circuit is coupled to the first voltage generating circuit, and the second voltage generating circuit includes: k low-pass filter circuits, where k is a positive integer, Among them, k low-pass filter circuits are connected in series in sequence, the input end of the first low-pass filter circuit is coupled to the first voltage generated by the first voltage generating circuit, and the output end of the kth low-pass filter circuit outputs the second voltage.

4. The LDO output voltage stability monitoring circuit according to claim 3, wherein: The low-pass filter circuit includes: a filter resistor and a filter capacitor. Wherein, one end of the filter resistor serves as the input end of the low-pass filter circuit, and the other end of the filter resistor serves as the output end of the low-pass filter circuit; One end of the filter capacitor is coupled to the other end of the filter resistor, and the other end of the filter capacitor is coupled to the ground.

5. The LDO output voltage stability monitoring circuit according to claim 2, wherein: The second voltage generating circuit provides a second reference voltage as the second voltage, wherein the value of the second reference voltage is equal to the DC component of the first divided voltage minus the conduction voltage of the diode.

6. The LDO output voltage stability monitoring circuit according to claim 1, wherein: The comparison circuit includes a comparator, The positive input terminal of the comparator is coupled to the second voltage, the negative input terminal of the comparator is coupled to the first voltage, and the output terminal of the comparator outputs the voltage comparison signal.

7. The LDO output voltage stability monitoring circuit according to claim 1, wherein: The logic circuit includes: an AND gate, The first input terminal of the AND gate is coupled to the voltage comparison signal output by the comparison circuit, the second input terminal of the AND gate is coupled to the enable signal of the LDO main circuit, and the output terminal of the AND gate is coupled to the enable terminal of the error amplifier in the LDO main circuit.

8. The LDO output voltage stability monitoring circuit according to claim 1, wherein: The voltage divider circuit includes a second resistor and a third resistor. Wherein, one end of the second resistor is coupled to the output voltage of the LDO main circuit, and the other end of the second resistor is coupled to one end of the third resistor; The other end of the third resistor is coupled to the ground, and a node between the second resistor and the third resistor outputs the first divided voltage.

9. The LDO output voltage stability monitoring circuit according to claim 3, wherein: The comparison speed of the comparison circuit is positively correlated with the number k of low-pass filter circuits in the second voltage generating circuit.

10. The LDO output voltage stability monitoring circuit according to claim 1, wherein: The LDO main circuit includes: the first transistor, an error amplifier, a fourth resistor, a fifth resistor, and an output capacitor. Wherein, a first electrode of the first transistor is coupled to the input voltage, a second electrode of the first transistor serves as an output terminal of the LDO main circuit to output the output voltage, and a control electrode of the first transistor is coupled to the output terminal of the error amplifier; One end of the fourth resistor is coupled to the output terminal, the other end of the fourth resistor is coupled to one end of the fifth resistor, and the other end of the fifth resistor is coupled to the ground terminal; One end of the output capacitor is coupled to the output terminal, and the other end of the output capacitor is coupled to the ground terminal; A positive input terminal of the error amplifier is coupled to the first reference voltage, a negative input terminal of the error amplifier is coupled to a node between the fourth resistor and the fifth resistor, and an enable terminal of the error amplifier is coupled to an output terminal of the logic circuit.

Images