Multichannel signal sampling device and calibration system

Abstract

The present disclosure provides a multi-channel signal sampling device and a calibration system, belonging to the technical field of signal processing; the multi-channel signal sampling device comprises a PXIe chassis and at least two acquisition cards arranged in the PXIe chassis; the multi-channel signal sampling device further comprises a synchronization program component, which is executed to determine the delay data between each channel of each acquisition card and the trigger channel according to the trigger channel currently located in the first target acquisition card and the pre-stored synchronization calibration basic data, and to synchronize each channel and the trigger channel according to the delay data; the synchronization calibration basic data comprises single-board calibration data and cross-board calibration data; the multi-channel signal sampling device can solve the problems of high synchronization calibration cost and design difficulty existing in the current PXIe sampling device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of signal processing, and particularly relates to a multi-channel signal sampling device and a calibration system. BACKGROUND

[0002] PXIe (PCI Express Extensions for Instrumentation) test system is favored by most integrated circuit test manufacturers due to its standardization, universality and high maturity. For a PXIe multi-channel signal sampling device or system, a user can use different numbers of PXIe acquisition cards according to actual needs; however, even if the PXIe sampling system using the same type of acquisition card, there will inevitably be a delay, especially in the GHz high-speed signal acquisition application, this delay will cause the collected signal to have obvious misalignment, generally the misalignment is required to be less than one-fifth of the maximum bandwidth period of the acquisition card, that is, the misalignment needs to be less than 20 ps when the bandwidth is 1 GHz, and the higher the bandwidth, the higher the requirement, therefore, synchronization calibration is needed to improve the sampling accuracy of the signal.

[0003] At present, the synchronization calibration solution for the PXIe multi-channel signal sampling device mostly focuses on the hardware direction, for example, some use a specially designed clock board, and some use a high-precision synchronization machine to directly generate a high-precision synchronous sampling clock and a trigger signal, but there is a problem of high cost and design difficulty. SUMMARY

[0004] In view of the above problems, the present disclosure provides a multi-channel signal sampling device and a calibration system, which can reduce the hardware cost and design difficulty while ensuring the synchronization calibration accuracy.

[0005] In a first aspect, an embodiment provides the following technical solutions:

[0006] The multi-channel signal sampling device comprises a PXIe chassis and at least two acquisition cards arranged in the PXIe chassis, and the acquisition cards comprise a plurality of channels; the multi-channel signal sampling device further comprises a synchronization program component, which is executed to: determine delay data between each channel and a trigger channel of each acquisition card according to the trigger channel currently located in a first target acquisition card and pre-stored synchronization calibration basic data, and perform synchronization between each channel and the trigger channel according to the delay data; the synchronization calibration basic data comprises single-board calibration data and cross-board calibration data, the single-board calibration data comprises a number of interpolation points of delay between a trigger position of each channel in each acquisition card and a trigger position of a reference channel of the acquisition card, and the cross-board calibration data comprises a number of interpolation points of delay between the trigger position of the reference channel of each acquisition card and a trigger position of a reference channel of a second target acquisition card; the trigger position of each channel is a position at which a value of an interpolation point reaches a set value in sampling data of a trigger signal, and N interpolation points are included between two adjacent sampling points in the sampling data, and N is an integer greater than or equal to 2.

[0007] In some embodiments, the multi-channel signal sampling device further comprises a controller arranged in the PXIe chassis, each acquisition card is provided with a processor, and the synchronization program component comprises a first synchronization program and a second synchronization program; the first synchronization program is executed by the controller to: in response to a user instruction, determine a trigger channel located in a first target acquisition card, calculate a first number of interpolation points of difference between each channel in each acquisition card and the trigger channel according to the single-board calibration data and the cross-board calibration data, and send the first number of interpolation points of difference to the processor of the corresponding acquisition card as delay data; and the second synchronization program is executed by the processor to: perform synchronization between each channel in the acquisition card and the trigger channel according to the delay data.

[0008] In some embodiments, when the first target acquisition card is a p1th acquisition card, the trigger channel is a qth channel of the p1th acquisition card, the second target acquisition card is a p2th acquisition card, and the reference channel of all the acquisition cards is a kth channel of the acquisition card, the first synchronization program is executed by the controller to: calculate a first number of interpolation points of difference between a jth channel in an ith acquisition card and the trigger channel according to n_skew i_jk and n_skew p1_qk in the single-board calibration data, and n_skew ip2_k and n_skew p1p2_k in the cross-board calibration data; wherein n_skew i_jk is a number of interpolation points of delay between the jth channel of the ith acquisition card and the kth channel of the ith acquisition card; n_skew p1_qk is a number of interpolation points of delay between the qth channel of the p1th acquisition card and the kth channel of the p1th acquisition card; n_skewip2_k is the number of interpolation points between the kth channel of the ith acquisition card and the kth channel of the p2th acquisition card; n_skew p1p2_k is the number of interpolation points between the kth channel of the p1th acquisition card and the kth channel of the p2th acquisition card; i, p1 and p2 are any integer in 1 to B, j, q and k are any integer in 1 to C, B is the number of acquisition cards, C is the number of channels in each acquisition card, B≥2 and is an integer, C≥2 and is an integer.

[0009] In some embodiments, the second synchronization program is executed by the processor to achieve: obtaining the number of interval interpolation points K_insert between the trigger sampling point of the trigger channel and the trigger position; and TRIG obtaining the second number of interpolation points according to the first number of interpolation points and K_insert TRIG , and performing synchronization between each channel in the acquisition card and the trigger channel according to the second number of interpolation points; wherein the trigger sampling point is the first sampling point after the trigger position in the sampling data of the trigger signal.

[0010] In some embodiments, the second synchronization program is executed by the processor to achieve: for each frame of sampling data corresponding to each channel in the acquisition card, shifting the data starting point of the sampling data according to the second number of interpolation points to obtain a shifted data starting point, and sending target sampling data to the controller according to the shifted data starting point; wherein the target sampling data includes L interpolation points starting from the shifted data starting point; or the target sampling data includes L / M extraction interpolation points starting from the shifted data starting point, there are M interpolation points between adjacent two extraction interpolation points, L>M≥2 and L, M are integers.

[0011] In a second aspect, based on the same inventive concept, an embodiment provides the following technical solutions:

[0012] A kind of multi-channel signal sampling calibration system, including multi-channel signal sampling device, signal distribution circuit, calibration program component and synchronization program component;Multi-channel signal sampling device includes PXIe chassis and acquisition card, PXIe chassis is equipped with multiple slot, slot is used to insert acquisition card, and acquisition card is equipped with multiple channels;Calibration system has multiple specifications, and different specifications of calibration system have different acquisition card quantity, or acquisition card quantity is same but slot is different;For any kind of specification of calibration system, signal distribution circuit is connected acquisition card, for distributing trigger signal to the multiple channels of acquisition card, obtains the sampling data of multiple channels corresponding trigger signal, and sampling data includes multiple sampling points;Calibration program component is used to be executed to realize: interpolation processing is carried out to sampling data, inserts N interpolation points between adjacent two sampling points, determines the trigger position corresponding to each channel according to interpolation point, and determines synchronization calibration basic data according to trigger position;N≥2 and integer, trigger position is the position when the value of interpolation point in sampling data reaches set value;Synchronization program component is used to be executed to realize: according to the trigger channel currently located in the first target acquisition card and synchronization calibration basic data, determine the delay data between each channel in each acquisition card and trigger channel, and synchronize between each channel and trigger channel according to delay data;Synchronization calibration basic data includes single board calibration data and cross board calibration data, and single board calibration data includes the number of delay interpolation points between the trigger position of each channel in each acquisition card and the trigger position of reference channel of the acquisition card, and cross board calibration data includes the number of delay interpolation points between the trigger position of reference channel of each acquisition card and the trigger position of reference channel of the second target acquisition card.

[0013] In some embodiments, the signal distribution circuit includes a first power divider provided on each acquisition card, the acquisition card further includes a processor and a plurality of analog-to-digital converters, an input end of each analog-to-digital converter is connected to an output end of one channel, and output ends of the plurality of analog-to-digital converters are connected to the processor;The input end of the first power divider is connected to the processor, and the output end is connected to the input end of the plurality of channels;The first power divider is used to obtain one trigger signal through the processor and distribute the trigger signal to each channel in the acquisition card, so that the processor obtains first sampling data of each channel through the analog-to-digital converter;The calibration program component is used to be executed by the processor to realize: interpolation processing is carried out to the first sampling data, the trigger position corresponding to each channel in the acquisition card and the trigger sampling point are determined according to the interpolation point, and the single board calibration data are determined according to the trigger position and the trigger sampling point;Wherein, the trigger sampling point is the first sampling point after the trigger position in the first sampling data.

[0014] In some embodiments, the calibration system further includes a controller disposed in a PXIe chassis, and the calibration program component is configured to be executed by a processor of the i-th acquisition card to implement: obtaining the sequence number n_pos of the trigger sampling point of the j-th channel of the i-th acquisition card in the storage space i_j The number of interpolation points between the trigger sampling point and the trigger position K_insert i_j , and the sequence number n_pos of the trigger sampling point of the kth channel of the i-th acquisition card in the storage space i_k The number of interpolation points between the trigger sampling point and the trigger position K_insert i_k ; According to N, n_pos i_j 、K_insert i_j 、n_pos i_k and K_insert i_k , determine the number of delay interpolation points n_skew between the jth channel of the i-th acquisition card and the kth channel of the i-th acquisition card i_jk And n_skew i_jk Sent to the controller as single-board calibration data; where the kth channel is the reference channel; i is any integer from 1 to B, j is an integer from 1 to C, k is any integer from 1 to C, B is the number of acquisition cards, C is the number of channels in each acquisition card, B ≥ 2 and is an integer, and C ≥ 2 and is an integer.

[0015] In some embodiments, the acquisition card is provided with a processor, multiple analog-to-digital converters and multiple channels, the input end of one analog-to-digital converter is connected to the output end of one channel, and the output ends of the multiple analog-to-digital converters are connected to the processor; the signal distribution circuit includes a second power divider, the output end of the second power divider is connected to the reference channel of the master acquisition card and the reference channel of the first slave acquisition card, and the input end is connected to the master acquisition card, which is the second target acquisition card; the second power divider is used to obtain a trigger signal through the master acquisition card, and distribute the trigger signal to the reference channel of the first slave acquisition card and the reference channel of the master acquisition card to obtain the second sampling data of the reference channel of the master acquisition card, and the reference channel of the first slave acquisition card. The calibration program component is configured to be executed to implement: interpolating the second sampling data, and determining the trigger position and trigger sampling point of the reference channel of the master acquisition card according to the interpolation point; interpolating the third sampling data, and determining the trigger position and trigger sampling point of the reference channel of the first slave acquisition card according to the interpolation point; and determining cross-board calibration data between the first slave acquisition card and the master acquisition card according to the trigger position and trigger sampling point of the reference channel of the master acquisition card and the trigger position and trigger sampling point of the reference channel of the first slave acquisition card; wherein the trigger sampling point is the first sampling point located after the trigger position in the second sampling data or the third sampling data.

[0016] In some embodiments, the calibration system further includes a controller disposed in a PXIe chassis; the calibration program component includes a first calibration program and a second calibration program; when the reference channel of all acquisition cards is the kth channel, the first slave acquisition card is the i-th acquisition card, and the master acquisition card is the p2-th acquisition card, the first calibration program is configured to be executed by a processor of the i-th acquisition card to implement: obtaining a sequence number n_pos of a trigger sampling point of the k-th channel of the i-th acquisition card in a storage space i_k And the number of interpolation points between the trigger sampling point and the trigger position K_insert i_k , and n_pos i_k and K_insert i_k Sent to the controller; the first calibration program is used to be executed by the processor of the p2 acquisition card to achieve: obtaining the sequence number n_pos of the trigger sampling point of the kth channel of the p2 acquisition card in the storage space p2_k , the number of interpolation points between the trigger sampling point and the trigger position K_insert p2_k , and n_pos p2_k and K_insert p2_k Sent to the controller; the second calibration program is used to be executed by the controller to achieve: obtaining the interval sampling period n_diff between the starting sampling point of the kth channel of the i-th acquisition card and the starting sampling point of the kth channel of the p2 acquisition card in the time domain, according to N, n_diff, n_pos i_k 、K_insert i_k 、n_pos p2_k 、K_insert p2_k , calculate the number of delay interpolation points n_skew between the kth channel of the i-th acquisition card and the kth channel of the p2-th acquisition card ip2_k And n_skew ip2_k As cross-board calibration data; where i and p2 are any integers from 1 to B, k is any integer from 1 to C, B is the number of acquisition cards, C is the number of channels in each acquisition card, B ≥ 2 and is an integer, and C ≥ 2 and is an integer.

[0017] According to a technical solution in the above embodiment, the following beneficial effects or advantages are achieved:

[0018] The present disclosure provides a multi-channel signal sampling device, which can calculate the delay data of each channel in each acquisition card relative to the trigger channel according to the current trigger channel by executing a synchronization program component using the pre-stored or pre-prepared synchronization calibration basic data after each modification of the trigger source, and perform synchronization calibration between each channel and the trigger channel according to the delay data; the synchronization calibration basic data includes single-board calibration data and cross-board calibration data, the single-board calibration data is the interpolation point number of the trigger sampling point of each channel in the acquisition board relative to the trigger sampling point of the reference channel of the acquisition card, and the cross-board calibration data is the interpolation point number of the trigger sampling point of the reference channel in other acquisition boards relative to the trigger sampling point of the reference channel in the second target acquisition card; the trigger signal is used as the reference object because its trigger position is easier to locate, and in combination with the data interpolation method, N interpolation points are formed between the adjacent two sampling points in the sampling data, and the correct trigger position of the trigger signal can be more accurately found through the interpolation points, thereby improving the accuracy of the synchronization calibration basic data determined according to the trigger position, and further improving the determination accuracy of the delay data between channels, so that the trigger synchronization resolution and accuracy of the sampling device are significantly improved; at the same time, the present disclosure transfers the acquisition card trigger synchronization calibration problem from the hardware field to the digital signal processing field through the data interpolation and pre-stored synchronization calibration basic data scheme, without using high-precision synchronization devices such as clock boards or synchronization machines, thereby realizing the reduction of hardware cost and design difficulty while ensuring the synchronization calibration accuracy.

[0019] The above description is only a summary of the technical scheme of the present disclosure, in order to enable one skilled in the art to more clearly understand the technical means of the present disclosure, and to implement the content of the specification, and in order to enable the above and other purposes, features and advantages of the present disclosure to be more apparent and easy to understand, the following specific embodiments of the present disclosure are described. BRIEF DESCRIPTION OF DRAWINGS

[0020] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not meant to limit the present disclosure. Moreover, the same reference numerals in the attached drawings indicate the same or similar components.

[0021] Figure 1 A schematic diagram of a multi-channel signal sampling device according to one embodiment of the present disclosure is shown.

[0022] Figure 2 A data interpolation schematic diagram of a fast edge signal according to one embodiment of the present disclosure is shown.

[0023] Figure 3 A data starting point translation schematic diagram in the synchronization stage according to one embodiment of the present disclosure is shown.

[0024] Figure 4 A synchronization flow diagram of a multi-channel signal sampling device according to an embodiment of the present disclosure is shown.

[0025] Figure 5 A framework diagram of a calibration system for multi-channel signal sampling according to an embodiment of the present disclosure is shown.

[0026] Figure 6 A detailed architecture diagram of a calibration system according to an embodiment of the present disclosure is shown.

[0027] Figure 7 A diagram showing the number of delay interpolation points n_skew i_21 between channel 2 and channel 1 in the ith acquisition card according to an embodiment of the present disclosure is shown.

[0028] Figure 8 A diagram showing the number of delay interpolation points n_skew 21_1 between the reference channel ch1 of the board: acquisition card 2 and the reference channel ch1 of the main board: acquisition card 1 according to an embodiment of the present disclosure is shown.

[0029] Figure 9 A synchronization calibration flow diagram of a calibration system after the hardware composition is changed according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that the description is merely exemplary and is not intended to limit the scope of the present disclosure. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid obscuring the concept of the present disclosure.

[0031] In the drawings, various structural diagrams according to embodiments of the present disclosure are shown. These diagrams are not drawn to scale, in which certain details are exaggerated for the purpose of clarity and certain details can be omitted. The shapes of various regions, layers, and their relative sizes and positional relationships shown in the drawings are merely exemplary, and in actuality, they can deviate due to manufacturing tolerances or technical limitations, and a person skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0032] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the meanings as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms are used herein to distinguish one element from another, but do not necessarily require or imply a serial or chronological order, unless otherwise indicated by the context. Likewise, the terms "a", "an", or "the" do not require or imply a quantity of more than one, unless otherwise indicated by the context. The terms "comprises", "comprising", "includes", "including" and the like can mean the presence of a stated element or items in addition to those recited in the claims and the like, and do not preclude the presence or addition of other elements or items. The terms "connected" and "coupled" and the like are not limited to direct or physical connections or couplings, but can also include indirect or electrical connections or couplings.

[0033] A PXIe multi-channel signal sampling device (also referred to as a PXIe sampling system) includes a PXIe chassis and multiple PXIe acquisition cards. The PXIe chassis provides physical installation space, power supply, cooling fan, and system bus interconnection (i.e., PXIe backplane) for all modules. The PXIe chassis is provided with multiple slots, and users can insert different numbers of acquisition cards in different slots according to actual needs. However, even if the same model of PXIe acquisition card is used, different card individuals and insertion in different slots will cause changes in the inter-channel delay. In particular, in GHz high-speed signal acquisition applications, this delay will cause the collected signals to have obvious misalignment. Generally, the misalignment is required to be no more than one-fiftieth of the maximum bandwidth period of the PXIe acquisition card, i.e., the misalignment needs to be less than 20 ps (picoseconds) when the bandwidth is 1 GHz, and the requirement is higher if the bandwidth is higher.

[0034] The delay in a PXIe system is diverse, for example, there is a skew of hundreds of ps between the reference clocks of different slots, there is a certain signal delay between the channels on the PXIe acquisition card, and there is a certain delay between the sampling time and the sampling clock inside the analog digital converter (ADC). These delays are stable and unchangeable for a fixed hardware system, but users need to recalibrate the inter-channel delay once for each newly built PXIe system, so a simple and inexpensive calibration synchronization scheme is needed.

[0035] Currently, the trigger synchronization calibration solution of the PXIe sampling device composed of multiple PXIe acquisition cards mostly adopts a hardware scheme: for example, some use a specially designed clock board to achieve higher precision clock synchronization through a special clock slot, but this has the problems of high cost and many products without a clock slot in the PXIe chassis, thus having great limitations; some use the internal phase-locked loop (PLL) of the processor (such as a field programmable gate array, FPGA) of the PXIe acquisition card to synchronize the PXIe acquisition card to the PXIe backplane reference clock, but the skew of the reference clock is not calibrated, and the skew of the acquisition card reaches hundreds of ps, so the synchronization precision cannot meet the needs of acquisition cards with GHz sampling rate; some use a scheme in which a synchronization machine generates a synchronization trigger signal or a synchronization clock, but this has the problems of high cost, many and complex connections, and even the volume of the synchronization machine is larger than that of the PXIe sampling device, so it is not suitable for PXIe sampling devices with dense boards.

[0036] A few trigger synchronization calibration solutions of PXIe sampling devices adopt a solution of implementing calibration and compensation in the digital domain, but only the sampling point is translated, the calibration precision is limited by the ADC sampling rate, and there is at least a 10-fold gap between the target precision, so high-precision trigger synchronization calibration of 10 ps cannot be achieved.

[0037] In view of the problems of high cost of the hardware scheme and insufficient precision of the software scheme in the synchronization calibration of the PXIe sampling device, in a first aspect, in an optional embodiment, referring to Figure 1 , a multi-channel signal sampling device 10 is provided, which includes a PXIe chassis 11 and at least two acquisition cards 12 arranged in the PXIe chassis 11, the acquisition card 12 including multiple channels; the multi-channel signal sampling device 10 further includes a synchronization program component, which is executed to determine the delay data between each channel in each acquisition card 12 and the trigger channel according to the trigger channel currently located in the first target acquisition card 12 and the pre-stored synchronization calibration basic data, and to perform synchronization between each channel and the trigger channel according to the delay data; wherein the synchronization calibration basic data includes single-board calibration data and cross-board calibration data, the single-board calibration data includes the number of delay interpolation points between the trigger position of each channel in each acquisition card 12 and the trigger position of the reference channel of the acquisition card, and the cross-board calibration data includes the number of delay interpolation points between the trigger position of the reference channel of each acquisition card 12 and the trigger position of the reference channel of the second target acquisition card; the trigger position of each channel is the position when the value of the interpolation point reaches a set value in the sampling data of the trigger signal, and N interpolation points are included between two adjacent sampling points in the sampling data, N≥2 and is an integer.

[0038] Specifically, the present disclosure provides a PXIe sampling device, the hardware of which mainly includes a PXIe frame 11, a PXIe backplane 13, a controller ( Figure 1 The PXIe chassis 11 includes a housing and backplane design, providing physical mounting space for all modules and the necessary power supply and cooling systems. The PXIe chassis 11 is equipped with multiple standardized slots, including one system slot and multiple peripheral slots. The system slot is used to install the controller, while the peripheral slots are used to install various peripheral modules, such as instrument modules, switch modules, and the acquisition card 12 in the disclosed embodiment.

[0039] The PXIe backplane 13, installed at the rear of the PXIe chassis 11, is the core of the PXIe sampling device. It interconnects all slots through high-density connectors and carries: the PXIe bus, which is a high-speed serial PCI Express channel; and the PXI timing and trigger bus, including the reference clock, trigger lines, star trigger lines, etc., which are used to achieve high-precision synchronization and are responsible for data transmission and communication between modules.

[0040] The controller is the "brain" of the PXIe sampling device, responsible for the management and control of the entire device or system, and is therefore also called the system controller or master CPU. The controller can communicate with the computer through an interface, run the operating system and test applications, manage bus communications, perform data processing, and control peripheral modules.

[0041] A PXIe acquisition card (hereinafter referred to as acquisition card 12) is a type of peripheral module used to convert analog signals into digital information that can be processed by a computer at high speed and high precision. Acquisition card 12 may include a processor FPGA, multiple channels (Ch), and multiple analog-to-digital converters (ADCs). The input of each ADC is connected to the output of a channel, and the outputs of all ADCs are connected to the processor. A channel is responsible for receiving external analog signals and performing preliminary reception of various analog physical quantity signals (such as voltage and current), and is therefore also referred to as an analog channel. The ADC is used to convert the analog signals input by the channel into digital signals, generating sampled data comprising a large number of sampling points. In some embodiments, the number of ADCs is the same as the number of channels, meaning that there is a one-to-one correspondence between ADCs and channels. This is because the channels in acquisition card 12 are independent, and the delay between channels is unknown and random. By equipping each channel with an independent ADC for signal sampling, signal transmission and sampling between channels can be independent, thereby accurately measuring and obtaining synchronized calibration basic data for each channel.

[0042] The processor is a core processing unit of the acquisition card 12, and can perform various processing on the digital signal converted by the analog-to-digital converter ADC, such as interpolation processing and determination of a trigger position according to the present disclosure. Currently, a commonly used processor in the acquisition card 12 is a field programmable gate array (FPGA), and the embodiments of the present disclosure take the FPGA as an example for description unless otherwise specified.

[0043] The trigger channel is a channel for receiving or detecting a trigger signal. In the embodiments of the present disclosure, the trigger channel is determined according to a user-specified or modified trigger source during use of the PXIe sampling device, and thus the first target acquisition card is the acquisition card 12 where the trigger channel is located. The corresponding trigger signal can be one of a fast edge signal, a sine signal, a triangular signal, and a pulse signal, and these signals can be conveniently positioned to the correct trigger position. Taking the fast edge signal as an example, it is a signal with very fast rising time and falling time used by a high-speed serial data link in the PXIe sampling device. In the application of an oscilloscope, the fast edge signal can be a signal for instructing the oscilloscope to draw a waveform diagram, and can be used for calibration synchronization.

[0044] The PXIe multi-channel signal sampling device 10 provided by the present disclosure has pre-stored synchronization calibration basic data. After the user modifies the trigger source and determines a new trigger channel each time, the synchronization program component is executed to read the synchronization calibration basic data to calculate the delay data between each channel in each acquisition card 12 and the trigger channel, and then the delay data is sent to the processor FPGA of the corresponding acquisition card 12 for synchronization calibration. The synchronization calibration basic data can be pre-stored in the memory of the PXIe sampling device for being called by the controller at any time. The synchronization program component can be executed by the controller and / or the processor FPGA of the acquisition card 12 to complete the synchronization between each channel in each acquisition card 12 and the trigger channel.

[0045] The synchronization calibration basic data includes a data set of single-board calibration data and a data set of cross-board calibration data. The single-board calibration data refers to the delay between the trigger position of each channel and the trigger position of a reference channel in a single acquisition card 12, which is measured by the number of interpolation points of the difference or interval between the two, i.e., how many interpolation points the trigger positions of the two channels differ in the time domain or the digital domain. The cross-board calibration data refers to the delay between the trigger position of the reference channel of any one acquisition card 12 and the trigger position of the reference channel of a second target acquisition card, which is also measured by the number of interpolation points of the difference or interval in the time domain or the digital domain. The second target acquisition card can be regarded as a master acquisition card (referred to as a master board) set when the synchronization calibration basic data is obtained, and the other acquisition cards can be referred to as slave acquisition cards (referred to as slave boards). The cross-board calibration data between each slave board and the master board can be determined by taking the master board as a reference object.

[0046] The reference channel can be any one selected from the plurality of channels, and the delay between the other channels and the reference channel is calculated based on the reference channel; in order to more conveniently determine the synchronization calibration basis data, the channels with the same serial number in all the acquisition cards 12 can be the reference channels, for example, channel 1 (Ch1) of all the acquisition cards 12 is the reference channel, or channel 2 (Ch2) is the reference channel, which is not specifically limited herein.

[0047] The embodiment of the present disclosure inserts N times of sampling data by a data interpolation method, that is, inserts N interpolation points between any two adjacent sampling points, the interpolation points are “calculated sampling points” obtained by the data interpolation method according to the time and value corresponding to the sampling points, the interpolation points improve the resolution of the sampling data in the digital domain, and therefore the interpolation points can be used to more accurately locate the correct trigger position of the trigger signal, the accuracy of the synchronization calibration basis data obtained based on the trigger position is higher, and the accuracy of the synchronization calibration based on the synchronization calibration basis data is further improved.

[0048] In order to more intuitively explain the data interpolation, the trigger position and the delay between the channels, please refer to Figure 2 The provided schematic diagram of data interpolation of sampling data of an analog-to-digital converter (ADC) by using a fast edge signal as a trigger signal includes two fast edge signals, the fast edge signal of the upper route samples a trigger channel corresponding to a second target acquisition card (mainboard), and the fast edge signal of the lower route samples a trigger channel corresponding to any one acquisition card (slave board). In theory, the fast edge signals synchronously emitted are completely aligned after being sampled by the ADC, but due to reasons such as analog channel delay, ADC internal delay and sampling clock misalignment, the actual sampling waveform has a misalignment ∆T, as shown in Figure 2 For a PXIe acquisition card with a sampling frequency reaching GHz, the size of ∆T is generally -10 to +10 sampling periods and is a non-integer multiple; before interpolation, a set of trigger-stable PXIe hardware systems can stably sample two signals, but the resolution in the time domain is only 1 / Fs, Fs is the sampling frequency, as shown by the square points and the thin solid line in Figure 2 The resolution in the time domain cannot be accurately positioned to the correct trigger position of the fast edge signal, and accurate synchronization calibration basis data cannot be provided; in order to increase the resolution in the horizontal and vertical directions of the time domain, the data is interpolated, so that the resolution in the digital domain can be quantized by 1 / (Fs×N), N is the interpolation multiple, and the generated interpolation points are shown by the circular points in Figure 2 Compared with before interpolation, the interpolation points can more accurately locate the correct trigger position of the fast edge signal.

[0049] In addition, according to Figure 2It can be clear that after the trigger position is determined, the number of interval points K_insert between the correct trigger position of the rising edge signal and the trigger sampling point can be determined at the same time, and the delay between the channels can be determined according to the trigger position, the trigger sampling point and K_insert; the trigger sampling point of the disclosure refers to the sampling point after the trigger position of the trigger signal in the channel is correctly triggered, or the first sampling point after the trigger position; the trigger position refers to the position when the level of the trigger signal reaches a certain set value or threshold, indicating that the trigger signal is normally triggered at this moment; in order to facilitate distinction, this important sampling point after the correct trigger position is named as the trigger sampling point.

[0050] Therefore, the multi-channel signal sampling device 10 provided by the disclosure can calculate the delay data of each channel in each acquisition card 12 relative to the trigger channel according to the current trigger channel by executing the synchronization program component using the pre-stored or pre-prepared synchronization calibration basic data after modifying the trigger source each time, and perform synchronization calibration between each channel and the trigger channel according to the delay data; specifically, the synchronization calibration basic data includes single-board calibration data and cross-board calibration data, the single-board calibration data is the number of interval points of the trigger position of each channel in a single acquisition board relative to the trigger position of the reference channel of the acquisition card; the cross-board calibration data is the number of interval points of the trigger position of the reference channel in other acquisition boards relative to the trigger position of the reference channel in the second target acquisition card; the trigger position of the trigger signal is used as the reference object because it is easier to be positioned, and combined with the data interpolation method, N interval points are formed between the adjacent two sampling points in the sampling data, and the correct trigger position of the trigger signal can be more accurately found through these interval points, thereby improving the accuracy of the synchronization calibration basic data determined according to the trigger position, and further improving the determination accuracy of the delay data between the channels, so that the trigger synchronization resolution and accuracy of the sampling device are significantly improved; at the same time, through the data interpolation and pre-stored synchronization calibration basic data scheme, the trigger synchronization calibration problem of the acquisition card 12 is transferred from the hardware field to the digital signal processing field, without using high-precision synchronization devices such as clock boards or synchronization machines, so that the hardware cost and design difficulty are reduced while ensuring the synchronization calibration accuracy.

[0051] It should be noted that as long as the synchronization calibration basic data is predetermined and stored, the PXIe sampling device provided by the present disclosure can use the pre-stored synchronization calibration basic data to quickly perform synchronization calibration between each channel and the trigger channel of each acquisition card 12 as long as the hardware composition is unchanged, such as keeping the number of acquisition cards 12 and the inserted slot unchanged, even if the trigger source is modified multiple times during use and a new trigger channel is determined. Only when the hardware composition changes, the synchronization calibration basic data needs to be determined again, and then the synchronization calibration is performed.

[0052] In some embodiments, the synchronization program component includes a first synchronization program and a second synchronization program; the first synchronization program is executed by the controller to achieve: in response to a user instruction, determining a trigger channel located in a first target acquisition card, calculating a first interpolation point number of a difference between each channel and the trigger channel in each acquisition card 12 according to the single-board calibration data and the cross-board calibration data, and sending the first interpolation point number as delay data to the processor FPGA of the corresponding acquisition card 12; the second synchronization program is executed by the processor FPGA to achieve: synchronization between each channel and the trigger channel in the acquisition card according to the first interpolation point number.

[0053] Specifically, the user instruction is an instruction for indicating a new trigger source, the first synchronization program is stored in the controller, and is used to determine the trigger channel corresponding to the current trigger source according to the current user instruction when executed, and to calculate the delay data between each channel and the trigger channel, i.e. the first interpolation point number of the difference or interval in the digital domain, by calling the synchronization calibration basic data. Since the synchronization calibration basic data reflects the delay between the trigger position of any one channel and the trigger position of the reference channel in the calibration stage, the first interpolation point number of the interval between the trigger position of a certain channel and the trigger position of the trigger channel calculated by using the synchronization calibration basic data can accurately reflect the delay between the channel and the trigger channel. The second synchronization program can be stored in the processor FPGA of each acquisition card 12, and is used to synchronize each channel and the trigger channel in the acquisition card in turn according to the delay data.

[0054] In some embodiments, after obtaining the first interpolation point number, the first synchronization program can also further correct the first interpolation point number according to the delay between the trigger sampling point and the trigger position of the trigger channel, and send the corrected first interpolation point number as delay data to the processor FPGA of the corresponding acquisition card 12 for synchronization, so as to further improve the synchronization accuracy.

[0055] In some embodiments, when the first target acquisition card is the p1th acquisition card, the trigger channel is the qth channel of the p1th acquisition card, the second target acquisition card is the p2th acquisition card, and the reference channel of all acquisition cards 12 is the kth channel of the acquisition card, i.e., the p2th acquisition card is the master board specified in determining the synchronous calibration basis data, the other acquisition cards 12 are slave boards, and the serial numbers of the reference channels of all acquisition cards 12 are the same, which are the kth channel; the first synchronous program is executed by the controller to achieve: calculating the first interpolation point number between the jth channel in the ith acquisition card and the trigger channel according to n_skew i_jk and n_skew p1_qk in the single-board calibration data and n_skew ip2_k and n_skew p1p2_k in the cross-board calibration data; n_skew i_jk is the delay interpolation point number between the jth channel of the ith acquisition card and the kth channel of the ith acquisition card; n_skew p1_qk is the delay interpolation point number between the qth channel of the p1th acquisition card and the kth channel of the p1th acquisition card; n_skew ip2_k is the delay interpolation point number between the kth channel of the ith acquisition card and the kth channel of the p2th acquisition card; n_skew p1p2_k is the delay interpolation point number between the kth channel of the p1th acquisition card and the kth channel of the p2th acquisition card; i, p1 and p2 are any integer from 1 to B, j, q and k are any integer from 1 to C, B is the number of acquisition cards 12, C is the number of channels in each acquisition card 12, B≥2 and is an integer, and C≥2 and is an integer.

[0056] In some embodiments, the determination method of the first interpolation point number n_chskew ip1_jq1 is: adding n_skew i_jk and n_skew ip2_k to obtain a first sum; adding n_skew p1_qk and n_skew p1p2_k to obtain a second sum; and obtaining the first interpolation point number n_chskew ip1_jq1 between the jth channel in the ith acquisition card and the trigger channel according to the difference between the first sum and the second sum, which is mathematically expressed as formula 1a:

[0057] n_chskew ip1_jq1 =(n_skew i_jk +n_skew ip2_k)-( n_skew p1_qk +n_skew p1p2_k) (1a)

[0058] In some other optional embodiments, n_chskew can also be determined using formula 1b. ip1_jq1 :

[0059] n_chskew ip1_jq1 =(n_skew i_jk -n_skew p1_qk)+( n_skew ip2_k -n_skew p1p2_k) (1b)

[0060] After the controller executes the first synchronization program to obtain the first interpolation point number of each channel in all acquisition cards 12 relative to the trigger channel, it sends it to the processor FPGA of the corresponding acquisition card 12, for example, n_chskew ip1_jq1 Send to the processor FPGA of the i-th acquisition card, so that the processor FPGA of the i-th acquisition card executes the second synchronization program according to n_chskew ip1_jq1 Synchronize the jth channel of the i-th acquisition card with the qth channel of the p1-th acquisition card.

[0061] In some embodiments, when the second synchronization program is executed by the processor FPGA of the i-th acquisition card, the first interpolation point number n_chskew can be directly used. ip1_jq1 In other embodiments, the second synchronization program is executed by the processor FPGA to achieve: obtaining the number of interval interpolation points K_insert between the trigger sampling point and the trigger position of the trigger channel TRIG , according to the number of first interpolation points n_chskew ip1_jq1 and K_insert TRIG Get the second interpolation point number n_chskew ip1_jq2 , according to n_chskew ip1_jq2 Synchronize each channel in this acquisition card with the trigger channel.

[0062] Specifically, the number of first interpolation points n_chskew ip1_jq1 The signals of all channels can be calibrated to align with the signal of the trigger channel. However, considering that there is a certain random delay between the actual trigger position of the trigger source signal and the trigger sampling point, in order to further improve the accuracy of synchronous calibration, the random delay data K_insert of the trigger channel is obtained. TRIG , using K_insert TRIG Further fix n_chskew ip1_jq1 , you can get a more accurate and better synchronized second interpolation point number n_chskew ip1_jq2 Synchronize as delayed data.

[0063] The second delay data n_chskew can be calculated using the following formula: ip1_jq2 :

[0064] n_chskew ip1_jq2 = n_chskew ip1_jq1 +K_insert TRIG (2)

[0065] K_insert TRIG The acquisition method can be to use one trigger signal to trigger the trigger channel first, obtain the sampling data of the trigger channel, and then interpolate the sampling data through the processor FPGA of the p1 acquisition card, determine the trigger position and trigger sampling point of the trigger channel according to the interpolation point, and then obtain the K_insert corresponding to the current trigger channel. TRIG , and then send it to the processor FPGA of other acquisition card 12; get K_insert TRIG The method is the same as that in the above embodiment according to Figure 2 The principle of obtaining K_insert is the same and will not be repeated here.

[0066] When synchronizing, the second synchronization procedure can be based on the delay data n_chskew ip1_jq1 or n_chskew ip1_jq2 , shift the sampled data to achieve signal synchronization between the two channels.

[0067] With the second delay data n_chskew ip1_jq2 For example, in some embodiments, the second synchronization program is executed by the processor FPGA to achieve: for each frame of sampling data corresponding to each channel in this acquisition card, the data starting point of the sampling data is shifted according to the number of second interpolation points to obtain the shifted data starting point, and the target sampling data is sent to the controller according to the shifted data starting point.

[0068] Specifically, the data starting point is the starting sampling point where the processor FPGA of the acquisition card 12 sends useful sampled data to the subsequent device, that is, to the controller, and a certain length of sampled data is taken from the data starting point and sent to the subsequent stage for use; therefore, according to the second delay data n_chskew ip1_jq2 By shifting the old data starting point to obtain a new data starting point, the signal synchronization between the two channels can be completed.

[0069] In some embodiments, the target sampling data includes L interpolation points starting from the starting point of the translated data, where L>2 and is an integer; that is, all interpolation points within the translated length L are directly sent to the subsequent processing.

[0070] Specifically, the sampling data interpolated by the processor FPGA is temporarily stored in the memory or register DDR (double data rate synchronous dynamic random access memory) of the processor FPGA, and usually a small amount of data is stored before and after the sampling data of each frame. Figure 3 An example of data translation in synchronization is provided, assuming that the length of the basic demand data of the subsequent stage is L1 sampling points (including L1 x N interpolation points), Point1 is the starting point of the old useful data before synchronization, and L0 sampling points (including L0 x N interpolation points) are usually stored before and after the sampling data of length L1; without considering the trigger synchronization, L=L1 x N interpolation points are directly sent from the starting point of the old useful data Point1 to the subsequent stage for use; and in synchronization, Point1 is translated according to n_chskew Figure 3 . ip1_jq2 to obtain the starting point Point2 of the new useful data after synchronization (as shown in Figure 3 ), and then L=L1 x N interpolation points are sent from Point2 to the subsequent stage for use. The amount of translation is n_chskew ip1_jq2 .

[0071] In some embodiments, a part of the interpolated points after translation can also be extracted for processing by the subsequent stage, specifically including: the target sampling data includes L / M extracted interpolation points starting from the starting point of the translated data, there are M interpolation points between adjacent two extracted interpolation points, L>M≥2 and M is an integer; specifically, the extracted interpolation points are sent to the subsequent stage for use from the starting point Point2 of the new useful data, and one interpolation point is extracted every M interpolation points, a total of (L1 x N) / M interpolation points are continuously sent, so as to realize M times extraction of the sampling data after translation; only the extracted interpolation points are sent to the subsequent stage for processing and use, which can improve the speed of information processing and reduce the processing workload; in some embodiments, L can be divided by M, so as to facilitate extraction of the interpolation points.

[0072] In some embodiments, the above scheme can be combined to obtain an optional calibration and synchronization process of a multi-channel signal sampling device 10, please refer to Figure 4 , including steps S41-S472, specifically as follows:

[0073] S41: in response to a user instruction, determine the trigger channel after modifying the trigger source.

[0074] S42: using the pre-stored synchronization calibration basic data, calculate the first interpolation point number n_chskew ip1_jq1 of each channel in each acquisition card relative to the trigger channel.

[0075] S43: Get K_insert by interpolating and triggering the trigger channel sampling signal TRIG .

[0076] S44: According to n_chskew ip1_jq1 and K_insert TRIG Get the second interpolation point number n_chskew ip1_jq2 .

[0077] S45: Based on n_chskew ip1_jq2 Shift the data starting point.

[0078] S46: Determine whether to send the extracted interpolation points; if yes, jump to step S471, if not, jump to step S472.

[0079] S471: Based on the starting point of the shifted data, L / M extracted interpolation points are sent as target sampling data to the subsequent processing stage.

[0080] S472: Based on the starting point of the shifted data, L interpolation points are sent as target sampling data to a subsequent processing stage.

[0081] It can be clearly seen from the above embodiments that when the present invention realizes the triggered synchronous calibration of each channel, the synchronization or alignment of the data does not rely on hardware adjustment, but interpolates the sampling data of the analog-to-digital converter ADC in the digital domain, obtains the delay between each channel by calculating the number of interpolation points, and then shifts the interpolated sampling data according to the delay; after N-fold interpolation, the time domain resolution of the sampling is increased from the original 1 / Fs to 1 / (Fs×N), thereby ensuring the accuracy of the synchronous calibration without using high-precision synchronization devices, where Fs is the sampling frequency of the analog-to-digital converter ADC.

[0082] The embodiment of the first aspect introduces how to calculate the delay data of each channel of each acquisition card 12 relative to the new trigger channel according to the synchronization calibration basic data and how to perform synchronization calibration based on the delay data after adjusting the trigger source when the hardware composition of the multi-channel signal sampling device 10 remains unchanged; for situations where the hardware composition needs to be adjusted during use, such as installing a new acquisition card 12, or changing the installation slot of the acquisition card 12, etc., since the hardware composition has changed, it is necessary to first redetermine the synchronization calibration basic data and then use the new synchronization calibration basic data for synchronization.

[0083] Therefore, based on the same inventive concept, in the second aspect, in some other optional embodiments, please refer to Figure 5The application provides a calibration system for multi-channel signal sampling, comprising a multi-channel signal sampling device 10, a signal distribution circuit 20, a calibration program component and a synchronization program component; the multi-channel signal sampling device 10 comprises a PXIe chassis 11 and an acquisition card 12, the PXIe chassis 11 is provided with a plurality of slots, and the slots are used for inserting the acquisition card 12; the acquisition card 12 is provided with a plurality of channels; the calibration system has a plurality of specifications, different specifications of the calibration system have different numbers of acquisition cards 12, or the numbers of acquisition cards 12 are the same but the slots are different; for any specification of the calibration system, the signal distribution circuit 20 is connected with the acquisition card 12 and is used for distributing a trigger signal to a plurality of channels of the acquisition card 12 to obtain sampling data of the trigger signal corresponding to the plurality of channels, and the sampling data comprises a plurality of sampling points; the calibration program component is used for being executed to realize: interpolating the sampling data, inserting N interpolation points between two adjacent sampling points, determining a trigger position corresponding to each channel according to the interpolation points, and determining synchronization calibration basic data according to the trigger position; N is greater than or equal to 2 and is an integer, and the trigger position is a position at which a value of an interpolation point in the sampling data reaches a set value; the synchronization program component is used for being executed to realize: determining delay data between each channel in each acquisition card 12 and a trigger channel according to the trigger channel currently located in a first target acquisition card and the synchronization calibration basic data, and synchronizing between each channel and the trigger channel according to the delay data; wherein the synchronization calibration basic data comprises single-board calibration data and cross-board calibration data, the single-board calibration data comprises a number of delay interpolation points between the trigger position of each channel in each acquisition card 12 and the trigger position of a reference channel of the acquisition card, and the cross-board calibration data comprises a number of delay interpolation points between the trigger position of the reference channel of each acquisition card 12 and the trigger position of a reference channel of a second target acquisition card.

[0084] Specifically, the calibration system comprises the multi-channel signal sampling device 10 of the first aspect embodiment, and different specifications of the calibration system have changes in hardware components, for example, the PXIe chassis 11 comprises one system slot and a plurality of peripheral slots, a controller is inserted on the system slot, the same number of acquisition cards 12 are inserted on different peripheral slots, or different numbers of acquisition cards 12 are inserted on different peripheral slots; because the hardware components change, the originally pre-stored synchronization calibration basic data is no longer applicable, so it is necessary to first synchronously distribute trigger signals to different channels through the signal distribution circuit 20, then obtain new synchronization calibration basic data through the calibration program component, and then perform synchronization calibration through the synchronization program component; the scheme and principle of the synchronization program component are the same as those of the first aspect embodiment, and therefore the embodiment of the second aspect mainly introduces the working principles of the calibration program component and the signal distribution circuit 20.

[0085] In determining the synchronous calibration base data, in addition to accurately quantifying the delay K_insert between the trigger position and the trigger sampling point of each channel of each acquisition card 12, it is also necessary to accurately quantify: 1) the delay of the trigger sampling point of each channel in the same acquisition card 12 relative to the trigger sampling point of the reference channel, i.e. the single-board calibration data; 2) the delay of the trigger sampling point of the board relative to the trigger sampling point of the main board (the second target acquisition card) between different acquisition cards 12, i.e. the cross-board calibration data; the following implementation content will introduce the determination principle and method thereof respectively.

[0086] To accurately quantify the delay between each channel, it is necessary to use the signal distribution circuit 20 to synchronously distribute one trigger signal to each channel in one acquisition card 12, or to the channels of different acquisition cards 12; although it is theoretically "synchronous distribution", but in fact there is still an unavoidable delay, such as analog channel delay, ADC internal delay and sampling clock misalignment, etc.; therefore, the trigger sampling point of each channel is determined by the method of data interpolation, and the number of interpolation points between the trigger positions of each channel is determined to determine the synchronous calibration base data; the signal distribution circuit 20 can use a power divider or a brancher, etc., and the embodiments of the present disclosure are illustrated by taking the power divider as an example.

[0087] First of all, the single-board calibration data, in some embodiments, please refer to Figure 6 The provided calibration system, the signal distribution circuit 20 includes a first power divider 21 provided on each acquisition card 12, and the acquisition card 12 is also provided with a processor FPGA and a plurality of analog-to-digital converters ADC, the input end of one analog-to-digital converter ADC is connected to the output end of one channel, and the output ends of the plurality of analog-to-digital converters ADC are connected to the processor FPGA; the input end of the first power divider 21 is connected to the processor FPGA, and the output end is connected to the input end of the plurality of channels; the first power divider 21 is used to obtain one trigger signal through the processor FPGA, and distribute the trigger signal to each channel in the acquisition card, so that the processor FPGA obtains first sampling data of each channel through the analog-to-digital converter ADC; the calibration program component is used to be executed by the processor FPGA to realize: interpolating the first sampling data, determining the trigger position and the trigger sampling point corresponding to each channel in the acquisition card according to the interpolation point, and determining the single-board calibration data according to the trigger position and the trigger sampling point; wherein the trigger sampling point is the first sampling point after the trigger position in the first sampling data.

[0088] Specifically, please refer to Figure 6The multi-channel signal sampling device 10 further comprises a PXIe backplane 13 arranged in the PXIe chassis 11, and each acquisition card 12 is connected to the PXIe backplane 13 through a phase-locked loop (PLL), which generates a sampling clock signal, a processor FPGA main clock and a timing clock according to the backplane clock, and provides a stable and accurate clock reference for the sampling of an analog-to-digital converter (ADC), the operation of a processor FPGA and the like through locking the phase relationship, thereby ensuring the timing synchronization of the system.

[0089] The first power divider 21 can be regarded as an on-board power divider on the acquisition card 12, and thus one first power divider 21 is arranged on each acquisition card 12. The output end of the first power divider 21 can be connected to one end of a single-pole double-throw relay in each channel of the acquisition card, for example, connected to the single-pole double-throw relay in channel 1 through a PORT1 interface, connected to the single-pole double-throw relay in channel 2 through a PORT2 interface, and connected to the single-pole double-throw relay in channel C through a PORTC interface. The input end of the first power divider 21 can be connected to an I / O interface of the processor FPGA, and the processor FPGA is further connected to the PXIe backplane 13 through a PCIE interface. When determining the single-board calibration data, one trigger signal can be forwarded to the first power divider 21. The first power divider 21 synchronously distributes the trigger signal to each channel in the acquisition card, and after being sampled by the analog-to-digital converter ADC, first sampling data is obtained and temporarily stored in the memory DDR of the processor FPGA. Then, interpolation and triggering are performed through the calibration program component. The correct triggering position and the trigger sampling point of the trigger signal are determined by using the data interpolation method, and the number K_insert of interval interpolation points between the trigger position and the trigger sampling point of each channel can be obtained.

[0090] It should be noted that the input end of one analog-to-digital converter ADC is connected to the output end of one channel, and the output ends of all analog-to-digital sub-circuits are connected to the processor FPGA, because of the independence of the channels in the acquisition card 12. The delay between the channels is unknown and random. By equipping each channel with an independent analog-to-digital sub-circuit for signal sampling, the signal transmission and sampling between the channels can be independent of each other, so that the corresponding synchronous calibration basic data of each channel can be accurately measured.

[0091] In some embodiments, the calibration program component is configured to be executed by the processor FPGA of the ith acquisition card to achieve: obtaining the sequence number n_pos of the trigger sampling point of the jth channel of the ith acquisition card in the storage space i_j and the number K_insert of interval interpolation points between the trigger sampling point and the trigger position i_j and the sequence number n_pos of the trigger sampling point of the kth channel of the ith acquisition card in the storage space i_k and the number K_insert of interval interpolation points between the trigger sampling point and the trigger position i_k; according to N, n_pos i_j , K_insert i_j , n_pos i_k and K_insert i_k , determine the number of interpolation points n_skew i_jk between the jth channel of the ith acquisition card and the kth channel of the ith acquisition card, and send n_skew i_jk to the controller as single-board calibration data; the kth channel is the reference channel; i is any integer from 1 to B, j takes integers from 1 to C in turn, k is any integer from 1 to C, B is the number of acquisition cards 12, C is the number of channels in each acquisition card 12, B≥2 and is an integer, C≥2 and is an integer.

[0092] Specifically, in the PXIe system, each channel corresponds to a sampling point with a specific serial number in the storage space, and these serial numbers are used to identify and locate the position of the sampling point in the storage area; therefore, when the trigger sampling point is determined, the serial number of the trigger sampling point in the storage space is also obtained; and K_insert is the interval between the correct trigger position of the trigger signal and the trigger sampling point, which is measured by the number of interpolation points.

[0093] After obtaining n_pos and K_insert corresponding to each channel of the ith acquisition card, the calibration program component can continue to determine the number of delay interpolation points n_skew i_jk of each channel relative to the reference channel; it should be noted that n_skew i_jk can be calculated by the processor FPGA of the acquisition card and then sent to the controller, or n_pos i and K_insert i can be sent directly to the controller, and n_skew i_jk is calculated at the controller end.

[0094] Taking the jth channel as an example, the following is specific: according to n_pos i_j and n_pos i_k , the first serial number difference between the trigger sampling point of the jth channel and the trigger sampling point of the kth channel is obtained, and the first product of the interpolation point number is obtained based on the first serial number difference and N; according to the difference between K_insert i_j and K_insert i_k and the first product, the number of delay interpolation points n_skew i_jk is obtained; the reason why the first serial number difference is multiplied by N is that it represents the serial number difference of the sampling points, and there are N interpolation points between two adjacent sampling points, so when converting to the number of interpolation points, the interpolation multiple N needs to be multiplied.

[0095] The mathematical expression can be:

[0096] n_skew i_jk = (n_pos i_j -n_pos i_k ) x N + K_insert i_j -K_insert i_k (3)

[0097] Figure 7 Provided is a schematic diagram of the number of delay interpolation points n_skew i_21 in the case of j = 2 and k = 1, Figure 7 where CH1posstart refers to the starting sampling point of the trigger signal of channel CH1, and CH2posstart refers to the starting sampling point of the trigger signal of channel CH2; the delay of other channels relative to the reference channel CH1 is the same as Figure 7 and will not be repeated here.

[0098] Therefore, for each block of acquisition cards 12, a trigger signal is distributed to each channel using the first power divider 21 according to the above process. After sampling by the analog-to-digital converter ADC, the calibration program component calculates the number of delay interpolation points between each channel and the reference channel in the acquisition card using interpolation and triggering according to formula (3). The set of all delay interpolation points constitutes the single-board calibration data.

[0099] For cross-board calibration data, in some embodiments, referring to Figure 6 , the signal distribution circuit 20 includes a second power divider 22, the output end of the second power divider 22 is connected to the reference channel of the master acquisition card and the reference channel of the first slave acquisition card, and the input end is connected to the master acquisition card; the master acquisition card is the second target acquisition card; the second power divider 22 is used to obtain a trigger signal through the master acquisition card, and distribute the trigger signal to the reference channel of the first slave acquisition card and the reference channel of the master acquisition card, to obtain second sampling data of the reference channel of the master acquisition card, and third sampling data of the reference channel of the first slave acquisition card.

[0100] Specifically, when performing cross-board trigger synchronization calibration, the second power divider 22, that is, the external power divider, is used to synchronize the distribution of the trigger signal of the master acquisition card (master board, that is, the second target acquisition card) and the first slave acquisition card (slave board 1); as Figure 6As shown, taking the reference channel as channel 1 for example, the second power divider 22 is located outside the multi-channel signal sampling device 10, and its two output ends are connected to the peripheral function interfaces PFI of the two acquisition cards that need to be calibrated; for example, the output end OUT1 of the second power divider 22 is connected to the input end PORT1 of the master acquisition card, and the output end OUT2 is connected to the input end PORT1 of the first slave acquisition card; the input end IN of the second power divider 22 can be connected to the peripheral function interface PFI of the master acquisition card, and a trigger signal is set to be output from the PFI interface in the program, and the trigger signal is synchronously distributed to the PORT1 interface of the master acquisition card and the PORT1 interface of the first slave acquisition card through the second power divider 22; the PORT1 interface is connected to the other end of the single-pole double-throw relay in channel 1; after the trigger synchronization calibration between one slave acquisition card and the master acquisition card is completed, the output end OUT2 is switched to be connected to the PORT1 interface of another slave acquisition card, and the above trigger synchronization calibration process is repeated until the trigger synchronization calibration between all slave acquisition cards and the master acquisition card is completed; after the cross-board trigger synchronization calibration is completed, the second power divider 22 can be removed and no longer occupy the input port of the channel.

[0101] After the second power divider 22 distributes the trigger signal to the channel 1 of the two acquisition cards, the second sampling data and the third sampling data are obtained through the respective analog-to-digital converters ADC and sent to the processor FPGA of the acquisition card; correspondingly, the calibration program component is executed to: perform interpolation processing on the second sampling data, determine the trigger position and the trigger sampling point of the reference channel of the master acquisition card according to the interpolation point; perform interpolation processing on the third sampling data, determine the trigger position and the trigger sampling point of the reference channel of the first slave acquisition card according to the interpolation point; determine the cross-board calibration data between the first slave acquisition card and the master acquisition card according to the trigger position and the trigger sampling point of the reference channel of the master acquisition card and the trigger position and the trigger sampling point of the reference channel of the first slave acquisition card; wherein the trigger sampling point is the first sampling point after the trigger position in the second sampling data or the third sampling data.

[0102] Since the cross-board calibration data reflects the delay between the reference channels of the two acquisition cards 12, the cross-board calibration data can be determined by the controller of the PXIe sampling device, or the controller and the processor FPGA of the acquisition card 12 can cooperatively determine the cross-board calibration data.

[0103] Taking the latter as an example, in some embodiments, the calibration program component includes a first calibration program and a second calibration program; when the reference channel of all acquisition cards 12 is the kth channel, the first slave acquisition card is the ith acquisition card, and the master acquisition card is the p2th acquisition card, the first calibration program is executed by the processor FPGA of the ith acquisition card to: obtain the serial number n_pos i_kAnd the number of interpolation points between the trigger sampling point and the trigger position K_insert i_k , and n_pos i_k and K_insert i_k Sent to the controller; the first calibration program is used to be executed by the processor FPGA of the p2 acquisition card to achieve: obtaining the sequence number n_pos of the trigger sampling point of the kth channel of the p2 acquisition card in the storage space p2_k , the number of interpolation points between the trigger sampling point and the trigger position K_insert p2_k , and n_pos p2_k and K_insert p2_k Sent to the controller; the second calibration program is used to be executed by the controller to achieve: obtaining the interval sampling period n_diff between the starting sampling point of the kth channel of the i-th acquisition card and the starting sampling point of the kth channel of the p2 acquisition card in the time domain, according to N, n_diff, n_pos i_k 、K_insert i_k 、n_pos p2_k 、K_insert p2_k , calculate the number of delay interpolation points n_skew between the kth channel of the i-th acquisition card and the kth channel of the p2-th acquisition card ip2_k And n_skew ip2_k As cross-board calibration data between the first slave acquisition card and the master acquisition card; wherein, i and p2 are any integers from 1 to B, k is any integer from 1 to C, B is the number of acquisition cards 12, C is the number of channels in each acquisition card 12, B ≥ 2 and is an integer, C ≥ 2 and is an integer.

[0104] Specifically, the first calibration program is stored in the processor FPGA of the acquisition card 12, and is used to determine the sequence number n_pos of the trigger sampling point of the reference channel in the acquisition card in the storage space and the number of interpolation points K_insert between the trigger sampling point and the trigger position by interpolation and triggering, and send n_pos and K_insert to the controller; the second calibration program is stored in the controller, and when it is executed, it is based on the n_pos of the main acquisition board. p2_k 、K_insert p2_k and n_pos of the first slave card i_k 、K_insert i_k , calculate the number of delay interpolation points n_skew ip2_k ; It should be noted that n_pos p2_k and n_pos i_kare the serial numbers of the trigger sampling points in the storage space of the acquisition card, since there is a delay in cross-board triggering, for one frame of data of different boards, the starting sampling points of the two boards exist n_diff sampling period errors in the time domain, therefore, the controller or the processor FPGA can quantize n_diff between the two reference channels of the cross-board according to the starting points of the second sampling data and the third sampling data, and the quantization resolution is 1 sampling period.

[0105] In some embodiments, n_skew ip2_k The specific determination method is as follows: according to the difference between n_pos i_k and n_pos p2_k and n_diff, the second serial number difference between the trigger sampling point of the reference channel of the i-th acquisition card and the trigger sampling point of the reference channel of the p2-th acquisition card is obtained, and the second product of the interpolation point number is obtained based on the second serial number difference and N; according to the difference between K_insert p2_k and K_insert i_k and the second product, the delay interpolation point number n_skew ip2_k is obtained.

[0106] The mathematical expression is as follows:

[0107] n_skew ip2_k = (n_pos i_k -n_pos p2_k +n_diff) x N + K_insert p2_k -K_insert i_k (4)

[0108] For the sake of intuition, Figure 8 a schematic diagram of the delay interpolation point number n_skew 21_1 is provided when i=2, p2=1, k=1, that is, the main board is the acquisition card 12 inserted in the first slot of the PXIe chassis 11, the slave board is the acquisition card 12 inserted in the second slot, and the reference channel is channel 1 in each acquisition card 12. The delay of other channels relative to the reference channel ch1 can be obtained in the same way, which will not be described here.

[0109] Therefore, for the cross-board delay between each slave acquisition card and the master acquisition card, the second power divider 22 is used to distribute one trigger signal to the reference channels of the two acquisition cards according to the above process. After the analog-to-digital converter ADC sampling, the calibration program component calculates the delay interpolation point number of the reference channel between each slave acquisition card and the master acquisition card by interpolation and triggering using formula (4), and obtains the cross-board calibration data.

[0110] After obtaining the new synchronous calibration basis data of the sampling device with the changed specification, the following scheme is the same as that of the first aspect embodiment. After determining the new trigger channel, the synchronization program component performs synchronization between each channel of each acquisition board and the trigger channel according to the new synchronous calibration basis data, as follows:

[0111] The synchronization program component includes a first synchronization program and a second synchronization program. The first synchronization program is executed by the controller to achieve: in response to a user instruction, determining a trigger channel located in a first target acquisition card, calculating a first interpolation point number of a difference between each channel of each acquisition card 12 and the trigger channel according to single-board calibration data and cross-board calibration data, and sending the first interpolation point number as delay data to a processor FPGA of the corresponding acquisition card 12. The second synchronization program is executed by the processor FPGA to achieve: performing synchronization between each channel of the acquisition card and the trigger channel according to the first interpolation point number.

[0112] In some embodiments, when the first target acquisition card is a p1th acquisition card, the trigger channel is a qth channel of the p1th acquisition card, the second target acquisition card is a p2th acquisition card, and the reference channel of all acquisition cards 12 is a kth channel of the acquisition card, the first synchronization program is executed by the controller to achieve: calculating a first interpolation point number of a difference between a jth channel of an i th acquisition card and the trigger channel according to n_skew i_jk and n_skew p1_qk in the single-board calibration data, and n_skew ip2_k and n_skew p1p2_k in the cross-board calibration data.

[0113] In some embodiments, the second synchronization program is executed by the processor FPGA to achieve: obtaining an interval interpolation point number K_insert TRIG between a trigger sampling point of the trigger channel and a trigger position, obtaining a second interpolation point number according to the first interpolation point number and K_insert TRIG , and performing synchronization between each channel of the acquisition card and the trigger channel according to the second interpolation point number.

[0114] In some embodiments, the second synchronization program is executed by the processor FPGA to achieve: for each frame of sampling data corresponding to each channel of the acquisition card, shifting a data starting point of the sampling data according to the second interpolation point number to obtain a shifted data starting point, and sending target sampling data to the controller according to the shifted data starting point; the target sampling data includes L interpolation points starting from the shifted data starting point; or, the target sampling data includes L / M decimation interpolation points starting from the shifted data starting point.

[0115] The detailed explanation of the above scheme can refer to the related content of the first aspect embodiment, which will not be repeated here.

[0116] In actual implementation, please refer to Figure 6 , the calibration program component includes an interpolation module and a trigger module in the processor FPGA; the interpolation module is configured to perform interpolation processing on the sampling data to form N interpolation points between two adjacent sampling points, and the trigger module is configured to determine a trigger position and a trigger sampling point of the trigger signal according to the interpolation points, read a sequence number n_pos of the trigger sampling point in the storage space based on this, and determine an interval interpolation point number K_insert between the trigger position and the trigger sampling point; in addition, the single-board calibration data can be determined by the trigger module, and the cross-board basic data can be determined by a determination module in the controller to which the calibration program component belongs; the synchronization program component can include a determination module in the controller and a translation module and an extraction module in the processor FPGA, the determination module in the controller is configured to determine a first interpolation point number n_chskew ip1_jq1 ; the translation module is configured to translate the sampling data according to n_chskew ip1_jq1 , or determine a second interpolation point number n_chskew ip1_jq1 according to n_chskew TRIG and K_insert ip1_jq2 , and translate the sampling data according to n_chskew ip1_jq2 , so as to determine a new useful data starting point Point2; and the extraction module can extract an interpolation point every M interpolation points according to the new useful data starting point Point2, and continuously send L / M interpolation points to a subsequent stage for use, so as to realize M times extraction of the translated sampling data.

[0117] In the following embodiment, a calibration system provided by Figure 6 is combined to take the sampling device including B acquisition cards, each acquisition card is provided with C analog channels (channels), the main acquisition card in the determination of the synchronization calibration basic data is the first acquisition card, all reference channels are channel 1, and the trigger signal is a fast edge signal as an example; when the hardware composition of the sampling device is changed, an optional synchronization calibration process is as follows, please refer to Figure 9 , including steps S901-S91, which are as follows.

[0118] S901: After the hardware composition is changed, it is confirmed whether there is single-board calibration data, if yes, jump to step S906, if not, enter step S902.

[0119] S902: The relay is automatically switched to the first power divider 21.

[0120] S903: The processor FPGA sends a fast edge signal to the first power divider 21.

[0121] S904: The ADC collects the fast edge signal of each channel to obtain sampling data.

[0122] S905: The processor FPGA performs interpolation and triggering on the sampling data to obtain single-board calibration data.

[0123] Specifically, the calibration program component of the processor FPGA performs N times interpolation on the sampling data, determines the correct triggering position and triggering sampling point of the fast edge signal according to the interpolation points, and then determines K_insert and the sequence number n_pos of the triggering sampling point in the storage space of each channel according to the correct triggering position and the triggering sampling point. Based on the principle and formula 3, the number of delay interpolation points n_skew between each channel in each acquisition card and the reference channel of the acquisition card can be obtained. Figure 7 i_jk , specifically as follows.

[0124] n_skew 1_11 (=0), n_skew 1_21 , n_skew 1_31 , n_skew 1_41 ,……, n_skew 1_C1 .

[0125] n_skew 2_11 (=0), n_skew 2_21 , n_skew 2_31 , n_skew 2_41 ,……, n_skew 2_C1 .

[0126] …

[0127] n_skew B_11 (=0), n_skew B_21 , n_skew B_31 , n_skew B_41 ,……, n_skew B_C1 .

[0128] Therefore, the data set of the single-board calibration data includes a total of B×C delay interpolation point numbers, n_skew B_C1 represents the delay interpolation point number of channel C (CHC) on the Bth acquisition card relative to channel 1 (CH1) of the Bth acquisition card.

[0129] ​S906: The channel relay switches to the BNC port, sets the master-slave acquisition card, the cross-board trigger mode and the trigger line, etc.; for example, the first acquisition board is set as the master board and the others are set as the slave boards; in the cross-board trigger setting interface, the cross-board trigger mode to be used, the clock source and the cross-board trigger line, etc. are set.

[0130] S907: The delay between all the master-slave acquisition cards is judged: whether the cross-board basic data is completed, if yes, jump to step S912, if not, go to step S908.

[0131] S908: The output end of the second power divider 22 is connected to the PORT1 interface of the master acquisition card and one slave acquisition card, and the input end is connected to the PFI interface of another slave acquisition card.

[0132] S909: One fast edge signal is sent to the master acquisition card and the slave acquisition card through the second power divider 22.

[0133] S910: The fast edge signal is collected by the ADC to obtain the sampling data.

[0134] S911: The cross-board basic data is obtained through interpolation and triggering.

[0135] Specifically, the OUT1 end of the second power divider 22 is always connected to the master board: the PORT1 of the first acquisition card, and the OUT2 is connected to the PORT1 of the second, third, …, Bth board (slave acquisition card) in turn, B-1 times of testing are performed, and in each test, the data of each channel 1 (CH1) is interpolated, triggered by the processor FPGA and the controller, K_insert, n_pos and n_diff of each CH1 are obtained, and the number of delay interpolation points n_skew between the reference channel of each slave acquisition card and the reference channel of the master acquisition card is calculated according to the principle shown in the formula (4). Figure 8 The number of delay interpolation points n_skew between the reference channel of each slave acquisition card and the reference channel of the master acquisition card is calculated according to the principle shown in the formula (4). ip2_k Specifically, n_skew 11_1 = 0, n_skew 21_1 = 1, n_skew 31_1 = 2, n_skew 41_1 = 3, …, n_skew B1_1 .

[0136] Therefore, the data set of the cross-board calibration data includes B number of delay interpolation points in total, n_skew B1_1 represents the number of delay interpolation points of the reference channel (CH1) on the Bth acquisition card relative to the channel 1 (CH1) of the first acquisition card.

[0137] S912: The single-board calibration data and the cross-board calibration data are stored to obtain the synchronization calibration basic data.

[0138] B×C single-board calibration data and B cross-board calibration data, together with the number of the acquisition card 12 constituting this system and the number of the slot in which it is located, are stored in the memory as a set of system synchronous calibration basic data. As long as the hardware composition remains unchanged, the synchronous calibration basic data does not need to be remeasured; at this point, the synchronous calibration basic data is acquired.

[0139] S913: After the trigger source is modified, the number of first interpolation points n_chskew of each channel relative to the trigger channel is calculated based on the new trigger channel and the synchronous calibration basic data. ip1_jq1 .

[0140] Specifically, in the subsequent use process, as long as the trigger source is modified, the controller needs to calculate the number of delay interpolation points n_chskew of each channel relative to the new trigger channel through formula (1): ip1_jq1 and stores it in the registers of the controller and processor FPGA; at this point, the synchronous data corresponding to any trigger source is acquired.

[0141] S914: Get K_insert based on the interpolation and triggering of the trigger channel sampling signal TRIG .

[0142] S915: According to n_chskew ip1_jq1 、K_insert TRIG Get the second interpolation point number n_chskew ip1_jq2 .

[0143] Specifically, n_chskew ip1_jq1 All channels can be calibrated to align with the signal of the trigger channel, but because there is a K_insert between the actual trigger position of the trigger source signal and the trigger sampling point TRIG Therefore, the number of second interpolation points n_chskew that need to be shifted can be calculated by formula (2) for other channels. ip1_jq2 .

[0144] S916: Based on n_chskew ip1_jq2 Shift the data starting point.

[0145] S917: Determine whether to send the extracted interpolation points. If yes, go to step S918; if not, go to step S919.

[0146] S918: According to the starting point of the shifted data, L / M extracted interpolation points are sent as target sampling data to the subsequent processing.

[0147] S919: According to the starting point of the translated data, L interpolation points are sent as target sampling data to the subsequent processing.

[0148] In other words, you can choose to send the interpolation points after translation directly to the subsequent processing, or you can extract the interpolation points after translation and only send the extracted data to the subsequent processing, thereby improving the speed.

[0149] In general, the embodiments of the present disclosure provide a PXIe-based multi-channel signal sampling device 10 and a calibration system, which have the following advantages.

[0150] 1) By using the data interpolation method, the trigger synchronization calibration problem of the acquisition card 12 is transferred from the hardware to the digital signal processing field, which reduces the hardware cost and design difficulty and avoids various problems in solving high-precision trigger synchronization with hardware.

[0151] 2) The synchronization calibration basic data obtained through interpolation processing is used to synchronize each channel with the trigger channel, so that the sampling device and calibration system have high resolution and accuracy, reaching 1 / (Fs×N).

[0152] 3) A complete set of trigger synchronization calibration system based on data interpolation is proposed. The hardware design uses an onboard first power divider 21 and an external second power divider 22 to generate the synchronization signal required for calibration. No other dedicated instruments are required, and the additional hardware cost required is negligible.

[0153] In the third aspect, based on the same inventive concept, in another optional embodiment, an electronic device is provided, including the multi-channel signal sampling device 10 provided in the embodiment of the first aspect, or the calibration system provided in the embodiment of the second aspect.

[0154] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0155] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A multi-channel signal sampling device, characterized in that: The system comprises a PXIe chassis and at least two acquisition cards arranged in the PXIe chassis, wherein the acquisition cards include multiple channels; The multi-channel signal sampling device further includes a synchronization program component, wherein the synchronization program component is executed to: determine delay data between each channel in each acquisition card and the trigger channel based on a trigger channel currently located on the first target acquisition card and pre-stored synchronization calibration basic data, and synchronize each channel with the trigger channel based on the delay data; Among them, the synchronous calibration basic data includes single-board calibration data and cross-board calibration data. The single-board calibration data includes the number of delay interpolation points between the trigger position of each channel in each of the acquisition cards and the trigger position of the reference channel of the current acquisition card. The cross-board calibration data includes the number of delay interpolation points between the trigger position of the reference channel of each of the acquisition cards and the trigger position of the reference channel of the second target acquisition card. The trigger position of each of the channels is the position when the value of the interpolation point reaches the set value in the sampling data of the trigger signal. There are N interpolation points between two adjacent sampling points in the sampling data, and N≥2 is an integer.

2. The multi-channel signal sampling device according to claim 1, wherein: It also includes a controller arranged in the PXIe chassis, each of the acquisition cards is provided with a processor, and the synchronization program component includes a first synchronization program and a second synchronization program; The first synchronization program is executed by the controller to: determine, in response to a user instruction, a trigger channel located in a first target acquisition card, calculate, based on the single-board calibration data and the cross-board calibration data, a first interpolation point number of differences between each channel in each of the acquisition cards and the trigger channel, and send the first interpolation point number as the delay data to a processor of the corresponding acquisition card; The second synchronization program is executed by the processor to achieve: synchronization between each of the channels in the acquisition card and the trigger channel according to the delay data.

3. The multi-channel signal sampling device according to claim 2, wherein: When the first target acquisition card is the p1 acquisition card, the trigger channel is the qth channel of the p1 acquisition card, the second target acquisition card is the p2 acquisition card, and the reference channel of all acquisition cards is the kth channel of the acquisition card, the first synchronization program is executed by the controller to achieve: according to the n_skew in the single board calibration data i_jk and n_skew p1_qk , and n_skew in the cross-board calibration data ip2_k and n_skew p1p2_k , calculating the number of first interpolation points of difference between the jth channel in the i-th acquisition card and the trigger channel; Among them, the n_skew i_jk is the number of delay interpolation points between the jth channel of the i-th acquisition card and the kth channel of the i-th acquisition card; the n_skew p1_qk is the number of delay interpolation points between the qth channel of the p1th acquisition card and the kth channel of the p1th acquisition card; the n_skew ip2_k is the number of delay interpolation points between the kth channel of the i-th acquisition card and the kth channel of the p2-th acquisition card; the n_skew p1p2_k is the number of delay interpolation points between the kth channel of the p1th acquisition card and the kth channel of the p2th acquisition card; i, p1 and p2 are any integers from 1 to B, j, q and k are any integers from 1 to C, B is the number of the acquisition cards, C is the number of channels in each acquisition card, B ≥ 2 and is an integer, C ≥ 2 and is an integer.

4. The multi-channel signal sampling device according to claim 2, wherein: The second synchronization program is executed by the processor to implement: Get the number of interpolation points K_insert between the trigger sampling point and the trigger position of the trigger channel TRIG , according to the first number of interpolation points and the K_insert TRIG Obtaining a second interpolation point number, and synchronizing each of the channels in the acquisition card with the trigger channel according to the second interpolation point number; The trigger sampling point is the first sampling point after the trigger position in the sampling data of the trigger signal.

5. The multi-channel signal sampling device according to claim 4, wherein: The second synchronization program is executed by the processor to implement: For each frame of sampling data corresponding to each channel in the acquisition card, shifting the data starting point of the sampling data according to the second interpolation point number to obtain a shifted data starting point, and sending target sampling data to the controller according to the shifted data starting point; In which, the target sampling data includes L interpolation points starting from the starting point of the translated data; or, the target sampling data includes L / M extraction interpolation points starting from the starting point of the translated data, and there are M interpolation points between two adjacent extraction interpolation points, L>M≥2 and L and M are both integers.

6. A calibration system for multi-channel signal sampling, characterized in that: The multi-channel signal sampling device includes a multi-channel signal sampling device, a signal distribution circuit, a calibration program component, and a synchronization program component. The multi-channel signal sampling device includes a PXIe chassis and an acquisition card. The PXIe chassis is provided with multiple slots for inserting the acquisition card, which has multiple channels. The calibration system has multiple specifications. Different specifications of the calibration system have different numbers of acquisition cards, or the same number of acquisition cards are inserted in different slots. For any specification of the calibration system, the signal distribution circuit is connected to the acquisition card, and is used to distribute the trigger signal to multiple channels of the acquisition card to obtain sampling data of the trigger signal corresponding to the multiple channels, and the sampling data includes multiple sampling points; The calibration program component is configured to be executed to: interpolate the sampled data, insert N interpolation points between two adjacent sampled points, determine a trigger position corresponding to each channel based on the interpolation points, and determine synchronous calibration basic data based on the trigger positions; N is an integer greater than or equal to 2, and the trigger position is a position at which the value of the interpolation point in the sampled data reaches a set value; The synchronization program component is configured to be executed to: determine delay data between each channel in each acquisition card and the trigger channel based on the trigger channel currently located on the first target acquisition card and the synchronization calibration basic data, and synchronize each channel with the trigger channel based on the delay data; Among them, the synchronous calibration basic data includes single-board calibration data and cross-board calibration data. The single-board calibration data includes the number of delay interpolation points between the trigger position of each channel in each of the acquisition cards and the trigger position of the reference channel of the current acquisition card. The cross-board calibration data includes the number of delay interpolation points between the trigger position of the reference channel of each of the acquisition cards and the trigger position of the reference channel of the second target acquisition card.

7. The calibration system according to claim 6, wherein: The signal distribution circuit includes a first power splitter provided on each acquisition card. The acquisition card is further provided with a processor and multiple analog-to-digital converters. The input end of one of the analog-to-digital converters is connected to the output end of one of the channels, and the output ends of the multiple analog-to-digital converters are connected to the processor. The input end of the first power splitter is connected to the processor, and the output end is connected to the input ends of the multiple channels. The first power divider is used to obtain a trigger signal through the processor and distribute the trigger signal to each channel in the acquisition card, so that the processor obtains the first sampling data of each channel through the analog-to-digital converter; The calibration program component is configured to be executed by the processor to implement: performing interpolation processing on the first sampling data, determining a trigger position and a trigger sampling point corresponding to each channel in the acquisition card according to the interpolation point, and determining the single board calibration data according to the trigger position and the trigger sampling point; The trigger sampling point is the first sampling point after the trigger position in the first sampling data.

8. The calibration system according to claim 7, wherein: The system further includes a controller disposed in the PXIe chassis, wherein the calibration program component is configured to be executed by a processor of the i-th acquisition card to implement: Get the sequence number n_pos of the trigger sampling point of the jth channel of the i-th acquisition card in the storage space i_j and the number of interpolation points K_insert between the trigger sampling point and the trigger position i_j , and the sequence number n_pos of the trigger sampling point of the kth channel of the i-th acquisition card in the storage space i_k and the number of interpolation points K_insert between the trigger sampling point and the trigger position i_k ; According to the N, the n_pos i_j 、K_insert i_j 、n_pos i_k and the K_insert i_k , determine the number of delay interpolation points n_skew between the jth channel of the i-th acquisition card and the kth channel of the i-th acquisition card i_jk and set the n_skew i_jk sending it to the controller as the single board calibration data; Among them, the kth channel is the reference channel; i is any integer from 1 to B, j is an integer from 1 to C in sequence, k is any integer from 1 to C, B is the number of the acquisition cards, C is the number of channels in each acquisition card, B ≥ 2 and is an integer, and C ≥ 2 and is an integer.

9. The calibration system according to claim 6, wherein: The acquisition card is provided with a processor, multiple analog-to-digital converters, and multiple channels. The input end of one of the analog-to-digital converters is connected to the output end of one of the channels, and the output ends of the multiple analog-to-digital converters are connected to the processor. The signal distribution circuit includes a second power splitter. The output end of the second power splitter is connected to the reference channel of the master acquisition card and the reference channel of the first slave acquisition card, and the input end is connected to the master acquisition card. The master acquisition card is the second target acquisition card. The second power splitter is configured to obtain a trigger signal through the master acquisition card, and distribute the trigger signal to a reference channel of the first slave acquisition card and a reference channel of the master acquisition card, so as to obtain second sampled data of the reference channel of the master acquisition card and third sampled data of the reference channel of the first slave acquisition card; The calibration program component is configured to be executed to: interpolate the second sampled data and determine the trigger position and trigger sampling point of the reference channel of the master acquisition card according to the interpolation point; interpolate the third sampled data and determine the trigger position and trigger sampling point of the reference channel of the first slave acquisition card according to the interpolation point; and determine cross-board calibration data between the first slave acquisition card and the master acquisition card according to the trigger position and trigger sampling point of the reference channel of the master acquisition card and the trigger position and trigger sampling point of the reference channel of the first slave acquisition card; The trigger sampling point is the first sampling point after the trigger position in the second sampling data or the third sampling data.

10. The calibration system according to claim 9, wherein: The system further includes a controller disposed in the PXIe chassis; the calibration program component includes a first calibration program and a second calibration program; when the reference channel of all acquisition cards is the kth channel, the first slave acquisition card is the i-th acquisition card, and the master acquisition card is the p2-th acquisition card, the first calibration program is configured to be executed by a processor of the i-th acquisition card to implement: Get the sequence number n_pos of the trigger sampling point of the kth channel of the i-th acquisition card in the storage space i_k And the number of interval interpolation points K_insert between the trigger sampling point and the trigger position i_k and the n_pos i_k and the K_insert i_k Sending to the controller; The first calibration program is configured to be executed by a processor of the p2 acquisition card to implement: Get the sequence number n_pos of the trigger sampling point of the kth channel of the p2th acquisition card in the storage space p2_k , the number of interpolation points between the trigger sampling point and the trigger position K_insert p2_k and the n_pos p2_k and the K_insert p2_k Sending to the controller; The second calibration program is configured to be executed by the controller to implement: Get the interval sampling period n_diff between the starting sampling point of the kth channel of the i-th acquisition card and the starting sampling point of the kth channel of the p2-th acquisition card in the time domain, and calculate the interval sampling period n_diff based on N, n_diff, and n_pos. i_k 、K_insert i_k 、n_pos p2_k 、K_insert p2_k , calculate the number of delay interpolation points n_skew between the kth channel of the i-th acquisition card and the kth channel of the p2-th acquisition card ip2_k and set the n_skew ip2_k as the cross-plate calibration data; Wherein, i and p2 are any integers from 1 to B, k is any integer from 1 to C, B is the number of acquisition cards, C is the number of channels in each acquisition card, B ≥ 2 and is an integer, and C ≥ 2 and is an integer.

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