Data processing method, electronic device and storage medium

Abstract

The present invention provides a data processing method, electronic device, and storage medium that can be applied to the field of storage technology. The data processing method includes: in response to a read request for reading data of a first flash memory block, updating a read count of the first flash memory block to obtain a target read count; when the target read count is greater than a predetermined read count threshold, detecting a relationship between the target read count and a data migration step length to obtain a detection result, wherein the data migration step length is determined based on an upper limit value of the target read count, a predetermined read count threshold, and the number of data units in the first flash memory block, the upper limit value of the target read count being greater than the predetermined read count threshold and decreasing with the number of erase and write times of the first flash memory block; and when the detection result indicates that the target read count is an integer multiple of the data migration step length, determining a target data unit to be migrated from multiple data units in the first flash memory block, so as to migrate the target data unit to a second flash memory block.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a data processing method, electronic equipment and storage medium. Background Art

[0002] Read disturb in solid-state drives (SSDs) occurs when multiple read operations are performed on a single block of non-volatile memory (NAND Flash Memory), potentially affecting adjacent storage cells and leading to data read errors. With the widespread adoption of SSDs in high-performance storage, effectively managing read disturb has become crucial for improving SSD reliability and extending SSD lifespan. However, current approaches to addressing read disturb often use fixed thresholds or workload-based approaches to set read count thresholds. These approaches focus on a relatively narrow range of characteristics, making it difficult to effectively reduce the data read error rate caused by read disturb using current read count thresholds, thereby hindering SSD reliability and extending SSD lifespan. Summary of the Invention

[0003] In view of the above problems, the present invention provides a data processing method, an electronic device, and a storage medium for improving the reliability of an SSD and extending the service life of an SSD.

[0004] One aspect of the present invention provides a data processing method, comprising: in response to a read request for reading data of a first flash memory block, updating a read count of the first flash memory block to obtain a target read count; when the target read count is greater than a predetermined read count threshold, detecting the relationship between the target read count and a data migration step to obtain a detection result, wherein the data migration step is determined based on an upper limit value of the target read count, a predetermined read count threshold, and the number of data units in the first flash memory block, and the upper limit value of the target read count is greater than the predetermined read count threshold and decreases with the number of erase and write times of the first flash memory block; when the detection result indicates that the target read count is an integer multiple of the data migration step, determining a target data unit to be migrated from a plurality of data units in the first flash memory block so as to migrate the target data unit to a second flash memory block.

[0005] Another aspect of the present invention provides an electronic device, comprising: one or more processors; a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above-mentioned data processing method.

[0006] Another aspect of the present invention further provides a computer-readable storage medium having a computer program or instruction stored thereon, which implements the steps of the above-mentioned data processing method when the computer program or instruction is executed by a processor.

[0007] According to an embodiment of the present invention, the read count of the first flash memory block is updated in response to a read request to obtain a target read count; when the target read count is greater than a predetermined read count threshold and the target read count is an integer multiple of the data migration step, the target data unit to be migrated is determined from multiple data units of the first flash memory block so that the target data unit can be migrated to the second flash memory block. Since the relationship between the target read count and the data migration step is compared during the data processing process, the data unit can be migrated when the target read count is an integer multiple of the data migration step, thereby achieving phased migration of the data unit and avoiding performance fluctuations on the SSD caused by a one-time migration of the data unit. On the other hand, the data migration step is determined based on the target read count upper limit, and the target read count upper limit decreases with the number of erase and write times of the first flash memory block. Since the erase and write characteristics dimension is added in the process of setting the target read count upper limit, the problem of oxide layer degradation caused by a high number of erase and write times, which is ignored by the current read count threshold, can be paid attention to. Since read disturb can also occur when the oxide layer is rolled back, data read disturb management based on the target read count upper limit value dynamically adjusted according to the number of erase and write times can reduce the data read error rate caused by read disturb, thereby achieving the technical effect of improving SSD reliability and extending SSD service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0009] Figure 1 An application scenario diagram of a data processing method according to an embodiment of the present invention is shown.

[0010] Figure 2 A flow chart of a data processing method according to an embodiment of the present invention is shown.

[0011] Figure 3 A flow chart of a data processing method according to another embodiment of the present invention is shown.

[0012] Figure 4 A structural block diagram of a data processing device according to an embodiment of the present invention is shown.

[0013] Figure 5 A block diagram of an electronic device suitable for implementing a data processing method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0014] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0015] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0016] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0017] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0018] Currently, most solutions to the read disturb problem use fixed thresholds or workload-based approaches to set read count limits. Fixed thresholds pre-set a fixed read count limit for all flash memory blocks, but fail to account for increased read disturb sensitivity due to varying wear levels. Furthermore, different program / erase (PE) counts can also lead to varying read disturb susceptibility for different flash memory blocks. Statistical model-based approaches analyze historical workload characteristics to predict areas likely to experience read disturb in the future and adjust the read count limit accordingly. While this approach can reflect actual workload conditions to a certain extent, it still lacks direct consideration of the critical factor of PE counts. It can be difficult to accurately identify flash memory blocks that are more vulnerable due to high PE counts. Alternatively, while machine learning algorithms can dynamically adjust the read count limit for each flash memory block based on real-time monitoring data, these approaches offer greater flexibility. However, if the cluster learning algorithm's training dataset lacks information on PE counts, the machine learning algorithm may not effectively capture the impact of PE counts on read disturb, thus affecting prediction accuracy.

[0019] The above methods usually ignore the impact of the number of PE times of the flash memory block on the read interference resistance of the flash memory block. In fact, as the number of PE times increases, the physical properties of the flash memory block will change, the oxide layer of the flash memory unit will gradually degrade, the read interference resistance of the flash memory block will decrease, and the sensitivity of the flash memory block to read interference will also increase accordingly. In view of this, in order to overcome the above limitations and defects, the read interference management strategy should pay more attention to the impact of the number of PE times on the read interference capability, and overcome the read interference problem by introducing more dimensional information (such as the number of PE times, error rate trends, etc.). Therefore, an embodiment of the present invention provides a data processing method that can dynamically adjust the read count upper limit value in combination with the PE number, and realize phased data migration based on the read count upper limit value, so as to improve the reliability of the SSD, extend the life of the SSD, and reduce the data error rate.

[0020] Figure 1 An application scenario diagram of a data processing method according to an embodiment of the present invention is shown.

[0021] like Figure 1As shown, an application scenario 100 according to this embodiment may include a host 101 and an SSD 102, with SSD 102 electrically connected to host 101. SSD 102 may include a first flash memory block 102-1 and a second flash memory block 102-2. Each of first flash memory block 102-1 and second flash memory block 102-2 may include multiple data units for storing data. Host 101 may send a read request to SSD 102 to read data from first flash memory block 102-1. SSD 102 may respond to the read request. For example, SSD 102 may further include a control unit configured to update a read count of first flash memory block 102-1 in response to the read request to obtain a target read count; and when the target read count is greater than a predetermined read count threshold and is an integer multiple of a data migration step size, migrate the target data units to be migrated in first flash memory block 102-1 to second flash memory block 102-2. It should be noted that the data processing method provided in the embodiments of the present invention can generally be executed by SSD 102. Accordingly, the data processing device provided in the embodiment of the present invention may generally be disposed in the SSD 102 .

[0022] It should be understood that Figure 1 The number of host terminals and SSDs in FIG is merely illustrative. Any number of host terminals and SSDs may be used as required.

[0023] The following will be based on Figure 1 The scene described by Figure 2 The data processing method according to the embodiment of the present invention is described in detail.

[0024] Figure 2 A flow chart of a data processing method according to an embodiment of the present invention is shown.

[0025] like Figure 2 As shown, the data processing method of this embodiment includes operations S210 to S230.

[0026] In operation S210 , in response to a read request for reading data of a first flash memory block, a read count of the first flash memory block is updated to obtain a target read count.

[0027] In operation S220, when the target read count is greater than the predetermined read count threshold, the relationship between the target read count and the data migration step is detected to obtain a detection result, wherein the data migration step is determined based on the target read count upper limit value, the predetermined read count threshold value, and the number of data units in the first flash memory block, the target read count upper limit value is greater than the predetermined read count threshold value, and decreases with the number of erase and write times of the first flash memory block.

[0028] In operation S230 , when the detection result indicates that the target read count is an integer multiple of the data migration step length, a target data unit to be migrated is determined from the plurality of data units in the first flash memory block, so as to migrate the target data unit to the second flash memory block.

[0029] In some embodiments, a NAND flash memory may include multiple flash blocks, which are physical management units of the NAND flash memory. The first flash block and the second flash block may be two different flash blocks in the multiple flash blocks of the NAND flash memory. Each flash block may include multiple data units (data frames), which may be units for reading or writing data.

[0030] In some embodiments, a read request may be a request initiated by a terminal device to read data on a first flash memory block, such as a request to read data on a data unit of the first flash memory block. For example, a user or an intelligent robot may generate a read request by clicking a button on the terminal device for generating a read request; or, in an interface for generating a read request, enter relevant information about the data to be read, such as an identifier of the first flash memory block and key fields of the data content, to generate a read request.

[0031] In some embodiments, a read count can be set for the first flash memory block. This read count can record the number of times the first flash memory block has been read. This read count can be used to manage read disturb on the first flash memory block. For example, each time a read operation is performed on the first flash memory block, the read count of the first flash memory block can be incremented by 1 to obtain a target read count. A section of the SSD's double data rate (DDR) memory space can be selected to store the read count corresponding to each physical flash memory block on the SSD.

[0032] In some embodiments, the predetermined read count threshold may be a value used to trigger a determination of whether data migration is required. The predetermined read count threshold may be less than a target read count upper limit. The predetermined read count threshold may be determined based on the physical properties of the flash memory block (e.g., the structure and composition of the flash memory block, as well as its physical size). If the physical properties of the flash memory block do not change,

[0033] In some embodiments, the target read count upper limit value may be the maximum number of reads allowed by the first flash memory block. The target read count upper limit value may decrease with the number of PEs in the first flash memory block. The data processing method of an embodiment of the present invention may move all data units on the first flash memory block to the second flash memory block before the target read count reaches the target read count upper limit value. This not only avoids performance fluctuations caused by moving all data units on the first flash memory block at once when the target read count exceeds the target read count upper limit value, but also reduces the probability of errors caused by read interference when the user reads data.

[0034] In some embodiments, the data migration step length may be determined based on a predetermined read count threshold, a target read count upper limit, and the number of data units in the first flash memory block. The data migration step length determination process is shown in formula (1).

[0035] (1)

[0036] in, is the data migration step, is the target read count upper limit value, is the predetermined read count threshold, and N is the number of data units in the first flash memory block.

[0037] Whenever the target read count increases by an integer multiple of the data migration step size, a target data unit can be moved from the first flash memory block, so that all valid data can be moved before the target read count of the first flash memory block reaches the target read count upper limit.

[0038] In some embodiments, when the target read count increases by an integer multiple of the data migration step size, the migrated target data unit may be any one of the multiple data units in the first flash memory block and may be migrated to the second flash memory block.

[0039] According to an embodiment of the present invention, the read count of the first flash memory block is updated in response to a read request to obtain a target read count; when the target read count is greater than a predetermined read count threshold and the target read count is an integer multiple of the data migration step, the target data unit to be migrated is determined from multiple data units of the first flash memory block so that the target data unit can be migrated to the second flash memory block. Since the relationship between the target read count and the data migration step is compared during the data processing process, the data unit can be migrated when the target read count is an integer multiple of the data migration step, thereby achieving phased migration of the data unit and avoiding performance fluctuations on the SSD caused by moving the data unit at one time. On the other hand, the data migration step is determined based on the upper limit of the target read count, and the upper limit of the target read count decreases with the number of PEs of the first flash memory block. Since the dimension of erase and write characteristics is added in the process of setting the upper limit of the target read count, the problem of oxide layer degradation caused by high number of PEs, which is ignored by the current read count threshold, can be paid attention to. Since read disturb can also occur when the oxide layer is rolled back, data read disturb management based on the target read count upper limit value dynamically adjusted according to the number of PEs can reduce the data read error rate caused by read disturb, thereby achieving the technical effect of improving SSD reliability and extending SSD service life.

[0040] In some embodiments, the target read count upper limit value described above can be determined as follows: based on the first current PE number of the first flash memory block and the PE number upper limit value of the first flash memory block, determine the first influence coefficient of the PE number on the target read count upper limit value, wherein when the first current PE number of the first flash memory block reaches the PE number upper limit value, generate an alarm information indicating that the first flash memory block has failed; based on the initial read count upper limit value of the first flash memory block and the first influence coefficient, determine the target read count upper limit value, the initial read count upper limit value represents the read count upper limit of the first flash memory block when no erasure occurs, and is greater than the target read count upper limit value.

[0041] In some embodiments, the process of determining the target read count upper limit value may be as shown in formula (2).

[0042] (2)

[0043] in, is the target read count upper limit value, is the upper limit of the initial read count, is the first current PE number, The upper limit of PE times is the maximum number of PEs supported by the flash memory, and the first current PE number in the first flash memory block Reach the upper limit of PE times In this case, an alarm message indicating that the first flash memory block may fail may be generated. is the attenuation coefficient, calibrated experimentally, is the first influence coefficient.

[0044] In some embodiments, the initial read count upper limit value may represent the read count upper limit of the first flash memory block when no erase or write occurs, and may be greater than the target read count upper limit value. The initial read count upper limit value may be an initial maximum read count value for each flash memory block set based on factory process characteristics of the flash memory block.

[0045] In some embodiments, rising temperatures can significantly accelerate the degradation of the flash memory block oxide layer, leading to faster charge leakage, shorter data retention times, and increased data read error rates. To offset this effect, a temperature correction factor can be introduced during the determination of the target read count upper limit. For example, the temperature correction factor is derived based on the relationship between the actual detected temperature of the flash memory block and a predetermined reference temperature. The target read count upper limit is determined based on the initial read count upper limit of the first flash memory block, the first influence coefficient, and the temperature correction factor.

[0046] For example, when the actual temperature of the detected flash memory block is greater than the predetermined reference temperature, this situation may accelerate the retreat of the oxide layer, making the risk of read interference higher. In this case, the temperature correction factor can be reduced (compared to the case where the actual temperature of the flash memory block is less than or equal to the predetermined reference temperature), thereby causing the target read count upper limit to be reduced. A small target read count upper limit can reduce the data migration step size, so that the data units on the first flash memory block can be migrated earlier, avoiding the read interference problem caused by high temperature.

[0047] When the detected actual temperature of the SSD is equal to the predetermined reference temperature, the target read count upper limit value may be determined using only the initial read count upper limit value and the first influence coefficient.

[0048] When the detected actual temperature of the SSD is lower than the predetermined reference temperature, the obtained temperature correction factor may be larger (compared to the case where the actual temperature of the SSD is higher than the predetermined reference temperature), thereby causing the target read count upper limit value to be larger. A larger target read count upper limit value can reduce unnecessary migration resource consumption.

[0049] According to an embodiment of the present invention, by introducing a temperature correction factor and adjusting the target read count upper limit value according to the temperature correction factor, when the actual temperature is higher than a predetermined reference temperature, the target read count upper limit value is reduced to offset the effect of high temperature accelerating the degradation of the oxide layer of the flash memory block; when the actual temperature is lower than the predetermined reference temperature, the target read count upper limit value is appropriately increased to reduce the resource consumption of migration; in this way, the technical effect of improving data processing flexibility can be achieved.

[0050] In some embodiments, a machine learning prediction model can be introduced to dynamically optimize the attenuation coefficient by combining multiple parameters such as PE times, temperature, and data read error rate. and data migration step to improve the model's adaptability.

[0051] According to an embodiment of the present invention, the target read count upper limit for each flash memory block can be dynamically adjusted through the process shown in formula (2). Compared to fixed threshold technical solutions, this process directly links the PE count of a flash memory block with its read disturb resistance, achieving for the first time dynamic adjustment of the read count threshold based on the degree of wear. This can exponentially reduce the read tolerance of blocks with high PE counts, resolving the problem of oxide layer degradation caused by ignoring high PE counts when setting the read count threshold using fixed threshold methods or workload-based methods.

[0052] In some embodiments, the above-mentioned target read count upper limit value can also be dynamically updated. For example, a second current PE number of the first flash memory block can be obtained. When the difference between the second current PE number and the first current PE number of the first flash memory block is an integer multiple of the erase step size, the first influence coefficient is reduced to a second influence coefficient based on the second current PE number and the PE number upper limit value, where the second current PE number represents the PE number of the first flash memory block when a predetermined period of time has passed after the first current PE number is reached. The target read count upper limit value is reduced based on the second influence coefficient and the initial read count upper limit value to obtain an updated target read count upper limit value.

[0053] In some embodiments, the process of obtaining the updated target read count upper limit value may be as shown in formula (3).

[0054] (3)

[0055] in, The updated target read count upper limit value is is the second current PE number, is the second influence coefficient.

[0056] In some embodiments, the second current PE number is the PE number after the first current erasure coefficient has passed a predetermined time. The second current PE number may be greater than the first current PE number, and the predetermined time may be adaptively adjusted according to actual needs.

[0057] In some embodiments, the erase step size can be set based on a speed curve of a NAND flash memory block, in which the bit error rate increases with the number of PEs. In some embodiments, the speed curve can be divided into stages, and different erase step sizes can be set for different PEs in different stages. For example, the erase step size can be reduced as the number of PEs increases. In this way, the frequency of adjusting the target read count upper limit can be increased as the number of PEs increases, thereby preventing read disturb issues and reducing the probability of data corruption.

[0058] The erase step size can be used to determine whether the target read count upper limit needs to be updated. When the difference between the second current PE count and the first current PE count is divisible by the erase step size, the target read count upper limit can be updated. If the target read count upper limit is not updated, oxide layer oxidation caused by the increase in PE counts may be ignored, which in turn affects the management of read disturb issues, thereby preventing data corruption in advance. If the difference between the second current PE count and the first current PE count is not divisible by the erase step size, the target read count upper limit may not be updated.

[0059] According to an embodiment of the present invention, by periodically calibrating the target read count upper limit value, it is possible to reduce resource consumption caused by frequent calibration of the target read count upper limit value, and avoid excessive accumulation of read interference on high-wear flash memory blocks, thereby effectively reducing the error probability caused by read interference and extending the service life of SSD hard drive flash memory.

[0060] In some embodiments, the process of determining the target data unit to be migrated from multiple data units of the first flash memory block mentioned in the above operation may include the following operations: selecting at least one data unit from a hot data unit group of the first flash memory block as the target data unit, wherein the hot data unit group is obtained by grouping multiple data units based on the relationship between the access frequency of the data units within a predetermined time period and a predetermined access frequency threshold, and the access frequency of the data units in the hot data unit group is greater than or equal to the predetermined access frequency threshold.

[0061] In some embodiments, when migrating target data units, differentiated migration strategies can be used. Data units with high-frequency access rates are preferentially migrated based on the hot and cold properties of the data units to reduce the read interference risk of high-frequency access data. For example, for the data units in the first flash memory block, multiple data units can be grouped based on the relationship between the access frequency of the data units within a predetermined time period and the predetermined access frequency threshold. Data units with an access frequency greater than or equal to the predetermined access frequency threshold are regarded as a hot data unit group with a high-frequency access rate, and data units with an access frequency less than the predetermined access frequency threshold are regarded as a cold data unit group with a low-frequency access rate. Both the predetermined time period and the predetermined access frequency threshold can be adaptively adjusted according to actual needs.

[0062] The target data unit to be migrated in the first flash memory block may be any data unit from the hot data unit group.

[0063] According to an embodiment of the present invention, by grouping data units according to their access frequency and using differentiated migration strategies to prioritize migrating data units in hot data unit groups, the risk of read interference for data with high access frequency can be reduced and data security can be improved.

[0064] In some embodiments, the above-mentioned process of selecting at least one data unit from the hot data unit group of the first flash memory block as the target data unit may include the following operations: using a data unit with a data read error rate having a predetermined ranking in the hot data unit group as the target data unit, where the predetermined ranking is the position of the data unit whose data read error rate is greater than a predetermined data read error rate threshold in the data unit data read error rate arrangement result.

[0065] In some embodiments, when determining the target data unit from the hot data unit group, the data unit with a predetermined data read error rate in the hot data unit group can be used as the target data unit. For example, the data units can be sorted in descending order according to the data read error rate of the data units to obtain a data read error rate arrangement result. The predetermined rank can be the position in the sorting result where the data unit with a data read error rate greater than a predetermined data read error rate threshold is located, that is, the data unit with a data read error rate greater than the predetermined data read error rate threshold is used as the target data unit to be migrated, and the predetermined data read error rate threshold can be adaptively adjusted according to actual needs. In another embodiment, the predetermined rank can also be the first position in the specified sorting result, that is, the data unit with the highest data read error rate in the first position is used as the target data unit to be migrated.

[0066] According to an embodiment of the present invention, by comparing the data read error rates of data units and prioritizing the migration of data units with high data read error rates, further errors in the data units can be avoided, the risk of read interference of the data units can be reduced, the security of the data can be improved, and problems such as SSD failure due to sudden high bit errors can be reduced, thereby improving the reliability of the SSD and extending the service life of the SSD.

[0067] In some embodiments, the process of migrating the target data unit to the second flash memory block may include the following operations: migrating the data to be migrated in the target data unit to the read buffer of the first flash memory block; migrating the data to be migrated in the read buffer to the write buffer of the second flash memory block, so that the data to be migrated is written to the second flash memory block through the write buffer.

[0068] In some embodiments, when migrating a target data unit, the data to be migrated of the target data unit can be first migrated to a read buffer (Read Buffer), and then migrated from the read buffer to a write buffer (WriteBuffer) of the second flash memory block. The data to be migrated in the write buffer can be written to the second flash memory block.

[0069] According to an embodiment of the present invention, by introducing a dual buffer mechanism such as a read buffer and a write buffer, the read buffer can temporarily store data to be migrated, releasing the access bandwidth of the first flash memory block; the write buffer can write data in batches to the second flash memory block, reducing frequent small-scale write operations; such decoupling of read and write operations can reduce the migration time caused by the need to wait for the second flash memory block to complete the write preparation work, improve data migration efficiency, and there can be no conflict between data reading and writing, which can improve the accuracy and security of data migration.

[0070] In some embodiments, the following operations can be performed on the read buffer or the write buffer: obtain the space utilization of the read buffer or the write buffer; when the space utilization exceeds a predetermined expansion threshold, trigger the expansion operation to obtain the expanded read buffer or the expanded write buffer; when the space utilization of the expanded read buffer or the expanded write buffer exceeds a predetermined expansion upper limit, push an alarm message to the target object.

[0071] In some embodiments, the predetermined expansion upper limit is greater than a predetermined expansion threshold. The target object may include an operation and maintenance manager or an intelligent robot. The alarm information may include information that the buffer capacity is about to be saturated.

[0072] According to an embodiment of the present invention, when the space utilization rate exceeds a predetermined expansion threshold, an expansion operation can be triggered, and expansion can be automatically performed, thereby improving the intelligence and efficiency of data processing. On the other hand, setting a predetermined expansion upper limit can prevent the read buffer or write buffer from expanding indefinitely, thereby implementing security constraints on the read buffer or write buffer and avoiding resource exhaustion. By pushing alarm information to the target object, it can be facilitated for the target object to process the read buffer or write buffer in a timely manner, ensuring data security and maintaining data processing efficiency.

[0073] In some embodiments, when migrating the target data unit's to-be-migrated data to the read buffer, data with an access frequency exceeding a predetermined data access frequency threshold can be prioritized for migration to the read buffer of the first flash memory block based on the access frequency of the to-be-migrated data. Accordingly, data with an access frequency exceeding the predetermined data access frequency threshold can be prioritized for migration from the read buffer to the write buffer, and data with an access frequency exceeding the predetermined data access frequency threshold can be prioritized for migration from the write buffer to the second flash memory block. This prioritizes the integrity of frequently accessed data to be migrated, thereby improving data reliability.

[0074] In some embodiments, when the data to be migrated is written to the second flash memory block, in response to the operation of writing the data to be migrated in the write buffer to the second flash memory block, according to the location information of the data to be migrated in the second flash memory block, in the file used to store the physical address of the data to be migrated, the physical address of the data to be migrated can be changed from the first flash memory block to the second flash memory block.

[0075] In some embodiments, the file used to store the physical addresses of the data to be migrated may include a logical to physical mapping table (L2P). The L2P table may be a data structure in the SSD that records the correspondence between the logical addresses accessed by the user (such as the logical addresses seen by the host or operating system) and the physical addresses of the actual stored data (such as the flash memory blocks and data units in the NAND). In response to the operation of writing the data to be migrated to the second flash memory block in the write buffer, it indicates that the physical address of the data to be migrated is changed from the first flash memory block to the second flash memory block. Therefore, the physical address of the data to be migrated in the L2P table can be changed from the first flash memory block to the second flash memory block to ensure that the physical address of the data to be migrated recorded in the L2P table is consistent with the actual storage address of the data to be migrated.

[0076] According to an embodiment of the present invention, by updating the physical addresses in the file used to store the physical addresses of the data to be migrated in real time, calibration protection of the physical addresses of the data to be migrated can be achieved, thereby ensuring the accuracy of the file used to store the physical addresses of the data to be migrated, and further ensuring the accuracy of data access, thereby improving the reliability of the SSD.

[0077] In some embodiments, based on the above-mentioned operating method, the data processing method may further include the following operations: when the data migration of the target data unit to the second flash memory block is completed, updating the total number of data units in the first flash memory block to obtain the updated number; in response to the updated number reaching a predetermined value, recycling the first flash memory block.

[0078] In some embodiments, the predetermined value can be a value used to determine whether the first flash memory block needs to be recycled, such as 0. For example, when the target data unit is migrated from the first flash memory block to the second flash memory block, the total number of data units in the first flash memory block is reduced by 1 until the updated number is 0, indicating that there is no data unit in the first flash memory block and all data units have been migrated to the second flash memory block. In this case, the first flash memory block can be recycled. After being recycled, the first flash memory block can be reused and used to normally store user-written data.

[0079] According to an embodiment of the present invention, by timely recycling the first flash memory block, available space can be released, the storage capacity of the SSD can be maintained, and there are always idle available flash memory blocks, thereby improving the reliability of the SSD and extending the service life of the SSD.

[0080] In some embodiments, the execution entity of the above method can integrate a hardware acceleration module (such as a Field-Programmable Gate Array (FPGA) computing unit) to parallelly process the calculation of the target read count upper limit value and the task of migrating data units, thereby reducing the load on the central processing unit on the server and reducing the read and write latency of the server.

[0081] In some embodiments, based on the above method, a real-time health model can be constructed by integrating multiple physical parameters (such as the number of PEs, voltage drift, and error correction feedback from the Error Correction Code (ECC)) to achieve more accurate SSD life prediction and data read error rate control, forming a full-stack optimization closed loop from algorithm to hardware.

[0082] Compared with the fixed threshold solution, the data processing method provided by the embodiment of the present invention constructs an exponential decay threshold model based on the degree of PE wear as shown in formula (2), so that the read tolerance of high PE number blocks decreases exponentially. =3000) remains unchanged, by intelligently predicting the risk of data failure, the uncorrectable bit error rate (UBER) is reduced from 1E-13 to 1E-15. At the same time, a phased data migration mechanism is adopted. The data migration step length is calculated by formula (1). Before reaching the target read count upper limit, the data length is migrated frame by frame in a granular manner, and the data migration is dispersed into multiple small steps. Compared with the centralized migration scheme of all data units in the all-flash block, the method of the embodiment of the present invention can avoid the performance fluctuation caused by one-time migration, and can reduce the burst input / output (I / O) delay peak and write amplification factor (WA). On the other hand, the above method combines periodic threshold calibration with real-time update of the L2P table to form a triple synergistic mechanism of dynamic attenuation, step-by-step migration, and calibration protection. This scheme significantly reduces the read disturbance error rate and achieves a balance between SSD performance and reliability in high-wear scenarios.

[0083] Figure 3 A flow chart of a data processing method according to another embodiment of the present invention is shown.

[0084] like Figure 3 As shown, the data processing method may include operations S301 to S309.

[0085] In operation S301, an initial read count upper limit value of a first flash memory block is set.

[0086] In operation S302, a target read count upper limit value is set according to a current PE number of a first flash memory block.

[0087] In operation S303, a read request is received and a target page in the first flash memory block is read. When the SSD receives the read request from the host, it reads the NAND according to the parsed read command and address, and adds 1 to the read count corresponding to the first flash memory block where the read target page is located, thus executing operation S304.

[0088] In operation S304 , the read count of the first flash memory block is increased by 1 to obtain a target read count.

[0089] In operation S305, it is determined whether the target read count is greater than a predetermined read count threshold. If the target read count is greater than the predetermined read count threshold, operation S306 is executed; if the target read count is less than the predetermined read count threshold, the process jumps to the end operation.

[0090] In operation S306, it is determined whether the target read count is divisible by the data migration step length. If the target read count is divisible by the data migration step length, operation S307 is executed; if the target read count is not divisible by the data migration step length, the process jumps to the end operation.

[0091] In operation S307 , the first data unit in the first flash memory block is selected as the target data unit and migrated to the second flash memory block.

[0092] In operation S308 , after all data units of the first flash memory block are migrated, the first flash memory block is recycled.

[0093] In operation S309, it is determined whether the number of PEs increased by the first flash memory block is divisible by the erase step size. If the number of PEs increased by the first flash memory block is divisible by the erase step size, the process starts from operation S302; if the number of PEs increased by the first flash memory block is not divisible by the erase step size, the process jumps to the end operation.

[0094] According to an embodiment of the present invention, a NAND flash memory data processing method based on a dynamic target read count upper limit dynamically adjusts the target read count upper limit of a flash memory block using an exponential decay function. Specifically, the target read count upper limit is calculated based on the number of PEs in the flash memory block and the initial read count upper limit that the flash memory block can withstand. Each flash memory block can contain N pages, each of which contains four data units (Dataframes). Each time a read operation is performed on a flash memory block, the read count of the flash memory block is incremented by 1 to obtain the target read count. When the target read count reaches an integer multiple of the data migration step size, the data units (Dataframes) are migrated in stages to avoid performance fluctuations caused by a one-time migration. Simultaneously, the target read count upper limit is updated when the PE count increment of the flash memory block reaches the erase / write step size. Data integrity protection is achieved by real-time updating of the L2P table and writing new flash memory block data. This method effectively reduces the probability of errors caused by read disturb and extends the lifespan of SSD flash memory through the triple mechanism of dynamic decay of the target read count upper limit, step-by-step data migration, and periodic threshold calibration.

[0095] It should be noted that, unless it is clearly stated that there is a sequence of execution between different operations shown in the flowchart in the embodiments of the present invention, or there is a sequence of execution between different operations in technical implementation, otherwise, the execution order of multiple operations may not be prioritized, and multiple operations may also be executed simultaneously.

[0096] Based on the above data processing method, the present invention also provides a data processing device. Figure 4 The device is described in detail.

[0097] Figure 4 A structural block diagram of a data processing device according to an embodiment of the present invention is shown.

[0098] like Figure 4 As shown, the data processing device 400 of this embodiment includes a first update module 410 , a detection module 420 and a migration module 430 .

[0099] The first update module 410 is configured to update a read count of the first flash memory block in response to a read request for reading data of the first flash memory block to obtain a target read count.

[0100] The detection module 420 is used to detect the relationship between the target read count and the data migration step when the target read count is greater than a predetermined read count threshold, and obtain a detection result, wherein the data migration step is determined based on the target read count upper limit value, the predetermined read count threshold value, and the number of data units in the first flash memory block, the target read count upper limit value is greater than the predetermined read count threshold value, and decreases with the number of erase and write times of the first flash memory block.

[0101] The migration module 430 is configured to determine a target data unit to be migrated from the multiple data units in the first flash memory block when the detection result indicates that the target read count is an integer multiple of the data migration step length, so as to migrate the target data unit to the second flash memory block.

[0102] In some embodiments, the data processing device may further include a first determining module and a second determining module.

[0103] The first determination module is used to determine a first influence coefficient of the number of erase and write times on the target read count upper limit value based on the first current number of erase and write times of the first flash memory block and the upper limit value of the number of erase and write times of the first flash memory block, wherein when the first current number of erase and write times of the first flash memory block reaches the upper limit value of the number of erase and write times, an alarm information indicating that the first flash memory block has failed is generated.

[0104] The second determination module is used to determine a target read count upper limit value based on an initial read count upper limit value of the first flash memory block and a first influence coefficient, wherein the initial read count upper limit value represents the read count upper limit of the first flash memory block when no erasure or writing occurs and is greater than the target read count upper limit value.

[0105] In some embodiments, the data processing device may further include a first adjustment module and a second adjustment module.

[0106] The first adjustment module is used to reduce the first influence coefficient to a second influence coefficient based on the second current erase number and the upper limit of the erase number when the difference between the second current erase number and the first current erase number of the first flash memory block is an integer multiple of the erase step size, wherein the second current erase number represents the erase number of the first flash memory block when a predetermined time period has passed after the first current erase number is reached.

[0107] The second adjustment module is configured to reduce the target read count upper limit value according to the second influence coefficient and the initial read count upper limit value to obtain an updated target read count upper limit value.

[0108] In some embodiments, the migration module 430 may include a selection unit.

[0109] A selection unit is configured to select at least one data unit from a hot data unit group of the first flash memory block as a target data unit, wherein the hot data unit group is obtained by grouping a plurality of data units based on a relationship between an access frequency of the data units being accessed within a predetermined time period and a predetermined access frequency threshold, and the access frequency of the data units in the hot data unit group is greater than or equal to the predetermined access frequency threshold.

[0110] In some embodiments, the selection unit may include a selection sub-unit.

[0111] A selection subunit is used to select a data unit with a predetermined data read error rate in the hot data unit group as a target data unit. The predetermined position is the position of the data unit with a data read error rate greater than a predetermined data read error rate threshold in the data unit data read error rate arrangement result.

[0112] In some embodiments, the migration module 430 may further include a first migration unit and a second migration unit.

[0113] The first migration unit is configured to migrate the data to be migrated in the target data unit to the read buffer of the first flash memory block.

[0114] The second migration unit is configured to migrate the data to be migrated in the read buffer to the write buffer of the second flash memory block, so as to write the data to be migrated into the second flash memory block through the write buffer.

[0115] In some embodiments, the data processing apparatus may further include a modification module.

[0116] A change module is used to respond to the operation of writing the data to be migrated in the write buffer into the second flash memory block, and according to the location information of the data to be migrated in the second flash memory block, change the physical address of the data to be migrated from the first flash memory block to the second flash memory block in the file used to store the physical address of the data to be migrated.

[0117] In some embodiments, the data processing device may further include a second update module and a recycling module.

[0118] The second update module is configured to update the total number of data units in the first flash memory block to obtain an updated number when the data migration from the target data unit to the second flash memory block is completed.

[0119] The recycling module is configured to recycle the first flash memory block in response to the number of updates reaching a predetermined value.

[0120] According to embodiments of the present invention, any multiple modules among the first update module 410, the detection module 420, and the migration module 430 may be combined into a single module, or any one of these modules may be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of other modules and implemented in a single module. According to embodiments of the present invention, at least one of the first update module 410, the detection module 420, and the migration module 430 may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or may be implemented in hardware or firmware through any other suitable means of circuit integration or packaging, or may be implemented in any one of software, hardware, and firmware, or any suitable combination thereof. Alternatively, at least one of the first update module 410, the detection module 420, and the migration module 430 may be at least partially implemented as a computer program module that, when executed, performs the corresponding functionality.

[0121] Figure 5 A block diagram of an electronic device suitable for implementing a data processing method according to an embodiment of the present invention is shown.

[0122] like Figure 5 As shown, an electronic device 500 according to an embodiment of the present invention includes a processor 501, which can perform various appropriate actions and processes based on programs stored in a read-only memory (ROM) 502 or programs loaded from a storage unit 508 into a random access memory (RAM) 503. The processor 501 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or related chipsets and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 501 may also include onboard memory for caching purposes. The processor 501 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0123] Various programs and data required for the operation of the electronic device 500 are stored in the RAM 503. The processor 501, ROM 502, and RAM 503 are connected to each other via a bus 504. The processor 501 executes the programs in the ROM 502 and / or RAM 503 to perform various operations according to the method flow of the embodiment of the present invention. It should be noted that the programs may also be stored in one or more memories other than the ROM 502 and RAM 503. The processor 501 may also execute the programs stored in the one or more memories to perform various operations according to the method flow of the embodiment of the present invention.

[0124] According to an embodiment of the present invention, electronic device 500 may further include an input / output (I / O) interface 505, which is also connected to bus 504. Electronic device 500 may also include one or more of the following components connected to I / O interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including devices such as a cathode ray tube (CRT), liquid crystal display (LCD), and speakers; a storage section 508 including a hard disk; and a communication section 509 including a network interface card such as a LAN card or modem. Communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to I / O interface 505 as needed. Removable media 511, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in drive 510 as needed, so that computer programs read from the removable media can be installed into storage section 508 as needed.

[0125] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments, or may exist independently and not incorporated into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0126] According to an embodiment of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, and may include, for example, but not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present invention, a computer-readable storage medium may include the ROM 502 and / or RAM 503 described above, and / or one or more memories other than ROM 502 and RAM 503.

[0127] The embodiments of the present invention further include a computer program product, which includes a computer program containing program code for executing the method shown in the flowchart. When the computer program product is executed in a computer system, the program code is used to cause the computer system to implement the data processing method provided by the embodiments of the present invention.

[0128] The computer program executes the above functions defined in the system / device of the embodiment of the present invention when the computer program is executed by the processor 501. According to the embodiment of the present invention, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0129] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal on a network medium, downloaded and installed via the communication portion 509, and / or installed from a removable medium 511. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0130] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 509 and / or installed from the removable medium 511. When the computer program is executed by the processor 501, the above-described functions defined in the system of the embodiment of the present invention are performed. According to the embodiment of the present invention, the systems, devices, means, modules, units, etc. described above can be implemented by computer program modules.

[0131] According to an embodiment of the present invention, the program code for executing the computer program provided by the embodiment of the present invention can be written in any combination of one or more programming languages. Specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0132] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0133] It will be understood by those skilled in the art that the features described in the various embodiments of the present invention may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention may be combined and / or coupled in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or couplings fall within the scope of the present invention.

[0134] The above describes embodiments of the present invention. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A data processing method, characterized in that: The method comprises: In response to a read request for reading data of a first flash memory block, updating a read count of the first flash memory block to obtain a target read count; When the target read count is greater than a predetermined read count threshold, a relationship between the target read count and a data migration step length is detected to obtain a detection result, wherein the data migration step length is determined based on a target read count upper limit value, the predetermined read count threshold value, and the number of data units in the first flash memory block, the target read count upper limit value is greater than the predetermined read count threshold value, and decreases with the number of erase and write times of the first flash memory block. The process of determining the data migration step length is shown in the formula: ,in, is the data migration step, is the target read count upper limit value, is a predetermined read count threshold, N is the number of data units in the first flash memory block; When the detection result indicates that the target read count is an integer multiple of the data migration step length, a target data unit to be migrated is determined from the multiple data units of the first flash memory block, so as to migrate the target data unit to the second flash memory block.

2. The method according to claim 1, characterized in that The target read count upper limit is determined as follows: determining, based on a first current erase / write count of the first flash memory block and an upper limit of the erase / write count of the first flash memory block, a first influence coefficient of the erase / write count on the target read count upper limit, wherein when the first current erase / write count of the first flash memory block reaches the upper limit of the erase / write count, generating an alarm indicating failure of the first flash memory block; The target read count upper limit value is determined based on the initial read count upper limit value of the first flash memory block and the first influence coefficient. The initial read count upper limit value represents the read count upper limit of the first flash memory block when no erasure or writing occurs, and is greater than the target read count upper limit value.

3. The method according to claim 2, characterized in that The method further comprises: When a difference between a second current erase / write count of the first flash memory block and the first current erase / write count is an integer multiple of the erase step length, reducing the first influence coefficient to a second influence coefficient according to the second current erase / write count and the upper limit of the erase / write count, wherein the second current erase / write count represents the erase / write count of the first flash memory block when a predetermined time has passed after the first current erase / write count is reached; According to the second influence coefficient and the initial read count upper limit value, the target read count upper limit value is reduced to obtain an updated target read count upper limit value.

4. The method according to claim 1, wherein The determining a target data unit to be migrated from the plurality of data units of the first flash memory block includes: At least one data unit is selected from a hot data unit group of the first flash memory block as the target data unit, wherein the hot data unit group is obtained by grouping a plurality of the data units based on a relationship between an access frequency of the data units being accessed within a predetermined time period and a predetermined access frequency threshold, and an access frequency of the data units in the hot data unit group is greater than or equal to the predetermined access frequency threshold.

5. The method according to claim 4, characterized in that The selecting at least one data unit from the hot data unit group of the first flash memory block as the target data unit includes: A data unit with a predetermined ranking of data read error rates in the hot data unit group is used as a target data unit. The predetermined ranking is the position of the data unit with a data read error rate greater than a predetermined data read error rate threshold in the data unit data read error rate arrangement result.

6. The method according to claim 1, characterized in that Migrating the target data unit to the second flash memory block includes: Migrating the data to be migrated in the target data unit to the read buffer of the first flash memory block; The data to be migrated in the read buffer is migrated to the write buffer of the second flash memory block, so that the data to be migrated is written to the second flash memory block through the write buffer.

7. The method according to claim 6, characterized in that The method further comprises: In response to the operation of writing the data to be migrated in the write buffer to the second flash memory block, based on the location information of the data to be migrated in the second flash memory block, in the file used to store the physical address of the data to be migrated, the physical address of the data to be migrated is changed from the first flash memory block to the second flash memory block.

8. The method according to claim 1, characterized in that The method further comprises: When the data migration of the target data unit to the second flash memory block is completed, updating the total number of data units in the first flash memory block to obtain an updated number; In response to the number of updates reaching a predetermined value, the first flash memory block is reclaimed.

9. An electronic device comprising: one or more processors; a memory for storing one or more computer programs, It is characterized in that the one or more processors execute the one or more computer programs to implement the steps of the method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 8 are implemented.

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