Data accumulation methods, accumulators, chips, electronic devices

Abstract

This application provides a data accumulation method, accumulator, chip, and electronic device. The method includes: acquiring an instruction; the instruction includes an identifier for the data to be processed and the type of the data to be processed; the type is either a floating-point number or a fixed-point number; based on the identifier, sequentially reading a group of data; wherein each group includes a number of processed data, mC is the minimum processing amount per operation, nB is the number of bits in any processed data, and is a floor function; for each group, performing Wallace tree-based compression based on the type, performing leading zero detection on the compression result, and obtaining the accumulation result of the group of data. The method provided in this application reads a group of data sequentially based on the identifier in the instruction; wherein each group includes a preset number of processed data; for each group, performing Wallace tree-based compression based on the type, performing leading zero detection on the compression result, and obtaining the accumulation result of the group of data, thereby accelerating the data processing speed and improving processing efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data accumulation method, accumulator, chip, and electronic device. Background Technology

[0002] With the development of artificial intelligence, the demand for multiplication-accumulation calculations has surged. Taking deep learning technology as an example, it is a core technology of artificial intelligence and has played a significant role in promoting many applications.

[0003] Deep learning algorithms are typically computationally intensive, and matrix multiplication, a core component of these algorithms, is a computationally and data-intensive operation. Deep learning algorithms require a large number of matrix multiplication operations.

[0004] In existing technologies, when performing data accumulation, it is necessary to accumulate the data in each row one by one and then output the horizontal accumulation result. However, each instruction can only operate on one data in the matrix. Therefore, matrix operations need to be broken down into operations on multiple data. Since the amount of data in matrix operations is large, the efficiency is extremely low and the power consumption is high during the data accumulation calculation process. Summary of the Invention

[0005] To address one of the aforementioned technical deficiencies, this application provides a data accumulation method, an accumulator, a chip, and an electronic device.

[0006] The first aspect of this application provides a data accumulation method, characterized in that the method includes:

[0007] Obtain the instruction; the instruction includes an identifier for the data to be processed and the type of the data to be processed; the type is either a floating-point number or a fixed-point number.

[0008] Based on the identifier, read a set of data sequentially; each set includes The number of data points to be processed is given by mC, where mC is the minimum processing size per run and nB is the number of bits in any given data set. It is the floor function;

[0009] For each group, Wallace tree-based compression is performed based on the type. Leading zero detection is performed on the compression result to obtain the cumulative result of the data in that group.

[0010] Optionally, for any set, Wallace tree-based compression is performed based on type, including:

[0011] Based on the type and the processed data of any group, determine the first data tD1;

[0012] Compression of tD1 based on Wallace tree yields two second data points. and

[0013] Will and Add them together to get the compressed result.

[0014] Optionally, the first data tD1 is determined based on the type and the processed data of any group, including:

[0015] If the type is a fixed-point number, then tD1 is determined to be the processing data for any group;

[0016] If the type is floating-point, then the data in any group is shifted according to the type to obtain tD1.

[0017] Optionally, depending on the type, the processed data of any group is shifted to obtain tD1, including:

[0018] Based on the type, extract the exponent and mantissa of each processed data in any group;

[0019] Determine the complement of each digit;

[0020] Based on the complements of each exponent and each mantissa, perform an order shift to obtain the third data tD3;

[0021] After performing floating-point special value detection on tD3, tD1 is obtained.

[0022] Optionally, based on the complement of each exponent and each mantissa, an order-shifting operation is performed to obtain the third data tD3, including:

[0023] Determine the maximum value E among the indices. max ;

[0024] For any processed data, the docking shift is performed through the following steps to obtain the corresponding tD3:

[0025] Set the bit count value nC i =0;

[0026] Calculate E sequentially from the least significant digit to the most significant digit. max With E i The difference between each value Each time the difference nC is obtained i All increment by 1; simultaneously, whenever nC i When a non-zero segment value is reached, the difference between each bit in the current segment value (-1) and the previous segment value is shifted. according to Shift the shift result of the previous segment to obtain tD3 corresponding to any processed data;

[0027] Where i is the data identifier being processed, and E i To process the exponent of data i, j is a bit identifier. For E max With E i The difference between the j-th positions; the first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1; v is the segment identifier, and the initial value of v is 1. If v = 1, the shift result of the previous segment is src. i It consists of the sign bit and the complement of the mantissa of the processed data i.

[0028] Optionally, the segment values ​​are 0, 3, 6, and 11;

[0029] Whenever nC i When a non-zero segment value is reached, the difference between each bit in the current segment value and the target segment value is shifted. according to The shift result of the previous segment is shifted to obtain tD3 corresponding to any processed data, including:

[0030] When nC i When the value is 3, the difference between the 2nd and 0th digits is used to form the shift value. src i Move right This gives the shift result of the first segment.

[0031] When nC i When the value is 6, the difference between the 5th and 3rd digits is shifted. Will Move right The second segment is shifted to obtain the result.

[0032] When nC i When the value is 11, the difference between the 10th and 6th digits is shifted. like Then determine the data i to be processed Otherwise, determine that tD3 = 0 for the data i being processed.

[0033] Optionally, leading zero detection is performed on the compression result to obtain the cumulative result of the data set, including:

[0034] The number of bits to be judged (nd) is the total number of bits in the compression result;

[0035] The compression result is designated as the fourth data tD4;

[0036] Determine if the high nd bits of tD4 are all 0;

[0037] If all bits are 0, then when nd is the total number of bits in the compressed result, the fifth data tD5 = 0; when nd is the total number of bits in the uncompressed result, tD4 = tD4 << nd is determined. If nd = 1, then tD5 = tD4; if nd ≠ 1, then... Repeat the step of checking whether the high nd bits of tD4 are all 0 and the subsequent steps;

[0038] If not all zeros, then when nd = 1, we get tD5 = tD4; when nd ≠ 1, Repeat the step of checking if the high nd bits of tD4 are all 0, and the subsequent steps; where... It is the floor function;

[0039] Expanding tD5 yields the sixth data tD6;

[0040] After performing floating-point special value detection on tD6, the cumulative result of this set of data is obtained.

[0041] A second aspect of this application provides an accumulator, the accumulator comprising:

[0042] The acquisition module is used to acquire instructions; the instructions include an identifier for the data to be processed and the type of the data to be processed; the type is either a floating-point number or a fixed-point number.

[0043] The read module is used to read a set of data sequentially based on an identifier; each set includes... The number of data points to be processed is given by mC, where mC is the minimum processing size per run and nB is the number of bits in any given data set. It is the floor function;

[0044] The accumulation module is used to perform Wallace tree-based compression on each group read by the reading module, perform leading zero detection on the compression result, and obtain the accumulation result of the group of data.

[0045] A third aspect of this application provides a chip comprising: the accumulator described in the second aspect above;

[0046] The accumulator is used to implement the data accumulation method described in the first aspect above.

[0047] A fourth aspect of this application provides an electronic device comprising: the chip described in the third aspect.

[0048] This application provides a data accumulation method, accumulator, chip, and electronic device. The method includes: acquiring an instruction; the instruction includes an identifier for processing data and a type of data to be processed; the type is either a floating-point number or a fixed-point number; and sequentially reading a group of data based on the identifier; wherein each group includes... The number of data points to be processed is given by mC, where mC is the minimum processing size per run and nB is the number of bits in any given data set. The method described in this application uses a floor function to extract data from a set of data. For each set, Wallace tree-based compression is performed based on the data type. Leading zeros are then checked on the compression result to obtain the accumulated result of that set of data. The method reads a set of data sequentially based on the identifier in the instruction. Each set includes a preset number of data items. For each set, Wallace tree-based compression is performed based on the data type. Leading zeros are then checked on the compression result to obtain the accumulated result of that set of data, thus accelerating the data processing speed and improving processing efficiency. Attached Figure Description

[0049] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0050] Figure 1 A flowchart illustrating a data accumulation method provided in an embodiment of this application;

[0051] Figure 2 A schematic diagram of an fp64 data format provided in an embodiment of this application;

[0052] Figure 3 A schematic diagram of an fp32 data format provided in an embodiment of this application;

[0053] Figure 4 A schematic diagram of a Wallace tree provided for an embodiment of this application;

[0054] Figure 5 A schematic diagram of an accumulator provided in an embodiment of this application;

[0055] Figure 6 This is a schematic diagram of the structure of a vector processor provided in an embodiment of this application;

[0056] Figure 7 This is a schematic diagram of the structure of a high-performance processor provided in an embodiment of this application;

[0057] Figure 8 This is a schematic diagram of the structure of a scalar processor provided in an embodiment of this application;

[0058] Figure 9 This is a schematic diagram of the structure of a synchronization unit for a scalar processor provided in an embodiment of this application. Detailed Implementation

[0059] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0060] In the process of developing this application, the inventors discovered that deep learning algorithms are typical computationally intensive algorithms, and matrix multiplication, as the core component of these algorithms, is a computationally and data-intensive operation. Deep learning algorithms require a large number of matrix multiplications. In existing technologies, when accumulating data, each row of data needs to be accumulated one by one before outputting the horizontal accumulation result. However, each instruction can only operate on one data point in the matrix, thus matrix operations need to be broken down into operations on multiple data points. Due to the large amount of data involved in matrix operations, the efficiency during data accumulation calculations is extremely low and the power consumption is high.

[0061] To address the aforementioned problems, this application provides a data accumulation method, accumulator, chip, and electronic device. The method includes: acquiring an instruction; the instruction includes an identifier for the data to be processed and a type of data to be processed; the type is either a floating-point number or a fixed-point number; and sequentially reading a group of data based on the identifier; wherein each group includes... The number of data points to be processed is given by mC, where mC is the minimum processing size per run and nB is the number of bits in any given data set. The method described in this application uses a floor function to extract data from a set of data. For each set, Wallace tree-based compression is performed based on the data type. Leading zeros are then checked on the compression result to obtain the accumulated result of that set of data. The method reads a set of data sequentially based on the identifier in the instruction. Each set includes a preset number of data items. For each set, Wallace tree-based compression is performed based on the data type. Leading zeros are then checked on the compression result to obtain the accumulated result of that set of data, thus accelerating the data processing speed and improving processing efficiency.

[0062] See Figure 1 This embodiment provides a data accumulation method, the implementation process of which is as follows:

[0063] 101, Get Instructions.

[0064] The instruction includes an identifier for the data to be processed and the type of data to be processed. The type can be either a floating-point number or a fixed-point number.

[0065] Before executing the method provided in this embodiment, corresponding data is stored based on the computational requirements. For example, if the computational requirement is to calculate the multiplication of two matrices, then the data of the two matrices will be stored. Then, the data identifier (such as the data storage location, which only needs to uniquely point to the data, that is, the data can be accurately read based on the identifier) ​​and the data type are written into the instruction.

[0066] The data type can be a fixed-point number (such as int32) or a floating-point number (such as fp32 or fp64). For example, a 40-bit instruction might include an identifier for the data to be processed and a 2-bit data type. If these 2 bits are 01, it indicates that the data type is fp64 (double-precision floating-point); 10 indicates that the data type is fp32 (single-precision floating-point); and 11 indicates that the data type is int32 (32-bit signed integer).

[0067] The identification of the data processed above is only an example; in actual applications, it can be determined based on pre-configured information.

[0068] The method in this embodiment does not limit the type of data processed; that is, the method in this embodiment can process any type of data.

[0069] In step 101, the instruction is obtained, and the identifier of the data to be processed and the type of data to be processed are obtained from the instruction.

[0070] 102. Based on the identifier, read a set of data sequentially.

[0071] Each group includes The number of data points to be processed is given by mC, where mC is the minimum processing size per run and nB is the number of bits in any given data set. This is the floor function.

[0072] For example, if the minimum processing size per operation is 512 bits, and the data type is fp64, then the data size is 64 bits, and a set of data includes... Each time, eight pieces of data will be read to form a group, meaning each group of data will include eight pieces of data to be processed.

[0073] For example, if the minimum processing size per operation is 512 bits, and the data type is fp32, then the data bit width is 32 bits, and a set of data includes... Each time, 16 pieces of data will be read to form a group, meaning each group of data will include 16 pieces of data.

[0074] For example, if the minimum processing size is 512 bits and the data type is int32, then the processed data is 32 bits long. A set of data includes... Each time, 16 pieces of data will be read to form a group, meaning each group of data will include 16 pieces of data.

[0075] In addition, the data read is arranged in a close-knit group. For example, a group of data may include: data 0, data 1, data 2, data 3, data 4, data 5, data 6, and data 7. This group of data is shown in Table 1.

[0076] Table 1

[0077]

[0078] For ease of description, unless otherwise specified, the method provided in this embodiment will be described using the minimum processing amount of 512 bits, the data type of the processed data as fp64, and 8 data points of processed data acquired each time. For other types of processed data, refer to fp64 and will not be described in detail.

[0079] 103. For each group, Wallace tree-based compression is performed based on the type. Leading zero detection is performed on the compression result to obtain the cumulative result of the data in that group.

[0080] In the specific implementation, step 102 is executed once to read a set of data, and then step 103 is executed again to perform type-based Wallace tree compression. Leading zeros are checked on the compressed result to obtain the accumulated result of this set of data. Then step 102 is executed again to read the next set of data, and step 103 is executed again to perform type-based Wallace tree compression. Leading zeros are checked on the compressed result to obtain the accumulated result of this set of data. Then step 102 and step 103 are executed again, and so on, until all processed data has undergone step 102 and step 103 once to obtain the accumulated result.

[0081] For any set of data read in step 102 (for example, the set of data includes processed data 0, processed data 1, processed data 2, processed data 3, processed data 4, processed data 5, processed data 6, and processed data 7), in step 103, the set of data will be compressed based on type using a Wallace tree, and the compression result will be checked for leading zeros to obtain the cumulative result of the set of data.

[0082] The implementation details are as follows:

[0083] 1. Type-based compression based on Wallace tree.

[0084] 1) Determine the first data tD1 based on the type and the processing data of any group.

[0085] If the type is a fixed-point number (such as int32), then tD1 is determined to be the processing data for any group. Therefore, tD1 also includes 7 data items: processing data 0, processing data 1, processing data 2, processing data 3, processing data 4, processing data 5, processing data 6, and processing data 7.

[0086] If the data type is floating-point (such as fp32 or fp64), then the data in any group is shifted according to its type to obtain tD1. The specific implementation process is as follows:

[0087] (1) Extract the exponent and mantissa of each processed data in any group according to the type.

[0088] Different types of data have their own data formats. For example, fp64 represents 64 bits of binary, where there is 1 bit for the sign, 11 bits for the exponent, and 52 bits for the fraction. Figure 2 As shown.

[0089] For example, fp32 represents 32 bits of binary, where 1 bit is the sign bit, 8 bits are the exponent, and 23 bits are the fraction. Figure 3 As shown.

[0090] Here, you can read the corresponding data from the exponent and bit positions based on the data type.

[0091] For example, this set of data includes processed data 0, processed data 1, processed data 2, processed data 3, processed data 4, processed data 5, processed data 6, and processed data 7. The type of the processed data is fp64. Therefore, the content [51:0] from processed data 0 is used as the mantissa F0, and the content [62:52] from processed data 0 is used as the exponent E0. The content [51:0] from processed data 1 is used as the mantissa F1, and the content [62:52] from processed data 1 is used as the exponent E1. The content [51:0] from processed data 2 is used as the mantissa F2, and the content [62:52] from processed data 2 is used as the exponent E2. …The content [51:0] from processed data 7 is used as the mantissa F7, and the content [62:52] from processed data 7 is used as the exponent E7.

[0092] In this step, eight exponents (such as E0, E1, E2, E3, E4, E5, E6, E7) and eight mantissas (such as F0, F1, F2, F3, F4, F5, F6, F7) of the eight processed data will be extracted.

[0093] It should be noted that in this embodiment and subsequent embodiments, when expressing the number of bits, [51:0] represents the 51st bit to the 0th bit, and [62:52] represents the 62nd bit to the 52nd bit. If there are similar expressions, please refer to this, and no further specific explanation will be given.

[0094] At the same time, the symbols of each processed data in any group will also be extracted here.

[0095] (2) Determine the complement of each mantissa.

[0096] In this step, existing schemes can be used to determine the complement of each mantissa. For example, determine the complements of F0, F1, F2, F3, F4, F5, F6, and F7 as F'0, F'1, F'2, F'3, F'4, F'5, F'6, and F'7.

[0097] (3) Based on the complement of each exponent and each mantissa, perform an alignment shift to obtain the third data tD3.

[0098] The docking shift process is as follows: Determine the maximum value E among the various indices. max For any processed data, the corresponding tD3 is obtained by performing docking shifting through the following steps:

[0099] Set the bit count value nC i =0.

[0100] Calculate E sequentially from the least significant digit to the most significant digit. max With E i The difference between each value Each time the difference nC is obtained i All increment by 1. Also, whenever nC... i When a non-zero segment value is reached, the difference between each bit in the current segment value (-1) and the previous segment value is shifted. according to The shift result of the previous segment is shifted to obtain tD3 corresponding to any processed data.

[0101] Where i is the data identifier being processed, and E i To process the exponent of data i, j is a bit identifier. For E max With E iThe difference between the j-th positions. The first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1. v is the segment identifier, and the initial value of v is 1. If v = 1, the shift result of the previous segment is src. i It consists of the sign bit and the two's complement of the mantissa of the processed data i, such as src i It consists of the overflow bit, the complement of the mantissa of the processed data i, and the precision bits.

[0102] In specific implementations, such as fp64, src i It is 65 bits, where [64:60] are overflow bits, which can be obtained by expanding the sign bit or by copying the sign bit to 5 bits. [59:8] are the mantissa bits, which are the two's complement of the mantissa. [7:0] are the precision bits, which are all 0. The precision bits are used for subsequent Wallace number compression. For example, fp32, src i The number is 37 bits, of which [36:32] are overflow bits, which can be obtained by expanding the sign bit or by copying the sign bit to 5 bits. [31:8] are the mantissa bits, which are the two's complement of the mantissa with hidden bits. [7:0] are the precision bits, which are all 0. The precision bits are used for subsequent Wallace number compression.

[0103] The segment values ​​are 0, 3, 6, and 11.

[0104] Whenever nC i When a non-zero segment value is reached, the difference between each bit in the current segment value and the target segment value is shifted. according to The implementation details of shifting the shift result of the previous segment to obtain tD3 corresponding to any processed data are as follows:

[0105] When nC i When the value is 3, the difference between the 2nd and 0th digits is used to form the shift value. src i Move right This gives the shift result of the first segment.

[0106] Specific The implementation process is shown in Table 2:

[0107] Table 2

[0108]

[0109]

[0110] When nC i When the value is 6, the difference between the 5th and 3rd digits is shifted. Will Move right The second segment is obtained by shifting the position.

[0111] Specific The implementation process is shown in Table 3:

[0112] Table 3

[0113]

[0114] When nC i When the value is 11, the difference between the 10th and 6th digits is shifted. like Then determine the data i to be processed Otherwise, determine that tD3 = 0 for the data i being processed.

[0115] The specific implementation process of tD3 is shown in Table 4:

[0116] Table 4

[0117]

[0118] Taking the group as an example, which includes 8 data points, namely data 0, data 1, data 2, data 3, data 4, data 5, data 6, and data 7, with the 8 exponents being E0, E1, E2, E3, E4, E5, E6, and E7, and the 8 mantissas having the complements F'0, F'1, F'2, F'3, F'4, F'5, F'6, and F'7, and the segment values ​​being 0, 3, 6, and 11, the above docking and shifting process will be illustrated.

[0119] Determine the maximum value E among E0, E1, E2, E3, E4, E5, E6, and E7. max .

[0120] For processing data 0: Set the bit count value nC0 = 0.

[0121] Calculate E max The difference between the 0th bit and the 0th bit of E0 nC0 = nC0 + 1 = 1; Calculate E max The difference between the first bit and the first bit of E0 nC0 = nC0 + 1 = 2; Calculate E max The difference between the second digit and the second digit of E0 nC0 = nC0 + 1 = 3; at this point, nC0 reaches the first non-zero segment value (i.e., 3), so the difference between bits 2, 1, and 0 forms the shift value. (Right now for ); The shift result of the first segment is obtained. Where src0 is the sign bit of the data 0, the two's complement of the mantissa of the data 0, and the precision bits.

[0122] Calculate E max The difference between the 3rd bit and the 3rd bit of E0 nC0 = nC0 + 1 = 4; Calculate E max The difference between the 4th bit and the 4th bit of E0 nC0 = nC0 + 1 = 5; Calculate E max The difference between the 5th bit and the 5th bit of E0 nC0 = nC0 + 1 = 6; at this point, nC0 reaches the second non-zero segment value (i.e., 6), so the difference between the 5th, 4th, and 3rd bits is used to form the shift value. (Right now for The shift result of the second segment is obtained.

[0123] Calculate E max The difference between the 6th bit and the 6th bit of E0 nC0 = nC0 + 1 = 7; Calculate E max The difference between the 7th bit and the 7th bit of E0 nC0 = nC0 + 1 = 8; Calculate E max The difference between the 8th bit and the 8th bit of E0 nC0 = nC0 + 1 = 9; Calculate E max The difference between the 9th bit and the 9th bit of E0 nC0 = nC0 + 1 = 10; Calculate E max The difference between the 10th bit and the 10th bit of E0 nC0 = nC0 + 1 = 11; at this point, nC0 reaches the third non-zero segment value (i.e., 11), which is also the last segment value. The difference between bits 10, 9, 8, 7, and 6 is then used to form a shift value. (Right now for );like Then we get the data corresponding to processing data 0. Otherwise, the result is tD3 = 0 corresponding to the processed data 0.

[0124] For processing data 1: Set the bit count value nC1 = 0.

[0125] Calculate E max The difference between the 0th bit and the 0th bit of E1 nC1 = nC1 + 1 = 1; Calculate E max The difference between the first digit and the first digit of E1 nC1 = nC1 + 1 = 2; Calculate Emax The difference between the second digit and the second digit of E1 nC1 = nC1 + 1 = 3; at this point, nC1 reaches the first non-zero segment value (i.e., 3), so the difference between bits 2, 1, and 0 forms the shift value. (Right now for ); The shift result of the first segment is obtained. Where src1 is the sign bit of processed data 1 + the complement of the mantissa of processed data 1 + the precision bits.

[0126] Calculate E max The difference between the 3rd digit and the 3rd digit of E1 nC1 = nC1 + 1 = 4; Calculate E max The difference between the 4th bit and the 4th bit of E1 nC1 = nC1 + 1 = 5; Calculate E max The difference between the 5th bit and the 5th bit of E1 nC1 = nC1 + 1 = 6; at this point, nC1 reaches the second non-zero segment value (i.e., 6), so the difference between the 5th, 4th, and 3rd bits is used to form a shift number. (Right now for The shift result of the second segment is obtained.

[0127] Calculate E max The difference between the 6th bit and the 6th bit of E1 nC1 = nC1 + 1 = 7; Calculate E max The difference between the 7th bit and the 7th bit of E1 nC1 = nC1 + 1 = 8; Calculate E max The difference between the 8th bit and the 8th bit of E1 nC1 = nC1 + 1 = 9; Calculate E max The difference between the 9th bit and the 9th bit of E1 nC1 = nC1 + 1 = 10; Calculate E max The difference between the 10th bit and the 10th bit of E1 nC1 = nC1 + 1 = 11; at this point, nC1 reaches the third non-zero segment value (i.e., 11), which is also the last segment value. The difference between bits 10, 9, 8, 7, and 6 is then used to form a shift value. (Right now for );like Then we get the data corresponding to processed data 1. Otherwise, the result is tD3 = 0 for processed data 1.

[0128] …

[0129] Until data 7 is processed, we get 8 data points corresponding to tD3, that is, there are 8 tD3, each corresponding to one data point.

[0130] It should be noted that regardless of the number of digits in the last digit, the final tD3 can be obtained by the difference of the first 11 digits, thus completing the docking and shifting process.

[0131] In the shift process described in (3) above, the difference between all 11 bits is not calculated before shifting them all at once. Instead, the shift is performed whenever a difference between segments is obtained. This method will shift the whole into multiple shifts based on the minimum shift width, which can improve the shifting speed.

[0132] (4) After performing floating-point special value detection on tD3, tD1 is obtained.

[0133] In this process, the existing floating-point special value detection method will be used to detect 8 tD3 values, and tD1 will be obtained after the detection.

[0134] After detecting floating-point special values, special values ​​such as 0, infinity, and NaN can be detected.

[0135] NaN is used to represent undefined or unrepresentable values, such as 0 / 0, ∞-∞, etc.

[0136] For example, for each processed data (fp64 or pf32), when the value of the exponent part is the maximum value and the value of the mantissa part is 0, infinity is detected; when the value of the exponent part is the maximum value and the value of the mantissa part is not 0, not a number is detected; when the value of the exponent part is 0 and the value of the fraction part is also 0, zero is detected.

[0137] The results of multiplying and adding special values ​​are deterministic. For example, the result of multiplying any number by zero is zero; the result of multiplying infinity by zero is NaN; the result of adding zero to any number is the number itself; when a non-zero number is multiplied by infinity, the result is positive infinity or negative infinity, depending on the sign of the multiplier; the result of adding positive infinity or negative infinity to any positive or negative number is positive infinity or negative infinity, respectively; the result of adding positive infinity and negative infinity is NaN; the result of multiplying or adding any number to NaN is NaN.

[0138] Taking fp64 as an example, after execution to this point, we will get eight 65-bit tD1 values, that is, tD1 is 65 bits. Taking fp32 as an example, after execution to this point, we will get eight 37-bit tD1 values, that is, tD1 is 37 bits.

[0139] 2) Compress tD1 based on the Wallace tree to obtain two second data points. and

[0140] Since the Wallace tree adder only supports two's complement arithmetic, and the mantissa bits in tD1 are the two's complement of the mantissa of the processed data, tD1 can be compressed based on the Wallace tree to obtain two second data and

[0141] where the Wallace tree is as shown in Figure 4 and the adjacent two levels of the Wallace tree differ by 1 bit

[0142] 3) Add and to obtain the compression result

[0143] For example, if the processed data is fp64, the compression result is 65 bits; if the processed data is fp32, the compression result is 37 bits; if the processed data is int32, the compression result is 13 bits (where 5 bits are overflow bits)

[0144] 2. Perform leading zero detection on the compression result to obtain the accumulated result of this group of data

[0145] 1) Determine that the number of bits to be judged nd is the total number of bits of the compression result

[0146] 2) Determine the compression result as the fourth data tD4

[0147] 3) Judge whether the high nd bits of tD4 are all 0

[0148] 4) If all 0, when nd is the total number of bits of the compression result, obtain the fifth data tD5 = 0. When nd is not the total number of bits of the compression result, determine tD4 = tD4 << nd. If nd = 1, obtain tD5 = tD4. If nd ≠ 1, Repeat the steps of judging whether the high nd bits of tD4 are all 0 and the subsequent steps

[0149] If not all 0, when nd = 1, obtain tD5 = tD4. When nd ≠ 1, Repeat the steps of judging whether the high nd bits of tD4 are all 0 and the subsequent steps. Where is the ceiling function

[0150] 5) Expand tD5 to obtain the sixth data tD6

[0151] For example, fill 0s at the low positions of tD5 until the requirements are met to obtain tD6

[0152] 6) After performing floating-point special value detection on tD6, obtain the accumulated result of this group of data

[0153] The floating-point special value detection here is similar to the process of "obtaining tD1 after performing floating-point special value detection on tD3", so it will not be described in detail here. For details, please refer to the implementation process of obtaining tD1 after performing floating-point special value detection on tD3.

[0154] Taking the compression result as result 1, where all 65 bits in result 1 are 0, we determine nd = 65 and tD4 = result 1.

[0155] Since the high 65 bits of result 1 are all 0, nd = 65, meaning nd is the total number of bits in the compressed result. Therefore, the fifth data tD5 = 0 is obtained. Expanding tD5 yields the sixth data tD6. After performing floating-point special value detection on tD6, the cumulative result of this set of data is obtained.

[0156] Taking the compression result as result 2, and the 65 bits in result 1 not being all 0 as an example, we determine nd = 65 and tD4 = result 2.

[0157] If the high 65 bits of tD4 are not all zeros, then nd = 65 ≠ 1. Determine if the high 33 bits of tD4 are all 0.

[0158] If the high 33 bits of tD4 are all 0, then nd = 33, which is the total number of bits in the uncompressed result. Therefore, we determine that tD4 = tD4 << 33. Determine if the high 17 bits of tD4 are all 0s. If the high 33 bits of tD4 are not all 0s, then Determine if the high 17 bits of tD4 are all 0.

[0159] If the high 17 bits of tD4 are all 0, then nd = 17, which is the total number of bits in the uncompressed result. Therefore, we determine that tD4 = tD4 << 17. Determine if the high 9 bits of tD4 are all 0s. If the high 17 bits of tD4 are not all 0s, then Determine if the high 9 bits of tD4 are all 0.

[0160] If the high 9 bits of tD4 are all 0, then nd = 9, which is the total number of bits in the uncompressed result. Therefore, we determine that tD4 = tD4 << 9. Determine if the high 5 bits of tD4 are all 0s. If the high 9 bits of tD4 are not all 0s, then Determine if the high 5 bits of tD4 are all 0.

[0161] If the high 5 bits of tD4 are all 0, then nd = 5, which is the total number of bits in the uncompressed result. Therefore, we determine that tD4 = tD4 << 5. Determine if the high 3 bits of tD4 are all 0. If the high 5 bits of tD4 are not all 0, then Determine if the high 3 bits of tD4 are all 0.

[0162] If the high 3 bits of tD4 are all 0, then nd = 3, which is the total number of bits in the uncompressed result. Therefore, we determine that tD4 = tD4 << 3. Determine if the high 2 bits of tD4 are all 0s. If the high 3 bits of tD4 are not all 0s, then Determine if the high 2 bits of tD4 are all 0.

[0163] If the high two bits of tD4 are all 0, then nd = 2, which is the total number of bits in the uncompressed result. Therefore, we determine that tD4 = tD4 << 2. At this point, tD4 must be non-zero (because if it were 0, it would only mean that result 2 is all zeros, and tD5 = 0 was already obtained in the first judgment, so no further judgment would be made). The high 1 bit of tD4 is 0 (i.e., not all zeros), and nd = 1, so we get tD5 = tD4. We expand tD5 to get the sixth data tD6. After performing floating-point special value detection on tD6, we get the accumulated result of this set of data.

[0164] The aforementioned leading zero detection process can quickly and accurately determine tD6, thereby obtaining the cumulative result of this set of data.

[0165] In practice, step 103 is completed within three cycles. The first cycle determines the first data tD1 based on the type and the processed data from any group. The second cycle compresses tD1 using a Wallace tree to obtain two second data points. and Will and The results are added together to obtain the compressed result. The third cycle performs leading zero detection on the compressed result, obtaining the accumulated result of this set of data. This allows for continuous data processing, for example:

[0166] The first cycle involves fetching and parsing instructions.

[0167] In the second cycle, the first set of data is obtained.

[0168] In the third cycle, the first data tD1 of the first set of data is determined, and at the same time, the second set of data is acquired.

[0169] In the fourth cycle, the compression result of the first set of data is determined, the first data tD1 of the second set of data is determined, and the third set of data is acquired.

[0170] In the fifth cycle, the cumulative result of the first set of data is determined, the compression result of the second set of data is determined, the first data tD1 of the third set of data is determined, and the fourth set of data is acquired.

[0171] In the sixth cycle, the cumulative result of the second set of data is determined, the compression result of the third set of data is determined, the first data tD1 of the fourth set of data is determined, and the fifth set of data is acquired.

[0172] Execute sequentially until all processed data has been accumulated.

[0173] The solution in this embodiment can efficiently complete data accumulation through the above continuous processing.

[0174] This embodiment provides a data accumulation method, which obtains an instruction; the instruction includes an identifier for the data to be processed and the type of the data to be processed; the type is either a floating-point number or a fixed-point number; based on the identifier, a group of data is read sequentially; wherein, each group includes The number of data points to be processed is given by mC, where mC is the minimum processing size per run and nB is the number of bits in any given data set. The function is a floor function; for each group, Wallace tree-based compression is performed based on the type, and leading zero detection is performed on the compression result to obtain the accumulated result of the group of data. The method provided in this embodiment reads a group of data sequentially based on the identifier in the instruction; wherein, each group includes a preset number of processed data; for each group, Wallace tree-based compression is performed based on the type, leading zero detection is performed on the compression result to obtain the accumulated result of the group of data, which speeds up the data processing rate and improves processing efficiency.

[0175] Based on the same inventive concept of the data accumulation method, this embodiment provides an accumulator, see [link to accumulator]. Figure 5 The accumulator includes:

[0176] The acquisition module 501 is used to acquire instructions. Instructions include an identifier for the data to be processed and the type of the data. The type can be either a floating-point number or a fixed-point number.

[0177] The reading module 502 is used to read a group of data sequentially based on an identifier. Each group includes... The number of data points to be processed is given by mC, where mC is the minimum processing size per run and nB is the number of bits in any given data set. This is the floor function.

[0178] The accumulation module 503 is used to perform Wallace tree-based compression on each group read by the reading module 502, perform leading zero detection on the compression result, and obtain the accumulation result of the group of data.

[0179] The accumulation module 503 is used to determine the first data tD1 based on the type and the processed data of any group.

[0180] Compression of tD1 based on Wallace tree yields two second data points. and

[0181] Will and Add them together to get the compressed result.

[0182] Among them, the first data tD1 is determined based on the type and the processed data of any group, including:

[0183] If the type is a fixed-point number, then tD1 is determined to be the processing data for any group.

[0184] If the type is floating-point, then the data in any group is shifted according to the type to obtain tD1.

[0185] Among them, based on the type, the processed data of any group is shifted according to its order to obtain tD1, including:

[0186] Based on the type, extract the exponent and mantissa of each processed data in any group.

[0187] Determine the complement of each mantissa.

[0188] Based on the complements of each exponent and each mantissa, perform an order shift to obtain the third data tD3.

[0189] After performing floating-point special value detection on tD3, tD1 is obtained.

[0190] Specifically, based on the complements of each exponent and each mantissa, an order-aligned shift is performed to obtain the third data tD3, which includes:

[0191] Determine the maximum value E among the indices. max .

[0192] For any processed data, the docking shift is performed through the following steps to obtain the corresponding tD3:

[0193] Set the bit count value nC i =0.

[0194] Calculate E sequentially from the least significant digit to the most significant digit. max With E i The difference between each value Each time the difference nC is obtained i All increment by 1. Also, whenever nC... i When a non-zero segment value is reached, the difference between each bit in the current segment value (-1) and the previous segment value is shifted. according to The shift result of the previous segment is shifted to obtain tD3 corresponding to any processed data.

[0195] Where i is the data identifier being processed, and E i To process the exponent of data i, j is a bit identifier. For E max With E i The difference between the j-th positions. The first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1. v is the segment identifier, and the initial value of v is 1. If v = 1, the shift result of the previous segment is src. i It consists of the sign bit and the complement of the mantissa of the processed data i.

[0196] The segment values ​​are 0, 3, 6, and 11.

[0197] Whenever nC i When a non-zero segment value is reached, the difference between each bit in the current segment value and the target segment value is shifted. according to The shift result of the previous segment is shifted to obtain tD3 corresponding to any processed data, including:

[0198] When nC i When the value is 3, the difference between the 2nd and 0th digits is used to form the shift value. src i Move right This gives the shift result of the first segment.

[0199] When nC i When the value is 6, the difference between the 5th and 3rd digits is shifted. Will Move right The second segment is obtained by shifting the position.

[0200] When nC i When the value is 11, the difference between the 10th and 6th digits is shifted. like Then determine the data i to be processed Otherwise, determine that tD3 = 0 for the data i being processed.

[0201] The compression result is subjected to leading zero detection to obtain the cumulative result of this set of data, including:

[0202] The number of bits to be judged (nd) is the total number of bits in the compression result.

[0203] The compression result is designated as the fourth data point, tD4.

[0204] Determine if the high nd bits of tD4 are all 0.

[0205] If all bits are 0, then when nd is the total number of bits in the compressed result, the fifth data tD5 = 0 is obtained. When nd is the total number of bits in the uncompressed result, tD4 = tD4 << nd is determined. If nd = 1, then tD5 = tD4; if nd ≠ 1, then... Repeat the steps to determine whether the high nd bits of tD4 are all 0 and the subsequent steps.

[0206] If not all zeros, then when nd = 1, we get tD5 = tD4; when nd ≠ 1, Repeat the step of checking if the high nd bits of tD4 are all 0, and the subsequent steps. This is the floor function.

[0207] Expanding tD5 yields the sixth data tD6.

[0208] After performing floating-point special value detection on tD6, the cumulative result of this set of data is obtained.

[0209] This embodiment provides an accumulator that reads a set of data sequentially based on the identifier in the instruction; each set includes a preset number of processed data; for each set, Wallace tree-based compression is performed based on the type, leading zero detection is performed on the compression result, and the accumulator result of the set of data is obtained, which speeds up the data processing rate and improves processing efficiency.

[0210] Based on the same inventive concept of the data accumulation method, this embodiment provides a chip, which includes... Figure 5 The accumulator shown.

[0211] This accumulator is used to implement the data accumulation method shown in Figure 1.

[0212] Specifically, in the data accumulation method, an instruction is retrieved. This instruction includes an identifier for the data to be processed and the type of data to be processed. The type can be either a floating-point number or a fixed-point number.

[0213] Based on the identifier, read a set of data sequentially. Each set includes... The number of data points to be processed is given by mC, where mC is the minimum processing size per run and nB is the number of bits in any given data set. This is the floor function.

[0214] For each group, Wallace tree-based compression is performed based on the type. Leading zero detection is performed on the compression result to obtain the cumulative result of the data in that group.

[0215] Optionally, for any set, Wallace tree-based compression is performed based on type, including:

[0216] Based on the type and the processed data of any group, determine the first data tD1.

[0217] Compression of tD1 based on Wallace tree yields two second data points. and

[0218] Will and Add them together to get the compressed result.

[0219] Optionally, the first data tD1 is determined based on the type and the processed data of any group, including:

[0220] If the type is a fixed-point number, then tD1 is determined to be the processing data for any group.

[0221] If the type is floating-point, then the data in any group is shifted according to the type to obtain tD1.

[0222] Optionally, depending on the type, the processed data of any group is shifted to obtain tD1, including:

[0223] Based on the type, extract the exponent and mantissa of each processed data in any group.

[0224] Determine the complement of each mantissa.

[0225] Based on the complements of each exponent and each mantissa, perform an order shift to obtain the third data tD3.

[0226] After performing floating-point special value detection on tD3, tD1 is obtained.

[0227] Optionally, based on the complement of each exponent and each mantissa, an order-shifting operation is performed to obtain the third data tD3, including:

[0228] Determine the maximum value E among the indices. max .

[0229] For any processed data, the docking shift is performed through the following steps to obtain the corresponding tD3:

[0230] Set the bit count value nC i =0.

[0231] Calculate E sequentially from the least significant digit to the most significant digit. max With E i The difference between each value Each time the difference nC is obtained i All increment by 1. Also, whenever nC... iWhen a non-zero segment value is reached, the difference between each bit in the current segment value (-1) and the previous segment value is shifted. according to The shift result of the previous segment is shifted to obtain tD3 corresponding to any processed data.

[0232] Where i is the data identifier being processed, and E i To process the exponent of data i, j is a bit identifier. For E max With E i The difference between the j-th positions. The first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1. v is the segment identifier, and the initial value of v is 1. If v = 1, the shift result of the previous segment is src. i It consists of the sign bit and the complement of the mantissa of the processed data i.

[0233] Optionally, the segment values ​​are 0, 3, 6, and 11.

[0234] Whenever nC i When a non-zero segment value is reached, the difference between each bit in the current segment value and the target segment value is shifted. according to The shift result of the previous segment is shifted to obtain tD3 corresponding to any processed data, including:

[0235] When nC i When the value is 3, the difference between the 2nd and 0th digits is used to form the shift value. src i Move right This gives the shift result of the first segment.

[0236] When nC i When the value is 6, the difference between the 5th and 3rd digits is shifted. Will Move right The second segment is obtained by shifting the position.

[0237] When nC i When the value is 11, the difference between the 10th and 6th digits is shifted. like Then determine the data i to be processed Otherwise, determine that tD3 = 0 for the data i being processed.

[0238] Optionally, leading zero detection is performed on the compression result to obtain the cumulative result of the data set, including:

[0239] The number of bits to be judged (nd) is the total number of bits in the compression result.

[0240] The compression result is designated as the fourth data point, tD4.

[0241] Determine if the high nd bits of tD4 are all 0.

[0242] If all bits are 0, then when nd is the total number of bits in the compressed result, the fifth data tD5 = 0 is obtained. When nd is the total number of bits in the uncompressed result, tD4 = tD4 << nd is determined. If nd = 1, then tD5 = tD4; if nd ≠ 1, then... Repeat the steps to determine whether the high nd bits of tD4 are all 0 and the subsequent steps.

[0243] If not all zeros, then when nd = 1, we get tD5 = tD4; when nd ≠ 1, Repeat the step of checking if the high nd bits of tD4 are all 0, and the subsequent steps. This is the floor function.

[0244] Expanding tD5 yields the sixth data tD6.

[0245] After performing floating-point special value detection on tD6, the cumulative result of this set of data is obtained.

[0246] In a practical implementation, the chip can be a vector processor, with the accumulator serving as a functional unit within the vector processor.

[0247] In addition to an accumulator, a vector processor may also include a vector program control unit, other functional units, a register file, and scalar registers, such as... Figure 6 As shown.

[0248] In addition, the vector processor also includes: a private vector register for the vector interleaving unit and a private vector register for the vector access unit.

[0249] 1. Vector Program Control Unit

[0250] Vector program control unit, used for instruction fetching and instruction issuing.

[0251] That is, the vector program control unit is used to retrieve instructions, determine whether to execute them, and issue instructions to functional units based on the determination result.

[0252] The vector program control unit is also used to control command jumps.

[0253] The vector program control unit has scalar computation capabilities.

[0254] The vector program control unit interacts with the scalar register register.

[0255] In practical implementation, the vector program control unit is an instruction fetch and instruction issue unit. It fetches instructions from the cache based on the PC value, and after determining whether to execute, issues instructions to each functional unit based on the wait value (configured by the wait instruction). It also controls instruction jumps and has some scalar computation capabilities.

[0256] In addition, the vector program control unit is also used to receive start commands from other processing processors and start the vector processor. It also returns an indication signal to other processing processors indicating whether the vector processor has finished.

[0257] Taking other processing processors as scalar processors as an example, the vector program control unit receives the start command issued by the synchronization unit of the scalar processor, starts the vector processor to execute, and also returns an indication signal to the synchronization unit whether the vector processor execution has ended.

[0258] 2. Functional Units

[0259] Functional units are used to perform functional processing according to instructions.

[0260] For example, a functional unit receives instructions from a vector program control unit, processes the data accordingly, and outputs the processing results at the address specified in the instructions.

[0261] The functional units include: one or more vector operation units, one or more vector interleaving units, and one or more vector access units.

[0262] 1) Vector operation unit

[0263] Any vector operation unit is used to perform vector operations according to instructions.

[0264] For example, the vector operation unit is Figure 5 The accumulator shown.

[0265] 2) Vector interleaving unit

[0266] Any vector interleaving unit is used to perform data interleaving and logical processing according to instructions.

[0267] The vector interleaving unit is the control and data processing unit within the vector processor. It is responsible for interleaving data, supporting logical and some fixed-point and floating-point calculations. It also supports numerous customized instructions, including table lookup, horizontal calculation, sparse matrix calculation, precision conversion, and FIFO (First Input First Output) functions. It executes instructions such as data broadcasting, extraction, and internal interleaving.

[0268] Each vector interleaving unit has a set of private vector registers; therefore, the private vector registers of each vector interleaving unit correspond one-to-one with the vector interleaving units.

[0269] 3) Vector Access Unit

[0270] Each vector access unit is used to perform multi-mode memory access, address calculation, and scalar calculation according to instructions.

[0271] The vector access unit is the memory access unit within the vector processor, primarily responsible for reading / writing instructions and various scalar calculations.

[0272] The read / write instructions support multiple memory access modes, such as row mode, column mode, discrete mode, extended mode, and accumulation mode.

[0273] It supports multiple parameter configurations, with a maximum read / write instruction data width of up to 1024 bits. It executes instructions such as address calculation, load / store, etc.

[0274] All vector access units share a set of private vector registers, so the private vector registers of a vector access unit are shared by multiple vector access units.

[0275] 3. Register file stack

[0276] The register file is used to receive and return data after read / write requests. The data is rearranged and then returned. It interacts with functional units for read / write operations. The configuration registers of the vector program control unit are configured using data within the register file.

[0277] The register file stack is a general-purpose vector register stack, which is the main storage unit within the vector processor. It is responsible for receiving read and write requests and returning data. In some functions, it can rearrange the data before returning it to the requesting module.

[0278] The register file stack interacts with functional units within the vector processor (such as the floating-point multiply-accumulate subunit, floating-point arithmetic subunit, floating-point multiply-accumulate subunit, and tensor multiplication subunit), and also supports configuring the instruction fetch unit configuration register using data within the register file stack.

[0279] The register file is also used to write data to other processing units. It receives status messages from other processing units indicating whether the data has been written.

[0280] Taking other processing processors as examples, such as scalar processors, the synchronization unit of a scalar processor can write data to the register file, and the register file can also receive status information from the synchronization unit of the scalar processor to query whether the data has been written.

[0281] The depth of the register file heap is configurable.

[0282] In addition, read FIFO units and write FIFO units are set up between the vector processor and other computing processors.

[0283] The vector program control unit and other arithmetic processors both perform read operations on the read FIFO unit and write operations on the write FIFO unit.

[0284] Other processing units perform read or write operations on the vector register.

[0285] Taking other processing processors as examples, such as scalar processors, there are read FIFO and write FIFO units between the scalar processor and the vector processor for transmitting data. The scalar processor and the vector program control unit can perform read operations or write operations on the read and write FIFOs.

[0286] Meanwhile, the synchronization unit of the scalar processor can perform read or write operations on the scalar registers of the vector processor.

[0287] In addition, in practical implementations, this chip can also be a high-performance processor.

[0288] This high-performance processor includes scalar processors and vector processors.

[0289] The connection between scalar processors and vector processors can be as follows: Figure 7 As shown.

[0290] In this configuration, scalar processors and vector processors share memory. Furthermore, vector processors can only access memory and are executed solely by scalar processors.

[0291] A connection is established between scalar processors and vector processors. For example, scalar processors and vector processors can be connected via a dedicated instruction channel.

[0292] In addition, a high-performance processor may include two registers: one for the scalar processor and the other for the vector processor. The vector processor can read and write its corresponding register, while the scalar processor can read and write both its corresponding register and the register corresponding to the vector processor.

[0293] Scalar processors can read and write the registers of vector processors.

[0294] The scalar processor establishes a connection with global memory.

[0295] (a) Scalar Processor

[0296] See Figure 8The scalar processor may include: an instruction fetch unit, a register renaming unit, an arithmetic reserved stack unit, a memory reserved stack unit, a scalar arithmetic unit, a memory access unit, a program control unit, a synchronization unit, a pipeline control unit, a register file unit, and a special vector register file unit.

[0297] In addition, a scalar processor may include one or more other units, such as one or more other functional modules, one or more instruction caches, one or more data stores, one or more special vector registers, one or more status flag registers, etc.

[0298] 1. Instruction Fetch Unit

[0299] The instruction fetch unit is used to fetch and dispatch instructions.

[0300] Specifically, the instruction fetch unit generates an instruction fetch request address, outputs the fetch request address to the instruction cache for instruction fetching, receives instructions from the instruction cache, and stores them in the data storage. Each cycle, it sequentially reads qualified instructions from the data storage, decodes and performs relevant checks on the read instructions, and then dispatches the checked instructions sequentially.

[0301] For example, the instruction fetch unit generates an instruction fetch request address and outputs it to the instruction cache for instruction fetching. It also receives instructions from the instruction cache and stores them in the data storage. In each cycle, it sequentially searches for one or more instructions from the qualified instructions, performs decoding and related checks, and dispatches the qualified instructions in sequence. At most, it dispatches one program control unit instruction and one synchronization unit instruction at a time. In addition, it can dispatch one or more scalar arithmetic unit instructions and one or more memory access unit instructions at a time.

[0302] 2. Register renaming unit

[0303] The register renaming unit is used to receive instructions dispatched by the instruction fetch unit and to rename registers.

[0304] Specifically, the register renaming unit receives and stores instructions dispatched by the instruction fetch unit, renames special vector registers, performs instruction conditional decoding, and generates pipeline congestion signals. It receives data from one or more of the following: the scalar arithmetic unit, memory access unit, program control unit, synchronization unit, special vector registers, condition registers, and flag registers, and writes it back. It sends instructions to the arithmetic reserved stack unit, and stores them in one or more of the following: the program control unit, and the synchronization unit.

[0305] For example, the register renaming unit in a scalar processor is used to receive instructions dispatched by the instruction fetch unit and rename registers and special vector registers, decode instruction conditions, generate pipeline congestion signals, and simultaneously receive data from execution units (such as scalar arithmetic units, memory access units, program control units, and synchronization units) to write back registers, special vector registers, condition registers, and status flag registers and write them back to the corresponding registers.

[0306] Scalar processors support out-of-order write-back, resulting in high execution efficiency. They also distribute instructions to the arithmetic stack, storage stack, program control unit, or synchronization unit.

[0307] The register renaming unit bandwidth can be 6 bits, during which multiple (e.g., 4) input instructions can be valid at the same time.

[0308] There can be multiple condition registers, which are located in the register renaming unit.

[0309] The instructions for the scalar arithmetic unit and memory access unit support reading and writing condition registers.

[0310] The instructions for the synchronization unit support reading the condition register.

[0311] The program control unit's jump and function call instructions support reading the condition register.

[0312] When an instruction enters the condition register, the pipeline will be blocked if there are unexecuted instructions in the condition register.

[0313] In other words, the condition register is not renamed; when a read / write request occurs, a dispatch blocking mechanism is triggered to wait. The conditions register read / write rules are as follows:

[0314] ●Reading rules:

[0315] (1) All instructions in the scalar arithmetic unit, memory access unit, and synchronization unit support conditional execution and require reading the value of the condition register.

[0316] (2) The scalar arithmetic unit also supports read condition register instruction operations.

[0317] (3) The jump and function call instructions of the program control unit support reading condition register operations.

[0318] ●Write the rules:

[0319] (1) The scalar arithmetic unit supports the write condition register instruction.

[0320] (2) Scalar arithmetic unit logic and comparison instructions support the option to write to the condition register.

[0321] When a previously issued instruction to write to the condition register has not yet finished executing, and another instruction to read or write to the same condition register enters, the pipeline becomes congested, generating a condition execution block signal, and waits for the previous condition register to finish writing.

[0322] In addition, the register renaming unit includes one or more physical registers and one or more logical registers.

[0323] Each of the physical registers can be one of the following: a vector physical register, a condition register, or a flag register.

[0324] Any logic register can be one of the following: read-only register, vector logic register.

[0325] For example, a register renaming unit contains one or more physical registers, such as multiple 512-bit special vector registers, multiple condition registers, and a status flag register.

[0326] Among them, the special vector register is renamed, while the condition register and status flag register are not renamed.

[0327] There are multiple logic registers, such as read-only registers and multiple vector logic registers.

[0328] In addition, the mapping relationship between logical registers and physical registers is maintained by a register mapping table. The mapping relationship between vector logical registers and vector physical registers is maintained by a special vector register mapping table.

[0329] 1) Register Map Table

[0330] Initially, the mapped physical registers for all entries corresponding to logical register indices in the register map are all 0. When an instruction is executed, or when an interrupt occurs, the logical register allocated to the relevant physical register is determined, and the mapping of the entries corresponding to the allocated logical register indices in the register map is updated to the identifier of the relevant physical register.

[0331] For example, a register map table with a depth of 32 bits and a width of 6 bits stores the mapping relationship between all logical registers and all physical registers. Initially, the register map table is invalid, and all entries mapping physical registers are all 0. When a physical register is allocated to a logical register, the entry in the register map table corresponding to the logical register index is changed to the ID of that physical register.

[0332] It should be noted that the register map is only updated when an instruction is actually executed. If the conditional execution instruction is not executed, the register map will not be updated. In addition, the register map will not be updated when a jump occurs. However, when an interrupt occurs, the interrupt return address must update the register map to ensure that the interrupt can return normally.

[0333] 2) Special Vector Register Mapping Table

[0334] Initially, the mapped vector physical registers for all entries corresponding to vector logical register indices in the special vector register map are all 0. When an instruction is executed, the vector logical register allocated to the relevant vector physical register is determined, and the mapping of the entries corresponding to the allocated vector logical register indices in the special vector register map is updated to the identifier of the relevant vector physical register.

[0335] For example, the special vector register map table, with a depth of 4 bits and a width of 3 bits, stores the mapping relationship between all vector logic registers and all vector physical registers. Initially, the special vector register map table is invalid, and all entries mapping to vector physical registers are 0. When a vector physical register is allocated to a vector logic register, the entry in the special vector register map table corresponding to the vector logic register index is changed to the ID of that vector physical register.

[0336] It should be noted that the special vector register mapping table is only updated when the instruction is actually executed. If the conditional execution instruction is not executed, the special vector register mapping table will not be updated. In addition, the special vector register mapping table will not be updated when a jump occurs.

[0337] 3. Operations retain stack units

[0338] The operation-reserved stack unit is the issue queue of scalar operation units.

[0339] The arithmetic stack is used to receive instructions, dispatch and rename information from the register renaming unit and push them into the queue. Ready instructions are popped into the scalar arithmetic unit for execution.

[0340] The stack space is reserved for operations and is also used to decode input instructions and store instruction type information.

[0341] In other words, the arithmetic reserve stack is the dispatch queue of the scalar arithmetic unit. The arithmetic reserve stack receives instructions and related dispatch and renaming information from the register renaming unit and pushes them into the queue. It also pops ready instructions onto the scalar arithmetic unit for execution. The arithmetic reserve stack decodes the input instructions and stores the instruction type information.

[0342] In practice, the depth of the operation reserve stack can be flexibly adjusted, such as a depth of 8. Multiple scalar operation units share one operation reserve stack unit.

[0343] The rules for issuing and receiving instructions that reserve stack space are as follows:

[0344] (1) The output of the register renaming unit enters the operation retention stack unit.

[0345] (2) When there is any free scalar arithmetic unit, it will fetch instructions and operands from the arithmetic reserve stack and execute them.

[0346] (3) The principle of fetching instructions from the operation reserved stack is to fetch executable instructions that can be sent from the operation reserved stack in the order from front to back.

[0347] (4) Whether it is possible to send a value based on the values ​​of all source registers or special vector registers or condition registers and status flag registers is ready to be determined.

[0348] (5) If there are multiple instructions that can be sent, send the oldest instruction first according to the order of instructions.

[0349] (6) If any scalar arithmetic unit is blocked, it can no longer receive new instructions.

[0350] (7) If the instruction previously sent to any scalar arithmetic unit was a division instruction, a new division instruction can only be sent to it after the division result is calculated and the calculation completion En signal is returned.

[0351] 4. Store and retain stack units

[0352] The storage-reserved stack unit is the issue queue for memory access units.

[0353] The storage reserve stack unit is used to receive instructions and register renaming information from the register renaming unit and push them into the queue.

[0354] The storage reserve stack unit is also used to send a read request to the register renaming unit when the instruction address register is ready, and to save the read address operand.

[0355] The register renaming unit is also used to calculate the address after the instruction has obtained the address, decode the address, and save the decoded information.

[0356] The register renaming unit is also used to detect when the existence source register of any instruction is ready and the address decoding is complete, and then send it to the memory access unit for execution.

[0357] In practice, the depth of the memory reservation stack unit can be flexibly adjusted, such as 16. Multiple memory access units share one memory reservation stack unit. The memory reservation stack unit is the issue queue for memory access units. The memory reservation stack unit receives instructions and register renaming information from the register renaming unit and pushes them into the queue. When the instruction address register in the memory reservation stack unit is ready, a read request is sent to the register renaming unit, and the read address operand is saved to the queue. After the instruction in the memory reservation stack unit obtains the address, it can calculate the address and decode the address, saving the resulting decoding information to the queue. When the source register of an instruction (such as a write instruction) is ready in the memory reservation stack unit and the address decoding is complete, it can be issued to the memory access unit for execution. Before issuance, a series of checks are performed, such as address type checks, address comparison checks, and address forward checks.

[0358] The rules for storing and reserving stack cells for sending and receiving instructions are as follows:

[0359] (1) The output of the register renaming unit enters the memory retention stack unit.

[0360] (2) Once the source operand for the calculated address is ready, calculate the memory access address and store it in the memory reservation stack.

[0361] (3) Address-independent instructions: can be out of order. The out-of-order rules are: read instructions after read instructions, write instructions after read instructions, and read instructions after write instructions can all be sent out of order. Write instructions after write instructions need to be ordered (cannot be sent to different memory access units at the same time). Even if the address-independent write instructions are written after write instructions, the order still needs to be maintained.

[0362] (4) Address-related instructions: The order of read instruction followed by write instruction, write instruction followed by read instruction, write instruction followed by write instruction, and read instruction followed by read instruction must be guaranteed.

[0363] (5) When addresses are unrelated but are located in the same memory space as all instructions that have not been successfully sent (i.e. instructions on the way that have not been sent to the destination, including those at the memory access unit level and the memory access unit output level), they can be sent out of order to the same memory access unit, but they cannot be sent to two or more memory access units.

[0364] (6) Only one memory access instruction located in the same memory space but with unrelated addresses can be sent at the same time. Two or more memory access units cannot be sent at the same time.

[0365] (7) Address correlation judgment principle: whether addresses are related is determined by whether they are located in different storage spaces. If they are located in the same storage space, the address correlation is determined by the data granularity.

[0366] 5. Scalar Operation Unit

[0367] In a practical implementation, there can be one or more scalar operation units.

[0368] For example, a scalar processor includes two scalar arithmetic units, namely scalar arithmetic unit 0 and scalar arithmetic unit 1.

[0369] The scalar arithmetic unit is used to receive instructions and data sent by the arithmetic storage stack unit, perform operations on the data based on the instructions, and write the operation results back to the register renaming unit.

[0370] The scalar arithmetic unit is the computational unit of the scalar processor. It can perform various types of fixed-point and floating-point operations, such as addition, subtraction, multiplication, division, logical operations, comparison operations, and shifting. It receives instructions and data sent from the arithmetic stack, performs the operations, and writes the results back to the register file of the register renaming unit or the special vector register file.

[0371] The following are some example instructions. In actual implementation, the instructions are not limited to these, nor is it limited to including all of them.

[0372] Instructions at execution level 1 include: fixed-point addition and subtraction, logical instructions, shift instructions, fixed-point and floating-point comparison instructions, read / write Flag instructions, fixed-point and floating-point max / min instructions, ABS instructions, bit reversal instructions, selection instructions, special vector register dispatch instructions, read special vector register instructions, Byte reversal instructions, Merge instructions, immediate assignment instructions, FirstOne instructions, CRC instructions, floating-point classification instructions, floating-point partial field extraction instructions, and Rounding instructions.

[0373] Instructions with an execution level of three include: fixed-point multiplication instructions, fixed-to-floating-point conversion instructions, bit filtering instructions, count instructions, and floating-point addition and subtraction instructions.

[0374] Instructions that support bypass include: selection instructions, fixed-point addition and subtraction instructions, shift instructions, immediate assignment instructions, ABS instructions, logical instructions, comparison instructions, and maximum and minimum instructions.

[0375] The execution cycle of a division instruction is indeterminate and depends on the data of the divisor and dividend. Upon completion, the instruction generates a DivEn instruction, indicating its completion and outputting the result to the register file. No new division instructions can be input during the execution of a division instruction, but other scalar computation unit instructions can be input. The output result of the division is multiplexed with the output port of the first-stage pipeline. When the output port of the first-stage pipeline is not used by other scalar computation unit instructions, the division outputs its result and simultaneously outputs the DivEn flag. This DivEn flag is output to the arithmetic reserve stack, indicating that Div instructions can continue to be output to the current scalar computation unit.

[0376] 6. Memory access unit

[0377] In a practical implementation, there can be one or more memory access units.

[0378] For example, a scalar processor includes two memory access units, namely memory access unit 0 and memory access unit 1.

[0379] The memory access unit is used to receive instructions, data, and register information sent by the memory-reserved stack unit, and to read and write the data based on the instructions and register information.

[0380] The memory access unit is a functional module that executes memory access-related instructions in a scalar processor. The memory access unit receives instructions and data, as well as register-related information, from the memory-reserved stack. It executes the instructions accordingly, interacts with other units for data reading and writing, and writes data back to the register renaming unit for read and write instructions. This includes register-level read and write instructions, including 8-bit, 16-bit, 32-bit, 64-bit, or other bit granularities, as well as vector-level read and write instructions. Vector granularities include 128-bit, 256-bit, 512-bit, or other bit granularities. Different instructions have different processing times.

[0381] In addition, the memory access unit is responsible for providing the number of instructions required by the FENCE, and the memory access unit interacts with the memory reservation stack unit to complete the data storage configuration.

[0382] 7. Program Control Unit

[0383] In practice, there is only one program control unit.

[0384] The program control unit receives instructions and data from the register renaming unit, processes the data based on the instructions, and outputs the processing results.

[0385] The program control unit is a functional module that executes instructions related to the execution order of the scalar processor's control program. The program control unit receives instructions and data from the register renaming unit, processes the data accordingly, and outputs the processing results to other modules of the scalar processor. Different instructions have different processing time cycles.

[0386] The program control unit is responsible for controlling the direction of program execution (such as stopping, interrupting, jumping, and function calling), involving the execution of related instructions and the reading and writing control of configuration information; the program control unit is responsible for the configuration and prefetching operation of the instruction cache, as well as the FENCE operation; the program control unit is responsible for the reading, writing and control of the counter, as well as the reading and writing of some other control information, etc.

[0387] 8. Synchronization Unit

[0388] In practice, there is only one synchronization unit.

[0389] The synchronization unit is used for synchronizing the scalar processor and the vector processor.

[0390] like Figure 9 As shown, the synchronization unit establishes communication connections with the pipeline control unit, register renaming unit, program control unit, and vector processor.

[0391] The instructions for the synchronization unit come from the register renaming unit, and the reading and writing of data in the synchronization unit are all done in interaction with the register renaming unit.

[0392] The synchronization unit is used to receive the pause signal sent by the pipeline control unit and send the execution-level pause signal generated during communication with the vector processor to the pipeline control unit in order to generate the execution pause signal of the scalar processor.

[0393] The synchronization unit is used to generate instructions and transmit them to the program control unit.

[0394] In other words, the synchronization unit is the unit that synchronizes the scalar processor and the vector processor. It receives instructions and data from the register renaming unit, reads data from the vector processor and writes it back to the register file, and reads data from the register file unit or special vector register file unit and sends it to the vector processor. It is responsible for the startup and status query of the vector processor, such as querying the read and write FIFO (First Input First Out) in the vector program control unit of the vector processor, the configuration of the register file, the read or write of scalar registers, the status query of the register file, reading the FIFO depth, reading the startup vector processor instruction counter, etc., and providing synchronization unit instruction information to the program control unit.

[0395] The synchronization unit interacts with the pipeline control unit, register renaming unit, and program control unit within the scalar processor, as well as with the external vector processor, scalar processor, and vector processor transfer queue module. Synchronization unit instructions originate from the register renaming unit, and data reads and writes require interaction with this unit. It receives blocking signals from the pipeline control unit, generates its own execution-level blocking signal when communicating with the vector processor, and sends it to the pipeline control unit to generate the ExeStall signal affecting the entire scalar processor. The synchronization unit generates the instructions to be executed in the next cycle and transmits them to the program control unit for use by the program control unit's counter instructions. The synchronization unit interacts with the vector processor, including but not limited to: configuring the register file using special vector registers or registers, reading and writing scalar registers, and querying the write status of the register file. The scalar processor interacts with the scalar processor and vector processor transfer queue module, including but not limited to: starting the vector processor, querying the vector processor status, reading and writing FIFO data in the vector processor's instruction fetch unit, reading the FIFO depth, and reading the start vector processor instruction counter.

[0396] Therefore, in a specific implementation, the synchronization unit can have the following functions (it should be noted that the following functions are only examples, and other functions may also be available. This embodiment and subsequent embodiments do not limit the specific functions of the synchronization unit):

[0397] The Startup Vector Processor function is used to start the vector processor, including immediate start and register start, such as pipeline waiting until the start is successful, or writing the result of the start success or failure back to the destination register.

[0398] The query vector processor execution status function supports option B.

[0399] The read / write FIFO function is located in the instruction fetch unit of the vector processor. For example, the FIFO has a bit width of 32 bits. Reading / writing the FIFO will wait until success, or the result of reading / writing the FIFO will be written back to the register whether it is successful or not.

[0400] Write register file stack functionality, including special vector register write or register write.

[0401] The function allows reading and writing scalar registers, including reading and writing immediate indexes or register indexes.

[0402] The function queries the register file stack write-back status. If necessary, it waits until all writes to the register file stack are complete, or returns the result of whether the write to the register file stack is complete to the register.

[0403] When the relevant operation is not completed, a blocking signal is generated by the synchronization unit itself, and the unit blocks and waits. This signal is then sent to the pipeline control unit to generate a pipeline blocking signal.

[0404] A FIFO (such as a 32-bit deep FIFO) can be added between the scalar processor and the vector processor to store the vector processor start request. The read / write FIFO previously located in the vector processor is moved to the scalar processor and vector processor transfer queue module. The scalar processor and vector processor transfer queue module unit implements the functions of starting the vector processor, querying the vector processor execution status, reading and writing the FIFO, reading the FIFO depth, and reading the start vector processor instruction counter. The conditions for successfully starting the vector processor are that the start vector processor FIFO is not full and the query of the vector processor execution status is successful. The conditions for the vector processor status to stop are that the vector processor has finished executing and the start vector processor FIFO is empty.

[0405] 9. Production line control unit

[0406] The pipeline control unit is used to generate a pause signal for the pipeline and / or to generate start and stop signals for the scalar processor.

[0407] The pipeline control unit is the pipeline control unit of the scalar processor. It is connected to various units inside the scalar processor and is responsible for generating pipeline blocking signals, such as blocking in normal operation mode and blocking in debug mode.

[0408] The pipeline control unit also communicates with the communication and synchronization unit to generate signals for starting and stopping the scalar processor.

[0409] In addition, scalar processors can also perform conditional execution decoding in practical applications. For example, when performing conditional execution decoding, a scalar processor checks the preset bits of the instruction to determine the execution condition. If the condition is met, a valid instruction is output; otherwise, a null instruction is output. Here, a null instruction represents an empty instruction or an invalid instruction.

[0410] If a read / write operation is active in the condition register, pipeline blocking is triggered, waiting for the condition register write operation to complete before the read operation can proceed. There is no bypass for condition register reads and writes.

[0411] Taking two condition registers, namely condition register 0 and condition register 1, with the preset bits [29:28] as an example, when the scalar processor performs conditional execution decoding, it judges the execution conditions of the input instruction based on the [29:28] bits of the instruction set encoding. If the conditions are met, a valid instruction is output; otherwise, a null instruction is output.

[0412] In this instruction, bits [29:28] being 00 indicates that condition register 0 is 1 and the instruction is executed; bits [29:28] being 01 indicates that condition register 1 is 1 and the instruction is executed; bits [29:28] being 10 indicates that condition register 0 is executed; and bits [29:28] being 11 indicates that the instruction is executed unconditionally. If the condition is not met, the instruction is invalid and an empty instruction is output.

[0413] If there is a read / write dependency in the condition register, pipeline blocking is triggered, and the read operation is performed only after the condition register has been written. There is no bypass for condition register read / write operations.

[0414] (II) Vector Processor

[0415] The accumulator is a functional unit in a vector processor.

[0416] In a practical implementation, this chip can be a vector processor, with the accumulator serving as a functional unit within it. Besides the accumulator, a vector processor may also include a vector program control unit, other functional units, a register file, and scalar registers, such as... Figure 6 As shown.

[0417] In addition, the vector processor also includes: a private vector register for the vector interleaving unit and a private vector register for the vector access unit.

[0418] This embodiment provides a chip in which the accumulator reads a group of data sequentially based on the identifier in the instruction; wherein each group includes a preset number of processed data; for each group, Wallace tree-based compression is performed based on the type, leading zero detection is performed on the compression result, and the accumulation result of the group of data is obtained, thereby speeding up the data processing rate and improving processing efficiency.

[0419] Based on the same inventive concept of the data accumulation method, this embodiment provides an electronic device, which includes a chip.

[0420] The chip includes Figure 5 The accumulator shown.

[0421] This accumulator is used to implement the data accumulation method shown in Figure 1.

[0422] Specifically, in the data accumulation method, an instruction is retrieved. This instruction includes an identifier for the data to be processed and the type of data to be processed. The type can be either a floating-point number or a fixed-point number.

[0423] Based on the identifier, a set of data is read sequentially. Each set includes... The number of data points to be processed is given by mC, where mC is the minimum processing size per run and nB is the number of bits in any given data set. This is the floor function.

[0424] For each group, Wallace tree-based compression is performed based on the type. Leading zero detection is performed on the compression result to obtain the cumulative result of the data in that group.

[0425] Optionally, for any set, Wallace tree-based compression is performed based on type, including:

[0426] Based on the type and the processed data of any group, determine the first data tD1.

[0427] Compression of tD1 based on Wallace tree yields two second data points. and

[0428] Will and Add them together to get the compressed result.

[0429] Optionally, the first data tD1 is determined based on the type and the processed data of any group, including:

[0430] If the type is a fixed-point number, then tD1 is determined to be the processing data for any group.

[0431] If the type is floating-point, then the data in any group is shifted according to the type to obtain tD1.

[0432] Optionally, depending on the type, the processed data of any group is shifted to obtain tD1, including:

[0433] Based on the type, extract the exponent and mantissa of each processed data in any group.

[0434] Determine the complement of each mantissa.

[0435] Based on the complements of each exponent and each mantissa, perform an order shift to obtain the third data tD3.

[0436] After performing floating-point special value detection on tD3, tD1 is obtained.

[0437] Optionally, based on the complement of each exponent and each mantissa, an order-shifting operation is performed to obtain the third data tD3, including:

[0438] Determine the maximum value E among the indices. max .

[0439] For any processed data, the docking shift is performed through the following steps to obtain the corresponding tD3:

[0440] Set the bit count value nC i =0.

[0441] Calculate E sequentially from the least significant digit to the most significant digit. max With E iThe difference between each value Each time the difference nC is obtained i All increment by 1. Also, whenever nC... i When a non-zero segment value is reached, the difference between each bit in the current segment value (-1) and the previous segment value is shifted. according to The shift result of the previous segment is shifted to obtain tD3 corresponding to any processed data.

[0442] Where i is the data identifier being processed, and E i To process the exponent of data i, j is a bit identifier. For E max With E i The difference between the j-th positions. The first segment value is 0. If the current segment value is the first non-zero value, the target segment value is 0. If the current segment value is not the first non-zero value, the target segment value is the previous segment value of the current segment value + 1. v is the segment identifier, and the initial value of v is 1. If v = 1, the shift result of the previous segment is src. i It consists of the sign bit and the complement of the mantissa of the processed data i.

[0443] Optionally, the segment values ​​are 0, 3, 6, and 11.

[0444] Whenever nC i When a non-zero segment value is reached, the difference between each bit in the current segment value and the target segment value is shifted. according to The shift result of the previous segment is shifted to obtain tD3 corresponding to any processed data, including:

[0445] When nC i When the value is 3, the difference between the 2nd and 0th digits is used to form the shift value. src i Move right This gives the shift result of the first segment.

[0446] When nC i When the value is 6, the difference between the 5th and 3rd digits is shifted. Will Move right The second segment is obtained by shifting the position.

[0447] When nC i When the value is 11, the difference between the 10th and 6th digits is shifted. like Then determine the data i to be processed Otherwise, determine that tD3 = 0 for the data i being processed.

[0448] Optionally, perform leading zero detection on the compression result to obtain the accumulated result of this group of data, including:

[0449] Determine that the number of judgment bits nd is the total number of bits of the compression result.

[0450] Determine the compression result as the fourth data tD4.

[0451] Judge whether the high nd bits of tD4 are all 0.

[0452] If all are 0, when nd is the total number of bits of the compression result, obtain the fifth data tD5 = 0. When nd is not the total number of bits of the compression result, determine tD4 = tD4 << nd. If nd = 1, then obtain tD5 = tD4. If nd ≠ 1, then Repeat the steps of judging whether the high nd bits of tD4 are all 0 and the subsequent steps.

[0453] If not all are 0, when nd = 1, obtain tD5 = tD4. When nd ≠ 1, Repeat the steps of judging whether the high nd bits of tD4 are all 0 and the subsequent steps. Among them, is the ceiling function.

[0454] Expand tD5 to obtain the sixth data tD6.

[0455] After performing floating-point special value detection on tD6, obtain the accumulated result of this group of data.

[0456] This embodiment provides an electronic device. The accumulator in the electronic device sequentially reads a group of data based on the identifier in the instruction; where each group includes a preset number of processed data; for each group, perform compression based on Wallace tree according to the type, perform leading zero detection on the compression result, and obtain the accumulated result of this group of data, which speeds up the data processing rate and improves the processing efficiency.

[0457] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of the present application can be implemented in various computer languages, for example, object-oriented programming languages such as Java and interpreted scripting languages such as JavaScript, etc.

[0458] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0459] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0460] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0461] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0462] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A data accumulation method characterized by comprising: The method comprises: obtaining an instruction; the instruction comprises identification of processing data and a type of the processing data; the type is a type of floating point number or a type of fixed point number; Based on the identification, a set of data is read in turn; wherein each set includes a processing data, a single minimum processing data bit number, a bit number of any processing data, a floor function; for each group of processing data, performing Wallace tree-based compression based on the type, performing leading zero detection on a compression result, and obtaining an accumulated result of the group of data.

2. The method of claim 1, wherein, For any group of processing data, the Wallace tree-based compression based on the type comprises: determining first data from the type and the processing data of any of the groups ; Wallace tree-based compressed to obtain 2 second data and ; The and are added to obtain the compression result.

3. The method of claim 2, wherein, determining first data according to the type and the any group of processing data , comprising: if the type is a fixed point type, then determining processing data for any group; if the type is a floating point type, then, according to the type, the processing data of the any group is subjected to a scale shift to obtain .

4. The method of claim 3, wherein, The processing data of the any group is subjected to a stage shift according to the type, obtaining , comprising: according to the type, extracting an exponent and a mantissa of each processing data in the any group of processing data; determining a complement of each mantissa; According to the complements of the indices and the tail numbers, the third data is obtained by performing a shift of order ; right After performing floating-point special value detection, we obtain .

5. The method of claim 4, wherein, The third data is obtained by performing a shift according to the exponent and the complement of the mantissa , comprising: determining the maximum value in each index ; For any processed data, the interface shift is performed by the following steps to obtain the corresponding : Setting bit count value ; from low to high bit by bit and the difference between each bit , whenever a bit difference is obtained all plus 1; at the same time, whenever a non-zero segment value is reached, the difference between each bit of the current segment value-1 and the previous segment value is formed into a shift number , according to the shift result of the previous segment is shifted to obtain the corresponding to any processing data in, To process data identification, To process data The index, For bit identifier, for and Between The difference between the bits; the first segment value is 0, if the current segment value is the first non-zero value, then the target segment value is 0, if the current segment value is not the first non-zero value, then the target segment value is the previous segment value of the current segment value + 1; For segmentation identification, The initial value is 1, if Then the shift result of the previous segment The sign bit and the data processing The two's complement of the mantissa.

6. The method of claim 5, wherein, the segment value is 0, 3, 6, or 11; Said each time When reaching a non-0 segment value, the difference between each bit of the current segment value and the target segment value forms a shift number According to The shift result of the previous segment is shifted to obtain the corresponding , comprising: When the difference between the 2 and 0 bits forms a shift number , right shift by the shift number to obtain the shifted result of the first segment ; When the difference between 5 and 3 is formed into a shift number , right shift by 2 bits, obtaining the shift result of the second segment ; When the difference between 10 and 6 is formed into a shift number , if , it is determined to process data corresponding to , otherwise, it is determined to process data corresponding to .

7. The method of claim 1, wherein, the leading zero detection on the compression result to obtain the accumulated result of the group of data comprises: Determining the number of bits Total number of bits for the compressed result; determining the compression result as fourth data ; determining whether the high bits are all 0; If all zeros, then in When the total number of bits in the compression result is equal to the fifth data, the fifth data is obtained. ;exist When determining the total number of bits in the uncompressed result. ,like Then we get ,like ,but Repeatedly execute the judgment of high The steps to check if all bits are 0 and subsequent steps; If not all 0, then at time, get , at time, repeat the step of judging whether the high bits are all 0 and the subsequent steps S5, S6; wherein, is a rounding-up function; S5: To extend the sixth data ; S6: Perform floating-point special value detection on the data set to obtain the accumulated result of the data set. After floating-point special value detection, the accumulated result of the data set is obtained.

8. An accumulator characterized in that, the accumulator comprises: an obtaining module, configured to obtain an instruction; the instruction comprises identification of processing data and a type of the processing data; the type is a type of floating point number or a type of fixed point number; A reading module is configured to read a group of data in sequence based on the identifier, wherein each group includes a processing data, a single minimum processing data bit number, a bit number of any processing data, a floor function; an accumulating module, configured to, for each group read by the reading module, perform Wallace tree-based compression based on the type, perform leading zero detection on a compression result, and obtain an accumulated result of the group of data.

9. A chip, characterized by comprise: the accumulator of claim 8; the accumulator is used to implement the data accumulation method of any one of claims 1-7.

10. An electronic device, comprising: comprise: the chip of claim 9.

Images