Software upgrading method and device, equipment and storage medium

Abstract

The embodiment of the invention relates to a software upgrading method and device, equipment and a storage medium, and the method comprises the steps: receiving an upgrading initialization instruction, and detecting whether the upgrading initialization instruction meets a first preset requirement or not; under the condition that the upgrade initialization instruction meets a first preset requirement, receiving an erase instruction, and detecting whether the erase instruction meets a second preset requirement or not; under the condition that the erasure instruction meets a second preset requirement, performing erasure operation on the erasure area; receiving a write-in instruction, and detecting whether the write-in instruction meets a third preset requirement; and writing the upgrade data into the write-in area under the condition that the write-in instruction meets a third preset requirement. According to the embodiment of the invention, software upgrading can be realized under the condition of cooperative operation of the eSE system and the eSIM system.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of security upgrade technology, and in particular to a software upgrade method, apparatus, device, and storage medium. Background Art

[0002] Currently, the software upgrade method for combination chips (including the eSE system and the eSIM system) is basically to upgrade the entire memory of the chip. During the upgrade process, the system (eSE system and eSIM system) stops running and waits for the upgrade to be completed before re-executing the upgraded new system.

[0003] However, this software upgrade method can affect the operation of the eSIM system when the eSE system is upgraded, and vice versa, resulting in a poor customer experience. Therefore, a software upgrade method that allows for the coordinated operation of multiple systems is urgently needed. Summary of the Invention

[0004] In order to solve the above technical problems or at least partially solve the above technical problems, the embodiments of the present disclosure provide a software upgrading method, apparatus, device and storage medium.

[0005] A first aspect of an embodiment of the present disclosure provides a software upgrade method, which is applied to a combination chip, wherein the combination chip includes an eSE area and an eSIM area, wherein the method includes:

[0006] receiving an upgrade initialization instruction and detecting whether the upgrade initialization instruction meets a first preset requirement, wherein the upgrade initialization instruction includes an upgrade type, the upgrade type is used to characterize an upgrade area, and the upgrade area is one of the eSE area and the eSIM area, and the first preset requirement includes that the upgrade type matches a current task and the upgrade type matches a channel for issuing the upgrade initialization instruction;

[0007] If the upgrade initialization instruction meets the first preset requirement, receiving an erase instruction and detecting whether the erase instruction meets a second preset requirement, wherein the erase instruction is used to determine an erase area, and the second preset requirement includes that the erase area is located in the upgrade area;

[0008] When the erase instruction meets the second preset requirement, performing an erase operation on the erase area;

[0009] receiving a write instruction and detecting whether the write instruction meets a third preset requirement, wherein the write address is used to determine a write area, and the third preset requirement includes that the write area is located in the upgrade area;

[0010] When the write instruction meets the third preset requirement, the upgrade data is written into the write area.

[0011] A second aspect of an embodiment of the present disclosure provides a software upgrade device, which is applied to a combination chip, wherein the combination chip includes an eSE area and an eSIM area, wherein the device includes:

[0012] a first receiving module, configured to receive an upgrade initialization instruction and detect whether the upgrade initialization instruction meets a first preset requirement, wherein the upgrade initialization instruction includes an upgrade type, the upgrade type is used to characterize an upgrade area, and the upgrade area is one of the eSE area and the eSIM area, and the first preset requirement includes that the upgrade type matches a current task and matches a channel for issuing the upgrade initialization instruction;

[0013] a second receiving module configured to receive an erase instruction if the upgrade initialization instruction meets the first preset requirement, and detect whether the erase instruction meets a second preset requirement, wherein the erase instruction is used to determine an erase area, and the second preset requirement includes that the erase area is located within the upgrade area;

[0014] an erasing module, configured to perform an erasing operation on the erasing area if the erasing instruction meets the second preset requirement;

[0015] a third receiving module, configured to receive a write instruction and detect whether the write instruction meets a third preset requirement, wherein the write address is used to determine a write area, and the third preset requirement includes that the write area is located in the upgrade area;

[0016] A writing module is configured to write the upgrade data into the writing area if the writing instruction meets the third preset requirement.

[0017] A third aspect of an embodiment of the present disclosure provides an electronic device, comprising: a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor executes the method of the first aspect above.

[0018] A fourth aspect of an embodiment of the present disclosure provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method of the first aspect described above can be implemented.

[0019] The technical solution provided by the embodiments of the present disclosure has the following advantages over the prior art:

[0020] An embodiment of the present disclosure is capable of receiving an upgrade initialization instruction and detecting whether the upgrade initialization instruction meets a first preset requirement, wherein the upgrade initialization instruction includes an upgrade type, the upgrade type is used to characterize an upgrade area, the upgrade area is one of an eSE area and an eSIM area, and the first preset requirement includes that the upgrade type matches the current task and the upgrade type matches the channel for issuing the upgrade initialization instruction; when the upgrade initialization instruction meets the first preset requirement, receiving an erase instruction and detecting whether the erase instruction meets a second preset requirement, wherein the erase instruction is used to determine the erase area, and the second preset requirement includes that the erase area is located in the upgrade area; when the erase instruction meets the second preset requirement, performing an erase operation on the erase area; receiving a write instruction and detecting whether the write instruction meets a third preset requirement, wherein the write address is used to determine the write area, and the third preset requirement includes that the write area is located in the upgrade area; when the write instruction meets the third preset requirement, writing the upgrade data into the write area. It can be seen that by adopting the above technical solution, it is possible to distinguish whether the upgrade area is the eSE area or the eSIM area through the upgrade type, and then when the upgrade type matches the current task, the upgrade type matches the issuing channel of the upgrade initialization instruction, and the erase area and the write area are both located in the upgrade area, the upgrade data is written into the write area. In this way, the eSE task cannot access and modify the eSIM area, the hardware channel used by the eSE system cannot upgrade the eSIM system, and the operation of the eSIM system will not be affected when the eSE system is upgraded. Similarly, the eSE task cannot access and modify the eSIM area, the hardware channel used by the eSE system cannot upgrade the eSIM system, and the operation of the eSIM system will not be affected when the eSIM system is upgraded, thereby enabling the eSE system and the eSIM system to achieve software upgrades while operating in coordination. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0022] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0023] Figure 1 is a flowchart of a software upgrade method provided by an embodiment of the present disclosure;

[0024] Figure 2 This is a flowchart of an example of generating an upgrade script provided by an embodiment of the present disclosure;

[0025] Figure 3 This is a schematic diagram of the architecture of a combination chip provided by an embodiment of the present disclosure;

[0026] Figure 4 is a flowchart of an example of software upgrade provided by an embodiment of the present disclosure;

[0027] Figure 5 is a flowchart of another example of software upgrade provided by an embodiment of the present disclosure;

[0028] Figure 6 is a flowchart of another example of software upgrade provided by an embodiment of the present disclosure;

[0029] Figure 7 This is a structural diagram of a software upgrading device provided by an embodiment of the present disclosure;

[0030] Figure 8 It is a structural diagram of an electronic device in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features therein can be combined with each other in the absence of conflict.

[0032] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0033] Figure 1 This is a flowchart of a software upgrade method provided by an embodiment of the present disclosure. The method can be executed by a combination chip that integrates the eSE system and the eSIM system in the same chip. Accordingly, the combination chip includes an eSE area and an eSIM area that are isolated from each other, and the eSE system and the eSIM system each have their own hardware channels. The eSE system refers to a system that can implement the eSE function, the eSIM system refers to a system that can implement the eSIM function, the eSE area refers to a memory space allocated for the eSE system, and the eSE area stores codes written for implementing the eSE system. The eSIM area refers to a memory space allocated for the eSIM system, and the eSIM area stores codes written for implementing the eSIM system. Figure 1 As shown, the method provided in this embodiment includes the following steps:

[0034] S110: Receive an upgrade initialization instruction and detect whether the upgrade initialization instruction meets a first preset requirement, wherein the upgrade initialization instruction includes an upgrade type, which is used to identify the upgrade area, which is one of the eSE area and the eSIM area. The first preset requirement includes that the upgrade type matches the current task and matches the channel through which the upgrade initialization instruction is issued. In the disclosed embodiment, before performing a software upgrade on the combination chip, a user can first use a user device to generate an upgrade script, wherein the upgrade script includes an upgrade initialization instruction, an erase instruction, and a write instruction.

[0035] Specifically, the current task refers to the task currently being executed and associated with the software upgrade, wherein the current task is one of the eSE task (i.e., a specific operation or activity utilizing the eSE system) and the eSIM task (i.e., a specific operation or activity utilizing the eSIM system).

[0036] Specifically, the understanding of "the upgrade type matches the current task" is as follows: if the upgrade area is the eSE area and the current task is an eSE task, the upgrade type matches the current task. Similarly, if the upgrade area is the eSIM area and the current task is an eSIM task, the upgrade type matches the current task.

[0037] Specifically, the understanding of "the upgrade type matches the channel for issuing the upgrade initialization instruction" is as follows: if the upgrade area is the eSE area and the channel for issuing the upgrade initialization instruction is the hardware channel of the eSE system (such as the OMA channel), then the upgrade type matches the channel for issuing the upgrade initialization instruction. Similarly, if the upgrade area is the eSIM area and the channel for issuing the upgrade initialization instruction is the hardware channel of the eSIM system (such as the 7816 channel), then the upgrade type matches the channel for issuing the upgrade initialization instruction.

[0038] Optionally, the upgrade initialization instruction also includes an upgrade strategy, an upgrade version number, key material, a first ECC signature value and a first MAC value. Accordingly, the first preset requirement also includes at least one of the following: the upgrade version number meets the requirements of the upgrade policy, passes the ECC signature verification, for example, the first ECC signature value and the second ECC signature value are the same, and passes the MAC verification, for example, the first MAC value and the second MAC are the same.

[0039] Specifically, the upgrade strategy describes how to perform software upgrades, including but not limited to: upgrade strategies for version numbers, such as the upgrade version number (used to indicate which specific version of the product is used after the system is upgraded) needs to be higher than the current version number (used to indicate which specific version of the product the system is currently using), etc.

[0040] Specifically, key material refers to information used to generate a key, including but not limited to random numbers.

[0041] Specifically, the first ECC signature value is an ECC signature value calculated by the user equipment based on a preset ECC signature private key. The second ECC signature value is an ECC signature value calculated by the combination chip based on a preset ECC signature public key.

[0042] Specifically, the first MAC value is a MAC value generated by the user equipment based on the key material to generate a third key, and then based on the third key. The second MAC value is a MAC value generated by the combination chip based on the key material to generate a first key, and then based on the first key.

[0043] Further optionally, detecting whether the upgrade initialization instruction meets the first preset requirement includes: generating a second ECC signature value based on a preset ECC signature public key, generating a first key based on the key material when the first ECC signature value and the second ECC signature value are the same, and generating a second MAC value based on the first key, detecting whether the upgrade version number meets the requirements of the upgrade policy when the first MAC value and the second MAC value are the same, detecting whether the upgrade type matches the current task, and detecting whether the upgrade type matches the issuance channel of the upgrade initialization instruction, so as to detect whether the upgrade initialization instruction meets the first preset requirement.

[0044] S120. When the upgrade initialization instruction meets the first preset requirement, receive an erase instruction and detect whether the erase instruction meets the second preset requirement, wherein the erase instruction is used to determine the erase area, and the second preset requirement includes that the erase area is located in the upgrade area.

[0045] Optionally, the upgrade initialization instruction further includes a first hash value corresponding to the first address instruction, wherein, before receiving the erase instruction and detecting whether the erase instruction meets the second preset requirement, the method further includes:

[0046] receiving a first address instruction, wherein the first address instruction includes an erase reference address and a third hash value corresponding to the erase instruction, and correspondingly, the second preset requirement further includes that the fourth hash value is the same as the third hash value;

[0047] Calculate a second hash value corresponding to the first address instruction and detect whether the second hash value is the same as the first hash value.

[0048] Specifically, the first hash value is a hash value obtained by the user equipment performing hash calculation on the first address instruction, and the second hash value is a hash value obtained by the combination chip performing hash calculation on the first address instruction.

[0049] Further optionally, the erase instruction includes an erase offset address and a number of erased pages (or blocks), and receiving the erase instruction and detecting whether the erase instruction meets a second preset requirement includes:

[0050] When the second hash value is the same as the first hash value, receiving an erase instruction;

[0051] Calculate the fourth hash value corresponding to the erase instruction and detect whether the fourth hash value is the same as the third hash value. When the fourth hash value is the same as the third hash value, determine the erase area based on the erase base address, the erase offset address and the number of erased pages (or blocks) and detect whether the erase area is located in the upgrade area to detect whether the erase instruction meets the second preset requirement.

[0052] Specifically, the third hash value is a hash value obtained by the user equipment performing hash calculation on the erase instruction. The fourth hash value is a hash value obtained by the combination chip performing hash calculation on the erase instruction.

[0053] Specifically, the erase base address indicates which page (or block) to start erasing from, the erase offset address indicates the offset relative to the erase base address, that is, how far the data to be erased is from the erase base address, and the number of erased pages indicates the specific number of pages (or blocks) of data to be erased. Therefore, based on the erase base address, erase offset address, and number of erased pages (or blocks), the erased area can be determined, and further, whether the erased area is within the upgrade area can be determined.

[0054] Further optionally, the second preset requirement may also include that the erasing area is located within the authorized access area corresponding to the current task.

[0055] S130 : When the erase instruction meets the second preset requirement, perform an erase operation on the erase area.

[0056] Specifically, data in the erase area may be erased through an erase operation.

[0057] S140, receiving a write instruction and detecting whether the write instruction meets a third preset requirement, wherein the write instruction includes a write address and upgrade data, the write instruction is used to determine a write area, and the third preset requirement includes that the write area is within the upgrade area.

[0058] Specifically, the upgrade data can be an upgrade package corresponding to a patch upgrade, a differential upgrade, or a full upgrade. It is understood that patch upgrades and differential upgrades can reduce the size of the upgrade data, thereby reducing the time and cost of producing the upgrade data, and can also reduce upgrade time and improve upgrade efficiency.

[0059] Optionally, the erase instruction further includes a fifth hash value corresponding to the second address instruction, wherein, before receiving the write instruction and detecting whether the write instruction meets the third preset requirement, the method further includes:

[0060] receiving a second address instruction, wherein the second address instruction includes a write reference address and a seventh hash value corresponding to the write instruction, and correspondingly, the third preset requirement further includes that the seventh hash value and the eighth hash value are the same;

[0061] Calculate a sixth hash value corresponding to the second address instruction and detect whether the sixth hash value is the same as the fifth hash value.

[0062] Specifically, the fifth hash value is a hash value obtained by the user equipment performing hash calculation on the second address instruction. The sixth hash value is a hash value obtained by the combination chip performing hash calculation on the second address instruction.

[0063] Further optionally, the write instruction includes a write offset address and upgrade data, and receiving the write instruction and detecting whether the write instruction meets a third preset requirement include:

[0064] When the sixth hash value and the fifth hash value are the same, a write instruction is received;

[0065] Calculate the eighth hash value corresponding to the write instruction and detect whether the eighth hash value is the same as the seventh hash value. When the eighth hash value is the same as the seventh hash value, determine the write area based on the write base address, the write offset address and the upgrade data and detect whether the write area is located within the upgrade area to detect whether the write instruction meets the third preset requirement.

[0066] Specifically, the seventh hash value is a hash value obtained by the user device performing hash calculation on the write instruction, and the eighth hash value is a hash value obtained by the combination chip performing hash calculation on the write instruction.

[0067] Specifically, the write base address is used to indicate which page (or block) to start writing from, and the write offset address is used to indicate the offset relative to the write base address, that is, how far the specific location where the upgrade data is started is from the write base address. Therefore, based on the write base address, the write offset address, and the upgrade data, the write area can be determined, and further, whether the write area is within the upgrade area can be determined. Of course, it is also possible to determine whether the write area is within the erase area. Accordingly, the third preset requirement also includes that the write area is within the erase area.

[0068] Further optionally, the third preset requirement may also include that the writing area is located within the authorized access area corresponding to the current task.

[0069] S150 : When the write instruction meets the third preset requirement, write the upgrade data into the write area.

[0070] Specifically, the upgrade data may be written into the write area through a write operation, thereby achieving software upgrade.

[0071] Optionally, the upgrade initialization instruction further includes key material, wherein writing the upgrade data into the write area includes:

[0072] decrypting the upgrade data based on a second key, wherein the second key is generated from the key material;

[0073] Write the decrypted upgrade data into the write area.

[0074] Optionally, after S150 , the method further includes: receiving a verification instruction, and verifying the written data in the write area based on the verification instruction.

[0075] Further optionally, the write instruction further includes a ninth hash value corresponding to the third address instruction, wherein, before receiving the verification instruction and verifying the write data in the write area based on the verification instruction, the method further includes:

[0076] receiving a third address instruction, wherein the third address instruction includes a verification reference address and an eleventh hash value corresponding to the verification instruction;

[0077] Calculate the tenth hash value corresponding to the third address instruction and check whether the tenth hash value is the same as the ninth hash value;

[0078] The step of receiving a verification instruction and verifying the written data in the write area based on the verification instruction includes:

[0079] When the tenth hash value and the ninth hash value are the same, a verification instruction is received, wherein the verification instruction includes a verification offset address, a verification page number (or block number), and a first CRC value;

[0080] Calculate the twelfth hash value corresponding to the verification instruction and check whether the twelfth hash value is the same as the eleventh hash value;

[0081] When the twelfth hash value and the eleventh hash value are the same, a second CRC value is calculated based on the verification reference address, the verification offset address and the number of verification pages (or blocks), and when the first CRC value and the second CRC value are the same, it is determined that the written data verification has passed.

[0082] Specifically, the ninth hash value is a hash value obtained by the user equipment performing hash calculation on the third address instruction, and the tenth hash value is a hash value obtained by the combination chip performing hash calculation on the third address instruction.

[0083] Specifically, the eleventh hash value is a hash value obtained by the user equipment performing hash calculation on the verification instruction. The twelfth hash value is a hash value obtained by the combination chip performing hash calculation on the verification instruction.

[0084] Specifically, the verification reference address is used to indicate which page (or block) to start verification from, the verification offset address is used to indicate the offset relative to the verification reference address, that is, how far the specific location of the data to be verified is from the verification reference address, and the verification page number is used to indicate the specific number of pages (or blocks) of data to be verified. Therefore, based on the verification reference address, verification offset address, and verification page number, the verification area can be determined, and further, whether the verification area is located in the upgrade area can be determined. Of course, it can also be determined whether the verification area is located in the erase area.

[0085] Specifically, the first CRC value is a CRC value calculated by the user device for each page (or block) where the upgrade data is located. The second CRC value is a CRC value calculated by the chip device for each page (or block) where the write data is located.

[0086] Further optionally, before calculating the second CRC value based on the check base address, the check offset address and the number of check pages (or blocks), it is also possible to detect whether the check area is located in the accessible area corresponding to the current task. If so, the second CRC value is calculated based on the check base address, the check offset address and the number of check pages (or blocks).

[0087] It is understandable that, considering that the eSE system and the eSIM system have different hardware channels, and that a COS project contains multiple tasks, such as eSE tasks and eSIM tasks, during task execution, one task cannot directly access the code area and variables of another task. Similarly, during a software upgrade, one task should also not directly access the code area and variables of another task. Therefore, in the embodiments of the present disclosure, upgrade data is written when the upgrade type matches the current task, the upgrade type matches the channel used to issue the upgrade initialization instruction, and both the erase area and the write area are located within the upgrade area. This prevents the eSE task from accessing or modifying the eSIM area, and the hardware channel used by the eSE system cannot upgrade the eSIM system. This ensures that the operation of the eSIM system is not affected during the upgrade of the eSE system. Similarly, the eSE task cannot access or modify the eSIM area, and the hardware channel used by the eSE system cannot upgrade the eSIM system. This ensures that the operation of the eSIM system is not affected during the upgrade of the eSIM system. That is, the eSIM system is in an upgrade state without affecting the execution of the eSE tasks. Similarly, the eSE system is in an upgrade state without affecting the execution of the eSIM tasks, thereby achieving a secure upgrade of the coordinated operation of the eSE and eSIM systems.

[0088] It can be understood that by adding the first ECC signature value and the first MAC value to the upgrade initialization instruction and including the hash value of the next instruction in each instruction, the disclosed embodiment ensures the security of the upgrade script and restricts the execution of instructions to a sequential order, thereby ensuring the smooth execution of the upgrade script. Furthermore, by setting the ECC signature and MAC check to only the first upgrade initialization instruction, while the remaining instructions use hash values ​​to provide feedback on whether the upgrade script has been modified or damaged, the size of the upgrade script is reduced.

[0089] It is understandable that by setting the upgrade data to be transmitted in ciphertext and written to the memory in plaintext, the security of the software upgrade can be improved.

[0090] The software upgrade method provided by the embodiment of the present disclosure is described in detail below with reference to a specific example. Figure 2 As shown, the process of generating an upgrade script by the user device is as follows: determining the upgrade type, upgrade area, upgrade strategy, upgrade version number, key material, first ECC signature value, etc. Based on the key material, two pairs of symmetric keys (i.e., first key and second key) are generated using a specified key derivation algorithm. A first MAC value is generated based on the first key, the upgrade data is encrypted based on the second key, the hash value of each instruction other than the upgrade initialization instruction (first address instruction, erase instruction, second address instruction, write instruction, third address instruction, verification instruction, and upgrade end instruction, etc.) is calculated, and the CRC value of each page where the upgrade data is located (i.e., first CRC value) is calculated to generate the upgrade script. The instructions in the upgrade script are sent one by one to the combination chip to enable the combination chip to perform the software upgrade. The upgrade initialization instruction includes the upgrade type, upgrade strategy, upgrade version number, key material, first ECC signature value, first MAC value, and the hash value corresponding to the first address instruction (i.e., first hash value). The first address instruction includes the erase base address and the hash value corresponding to the erase instruction (i.e., third hash value). The erase instruction (e.g., erase NVM instruction) includes the erase offset address, the number of erase pages, and the hash value corresponding to the second address instruction (i.e., the fifth hash value). The second address instruction includes the write base address and the hash value corresponding to the write instruction (i.e., the seventh hash value). The write instruction (e.g., write NVM instruction) includes the write address offset, the encrypted upgrade data, and the hash value corresponding to the third address instruction (i.e., the ninth hash value). The third address instruction includes the check base address and the hash value corresponding to the check instruction (i.e., the eleventh hash value). The check instruction (e.g., check CRC value of each NVM page instruction) includes the check offset address, the check page number, the CRC value of each page (i.e., the first CRC value), and the hash value corresponding to the upgrade end instruction.

[0091] like Figure 3 As shown in the figure, the architecture of the combo chip includes an upgrade system. The combo chip consists of multiple tasks working together to meet the needs of different application scenarios. The eSE task or the eSIM task can switch to the upgrade system for upgrade via instructions. The upgrade system can upgrade the code and data areas (i.e., the eSE area) where the eSE task is located, and can also upgrade the code and data areas (i.e., the eSIM area) where the eSIM task is located.

[0092] like Figure 4 、 Figure 5 and Figure 6As shown, the process of software upgrade of the combination chip is as follows: after the upgrade starts, the combination chip records the current task. After entering the upgrade mode through the hardware channel where the current task is located, only the code area and data area of ​​the current task can be upgraded. The validity of the upgrade script is judged based on the ECC signature (i.e., the first ECC signature value and the second ECC signature value), and the integrity of the upgrade script is judged based on the MAC value (i.e., the first MAC value and the second MAC value). The upgrade area is determined according to the upgrade type, and the current task and the upgrade area are checked to see if they match. If they do not match, the upgrade mode is exited. If they do match, the upgrade continues. The upgrade version number is compared to see if it meets the requirements of the upgrade policy, such as requiring the upgrade version number to be higher than the current version. During the erase, write, and verify processes, it will be checked whether the upgrade area will be exceeded. If it exceeds the boundary, the upgrade mode will be exited, the remaining upgrade instructions will not be executed, and an error will be reported. After the upgrade data is written to the write area, the CRC of the page where the written data is located will be checked to determine whether the written data is correct. Specifically, after receiving the upgrade initialization instruction, the chip combination uses the ECC signature public key configured in the secure zone of the chip at the factory to calculate the signature value of the upgrade script (i.e., the second ECC value). This is compared with the signature value in the upgrade initialization instruction (i.e., the first ECC value). If the comparison succeeds, the key material in the upgrade initialization instruction is used through a key derivation algorithm to obtain two sets of symmetric keys. One of the symmetric keys is used to calculate the second MAC value, which is compared with the MAC value in the upgrade initialization instruction (i.e., the first MAC value). If the comparison succeeds, the upgrade information in the upgrade initialization instruction is compared to check whether it meets the requirements. This includes comparing the version number to see if it meets the requirements according to the upgrade policy requirements, comparing whether the upgrade type matches the current task, and comparing whether the upgrade script is delivered via the OMA channel if the current upgrade is for the eSE system. If the current upgrade is for the eSIM system, the upgrade script is delivered via the 7816 channel. After receiving the first address instruction, the hash value is first calculated and compared to see if it meets the requirements (i.e., whether the first hash value and the second hash value are the same). Receive the erase instruction, compare the hash value of the erase instruction to see if it meets the requirements (i.e., whether the third hash value and the fourth hash value are the same). After the comparison is successful, determine whether the erase area is within the upgrade area based on the upgrade area to ensure that the data area and code area of ​​another system cannot be erased. After receiving the second address instruction, first calculate and compare the hash value of the second address instruction to see if it meets the requirements (i.e., whether the fifth hash value and the sixth hash value are the same). Receive the write instruction, compare the hash value of the write instruction to see if it meets the requirements (i.e., whether the seventh hash value and the eighth hash value are the same). After the comparison is successful, use the previously generated symmetric key to decrypt the upgrade data first to determine whether the write area is within the upgrade area. After confirming that it meets the requirements, write the upgrade data.After receiving the third address instruction, first calculate and compare the hash value of the third address instruction to see if it meets the requirements (i.e., whether the ninth hash value and the tenth hash value are the same). Receive the verification instruction and compare the hash value of the verification instruction to see if it meets the requirements (i.e., whether the eleventh hash value and the twelfth hash value are the same). If the comparison passes, compare the CRC value of the actual memory based on the number of verification pages and the number of CRCs in the verification instruction. If the comparison passes, it proves that the written data is correct. Receive the upgrade end instruction and compare the hash value of the upgrade end instruction to see if it meets the requirements.

[0093] According to the disclosed embodiments, the combination chip can first verify the security and validity of the upgrade script. It then determines, based on the upgrade type and upgrade policy contained in the upgrade script, whether the upgrade version number meets the upgrade policy requirements, whether the hardware channel is compatible with the upgrade zone, and whether the current task is compatible with the upgrade zone. When these conditions are met, the system corresponding to the current task enters upgrade mode and upgrades without affecting the execution of the other system. That is, the two systems communicate using different hardware channels and can each enter upgrade mode and execute the upgrade script. Furthermore, when one system is operating normally, it receives a privileged user identity verification instruction and then sends a mode switch instruction to switch to upgrade mode and execute the upgrade script. If the upgrade script fails, it must execute the upgrade script again or execute a restore script issued by the host computer to restore the code. Otherwise, the incomplete upgrade process indicates that the currently written data is unreliable and cannot be used. During the upgrade process, this task does not affect the execution of other tasks because their code areas, data areas, and communication channels are isolated and do not affect each other. Upon the complete completion of the upgrade process, it indicates that the various verifications of the upgrade script have been passed, proving that the written data is valid. At this point, the upgrade process automatically exits upgrade mode and resets the task, which then restarts with the new data.

[0094] Figure 7 This is a structural diagram of a software upgrade device provided by an embodiment of the present disclosure. The software upgrade device can be understood as the above-mentioned combination chip or some functional modules in the above-mentioned combination chip. Figure 7 As shown, the software upgrading device includes:

[0095] a first receiving module 710 configured to receive an upgrade initialization instruction and detect whether the upgrade initialization instruction meets a first preset requirement, wherein the upgrade initialization instruction includes an upgrade type, the upgrade type being used to characterize an upgrade area, the upgrade area being one of the eSE area and the eSIM area, and the first preset requirement including that the upgrade type matches a current task and matches a channel for issuing the upgrade initialization instruction;

[0096] a second receiving module 720 configured to, if the upgrade initialization instruction meets the first preset requirement, receive an erase instruction and detect whether the erase instruction meets a second preset requirement, wherein the erase instruction includes an erase address, and the second preset requirement includes that the erase area corresponding to the erase address is located within the upgrade area;

[0097] An erasing module 730 is configured to perform an erasing operation on the erasing area if the erasing instruction meets the second preset requirement;

[0098] a third receiving module 740 configured to receive a write instruction and detect whether the write instruction meets a third preset requirement, wherein the write instruction includes a write address and upgrade data, and the third preset requirement includes that a write area corresponding to the write address is located within the upgrade area;

[0099] The writing module 750 is configured to write the upgrade data into the writing area if the writing instruction meets the third preset requirement.

[0100] Optionally, the upgrade initialization instruction also includes an upgrade strategy, an upgrade version number, a key material, a first ECC signature value and a first MAC value, wherein the first receiving module 710 includes a first detection submodule, the first detection submodule is used to detect whether the upgrade initialization instruction meets the first preset requirement, and the first detection submodule is specifically used to generate a second ECC signature value based on a preset ECC signature public key, and when the first ECC signature value and the second ECC signature value are the same, generate a first key based on the key material, and generate a second MAC value based on the first key, and when the first MAC value and the second MAC value are the same, detect whether the upgrade version number meets the requirements of the upgrade policy, detect whether the upgrade type matches the current task, and detect whether the upgrade type matches the issuing channel of the upgrade initialization instruction, so as to detect whether the upgrade initialization instruction meets the first preset requirement.

[0101] Optionally, the upgrade initialization instruction further includes a first hash value corresponding to the first address instruction, wherein the apparatus further includes: a fourth receiving module, configured to receive the first address instruction before receiving the erase instruction and detecting whether the erase instruction meets the second preset requirement, wherein the first address instruction includes an erase reference address and a third hash value corresponding to the erase instruction;

[0102] a first calculation module, configured to calculate a second hash value corresponding to the first address instruction and detect whether the second hash value is the same as the first hash value;

[0103] The erase instruction includes an erase offset address and an erase page number. The second receiving module 720 is specifically configured to receive the erase instruction when the second hash value is the same as the first hash value.

[0104] Calculate a fourth hash value corresponding to the erase instruction and detect whether the fourth hash value is the same as the third hash value. If the fourth hash value is the same as the third hash value, determine the erase area based on the erase base address, the erase offset address, and the number of erased pages and detect whether the erase area is located in the upgrade area, so as to detect whether the erase instruction meets the second preset requirement.

[0105] Optionally, the erase instruction further includes a fifth hash value corresponding to the second address instruction, wherein the apparatus further includes: a fifth receiving module, configured to receive the second address instruction before receiving the write instruction and detecting whether the write instruction meets the third preset requirement, wherein the second address instruction includes a write reference address and a seventh hash value corresponding to the write instruction;

[0106] a second calculation module, configured to calculate a sixth hash value corresponding to the second address instruction and detect whether the sixth hash value is the same as the fifth hash value;

[0107] The write instruction includes a write offset address and upgrade data, and the third receiving module 740 is specifically configured to receive the write instruction when the sixth hash value and the fifth hash value are the same;

[0108] Calculate an eighth hash value corresponding to the write instruction and detect whether the eighth hash value is the same as the seventh hash value. When the eighth hash value is the same as the seventh hash value, determine the write area based on the write base address, the write offset address and the upgrade data and detect whether the write area is located within the upgrade area, so as to detect whether the write instruction meets the third preset requirement.

[0109] Optionally, the upgrade initialization instruction further includes a key material, wherein the writing module 750 includes a first writing submodule, configured to write the upgrade data into the writing area, and the first writing submodule is specifically configured to decrypt the upgrade data based on a second key, wherein the second key is generated by the key material;

[0110] The decrypted upgrade data is written into the writing area.

[0111] Optionally, the device further includes: a sixth receiving module, configured to receive a verification instruction after writing the upgrade data into the write area, and verify the written data in the write area based on the verification instruction.

[0112] Optionally, the write instruction further includes a ninth hash value corresponding to the third address instruction, wherein the apparatus further includes: a seventh receiving module, configured to receive the third address instruction before receiving the verification instruction and verifying the write data in the write area based on the verification instruction, wherein the third address instruction includes a verification reference address and an eleventh hash value corresponding to the verification instruction;

[0113] a third calculation module, configured to calculate a tenth hash value corresponding to the third address instruction and detect whether the tenth hash value is the same as the ninth hash value;

[0114] The sixth receiving module is specifically configured to receive the verification instruction when the tenth hash value and the ninth hash value are the same, wherein the verification instruction includes a verification offset address, a verification page number, and a first CRC value;

[0115] Calculating a twelfth hash value corresponding to the verification instruction and detecting whether the twelfth hash value is the same as the eleventh hash value;

[0116] When the twelfth hash value and the eleventh hash value are the same, a second CRC value is calculated based on the verification offset address and the verification page number, and when the first CRC value and the second CRC value are the same, it is determined that the write data verification has passed.

[0117] The device provided in this embodiment can execute the method of any of the above embodiments, and its execution method and beneficial effects are similar, which will not be repeated here.

[0118] An embodiment of the present disclosure further provides an electronic device, comprising: a memory storing a computer program; and a processor for executing the computer program. When the computer program is executed by the processor, the method of any of the above embodiments can be implemented.

[0119] For example, Figure 8 This is a schematic diagram of the structure of an electronic device in the embodiment of the present disclosure. Figure 8, which shows a schematic structural diagram of an electronic device 800 suitable for implementing the embodiments of the present disclosure. The electronic device 800 in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 8 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0120] like Figure 8 As shown, the electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage device 808 into a random access memory (RAM) 803. Various programs and data required for the operation of the electronic device 800 are also stored in the RAM 803. The processing device 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0121] Typically, the following devices may be connected to the I / O interface 805: an input device 806 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 807 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 808 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 809. The communication device 809 may allow the electronic device 800 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 8 The electronic device 800 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed instead.

[0122] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 809, or installed from the storage device 808, or installed from the ROM 802. When the computer program is executed by the processing device 801, the above-mentioned functions defined in the method of the embodiment of the present disclosure are performed.

[0123] It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or component, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or component. In the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0124] In some embodiments, the client and server can communicate using any currently known or future developed network protocol, such as HTTP (HyperText Transfer Protocol), and can be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0125] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0126] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device executes the method described in any one of the above embodiments.

[0127] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including, but not limited to, object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0128] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of the boxes in the block diagram and / or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0129] The units involved in the embodiments described in this disclosure may be implemented in software or hardware, wherein the name of a unit does not necessarily limit the unit itself.

[0130] The functions described above herein may be performed, at least in part, by one or more hardware logic components. For example, and without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), and the like.

[0131] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0132] The embodiments of the present disclosure further provide a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the method of any of the above embodiments can be implemented. The execution method and beneficial effects are similar and will not be repeated here.

[0133] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0134] The foregoing description is intended only to provide specific embodiments of the present disclosure, intended to enable those skilled in the art to understand and implement the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the embodiments described herein, but rather to be construed in the broadest manner consistent with the principles and novel features disclosed herein.

Claims

1. A software upgrade method, characterized in that: Applied to a combination chip, the combination chip includes an eSE area and an eSIM area, wherein the method includes: receiving an upgrade initialization instruction and detecting whether the upgrade initialization instruction meets a first preset requirement, wherein the upgrade initialization instruction includes an upgrade type, the upgrade type is used to characterize an upgrade area, and the upgrade area is one of the eSE area and the eSIM area, and the first preset requirement includes that the upgrade type matches a current task and the upgrade type matches a channel for issuing the upgrade initialization instruction; If the upgrade initialization instruction meets the first preset requirement, receiving an erase instruction and detecting whether the erase instruction meets a second preset requirement, wherein the erase instruction is used to determine an erase area, and the second preset requirement includes that the erase area is located in the upgrade area; When the erase instruction meets the second preset requirement, performing an erase operation on the erase area; receiving a write instruction and detecting whether the write instruction meets a third preset requirement, wherein the write instruction includes a write address and upgrade data, the write address is used to determine a write area, and the third preset requirement includes that the write area is located within the upgrade area; When the write instruction meets the third preset requirement, the upgrade data is written into the write area.

2. The method according to claim 1, characterized in that The upgrade initialization instruction further includes an upgrade strategy, an upgrade version number, key material, a first ECC signature value, and a first MAC value, wherein detecting whether the upgrade initialization instruction meets the first preset requirement includes: A second ECC signature value is generated based on a preset ECC signature public key. When the first ECC signature value and the second ECC signature value are the same, a first key is generated based on the key material, and a second MAC value is generated based on the first key. When the first MAC value and the second MAC value are the same, whether the upgrade version number meets the requirements of the upgrade policy is detected, whether the upgrade type matches the current task, and whether the upgrade type matches the issuing channel of the upgrade initialization instruction, so as to detect whether the upgrade initialization instruction meets the first preset requirement.

3. The method according to claim 1, characterized in that The upgrade initialization instruction also includes a first hash value corresponding to the first address instruction, wherein, before receiving the erase instruction and detecting whether the erase instruction meets the second preset requirement, it also includes: receiving the first address instruction, wherein the first address instruction includes an erase reference address and a third hash value corresponding to the erase instruction; Calculating a second hash value corresponding to the first address instruction and detecting whether the second hash value is the same as the first hash value; The erase instruction includes an erase offset address and a number of erased pages, and the receiving of the erase instruction and detecting whether the erase instruction meets a second preset requirement includes: When the second hash value is the same as the first hash value, receiving the erase instruction; Calculate a fourth hash value corresponding to the erase instruction and detect whether the fourth hash value is the same as the third hash value. If the fourth hash value is the same as the third hash value, determine the erase area based on the erase base address, the erase offset address, and the number of erased pages and detect whether the erase area is located in the upgrade area, so as to detect whether the erase instruction meets the second preset requirement.

4. The method according to claim 1, wherein The erase instruction further includes a fifth hash value corresponding to the second address instruction, wherein, before receiving the write instruction and detecting whether the write instruction meets the third preset requirement, the method further includes: receiving the second address instruction, wherein the second address instruction includes a write reference address and a seventh hash value corresponding to the write instruction; Calculating a sixth hash value corresponding to the second address instruction and detecting whether the sixth hash value is the same as the fifth hash value; The write instruction includes a write offset address and upgrade data, and the receiving of the write instruction and detecting whether the write instruction meets a third preset requirement includes: When the sixth hash value and the fifth hash value are the same, receiving the write instruction; Calculate an eighth hash value corresponding to the write instruction and detect whether the eighth hash value is the same as the seventh hash value. When the eighth hash value is the same as the seventh hash value, determine the write area based on the write base address, the write offset address and the upgrade data and detect whether the write area is located within the upgrade area, so as to detect whether the write instruction meets the third preset requirement.

5. The method according to claim 1, wherein The upgrade initialization instruction also includes key materials, wherein writing the upgrade data into the write area includes: decrypting the upgrade data based on a second key, wherein the second key is generated from the key material; The decrypted upgrade data is written into the writing area.

6. The method according to claim 1, characterized in that After writing the upgrade data into the write area, the method further includes: A verification instruction is received, and the write data in the write area is verified based on the verification instruction.

7. The method according to claim 6, characterized in that The write instruction further includes a ninth hash value corresponding to the third address instruction, wherein, before receiving the verification instruction and verifying the write data in the write area based on the verification instruction, the method further includes: receiving the third address instruction, wherein the third address instruction includes a verification reference address and an eleventh hash value corresponding to the verification instruction; Calculating a tenth hash value corresponding to the third address instruction and detecting whether the tenth hash value is the same as the ninth hash value; The receiving of the verification instruction and verifying the written data in the write area based on the verification instruction includes: When the tenth hash value and the ninth hash value are the same, receiving the verification instruction, wherein the verification instruction includes a verification offset address, a verification page number, and a first CRC value; Calculating a twelfth hash value corresponding to the verification instruction and detecting whether the twelfth hash value is the same as the eleventh hash value; When the twelfth hash value and the eleventh hash value are the same, a second CRC value is calculated based on the verification reference address, the verification offset address and the verification page number, and when the first CRC value and the second CRC value are the same, it is determined that the write data verification has passed.

8. A software upgrade device, characterized in that: Applied to a combination chip, the combination chip includes an eSE area and an eSIM area, wherein the device includes: a first receiving module, configured to receive an upgrade initialization instruction and detect whether the upgrade initialization instruction meets a first preset requirement, wherein the upgrade initialization instruction includes an upgrade type, the upgrade type is used to characterize an upgrade area, and the upgrade area is one of the eSE area and the eSIM area, and the first preset requirement includes that the upgrade type matches a current task and matches a channel for issuing the upgrade initialization instruction; a second receiving module configured to receive an erase instruction if the upgrade initialization instruction meets the first preset requirement, and detect whether the erase instruction meets a second preset requirement, wherein the erase instruction is used to determine an erase area, and the second preset requirement includes that the erase area is located within the upgrade area; an erasing module, configured to perform an erasing operation on the erasing area if the erasing instruction meets the second preset requirement; a third receiving module, configured to receive a write instruction and detect whether the write instruction meets a third preset requirement, wherein the write address is used to determine a write area, and the third preset requirement includes that the write area is located in the upgrade area; A writing module is configured to write the upgrade data into the writing area if the writing instruction meets the third preset requirement.

9. An electronic device, characterized in that: include: A processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the processor performs the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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