Multi-bus fault injection circuit

Abstract

A multi-bus fault injection circuit disclosed by the present invention comprises a tracking control module, a verification module and a verification module, the verification module comprises a plurality of verification units, the tracking control module is used for feeding back different Put series signals to wake up the verification units when nodes output signals, and the same verification unit constructs fault codes injected by the nodes when waking up for the first time. And after the SAN is awakened for the second time, verifying node data on the serial bus at the SAN end, erasing and waiting for reconstruction when the node data is correct, and feeding back an Out series signal to the verification module for indication when the node data is wrong. Through a distributed dynamic reconfigurable fault injection mode, configuration can be automatically erased after verification is completed, real-time reconstruction is carried out according to new fault codes fed back by nodes, and the mutual testing function between any nodes is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of fault injection, and in particular to a multi-bus fault injection circuit. Background Art

[0002] Fault injection, as an active testing technique, artificially introduces faults to evaluate a system's behavior under abnormal conditions, effectively verifying the system's fault tolerance, error recovery mechanisms, and overall stability. However, in current hardware bus communication testing practices, the testing process is highly dependent on the resources of the master control. The entire system must complete injection and response reception for all test nodes through the master control node. This approach has low scalability, and the test scale is limited by the processing performance of the master control node. Summary of the Invention

[0003] In response to the above technical problems, the purpose of the present invention is to provide a multi-bus fault injection circuit, including a cycle control module, a check module, and a verification module. The verification module includes several verification units. The cycle control module is used to feedback different Put series signals to wake up the verification unit when the node outputs a signal. The same verification unit constructs a fault code injected by the node during the first wake-up. After the SAN wakes up for the second time, the node data on the serial bus at the SAN end is verified. If correct, it is erased and waits for reconstruction. If an error occurs, the Out series signal is fed back to the verification module for indication.

[0004] Furthermore, the verification unit includes a plurality of resistors, a plurality of diodes, a plurality of transistors, a plurality of field effect transistors, a plurality of inverting terminals, an operational amplifier, and a capacitor. The collector of the transistor Q1 in the plurality of diodes is connected to one end of the resistor R1, one end of the resistor R5, and one end of the resistor R8, and the base is connected to the drain of the field effect transistor Q3 and one end of the resistor R4; the collector of the transistor Q4 is connected to the inverting terminal of the operational amplifier U2, one end of the resistor R2, and the other end of the resistor R4, and the base is connected to the other end of the resistor R5; the output terminal of the operational amplifier U2 is connected to the Out_1 terminal; the input terminal of the inverter U3 is connected to the diode D 1 cathode, diode D2 cathode, one end of resistor R10, and the output end are connected to the gate of field-effect transistor Q2; the source of field-effect transistor Q2 is connected to the SAN terminal, and the drain is connected to the gate of field-effect transistor Q3 and one end of resistor R11; the source of field-effect transistor Q3 is connected to one end of capacitor C1; the other end of resistor R1 and the other end of resistor R2 are connected to the power supply; the anode of diode D1 is connected to the Put_1 terminal; the anode of diode D2 is connected to the Put_2 terminal; the emitter of transistor Q1, the emitter of transistor Q4, the other end of resistor R10, the other end of resistor R11, and the other end of capacitor C1 are grounded.

[0005] Furthermore, the control module includes a multiplexing chip, in which the second pin, fourth pin, seventh pin, and tenth pin of the multiplexing chip U1 are respectively connected to the Put_1 terminal, the Put_3 terminal, the Put_5 terminal, and the Put_7 terminal, the fifth pin, the sixth pin, the ninth pin, and the eleventh pin are respectively connected to the Put_2 terminal, the Put_4 terminal, the Put_6 terminal, and the Put_8 terminal, the first pin is connected to the Port terminal, the fourteenth pin is connected to the CLK terminal, the sixteenth pin is connected to the power supply, and the eighth pin is grounded.

[0006] Furthermore, the verification module includes an AND gate, wherein the first input terminal first pin and the second pin of the AND gate U4 are connected to the Out_1 terminal and the Out_2 terminal respectively, and the second input terminal fourth pin and the fifth pin are connected to the Out_3 terminal and the Out_4 terminal respectively.

[0007] Furthermore, the control module includes several multiplexing chips, wherein the second pin, the fourth pin, the seventh pin, the tenth pin, the first pin, the fifth pin, and the sixth pin of the multiplexing chip U5 in the multiplexing chips are respectively connected to the Put_1 terminal, the Put_3 terminal, the Put_5 terminal, the Put_7 terminal, the Put_9 terminal, the Put_11 terminal, and the Put_13 terminal, the ninth pin and the thirteenth pin are connected to the input terminal of the inverter U7 and the Put_15 terminal, and the fourteenth pin is connected to the fourteenth pin of the multiplexing chip U6 and the CLK terminal; The thirteenth pin of the multiplexing chip U6 is connected to the output end of the inverter U7, and the second pin, fourth pin, seventh pin, tenth pin, first pin, fifth pin, sixth pin, ninth pin and eleventh pin are connected to the Put end, Put_2 end, Put_4 end, Put_6 end, Put_8 end, Put_10 end, Put_12 end, Put_14 end and Put_15 end respectively; the sixteenth pin of the multiplexing chip U5 and the multiplexing chip U6 is connected to the power supply; the eighth pin of the multiplexing chip U5 and the multiplexing chip U6 is grounded.

[0008] Furthermore, the control module also includes several resistors, one end of the resistor R6 among the several resistors is connected to the 13th pin of the multiplexing chip U1; one end of the resistor R7 is connected to the 15th pin of the multiplexing chip U1; the other end of the resistor R6 and the other end of the resistor R7 are grounded.

[0009] Furthermore, the control module also includes a plurality of resistors, one end of the resistor R13 and one end of the resistor R14 among the plurality of resistors are respectively connected to the thirteenth pin and the fifteenth pin of the multiplexing chip U5; one end of the resistor R15 and one end of the resistor R16 are respectively connected to the thirteenth pin and the fifteenth pin of the multiplexing chip U6; the other end of the resistor R13, the other end of the resistor R14, the other end of the resistor R15, and the other end of the resistor R16 are grounded.

[0010] Furthermore, the verification unit further includes a plurality of resistors, wherein one end of the resistor R13 is connected to the power supply, and the other end is connected to the inverting end of the operational amplifier U2 and one end of the resistor R9; the other end of the resistor R9 is grounded.

[0011] Furthermore, it also includes a level conversion module, which is connected in series between the verification module and the bus and is used to convert the node level into a verification module recognition level.

[0012] The beneficial effects of the present invention compared with the prior art are: The present invention uses a distributed dynamically reconfigurable fault injection method to automatically erase the configuration after verification is completed, and reconstruct in real time according to the new fault code fed back by the node, thereby realizing the mutual testing function between any nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, a brief introduction is given below to the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0014] Figure 1 This is a schematic diagram of the overall structure provided by the present invention.

[0015] Figure 2 This is a schematic diagram of the structure of the verification unit provided by the present invention.

[0016] Figure 3 This is a schematic diagram of the structure of the control module provided by the present invention.

[0017] Figure 4 This is a schematic diagram of the verification module structure provided by the present invention.

[0018] Figure 5 This is a schematic diagram of another loop control module structure provided by the present invention. DETAILED DESCRIPTION

[0019] In order to make the objects and advantages of the present invention more clearly understood, the present invention is described in detail below with reference to the embodiments. It should be understood that the following text is only used to describe one or several specific implementation methods of the present invention and does not strictly limit the scope of protection specifically requested by the present invention.

[0020] like Figure 1As shown, the present invention discloses a multi-bus fault injection circuit, including a cycle control module, a check module, and a verification module. The check module includes a plurality of verification units. The cycle control module is used to feed back different Put series signals to wake up the check unit when the node outputs a signal. The same check unit constructs a fault code injected by the node during the first wake-up. After the SAN wakes up for the second time, the node data on the serial bus at the SAN end is verified. If correct, it is erased and waits for reconstruction. If an error occurs, the Out series signal is fed back to the verification module for indication.

[0021] like Figure 2 As shown, specifically, the verification unit includes a plurality of resistors, a plurality of diodes, a plurality of transistors, a plurality of field effect transistors, a plurality of inverting terminals, an operational amplifier, and a capacitor. The collector of the transistor Q1 in the plurality of diodes is connected to one end of the resistor R1, one end of the resistor R5, and one end of the resistor R8, and the base is connected to the drain of the field effect transistor Q3 and one end of the resistor R4; the collector of the transistor Q4 is connected to the inverting terminal of the operational amplifier U2, one end of the resistor R2, and the other end of the resistor R4, and the base is connected to the other end of the resistor R5; the output terminal of the operational amplifier U2 is connected to the Out_1 terminal; the input terminal of the inverter U3 is connected to the diode The cathode of D1, the cathode of diode D2, and one end of resistor R10 are connected to the gate of field-effect transistor Q2 at the output end; the source of field-effect transistor Q2 is connected to the SAN terminal, and the drain is connected to the gate of field-effect transistor Q3 and one end of resistor R11; the source of field-effect transistor Q3 is connected to one end of capacitor C1; the other end of resistor R1 and the other end of resistor R2 are connected to the power supply; the anode of diode D1 is connected to the Put_1 terminal; the anode of diode D2 is connected to the Put_2 terminal; the emitter of transistor Q1, the emitter of transistor Q4, the other end of resistor R10, the other end of resistor R11, and the other end of capacitor C1 are grounded.

[0022] like Figure 3 As shown, specifically, the control module includes a multiplexing chip, and the second pin, fourth pin, seventh pin, and tenth pin of the multiplexing chip U1 in the multiplexing chip are respectively connected to the Put_1 terminal, the Put_3 terminal, the Put_5 terminal, and the Put_7 terminal, the fifth pin, the sixth pin, the ninth pin, and the eleventh pin are respectively connected to the Put_2 terminal, the Put_4 terminal, the Put_6 terminal, and the Put_8 terminal, the first pin is connected to the Port terminal, the fourteenth pin is connected to the CLK terminal, the sixteenth pin is connected to the power supply, and the eighth pin is grounded.

[0023] like Figure 4 As shown, specifically, the verification module includes an AND gate, and the first input terminal first pin and second pin of the AND gate U4 are connected to Out_1 terminal and Out_2 terminal respectively, and the second input terminal fourth pin and fifth pin are connected to Out_3 terminal and Out_4 terminal respectively.

[0024] like Figure 5As shown, specifically, the control module includes several multiplexing chips, wherein the second pin, the fourth pin, the seventh pin, the tenth pin, the first pin, the fifth pin, and the sixth pin of the multiplexing chip U5 in the multiplexing chips are connected to the Put_1 terminal, the Put_3 terminal, the Put_5 terminal, the Put_7 terminal, the Put_9 terminal, the Put_11 terminal, and the Put_13 terminal respectively, the ninth pin and the thirteenth pin are connected to the inverter U7 input terminal and the Put_15 terminal, and the fourteenth pin is connected to the fourteenth pin of the multiplexing chip U6 and the CLK terminal. The thirteenth pin of the multiplexing chip U6 is connected to the output end of the inverter U7, and the second pin, fourth pin, seventh pin, tenth pin, first pin, fifth pin, sixth pin, ninth pin and eleventh pin are respectively connected to the Put end, Put_2 end, Put_4 end, Put_6 end, Put_8 end, Put_10 end, Put_12 end, Put_14 end and Put_15 end; the sixteenth pin of the multiplexing chip U5 and the multiplexing chip U6 is connected to the power supply; the eighth pin of the multiplexing chip U5 and the multiplexing chip U6 is grounded.

[0025] like Figure 3 As shown, specifically, the control module also includes several resistors, one end of the resistor R6 among the several resistors is connected to the thirteenth pin of the multiplexing chip U1; one end of the resistor R7 is connected to the fifteenth pin of the multiplexing chip U1; the other end of the resistor R6 and the other end of the resistor R7 are grounded.

[0026] like Figure 5 As shown, specifically, the control module also includes a plurality of resistors, one end of the resistor R13 and one end of the resistor R14 among the plurality of resistors are respectively connected to the thirteenth pin and the fifteenth pin of the multiplexing chip U5; one end of the resistor R15 and one end of the resistor R16 are respectively connected to the thirteenth pin and the fifteenth pin of the multiplexing chip U6; the other end of the resistor R13, the other end of the resistor R14, the other end of the resistor R15, and the other end of the resistor R16 are grounded.

[0027] like Figure 2 As shown, specifically, the verification unit further includes a plurality of resistors, wherein one end of the resistor R13 is connected to the power supply, and the other end is connected to the inverting end of the operational amplifier U2 and one end of the resistor R9; the other end of the resistor R9 is grounded.

[0028] Specifically, it also includes a level conversion module, which is connected in series between the verification module and the bus and is used to convert the node level into a verification module recognition level.

[0029] See Figure 1When the internal nodes in the node cluster on the bus send serial data to other nodes for injection, the verification module receives it synchronously. When the serial data is input, the control module feeds back the control signal to the verification module through the synchronous clock signal CLK. The number of bits of the verification module is composed of the number of verification units. The control module follows the serial data input and outputs different Put series signals to the verification unit in the verification module when the CLK is high. When the same verification unit receives the Put series signal for the first time, it dynamically constructs the fault code injected from the first node on the bus to the second node, and verifies the data fed back by the second node when receiving the Put series signal for the second time. When the verification is correct, the configuration is erased and waits for other nodes to reconstruct and verify again. At the same time, the Out series signal is fed back to the verification module. When an error occurs, the verification module outputs an indication signal.

[0030] See attached Figure 2 and attached Figure 3 , the CLK of the control module is the synchronous clock signal, the Put series is the wake-up signal end of the check unit, and the Port is to be connected; the SAN end of the check module is the serial data input end, and the Out series is the check bit data end. Figure 2The 4-bit cycle control module in is taken as an example. Assume that a fault is injected from node A in the node cluster on the bus to node B, and the data bit corresponding to node B is 1010. At this time, node A inputs serial data 1010 to the check unit and node B in sequence when the CLK synchronous clock signal is high. At the same time, the multiplexing chip U1 replaces the Put series signal to the check unit in sequence with the CLK signal input to wake up. When the 4-bit data input of node A is completed, the multiplexing chip U1 feeds back the Port signal to be received, and waits for node B to receive it and then feeds back 1010 to the check unit. During the feedback, the multiplexing chip U1 wakes up the same check unit with the CLK signal for verification. If the pass If the signal is normal, the original serial data will be erased, otherwise the corresponding fault code will be output to the verification module for indication. After erasure, it will be multiplexed to different nodes, and any node can input and output other nodes. In the specific principle, the CLK signal is input through the 14-pin of the multiplexing chip U1. The 3-pin of the multiplexing chip U1 is the reset pin or the initial bit pin. When the first data in the 4-bit serial data is input, the synchronous clock signal CLK inputs a high-level signal to the multiplexing chip U1. The 2-pin output Put_1 signal of the multiplexing chip U1 is input to the inverter U3 through the diode D1 for inversion. The gate to source of the field effect transistor Q2 is a negative voltage. The field effect tube Q2 is turned on, and the first data of the SAN end is input to the subsequent circuit through the field effect tube Q2. Assuming that the data is 1, the high-level signal is input to the source of the field effect tube Q3 after being pulled up by the field effect tube Q2 source, the field effect tube Q2 drain, and the resistor R11. The field effect tube Q3 gate to source positive voltage is turned on, and the power supply signal at the resistor R2 end is fed back to the collector of the transistor Q1 through the resistor R4, the source of the field effect tube Q3, the drain of the field effect tube Q3, and the resistor R8. The transistor Q1 is saturated, and the original resistor R1 power supply is fed back to the base signal of the transistor Q4 through the resistor R5. The base signal is transferred through the collector of the transistor Q1, the emitter of the transistor Q1 and the ground loop, and the transistor Q4 is cut off. , the potential of the resistor R2 and the resistor R4 ends are pulled up and input to the operational amplifier U2, and the operational amplifier U2 outputs the signal to Out_1. The resistor R3 and the resistor R9 set the initial static point reference voltage of the transistor Q4 and the transistor Q1, which can be greater than, or configured through the power supply. Assuming that the data is 0, the low-level signal is fed back to the source of the field effect transistor Q2, and the field effect transistor Q3 is cut off without positive voltage from the gate to the source. The transistor Q1 and the transistor Q4 are at the initial static operating point. At this time, the base voltages of the transistor Q1 and the transistor Q4 are close and in the amplification state. The power supply signal at the resistor R2 end is looped through the transistor Q4 and the ground, and the collector of the transistor Q4 and the resistor R2 end are at a low potential;When the second data is input, the CLK synchronous clock signal inputs a high-level signal to the multiplexing chip U1 again, and the 2-pin of the multiplexing chip U1 outputs the Put_3 signal to the second check unit. The above operation is performed according to the level state of the data. After the 4-bit data is input, the 1-pin of the multiplexing chip U1 outputs the Port waiting signal, waiting for the node corresponding to the 4-bit data to respond, and when the CLK inputs a high level again, the corresponding node inputs the same serial data to the SAN end. At the same time, the re-input of CLK allows the 5-pin of the multiplexing chip U1 to output the Put_2 signal, which is input to the inverter U3 through the diode D2 and is inverted, and the field effect transistor Q2 is turned on again. Assuming the first bit of the injection-initiating node output and the injection-responding node output are both 1, FET Q3 turns on again, the potential at capacitor C1 drops below the collector potential of transistor Q1, and the voltage at resistor R2 is input to capacitor C1 via resistor R4 and FET Q3. Capacitor C1 pulls up the voltage, then inputs it to the base of transistor Q4 via resistors R8 and R5. Transistor Q4 turns on, and the power signal at resistor R2 is pulled down through the transistor Q4 loop. Transistors Q1 and Q4 return to their quiescent points, and op amp U2 turns off. Assuming the injection-initiating node outputs 1 or the injection-responding node outputs 0 or 1, Out_1 remains unchanged or outputs 1 after a jump.

[0031] Attachment Figure 5 It is an 8-bit 256-1 node loop control module. The injection method is the same as the above. The difference is that when the 9-pin of the multiplexing chip U5 is output, one path of the feedback signal is sent to the 13-pin of the multiplexing chip U5 for interruption, and the other path is inverted by the inverter U7 to start the multiplexing chip U6. The interruption prevents the multiplexing chip U5 from resetting when the CLK inputs the signal again. At the same time, when the CLK inputs the signal again, the 1-pin of the multiplexing chip U6 outputs the Port signal. When the CLK is input again, the input signals of the remaining nodes wait for verification by the verification module. When there is a master control, the master control checks the 15-pin of the multiplexing chip U5 and the multiplexing chip U6 after the verification is completed. The 11th pin of the multiplexing chip U6 is connected in parallel with the 15th pin of the multiplexing chip U5 and the AND gate U4 for self-reset when used independently; the 8-bit loop control module verification in the verification module can be verified by an 8-input AND gate (not shown in the attached figure), and the resistor R6, resistor R7, resistor R13, resistor R14, resistor R15, and resistor R16 are all pull-down resistors, which pull down the signal when there is no upper control. The serial bus includes but is not limited to SPI, I2C, CAN, etc. The high and low levels between the verification module and the bus can be converted to 5V and 0V through a level conversion module (not shown in the attached figure).

[0032] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be encompassed therein. Any reference in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A multi-bus fault injection circuit, characterized in that: It includes a cycle control module, a check module, and a verification module. The check module includes several verification units. The cycle control module is used to feedback different Put series signals to wake up the verification unit when the node outputs a signal. The same verification unit constructs a fault code injected by the node during the first wake-up. After the SAN wakes up for the second time, it verifies the node data on the serial bus at the SAN end. If it is correct, it is erased and waits for reconstruction. If it is an error, it feeds back the Out series signal to the verification module for indication.

2. The multi-bus fault injection circuit according to claim 1, wherein: The verification unit includes a plurality of resistors, a plurality of diodes, a plurality of transistors, a plurality of field effect transistors, a plurality of inverting terminals, an operational amplifier, and a capacitor. The collector of the transistor Q1 among the plurality of diodes is connected to one end of the resistor R1, one end of the resistor R5, and one end of the resistor R8, and the base is connected to the drain of the field effect transistor Q3 and one end of the resistor R4; the collector of the transistor Q4 is connected to the inverting terminal of the operational amplifier U2, one end of the resistor R2, and the other end of the resistor R4, and the base is connected to the other end of the resistor R5; the output terminal of the operational amplifier U2 is connected to the Out_1 terminal; the input terminal of the inverter U3 is connected to the cathode of the diode D1 The output terminal is connected to the gate of the field-effect transistor Q2; the source of the field-effect transistor Q2 is connected to the SAN terminal, and the drain is connected to the gate of the field-effect transistor Q3 and one end of the resistor R11; the source of the field-effect transistor Q3 is connected to one end of the capacitor C1; the other end of the resistor R1 and the other end of the resistor R2 are connected to the power supply; the anode of the diode D1 is connected to the Put_1 terminal; the anode of the diode D2 is connected to the Put_2 terminal; the emitter of the transistor Q1, the emitter of the transistor Q4, the other end of the resistor R10, the other end of the resistor R11, and the other end of the capacitor C1 are grounded.

3. The multi-bus fault injection circuit according to claim 1, wherein: The control module includes a multiplexing chip, in which the second pin, the fourth pin, the seventh pin, and the tenth pin of the multiplexing chip U1 are connected to the Put_1 terminal, the Put_3 terminal, the Put_5 terminal, and the Put_7 terminal respectively, the fifth pin, the sixth pin, the ninth pin, and the eleventh pin are connected to the Put_2 terminal, the Put_4 terminal, the Put_6 terminal, and the Put_8 terminal respectively, the first pin is connected to the Port terminal, the fourteenth pin is connected to the CLK terminal, the sixteenth pin is connected to the power supply, and the eighth pin is grounded.

4. The multi-bus fault injection circuit according to claim 1, wherein: The verification module includes an AND gate, wherein the first input terminal, the first pin, and the second pin of the AND gate U4 are connected to the Out_1 terminal and the Out_2 terminal respectively, and the second input terminal, the fourth pin, and the fifth pin are connected to the Out_3 terminal and the Out_4 terminal respectively.

5. The multi-bus fault injection circuit according to claim 1, wherein: The control module includes several multiplexing chips, wherein the second pin, the fourth pin, the seventh pin, the tenth pin, the first pin, the fifth pin and the sixth pin of the multiplexing chip U5 in the multiplexing chips are connected to the Put_1 terminal, the Put_3 terminal, the Put_5 terminal, the Put_7 terminal, the Put_9 terminal, the Put_11 terminal and the Put_13 terminal respectively, the ninth pin and the thirteenth pin are connected to the input terminal of the inverter U7 and the Put_15 terminal, and the fourteenth pin is connected to the fourteenth pin of the multiplexing chip U6 and the CLK terminal; The thirteenth pin of chip U6 is connected to the output end of inverter U7, and the second pin, fourth pin, seventh pin, tenth pin, first pin, fifth pin, sixth pin, ninth pin and eleventh pin are connected to Put, Put_2, Put_4, Put_6, Put_8, Put_10, Put_12, Put_14 and Put_15 respectively; the sixteenth pin of multiplexing chip U5 and multiplexing chip U6 is connected to the power supply; the eighth pin of multiplexing chip U5 and multiplexing chip U6 is grounded.

6. The multi-bus fault injection circuit according to claim 3, characterized in that: The control module further includes a plurality of resistors, wherein one end of the resistor R6 is connected to the thirteenth pin of the multiplexing chip U1; one end of the resistor R7 is connected to the fifteenth pin of the multiplexing chip U1; the other ends of the resistor R6 and the other ends of the resistor R7 are grounded.

7. The multi-bus fault injection circuit according to claim 5, characterized in that: The control module also includes several resistors, one end of the resistor R13 and one end of the resistor R14 among the several resistors are respectively connected to the thirteenth pin and the fifteenth pin of the multiplexing chip U5; one end of the resistor R15 and one end of the resistor R16 are respectively connected to the thirteenth pin and the fifteenth pin of the multiplexing chip U6; the other end of the resistor R13, the other end of the resistor R14, the other end of the resistor R15, and the other end of the resistor R16 are grounded.

8. The multi-bus fault injection circuit according to claim 2, wherein: The verification unit further includes a plurality of resistors, wherein one end of the resistor R13 is connected to the power supply, and the other end is connected to the inverting end of the operational amplifier U2 and one end of the resistor R9; the other end of the resistor R9 is grounded.

9. The multi-bus fault injection circuit according to claim 1, wherein: It also includes a level conversion module, which is connected in series between the verification module and the bus and is used to convert the node level into a verification module recognition level.

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