Memory prefetching control method and device, storage medium and program product

Abstract

The invention discloses a memory prefetching control method and device, a storage medium and a program product, and relates to the technical field of computers. A heterogeneous logic model covering multiple access modes is constructed, a prefetch strategy candidate set is generated based on standard logic models corresponding to different access modes, the expression limitation of a single model on complex multi-mode access features is broken through, and access laws in different scenes can be comprehensively covered; through calculation, sorting and screening of the prefetch cost, targeted evaluation of the strategy is realized, bandwidth load aggravation and resource waste caused by redundant prefetch are avoided, and optimization of the target prefetch strategy in the aspects of low delay and high bandwidth utilization rate is ensured. According to the method and the device, the problems that a fixed logic model is difficult to adapt to dynamic diverse memory access behaviors and resource utilization is low in efficiency in the prior art are solved, and the technical effects that the method does not need to depend on fixed logic, can dynamically adapt to the change of the access mode through flexible combination and strategy screening of heterogeneous models, and is particularly suitable for terminal equipment with limited resources are achieved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a memory prefetch control method, device, storage medium, and program product. Background Art

[0002] In emerging application areas such as high-performance computing, edge intelligence, and real-time data processing, the rapid expansion of complex computing tasks and data-intensive applications has placed higher demands on low-latency, high-bandwidth memory access capabilities. Especially in resource-constrained end devices such as edge nodes and embedded platforms, memory access bottlenecks have become a key factor restricting overall computing performance and energy efficiency.

[0003] In related technologies, memory prefetch mechanisms based on fixed logic models are often used, such as sequential prediction, historical statistical analysis, or simple state machine logic. These methods usually assume that memory access presents a certain stable pattern and use a single rule to speculate on future access addresses. However, in reality, the memory access behavior of programs is significantly dynamic and diverse, and may exhibit multimodal characteristics such as burst access, short-cycle repetition, high concurrency conflicts, or hotspot locality. Fixed logic strategies often find it difficult to accurately capture these complex access characteristics, which can easily lead to a decrease in prefetch hit rate and an increase in redundant prefetches, thereby increasing the system bandwidth load, wasting storage resources, and even causing access conflicts, which in turn reduces system performance.

[0004] To address this issue, some methods have introduced analysis mechanisms based on feature models such as timing diagrams and access probability statistics, or employed prediction models based on historical trajectory fitting to improve prefetching adaptability. However, most of these methods still rely on a single model structure, lacking the ability to comprehensively represent heterogeneous access characteristics. Furthermore, they fail to implement targeted cost assessment and ranking optimization during policy selection, making it difficult to switch policies in a timely manner when access patterns suddenly change.

[0005] Therefore, how to build a prefetching strategy that can cover multiple access modes, achieve rapid adaptation and high-precision prefetching of current access behavior, and thus take into account system performance, delay control and resource utilization efficiency is a technical problem that technical personnel in this field urgently need to solve. Summary of the Invention

[0006] The present application provides a memory prefetch control method, device, storage medium and program product to at least solve the problems in related technologies that fixed logic models are difficult to adapt to dynamic and diverse memory access behaviors and resource utilization is inefficient. It achieves the technical effect of dynamically adapting to access mode changes through flexible combination and policy screening of heterogeneous models without relying on fixed logic, which is particularly suitable for resource-constrained terminal devices.

[0007] The present application provides a memory prefetch control method, comprising: constructing a heterogeneous logical model based on multiple standard logical models, wherein the multiple standard logical models correspond to different access modes respectively; inputting a current memory access sequence into the heterogeneous logical model to generate a prefetch strategy candidate set, wherein the prefetch strategy candidate set includes multiple prefetch strategies; calculating a corresponding prefetch cost for each prefetch strategy in the prefetch strategy candidate set, and sorting and screening the prefetch costs to determine a target prefetch strategy; and executing a corresponding memory prefetch operation from a target address set based on the target prefetch strategy.

[0008] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned memory prefetch control methods when executing the computer program.

[0009] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned memory prefetch control methods are implemented.

[0010] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned memory prefetch control methods when executed by a processor.

[0011] Through this application, by constructing a heterogeneous logical model covering multiple access modes, a set of prefetching strategy candidates is generated based on standard logical models corresponding to different access modes, breaking the limitation of a single model in expressing complex multimodal access features, and being able to comprehensively cover access patterns in different scenarios; by calculating, sorting, and screening prefetching costs, targeted evaluation of strategies is achieved, avoiding increased bandwidth load and resource waste caused by redundant prefetching, and ensuring the optimization of target prefetching strategies in terms of low latency and high bandwidth utilization. This application solves the problem in related technologies that fixed logical models are difficult to adapt to dynamic and diverse memory access behaviors and inefficient resource utilization, and achieves the technical effect of dynamically adapting to changes in access modes through flexible combination of heterogeneous models and policy screening without relying on fixed logic, which is particularly suitable for resource-constrained terminal devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 A flowchart of a memory prefetch control method provided in an embodiment of the present application.

[0014] Figure 2 A schematic diagram of a memory prefetch control device provided in an embodiment of the present application.

[0015] Figure 3 A schematic diagram of an electronic device provided in an embodiment of the present application.

[0016] Figure 4 A schematic diagram of a computer-readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0018] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0019] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0020] like Figure 1 The embodiment of the present application provides a memory prefetch control method. The method is described in detail in conjunction with the execution process of the memory prefetch control method. The method includes: S11: Build a heterogeneous logical model based on multiple standard logical models, where the multiple standard logical models correspond to different access modes.

[0021] Specifically, by integrating multiple standard logical models, we construct a heterogeneous logical model framework that can handle a variety of memory access patterns. The main purpose of this step is to eliminate the reliance on a single model to make prefetch decisions in a highly dynamic and variable memory access environment. Instead, we leverage multiple types of standard logical models to collaboratively perceive access behavior and evaluate access patterns from different modeling perspectives, thereby providing a more accurate and robust logical foundation for subsequent prefetch strategy generation.

[0022] Standard logical models can be structured modeling approaches designed for different access behavior characteristics. For example, some models are better at identifying access sequences with strong temporal correlation, such as sequential access or repetitive access patterns (typically logic models such as AIG (And-Inverter Graph) and XMG (XOR-Inverter Graph). Other models, however, prioritize capturing statistical features or contextual dependencies, such as statistical logic models like access popularity and jump distance distribution. These standard logical models extract predictability information from different dimensions of access sequences and integrate it into heterogeneous logical models through a unified interface. Heterogeneous logical models do not simply stack standard models. Instead, they are collaboratively enabled or adapted through specific combination or selection mechanisms (such as weight switching based on access characteristics or model fusion), thereby achieving generalized modeling of access patterns at the model structure level.

[0023] It's important to understand that this step doesn't construct a new model for every memory access sequence. Instead, it prepares multiple model templates with fixed structures but different logical orientations. These models are activated and combined as needed at runtime to handle different access scenarios. This structurally heterogeneous and logically coordinated modeling approach offers greater pattern adaptability and generalization capabilities for prefetch strategy generation than the single-model prediction methods of related technologies.

[0024] S12: Input the current memory access sequence into the heterogeneous logic model to generate a prefetch strategy candidate set, where the prefetch strategy candidate set includes multiple prefetch strategies.

[0025] Specifically, the constructed heterogeneous logical model is used to jointly model and analyze the current input memory access sequence, generating a set of candidate prefetch strategies tailored to the current access behavior. This set of candidate prefetch strategies represents multiple possible prefetch paths or operation modes, providing a strategic space for subsequent cost evaluation and decision screening. Due to the highly dynamic and uncertain nature of memory access behavior, it is not appropriate to directly output a single prefetch result. Instead, a candidate set is constructed to integrate the analytical perspectives of various logical models to improve the coverage and robustness of the strategy.

[0026] Specifically, after receiving a current segment (e.g., several past memory access sequences), the heterogeneous logic model invokes multiple standard logic models in parallel or alternately for inference. Each model proposes one or several possible prefetch suggestions based on its modeling approach and preferred characteristics (such as timing dependencies, statistical distribution, and contextual patterns). For example, one model might recommend prefetching address X based on jump distance patterns, while another might recommend prefetching addresses Y and Z based on access frequency trends. These suggestions, after being processed using a preset fusion strategy, collectively constitute the set of prefetch strategy candidates for the current moment.

[0027] Furthermore, to enhance prediction flexibility and accuracy, the prefetch strategies in this candidate set can include not only specific prefetch address targets but also policy-level parameters such as prefetch depth, coverage, trigger conditions, and instruction granularity. By converting model outputs into policy representations and collecting them into a set, this step essentially completes an abstract transformation from pattern recognition to multiple policy proposals. This preserves the information dimension of model reasoning while leaving room for optimization in the subsequent steps of policy cost evaluation and screening. This approach to generating candidate policy sets is highly scalable and can be flexibly adapted to different computing platforms and application scenarios.

[0028] It is important to understand that the timing graph model corresponding to the AIG structure maps the continuous memory access address sequence into a timing dependency graph, or in other words, maps the memory access sequence into a directed acyclic graph (DAG) to capture the sequential rules in program execution. Each node represents a memory address (for example, addresses A, B, C). The edges represent the access sequence between addresses (such as A→B→C). The timing relationship is described by AND-OR operations. For example, if address B must be accessed after A, the logical expression is Assuming the access sequence is A→B→C→B→D, the timing diagram contains the paths A→B→C and (B→D). The AIG structure can be used to derive the rule: if B is accessed, then C and D are prefetched.

[0029] The XMG structure's statistical model builds statistically driven logic rules based on access frequency and locality. This is implemented using an XOR-Majority operation. For example, if at least two of addresses X, Y, and Z are frequently accessed, the next address is prefetched. Frequently accessed addresses are given a higher weight. For example, if addresses X and Y are accessed 10 times in a short period of time, and Z is accessed twice, the statistical model generates a rule: if X and Y are accessed simultaneously, their adjacent addresses are prefetched.

[0030] If the heterogeneous logic model includes the standard logic models of the two structures (AIG and XMG), memory access sequences are mapped to both AIG and XMG structures. Complementary rules can be derived from the same data from different logical perspectives. For example, AIG focuses on temporal dependencies: accessing A requires accessing B; while XMG focuses on statistical combinations: A and C often occur together, so D needs to be prefetched.

[0031] The core steps of the strategy generation algorithm include: critical path extraction, identification of high-frequency paths (such as cyclic access sequences), generation of deep prefetch strategies (prefetching the next 3-5 addresses); locality analysis, partitioning regions according to access frequency (such as hot cache lines), generation of covering prefetch strategies (prefetching adjacent 64B data blocks). Finally, the candidate set of prefetch strategies is obtained. , is n prefetch strategies, E is the set of all prefetch strategies, and each prefetch strategy contains parameters such as prefetch depth and coverage. This process is implemented through a hybrid structure selection framework to ensure that the candidate strategies can capture both temporal regularities and statistical characteristics.

[0032] The logical function expression corresponding to the heterogeneous logical model is: Where, for The corresponding logical function value, It is the logical kernel function, AND-OR in AIG and XOR-Majority in XMG. is the weight parameter corresponding to step i, reflecting the impact of historical visits on the current prediction (e.g. (The most recent access is the most critical). Currently, weight parameters are typically fixed or manually adjusted. i is an index used to traverse the sequence from 1 to k. k is the maximum number of historical access steps considered by the logical kernel function. In the expression, k defines the range of the summation, considering historical access data from the current time step t back k steps. represents the memory access address at time step t, Represents the memory access address at time step ti, that is, the memory access address i steps before the current time step t.

[0033] In addition, the weight matrix corresponding to the weight parameters can be optimized by ridge regression to avoid overfitting. For example, if a strategy performs well in the training set but poorly in the test set, the regularization term It will suppress its weight.

[0034] For example, in a real case, a certain alternating memory access address sequence and , the letters A, B, C, D, E in each sequence represent the corresponding memory access addresses, and AIG modeling and XMG modeling are performed on them respectively to generate prefetch strategies, and a candidate set is given. Specifically, AIG modeling obtains two paths, path 1 is A→B→C→D, and path 2 is A→B→E. The strategy generated based on this is "when accessing B, prefetch C and E at the same time"; the statistical results of XMG modeling show that B appears 4 times, A appears 2 times, and C, D, and E appear 1 time each. The generated strategy is "if B is accessed, prefetch its adjacent address (C or E)". The candidate set includes: prefetch depth = 2 (B→C→D); coverage = 2 cache lines (prefetch 64B before and after B). Among them, it is necessary to understand that the memory access address sequence The correct approach is to construct the path as "A→B→C→D" or "A→B→C and B→D". The specific implementation is determined according to the current actual scenario.

[0035] S13: For each prefetch strategy in the prefetch strategy candidate set, calculate the corresponding prefetch cost, sort and filter the prefetch costs, and determine the target prefetch strategy.

[0036] Specifically, within the set of candidate prefetch strategies, the target prefetch strategy that best suits the current memory access scenario is identified. Since candidate strategies are often diverse and their effectiveness can vary significantly under different system states, static selection based solely on model scores or historical performance often fails to guarantee global optimality. To this end, this step introduces a dynamic evaluation mechanism using prefetch cost as a metric to comprehensively rank and screen strategies from multiple perspectives.

[0037] The composition of the prefetch cost is typically based on a trade-off between multiple factors, such as the memory access latency (or resource overhead) caused by executing a particular strategy and the prefetch hit rate benefit achieved by the strategy. The latency cost represents the extent to which the strategy's execution consumes system resources such as memory bandwidth and access paths, while the hit rate benefit reflects the strategy's effectiveness—that is, whether the prefetched data can actually be used in subsequent accesses. Based on this, these two dimensions are combined into a cost metric using a certain weighting method, and all candidate strategies are normalized and ranked to determine the strategy with the optimal performance-to-cost ratio.

[0038] This step not only evaluates policies based on static rules but also incorporates dynamic system feedback, such as current memory load, cache hit rate, and bandwidth bottlenecks, to adjust the weights of each evaluation dimension, thereby demonstrating environmental adaptability. Furthermore, this step offers a degree of robustness. When the cost values ​​of some policies deviate significantly due to system anomalies or sample drift, the evaluation mechanism can proactively identify and eliminate these anomalous policies, preventing misguided prefetching behavior. Finally, through a sorting and screening mechanism.

[0039] S14: Based on the target prefetch strategy, execute a corresponding memory prefetch operation from the target address set.

[0040] This step applies the selected target prefetch strategy to the memory system. By triggering the corresponding prefetch behavior, the data that may be accessed soon is loaded in advance from the target address set, thereby optimizing the processor's access efficiency to the memory. The target address set is usually an address sequence or address pattern derived from the prefetch strategy, and its composition can be determined based on multi-dimensional features such as the pattern matching results of the current access sequence, the access density distribution, or the access offset trend. The prefetch operation does not directly affect the current processing flow, but rather loads the data into the cache or other buffer area in advance without blocking the main thread.

[0041] During execution, the system dynamically schedules prefetch depth (e.g., prefetching N addresses) and prefetch granularity (e.g., per cache line or page). It also considers real-time operational conditions such as current memory bandwidth, cache occupancy, and access concurrency to determine whether to execute the target prefetch strategy immediately, delay it, or partially. This process emphasizes a balance between latency sensitivity and hit probability, ensuring that prefetching itself does not interfere with the main thread's bandwidth or cause cache pollution, thereby steadily improving overall system throughput and responsiveness.

[0042] Furthermore, the prefetching performed in this step also lays the foundation for the subsequent feedback learning mechanism. This monitors whether the prefetched data is actually hit in subsequent accesses and records the hits as historical samples, forming a lightweight policy verification loop. This feedback is used not only for policy optimization but also to improve the accuracy of access pattern re-identification, making the entire prefetching system more adaptable and evolvable.

[0043] In an exemplary embodiment, for each prefetch strategy in a set of prefetch strategy candidates, a corresponding prefetch cost is calculated, including: for each prefetch strategy in the set of prefetch strategy candidates, a corresponding delay cost and a hit rate gain are calculated; the delay cost represents the length of time that the execution of the prefetch strategy occupies the memory bus, and the hit rate gain represents the proportion of prefetched data corresponding to the prefetch strategy that is actually accessed; based on the delay cost and the hit rate gain, the corresponding prefetch cost is calculated.

[0044] In this embodiment, the prefetch cost is calculated for each prefetch strategy candidate, aiming to find the optimal strategy from multiple potential strategies for actual memory prefetch operations. This process first relies on two core performance metrics, namely latency cost and hit rate gain. The latency cost describes the system burden brought about by the execution of the prefetch strategy, which is mainly reflected in how much memory bus bandwidth the strategy occupies during execution, the extent of data transfer caused, and the possible blockage or interference of these transfer processes on current or future requests. The evaluation of this latency cost is usually dynamically calculated based on multiple dimensions such as the amount of prefetched data, the trigger frequency, the memory level of the target address (such as main memory or remote NUMA (Non-Uniform Memory Access) node), the current system's bandwidth utilization, and concurrent access conditions.

[0045] The corresponding hit rate gain is used to evaluate the effectiveness of the prefetch strategy, namely the probability or proportion of data prefetched by the strategy being hit in subsequent actual accesses. This metric reflects the contribution of prefetching behavior to the overall hit rate improvement and, therefore, indirectly represents the strategy's ability to improve system access latency. The hit rate gain can be predicted based on historical access data or modeled by combining access pattern classification (such as sequential access, random access, and cyclic access) with address locality characteristics. In some implementations, a short-term sliding window or long-term statistical mechanism is introduced to smooth the hit results to improve the stability and predictive accuracy of this metric.

[0046] Once the latency cost and hit rate gain are quantified into specific numerical values, they are input into a predefined cost function to calculate the final prefetch cost indicator. This cost function is usually a weighted combination model, which may be in the form of a linear combination or a nonlinear mapping structure, depending on the system objectives. The purpose of weighting is to provide adaptability to system preferences under different operating conditions: for example, in the case of high bandwidth occupancy, more emphasis may be placed on latency cost, thereby reducing prefetch interference; while in the stage of low hit rate, it may be more inclined to relax the constraints on latency and give priority to improving hit gain. This cost function construction and dynamic weight adjustment mechanism enable the system to achieve a flexible balance between multiple performance indicators and realize adaptive optimization.

[0047] Ultimately, this prefetch cost serves as a unified metric for evaluating the quality of each candidate strategy and is used for sorting and screening. This ensures that the target prefetch strategy selected by the system is both sufficiently effective and does not significantly impact system load. This evaluation and comparison mechanism not only enables quantitative decision-making on prefetch strategies but also lays the foundation for subsequent strategy feedback learning and dynamic adjustment.

[0048] Based on the above embodiments: In an exemplary embodiment, the corresponding prefetch cost is calculated based on the delay cost and the hit rate gain, including: for each prefetch strategy, obtaining the first weight corresponding to the delay cost and the second weight corresponding to the hit rate gain; based on the delay cost, the first weight, the hit rate gain and the second weight, calculating the corresponding prefetch cost.

[0049] In this embodiment, the prefetch cost assessment not only relies on the basic latency cost and hit rate gain itself, but also further introduces weight parameters to adapt and adjust system requirements under different operating scenarios. This weight-based cost modeling method embodies a strategy for achieving balanced optimization under multiple indicators. Specifically, for each candidate prefetch strategy, its corresponding latency cost and hit rate gain are obtained respectively, and two independent weight factors are introduced, namely the first weight of the latency cost and the second weight of the hit rate gain, to reflect the current system's focus on different performance goals (such as minimizing latency or maximizing hit rate).

[0050] The first weight is used to measure the current system's sensitivity to latency costs. When bandwidth pressure is high or prefetching behavior may compete with the main thread for resources, the first weight is dynamically increased to increase the influence of latency on the overall evaluation in cost calculation. Conversely, when bandwidth resources are relatively abundant, the first weight will be appropriately lowered to relax the constraints on latency overhead, allowing more potentially valuable prefetching strategies to be selected. Similarly, the second weight reflects the system's current emphasis on hit rate gain. If the current cache hit rate is low, increase the second weight so that strategies with high hit rates perform better in cost calculations, so as to achieve the goal of improving cache utilization efficiency as quickly as possible.

[0051] Once the latency penalty, hit rate gain, and their corresponding weights are obtained, the prefetch cost is calculated based on a weighted combination formula. Latency is a negative metric (higher, worse), and hit rate is a positive metric (higher, better). This differentiated combination allows the cost value to reflect the overall quality of the strategy across multiple performance metrics on a unified scale. Notably, this structure allows the system to directly numerically rank multiple strategies, making subsequent screening operations efficient, clear, and easy to automate.

[0052] Through this design, the entire prefetching policy evaluation system achieves a high degree of flexibility and dynamic adaptability. The introduction of weights not only avoids the limitations of hard-coding a fixed objective function but also provides adjustable control parameters for subsequent feedback optimization and online learning. In actual deployments, these weights can be adjusted in real time based on runtime statistics, ensuring that policy decisions remain effective and resource-sensitive across varying loads, application types, and access patterns.

[0053] In an exemplary embodiment, the method further includes: monitoring the bandwidth utilization and cache hit rate of the memory in real time; adjusting the first weight according to the bandwidth utilization; and adjusting the second weight according to the cache hit rate.

[0054] In this embodiment, in order to improve the adaptability and real-time performance of the prefetch control strategy, a dynamic monitoring mechanism for runtime performance indicators is introduced, specifically including real-time sampling and analysis of memory bandwidth utilization and cache hit rate. Bandwidth utilization reflects the current occupancy of the memory bus and is an important indicator for measuring whether the system has memory access congestion; the cache hit rate reveals the hit effect of the prefetch strategy on the actual accessed data and is a key parameter for evaluating prefetch benefits. By continuously monitoring these two indicators, the system can dynamically perceive the resource pressure and prefetch effect in the running state, thereby providing a basis for adjusting the prefetch strategy.

[0055] After obtaining these metrics, the weight parameters used to calculate prefetch costs are adjusted based on actual conditions. When high bandwidth utilization is detected, it indicates that current system resources are tight and prefetching operations may compete with normal access. In this case, the weight of the latency cost in the cost function is increased accordingly, that is, the value of the first weight is increased, so that strategies with high latency costs score lower in the ranking and are less likely to be selected. This can suppress potential bandwidth conflicts and prevent prefetching from interfering with the main thread. Conversely, if bandwidth utilization is low, indicating sufficient idle resources in the system, the first weight can be lowered, tolerating a certain degree of prefetching overhead in exchange for potential cache benefits.

[0056] Similarly, if the cache hit rate is low, this indicates that the current prefetch strategy's hit efficiency is suboptimal, leading to prefetch failure. In this case, the hit rate gain weight (the second weight) is increased accordingly to encourage strategies with higher hit rates to achieve higher overall scores in the ranking, thus facilitating the selection of strategies that improve cache hit rates. Conversely, if the cache hit rate is already high, the second weight can be appropriately lowered to avoid over-reliance on the hit rate and allow more room for other optimization objectives, such as latency control.

[0057] This mechanism enables the policy cost function to dynamically respond to runtime conditions, eliminating the need for static rule-based policy evaluation and instead enabling real-time trade-offs between current system load and performance requirements. This feedback-based adjustment mechanism enhances the prefetching system's adaptability, ensuring optimal prefetching performance and system stability across a variety of operational scenarios.

[0058] It is important to understand that the cost of delay ( ) reflects the memory bus occupancy time caused by executing a prefetch strategy and is a key metric for measuring the system bandwidth resource consumption of prefetch operations. Its physical significance lies in the fact that during a prefetch, the system must schedule data from multiple addresses into the cache. This process occupies the limited memory transmission channel and introduces potential latency. It is calculated as: = Number of prefetched addresses × Single address transmission time + Control overhead. If strategy e requires prefetching 3 addresses, each address takes 2 cycles, and the control overhead is 1 cycle, then =3×2+1=7, is the delay cost corresponding to prefetch strategy e.

[0059] Hit rate bonus This index characterizes the effectiveness of the prefetch strategy, that is, the proportion of prefetched data that is actually hit by subsequent access, reflecting the prediction accuracy of the strategy. The higher the index, the less invalid prefetching, and the greater the performance benefit brought by prefetching. The calculation method is = Number of hit addresses / Number of prefetched addresses. If prefetch strategy e prefetches 5 addresses, 3 of which are used by subsequent accesses, then =3 / 5=0.6, is the hit rate gain corresponding to prefetch strategy e.

[0060] After completing the calculation of the above two indicators, the system will integrate them into a weighted total cost function to form the final evaluation indicator for the candidate strategy. The cost function formula is: ; is the total cost corresponding to the prefetch strategy e, is the first weight, representing the trade-off parameter of the system’s sensitivity to bandwidth resources. is the second weight, which is used to regulate the system's preference for prefetch hit effects. If the system detects bandwidth shortage, α can be appropriately increased to suppress strategies with high bandwidth consumption. If the hit rate is low, γ can be increased to give priority to high hit strategies.

[0061] Comprehensive example: Assume that strategy 1 is: , Strategy 2 is: , Strategy 1 has a lower cost and is selected as the target strategy for final execution.

[0062] When combining candidates for cost evaluation, input the pre-selected strategy candidate set generated in the above steps . Traverse all pre-selection strategies: for the i-th pre-fetch strategy , calculate its and . Then regularized weight optimization is performed, formula middle, is the candidate strategy feature matrix (each row corresponds to strategy delay, hit rate and other features), for The transposed matrix of is a regularization term (to prevent overfitting and suppress strategies that perform well on the training set but poorly on the test set), L represents the strategy-target association matrix, connecting strategy features with decision targets, and M represents the regularization strategy feature matrix. is the inverse matrix of M. Finally, select by sorting, according to the total cost Sort in ascending order and select the strategy with the minimum cost , in order to complete the evaluation and optimization of the pre-selected strategies.

[0063] In actual cases, there are two candidate strategies: For prefetch depth = 2 (latency = 6 cycles, hit rate = 70%), To cover adjacent cache lines (latency = 10 cycles, hit rate = 90%), parameter setting is required when bandwidth is tight By calculating the total cost, , , Result: Select , because it is better when bandwidth is limited.

[0064] Through the above-mentioned cost function mechanism, not only a comprehensive evaluation of the performance of candidate strategies is achieved, but also the weight parameters can be dynamically adjusted according to the system resource status during operation, so that prefetch control can take into account both bandwidth efficiency and access hit rate, thereby realizing efficient and intelligent adaptive prefetch management.

[0065] In an exemplary embodiment, adjusting the first weight according to bandwidth utilization includes: when the bandwidth utilization is greater than a first preset threshold, adjusting the first weight to increase the impact of the delay cost; adjusting the second weight according to the cache hit rate includes: when the cache hit rate is less than a second preset threshold, adjusting the second weight to increase the impact of the hit rate gain.

[0066] In this embodiment, by monitoring memory bandwidth usage in real time, the weight of latency penalty in prefetching costs is dynamically adjusted. When bandwidth utilization exceeds a preset first threshold (e.g., 80%), it indicates that bus resources are becoming scarce, and the strategy should prioritize bus resource utilization. Therefore, the first weight corresponding to latency penalty is automatically increased, thereby strengthening the preference for low-bandwidth strategies in cost evaluation and preventing high-latency, high-prefetch strategies from further exacerbating bus load.

[0067] At the same time, the cache hit rate is continuously tracked to evaluate the effectiveness of the prefetch strategy in actual operation. When the cache hit rate is consistently below the second preset threshold (e.g., 60%), it indicates that the current prefetch strategy is insufficiently effective, with many ineffective prefetches. To guide the system to prefer strategies with better hit rates, the second weight of the hit rate gain is appropriately increased. This will increase the influence of the hit rate factor in the cost function in future strategy evaluations, thereby improving the overall system prefetch accuracy and resource efficiency.

[0068] For example, the initial state: , ; The bandwidth utilization rate was monitored to be 90%, and it was adjusted to , ; At this time, the system prefers a low-latency strategy.

[0069] Directly invert the matrix May cause numerical instability (e.g. matrix singularity), adding regularization term , adding small perturbations to the diagonal elements of the matrix to ensure reversibility. This is equivalent to imposing a "conservative constraint" on the weights of the strategies, preventing a strategy from being over-optimal in the training set due to chance.

[0070] In the prior art, storing a 1000×1000 matrix requires 1,000,000 cells. However, Cholesky decomposition accelerates this process by exploiting symmetry to compress it into a single-dimensional array, requiring only 500,500 cells, halving the memory footprint and increasing computational speed by a factor of 7. For example, if prefetch strategy 1 offers fast prefetching but a low hit rate, or prefetch strategy 2 offers slightly slower prefetching but a higher hit rate, the system will dynamically select the appropriate strategy based on the current memory bandwidth. This process utilizes ridge regression to optimize the weight matrix and regularization to prevent overfitting, ensuring robustness of strategy selection.

[0071] In an exemplary embodiment, after calculating the corresponding delay cost and hit rate gain for each prefetch strategy in the prefetch strategy candidate set, the memory prefetch control method also includes: detecting the delay cost and hit rate gain of each prefetch strategy; marking the prefetch strategy corresponding to the delay cost exceeding the first standard range or the hit rate gain exceeding the second standard range as an abnormal prefetch strategy; and eliminating the abnormal prefetch strategy from the prefetch strategy candidate set.

[0072] In this embodiment, in order to further improve the robustness and execution stability of the memory prefetch strategy, after calculating the delay cost and hit rate gain of the candidate prefetch strategy, a round of outlier detection mechanism is executed. Specifically, based on historical statistical data, a first standard range of delay cost (for example, mean , For a strategy, if its latency cost is significantly higher than the normal range (i.e., exceeding the upper limit of the first standard range), it indicates that it may cause abnormal utilization of system bandwidth resources. If its hit rate gain is significantly lower than the normal range (i.e., below the lower limit of the second standard range), it indicates that the strategy may have a large number of ineffective prefetches. Such strategies are uniformly marked as abnormal prefetch strategies and removed from the candidate set in this round of evaluation to prevent them from entering the final sorting and selection process.

[0073] In addition, an adaptive fallback mechanism is introduced to prevent continuous policy failures under extreme or sudden access patterns. This mechanism counts the number of candidate policies screened in consecutive rounds. If no prefetch policy passes the cost calculation and exception elimination process (i.e., no valid policy) in three consecutive rounds, a conservative prefetch strategy is temporarily enabled. For example, the prefetch depth is forced to be reduced to 1, and prefetching is performed only for the minimum access interval. This conservative strategy ensures the system's minimum prefetch response while avoiding resource waste and load surges, providing a buffer window for subsequent logical model parameter readjustment and policy generation.

[0074] In an exemplary embodiment, the memory prefetch control method further includes: for the prefetch data corresponding to each prefetch strategy, constructing a loss function based on the predicted hit probability and the actual hit probability; performing truncated back propagation on the memory access sequence based on the loss function, retaining the reverse gradient information of a preset truncation window; the preset truncation window includes a preset number of steps; according to the reverse gradient information and the preset learning rate, optimizing the model parameters of the heterogeneous logic model, the model parameters including an input sensitivity parameter and a historical attenuation parameter, the input sensitivity parameter represents the influence weight of the new memory access sequence on the prefetch strategy, and the historical attenuation parameter represents the influence weight of the historical memory access sequence in the prefetch strategy update.

[0075] In this embodiment, a model parameter training method based on truncated backpropagation is proposed to solve the dynamic adaptive optimization problem of memory prefetching strategy, so as to reduce training resource consumption and improve update response efficiency. The method first constructs a loss function to measure the difference between the predicted hit probability and the actual hit probability as the optimization target. The loss function is defined as ,in, Refers to the actual hit probability of the kth memory prefetch strategy, N represents the number of prefetches. The cross entropy loss measures the predicted hit probability The actual hit probability If the predicted hit probability is 80% ( ), the actual hit probability ( ), the loss is -ln0.8≈0.223. Based on this, instead of using the traditional full backpropagation method for long sequences, a truncated backpropagation strategy is adopted, which performs gradient calculations and parameter updates only within a preset truncation window (e.g., the most recent 10 memory accesses). This truncation window is limited to a number of steps to avoid excessive memory storage requirements due to the accumulation of historical states.

[0076] From a physical perspective, the backpropagation process of traditional neural networks or logical models requires retaining intermediate computational results (such as activation values ​​and gradients) at all time steps, causing memory usage to grow linearly with the number of time steps, making it difficult to deploy on resource-constrained hardware. However, a truncation strategy focuses only on access behavior from the most recent period, ignoring contributions from earlier historical gradients, significantly reducing the amount of state storage. For example, if a training sequence is 1000 steps long and 1MB of intermediate state is required to be stored at each step, the cost of full retention is 1GB of memory overhead. However, if only the gradient information from the most recent 10 steps is retained, the storage overhead is only 10MB, a reduction of over 90%.

[0077] Furthermore, to address the loss of long-term dependency information caused by truncated gradients, this embodiment introduces a dual strategy of dynamic adjustment and hybrid training. During operation, if significant periodicity is detected in the memory access sequence (e.g., a period of approximately 100 steps), the truncation window length is dynamically expanded (e.g., from 10 steps to 20 steps) to temporarily retain more historical states for parameter updates, thereby capturing periodic behavior characteristics.

[0078] Furthermore, a periodic full-gradient training mechanism is incorporated. This mechanism performs a complete backpropagation training every certain number of steps (e.g., 100 steps), calculating the gradient information for all historical steps to correct for biases that may be caused by short-term truncated training. This hybrid training approach balances resource efficiency and model accuracy, making the prefetch strategy more adaptable and stable when handling complex access patterns that combine short bursts with long-term regularity.

[0079] The parameter update formula is: , . is the input sensitivity parameter, which controls the impact of new input on the current state (such as the sensitivity of prefetching decisions); is the history decay parameter, which represents the decay rate of the control history state (such as the forgetting rate of old access patterns). j, f, x, and n represent the new input, activation function, current state, and index respectively in the parameter update formula. T represents the size of the truncation window, that is, only the gradient information of the most recent T steps is retained for parameter update. Truncation is implemented as follows: only the last time step ( and ) and discarding the gradient of earlier time steps (e.g. ). For example, the model parameters , the gradient calculation of the current moment T depends only on and , no need to save arrive data.

[0080] Furthermore, to increase the efficiency of matrix operations involved in gradient calculations, this embodiment introduces numerical optimization techniques such as Cholesky decomposition for accelerating updates of high-dimensional weight matrices. This method reduces the computational complexity of the original matrix inversion or linear equation solution from high complexity to low-order complexity, while also exhibiting good parallelism and cache friendliness on a variety of hardware platforms. While ensuring the update accuracy of model parameters (such as input sensitivity parameters and historical attenuation parameters), it effectively controls computational load and resource consumption, making this prefetch control solution practically deployable on resource-constrained platforms such as edge processors and embedded chips.

[0081] For example, when training a prefetch model, the input is the five most recent memory addresses, and the output is a prefetch suggestion.

[0082] Forward propagation: input sequence , generate candidate strategies (such as prefetch C and D) through AIG and XMG models, and calculate the hit probability (Predicted to hit 3 / 4 addresses).

[0083] Loss calculation: The actual hit address is C and ; Loss L=-ln0.75≈0.287.

[0084] Backward propagation (truncated): only keep the gradients of the last two steps (visiting B and D); update parameters p and q: ,in, is the preset learning rate, p new is the updated input sensitivity parameter, is the updated historical attenuation parameter, for example Matrix acceleration: Using Cholesky decomposition to update the weight matrix reduces memory usage from 4MB to 1MB. Utilizing 1-D Cholesky decomposition to accelerate matrix operations, the 1000×1000 matrix that originally required storage was compressed into a single-dimensional array, reducing memory usage by a factor of four. This optimization enables model deployment on resource-constrained edge devices while maintaining accuracy.

[0085] In an exemplary embodiment, it also includes: calculating the difference between the current memory access sequence and the previous memory access sequence; judging whether the current access mode has changed compared with the previous access mode based on the difference; if there is a change, triggering the logic switching mechanism of the heterogeneous logic model to switch to the logic model corresponding to the current access mode.

[0086] In this embodiment, a dynamic monitoring and logic switching mechanism is introduced to improve the prefetch strategy's responsiveness to changes in access patterns, given that memory access patterns can change over time. The core of this mechanism is to determine whether the access pattern has changed significantly by calculating the difference between the current access sequence and historical access sequences in real time. This triggers a logic switch in the heterogeneous logical model and selects a prefetch strategy generation path that better matches the current pattern.

[0087] In order to measure the differences between access patterns, the access sequence difference is selected as the key monitoring indicator. Specifically, the current access sequence and the access sequence of the previous time window can be represented as Scurr and Sprev respectively. The difference between them is characterized by calculating the Euclidean distance or Hamming distance between the two sequences (denoted as D(Scurr, Sprev)). For example, when the running state switches from sequential traversal to random jump, the distance value between the two access sequences will increase significantly. For example, the difference , is the difference, Represents the memory access sequence at the current time t (such as the last 100 addresses); Represents the memory access sequence at the previous moment t-1; Represents the Euclidean distance (or Hamming distance) of the sequence.

[0088] Setting preset thresholds , used to determine whether the access pattern has changed. When , the current access pattern is considered to have significantly deviated from the original pattern, triggering the reconstruction of the prefetch strategy. The physical meaning is that changes in access behavior will cause the original strategy built based on a certain pattern (such as sequential access) to become invalid. Therefore, the prefetch path must be dynamically adjusted to maintain high hit rate and low latency.

[0089] Once the logic switching mechanism is triggered, the optimal logic model is reselected based on the current access characteristics (for example, switching from a temporal dependency model to a statistical feature model), ensuring that the subsequently generated prefetch strategy is highly compatible with the current access behavior. This dynamic reconfiguration mechanism significantly enhances the system's robustness and adaptability during multi-task, multi-stage operation.

[0090] For example, the memory access sequence at the previous moment t-1 is: (Sequential access); the memory access sequence at the current time t: (random jump); calculate the difference . Set the preset threshold (such as ),when When the access pattern changes significantly, the difference exceeds the threshold, indicating that the original prefetching strategy may be invalid and logic reconstruction needs to be triggered.

[0091] In an exemplary embodiment, triggering a logic switching mechanism of a heterogeneous logical model to switch to a logical model corresponding to a current access mode includes: selecting a target standard logical model that is compatible with the current access mode from a plurality of standard logical models included in the heterogeneous logical model based on characteristics of the current access mode; deactivating policy generation functions of other standard logical models in the heterogeneous logical model that are incompatible with the current access mode; and regenerating a set of prefetch strategy candidates based on the target standard logical model.

[0092] In this embodiment, when a significant change in the current access pattern is detected from the existing pattern, the logic switching mechanism of the heterogeneous logic model is triggered to ensure that the prefetch strategy generation logic always matches the access characteristics. The first step of this logic switching mechanism is to identify the characteristics of the current access pattern, such as whether it is sequential, periodic, local, or random. This pattern is determined by statistically analyzing indicators such as the address spacing distribution of the access sequence, the repetition frequency, and the similarity of historical patterns.

[0093] For example, deactivate the old model and suspend the strategy generation of the current logical representation (such as the timing graph AIG); activate the new model and select the appropriate logical representation based on the current pattern characteristics; if the sequence is strong, use the timing graph (AIG); if the randomness is strong, switch to the statistical model (XMG); generate a new strategy and regenerate the pre-selected strategy candidate set according to the steps of the above embodiment. For example, in the initial mode, sequential access, use AIG to generate the strategy "prefetch the next 2 addresses"; if it is detected , switch to XMG and generate the strategy "Prefetch adjacent cache lines of high-frequency addresses".

[0094] It should be understood that the selection of the adapted target standard logical model here to regenerate the set of prefetch strategy candidates does not conflict with the step S12 of "inputting the current memory access sequence into the heterogeneous logical model to generate a set of prefetch strategy candidates". Specifically, in S12, during the initial stage or periodic evaluation, the heterogeneous logical model is used to simultaneously consider timing dependencies and statistical characteristics to generate a set of prefetch strategy candidates with different prefetch depths and coverages. This is done to ensure that no matter how the actual access pattern changes, there are sufficient strategies to choose from. The reason for selecting the target standard logical model in this embodiment is that during operation, when changes in the access pattern are detected and the prefetch strategy needs to be adjusted, a logical representation that best suits the current access pattern is selected for strategy generation. This selection is based on the principle of optimal matching of efficiency and effect, that is, finding the optimal solution under given conditions. Although multiple standard logical models (such as AIG and XMG models) are used simultaneously in step S12 to generate a set of prefetch strategy candidates, at any given point in time (especially after a change in the access pattern), the system will only activate one model that best suits the current scenario to make real-time decisions. This is because different access patterns may be more suitable for different prediction models, and enabling two models at the same time may result in waste of resources or increased decision complexity. Therefore, although S12 adopts multi-model joint modeling to generate a rich and diverse set of prefetch strategy candidates, this embodiment emphasizes selecting the most appropriate single model based on the current access pattern at a specific moment to achieve efficient prefetch decisions. There is no conflict between the two, but rather a complementary relationship. The former provides a broad basis for selection, while the latter ensures accuracy and efficiency in practical applications.

[0095] In an exemplary embodiment, based on the characteristics of the current access pattern, a target standard logical model adapted to the current access pattern is selected from multiple standard logical models included in the heterogeneous logical model, including: if the current access pattern is a sequential access pattern, then a standard logical model corresponding to a timing-dependent access pattern is selected as the target standard logical model; if the current access pattern is a random access pattern, then a standard logical model corresponding to a statistical feature-based access pattern is selected as the target standard logical model.

[0096] This selection process relies on extracting behavioral features of the access sequence, such as determining whether the access address has a linear growth trend, whether the access interval is stable, and whether there are repetitive patterns or random jumps. Specifically, if the current memory access pattern exhibits obvious sequential access characteristics, such as memory addresses increasing in fixed increments (such as A, A+1, A+2,...), the system prioritizes the standard logical model of timing-dependent access patterns as the target model. This model excels at leveraging the relationship between temporal continuity and address progression, and by modeling the offset patterns in the access sequence, it performs highly accurate predictive prefetching.

[0097] Conversely, if the current memory access behavior exhibits a random access pattern, meaning there's no clear linear or periodic pattern between access addresses, the system will prioritize a standard logic model based on statistical access patterns as the target model. This type of model focuses on learning probability distributions, sets of frequently accessed addresses, or characteristic patterns from historical data to adapt to irregular, jumpy access behavior, thereby maintaining a stable prefetch hit rate in complex access environments. The selected target standard logic model becomes the dominant module in the current heterogeneous model, used to generate a new set of prefetch strategy candidates.

[0098] To prevent interference from incompatible models, the policy generation functionality for other standard logical models within the heterogeneous logical model is temporarily disabled, retaining only the inference path of the target logical model. This process not only simplifies computational overhead and improves processing efficiency, but also effectively avoids policy conflicts between different models. The prefetch policy candidate set regenerated using the target standard logical model better reflects the memory access prediction requirements under the current access pattern, significantly improving the effectiveness and accuracy of prefetching.

[0099] In an exemplary embodiment, after selecting a target standard logical model that is compatible with the current access pattern from multiple standard logical models included in the heterogeneous logical model based on characteristics of the current access pattern, the memory prefetch control method further includes: dynamically adjusting model parameters of the heterogeneous logical model based on the characteristics of the current access pattern to adapt to the current access pattern; the model parameters include an input sensitivity parameter and a historical attenuation parameter.

[0100] To further improve the adaptability of the heterogeneous logical model to different memory access patterns, this embodiment dynamically adjusts key model parameters of the heterogeneous logical model based on the behavioral characteristics of the current access pattern after selecting the target standard logical model. This adjustment is intended to make the model more sensitive to local changes in access sequences while retaining reasonable historical information for more accurate policy output.

[0101] Model parameters include, but are not limited to, input sensitivity and history decay. The input sensitivity parameter represents the weight of the current input sequence's impact on the prefetching strategy output. A larger value indicates that the model prioritizes changes in current access behavior; this parameter is suitable for scenarios with frequent changes in access, such as bursty or irregular access patterns. The history decay parameter controls the model's retention of past access information. A smaller value indicates faster decay of historical information, and the model's preference for short-term memory. This parameter is suitable for scenarios with weak sequentiality or unstable access characteristics.

[0102] Through this dynamic adjustment mechanism, heterogeneous logical models can not only switch logical structures to match the global characteristics of access patterns, but also achieve soft adaptation at the model parameter level based on the details of access behavior.

[0103] In an exemplary embodiment, model parameters of a heterogeneous logic model are dynamically adjusted based on characteristics of a current access pattern, including: if the current access pattern exhibits periodic characteristics, a historical attenuation parameter is increased by a preset step; if the current access pattern exhibits burst characteristics, an input sensitivity parameter is increased by a preset step.

[0104] This embodiment not only addresses overall changes in access patterns by switching logical model structures, but also introduces a parameter-level fine-tuning mechanism based on access pattern characteristics to achieve a fine-grained response to local behavioral differences. When the current memory access pattern exhibits certain periodic characteristics (such as a stable cyclic structure in access addresses and regular time intervals), it can be inferred that historical behavior has strong predictive significance for future accesses. Therefore, the historical decay parameter is gradually increased in a preset step-by-step manner to extend the model's memory window for past access records, thereby enhancing its ability to capture cyclical behavior.

[0105] Conversely, when the current access pattern is detected to have significant bursty characteristics (such as sharp jumps in address access or concentrated access to a new data area), the historical pattern's value as a reference for current behavior decreases. To improve the model's responsiveness to new input sequences, the input sensitivity parameter is increased in preset steps, allowing the model to focus more on recent changes in access patterns and mitigate the influence of past data. This dynamic parameter adjustment strategy based on access pattern characteristics enables heterogeneous logic models to both retain valuable periodic information and quickly learn new bursty behaviors, balancing stability and flexibility, improving overall prefetching effectiveness and adaptability.

[0106] For example, the linear function adjustment formula: Dynamic adjustment rules: For periodic accesses, increase q (historical decay parameter) (e.g., from 0.6 to 0.8) to enhance memory of historical states. For bursty accesses, increase p (input sensitivity parameter) (e.g., from 0.5 to 0.7) to improve response to new inputs. For example, if periodic accesses are detected (e.g., A→B→C repeats every 100 steps), q is automatically increased to 0.8 to enhance capture of cyclic patterns. If a large number of random accesses occur suddenly, p is increased to 0.7 to quickly learn new address relationships.

[0107] In a specific embodiment, the video stream processing program initially reads frame data sequentially (mode 1), and then switches to random frame skipping and editing (mode 2).

[0108] Mode 1 (sequential access): uses the AIG model with the strategy of "prefetch next 3 frames"; parameters: .

[0109] Mode switch detected: Calculation , determined to be random access; triggering logic reconstruction and switching to the XMG model.

[0110] Mode 2 (Random Access): Generates a statistical strategy: "Prefetch the two most frequently appearing adjacent frames in the last 10 frames"; dynamically adjusts parameters: (Reducing historical dependence and enhancing immediate response).

[0111] Result: The prefetch hit rate increased from 70% in mode 1 to 85% in mode 2.

[0112] Anomaly Detection: If the strategy's hit rate falls below 40% for five consecutive times, or the latency cost exceeds twice the historical average, the prefetch strategy is identified as abnormal. The system reverts to a conservative strategy with a prefetch depth of 1 (prefetching only the next address) to reduce resource usage. Incremental learning collects data during the anomaly period and updates model parameters after offline training. An alarm mechanism notifies system administrators to investigate hardware or software anomalies. For example, if a sudden memory bus conflict causes a surge in prefetch latency, the system switches to a conservative strategy and records data from the conflict period for subsequent analysis.

[0113] A modular DFR model dynamically adjusts nonlinear function parameters. For example, if the current access is periodic, the system increases the feedback coefficient q to capture the cyclic pattern; if the access is highly bursty, the input scaling factor p is increased to accelerate the response. This dynamic adaptation ensures that the prefetch strategy always adapts to the actual scenario. This dual adaptive mechanism significantly improves the robustness and effectiveness of the memory prefetch strategy in diverse application scenarios.

[0114] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0115] like Figure 2, an embodiment of the present application also provides a memory prefetch control device, including: a heterogeneous modeling module 21, used to construct a heterogeneous logical model based on multiple standard logical models, and the multiple standard logical models correspond to different memory access modes respectively. A strategy generation module 22, used to input the current memory access sequence into the heterogeneous logical model, and generate a prefetch strategy candidate set containing multiple prefetch strategies. A cost evaluation module 23, used to calculate the corresponding prefetch cost for each prefetch strategy in the prefetch strategy candidate set, and sort and filter the prefetch costs to determine a target prefetch strategy. A prefetch execution module 24, used to execute a corresponding memory prefetch operation from a target address set based on the target prefetch strategy.

[0116] In an exemplary embodiment, the cost evaluation module 23 includes: a cost decomposition submodule, used to calculate the corresponding delay cost and hit rate gain for each of the prefetch strategies in the prefetch strategy candidate set; the delay cost represents the length of time the memory bus is occupied by executing the prefetch strategy, and the hit rate gain represents the proportion of prefetched data corresponding to the prefetch strategy that is actually accessed; a weighted cost calculation submodule, used to calculate the corresponding prefetch cost based on the delay cost and the hit rate gain.

[0117] In an exemplary embodiment, the weighted cost calculation submodule is specifically used to obtain, for each of the prefetch strategies, a first weight corresponding to the delay cost and a second weight corresponding to the hit rate gain; and calculate the corresponding prefetch cost based on the delay cost, the first weight, the hit rate gain and the second weight.

[0118] In an exemplary embodiment, it also includes: a dynamic weight adjustment module for monitoring the bandwidth utilization and cache hit rate of the memory in real time; adjusting the first weight according to the bandwidth utilization; and adjusting the second weight according to the cache hit rate.

[0119] In an exemplary embodiment, a dynamic weight adjustment module is specifically used to monitor the bandwidth utilization and cache hit rate of the memory in real time; when the bandwidth utilization is greater than a first preset threshold, the first weight is adjusted to increase the impact of the delay cost; and the second weight is adjusted according to the cache hit rate, including: when the cache hit rate is less than a second preset threshold, the second weight is adjusted to increase the impact of the hit rate gain.

[0120] In an exemplary embodiment, it also includes: an abnormal strategy elimination module, which is used to detect the delay cost and hit rate gain of each prefetch strategy; mark the prefetch strategy corresponding to the delay cost exceeding the first standard range or the hit rate gain exceeding the second standard range as an abnormal prefetch strategy; and eliminate the abnormal prefetch strategy from the prefetch strategy candidate set.

[0121] In an exemplary embodiment, it also includes: an adaptive training module, which includes: a loss function construction submodule, which is used to construct a loss function based on the predicted hit probability and the actual hit probability; a truncated backpropagation submodule, which is used to perform backpropagation within a preset truncation window; and a parameter update submodule, which is used to update the model parameters of the heterogeneous logic model according to the reverse gradient and the learning rate, including the input sensitivity parameter and the historical attenuation parameter.

[0122] In an exemplary embodiment, it also includes: an access mode detection module, which is used to calculate the difference between the current memory access sequence and the previous memory access sequence; based on the difference, it is determined whether the current access mode has changed compared with the previous access mode; and a logic switching module, which is used to trigger the logic switching mechanism of the heterogeneous logic model if a change occurs, so as to switch to a logic model corresponding to the current access mode.

[0123] In an exemplary embodiment, the logic switching module includes: a model selection submodule for selecting, based on characteristics of the current access mode, a target standard logic model that is compatible with the current access mode from a plurality of standard logic models included in the heterogeneous logic model; a model start / stop submodule for deactivating policy generation functions of other standard logic models in the heterogeneous logic model that are incompatible with the current access mode; and regenerating the prefetch strategy candidate set based on the target standard logic model.

[0124] In an exemplary embodiment, the parameter adaptive adjustment module is used to dynamically adjust the model parameters of the heterogeneous logic model based on the characteristics of the current access pattern to adapt to the current access pattern; the model parameters include input sensitivity parameters and historical attenuation parameters.

[0125] In an exemplary embodiment, if the current memory access pattern exhibits periodic characteristics, the historical attenuation parameter is increased at a preset step; if the current memory access pattern exhibits burst characteristics, the input sensitivity parameter is increased at a preset step.

[0126] For further introduction to the memory prefetch control device, please refer to the above embodiments, which will not be elaborated in this application.

[0127] like Figure 3 An embodiment of the present application further provides an electronic device, including a memory 101 and a processor 102, wherein the memory 101 stores a computer program, and the processor 102 is configured to run the computer program to execute the steps in any of the above-mentioned memory prefetch control method embodiments.

[0128] like Figure 4An embodiment of the present application further provides a computer-readable storage medium 201, in which a computer program 202 is stored, wherein the computer program 202 is configured to execute the steps of any of the above-mentioned memory prefetch control method embodiments when running.

[0129] In an exemplary embodiment, the computer-readable storage medium 201 may include, but is not limited to, various media that can store the computer program 202, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0130] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned memory prefetch control method embodiments are implemented.

[0131] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps of any of the above-mentioned memory prefetch control method embodiments.

[0132] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0133] The above is a detailed introduction to a memory prefetch control method, device, storage medium and program product provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A memory prefetch control method, characterized in that: include: Building a heterogeneous logical model based on multiple standard logical models, where the multiple standard logical models correspond to different access modes respectively; Inputting the current memory access sequence into the heterogeneous logic model to generate a prefetch strategy candidate set, wherein the prefetch strategy candidate set includes multiple prefetch strategies; For each of the prefetch strategies in the prefetch strategy candidate set, calculating a corresponding prefetch cost, and sorting and screening the prefetch costs to determine a target prefetch strategy; Based on the target prefetch strategy, a corresponding memory prefetch operation is performed from the target address set.

2. The memory prefetch control method according to claim 1, wherein: For each of the prefetch strategies in the prefetch strategy candidate set, calculating a corresponding prefetch cost includes: For each of the prefetch strategies in the prefetch strategy candidate set, calculating a corresponding delay cost and a hit rate gain; the delay cost represents the length of time the memory bus is occupied by executing the prefetch strategy, and the hit rate gain represents the proportion of prefetched data corresponding to the prefetch strategy that is actually accessed; Based on the delay cost and the hit rate gain, a corresponding prefetch cost is calculated.

3. The memory prefetch control method according to claim 2, wherein: Calculating a corresponding prefetch cost based on the delay cost and the hit rate gain includes: For each of the prefetch strategies, obtaining a first weight corresponding to the delay cost and a second weight corresponding to the hit rate gain; Based on the delay cost, the first weight, the hit rate gain and the second weight, a corresponding prefetch cost is calculated.

4. The memory prefetch control method according to claim 3, wherein: Also includes: Real-time monitoring of memory bandwidth utilization and cache hit rate; adjusting the first weight according to the bandwidth utilization; The second weight is adjusted according to the cache hit rate.

5. The memory prefetch control method according to claim 4, wherein: Adjusting the first weight according to the bandwidth utilization includes: When the bandwidth utilization is greater than a first preset threshold, adjusting the first weight to increase the impact of the delay cost; Adjusting the second weight according to the cache hit rate includes: When the cache hit rate is less than a second preset threshold, the second weight is adjusted to increase the influence of the hit rate gain.

6. The memory prefetch control method according to claim 2, wherein: After calculating the corresponding delay cost and hit rate gain for each of the prefetch strategies in the prefetch strategy candidate set, the memory prefetch control method further includes: Detecting the delay cost and hit rate gain of each prefetch strategy; Marking the prefetch strategy corresponding to the delay cost exceeding the first standard range or the hit rate gain exceeding the second standard range as an abnormal prefetch strategy; The abnormal prefetch strategy is eliminated from the prefetch strategy candidate set.

7. The memory prefetch control method according to claim 1, wherein: The memory prefetch control method further includes: For the prefetched data corresponding to each prefetch strategy, a loss function is constructed based on the predicted hit probability and the actual hit probability; Performing truncated back propagation on the memory access sequence based on the loss function, retaining reverse gradient information of a preset truncation window; the preset truncation window includes a preset number of steps; Based on the reverse gradient information and the preset learning rate, the model parameters of the heterogeneous logic model are optimized, where the model parameters include an input sensitivity parameter and a history decay parameter. The input sensitivity parameter represents the influence weight of the new memory access sequence on the prefetch strategy, and the history decay parameter represents the influence weight of the historical memory access sequence in the prefetch strategy update.

8. The memory prefetch control method according to claim 1, wherein: Also includes: Calculate the difference between the current memory access sequence and the previous memory access sequence; Determining whether the current access mode has changed compared to the previous access mode based on the difference; If a change occurs, the logic switching mechanism of the heterogeneous logical model is triggered to switch to the logical model corresponding to the current access mode.

9. The memory prefetch control method according to claim 8, wherein: Triggering a logic switching mechanism of the heterogeneous logical model to switch to a logical model corresponding to the current access mode includes: Based on the characteristics of the current access pattern, selecting a target standard logical model adapted to the current access pattern from a plurality of standard logical models included in the heterogeneous logical model; Deactivate a policy generation function of other standard logical models in the heterogeneous logical model that are not compatible with the current access mode; The prefetch strategy candidate set is regenerated based on the target standard logical model.

10. The memory prefetch control method according to claim 9, wherein: Selecting a target standard logical model adapted to the current access pattern from a plurality of standard logical models included in the heterogeneous logical model based on the characteristics of the current access pattern includes: If the current access mode is a sequential access mode, selecting a standard logic model corresponding to a timing-dependent access mode as a target standard logic model; If the current access mode is a random access mode, a standard logical model corresponding to the statistical characteristic access mode is selected as the target standard logical model.

11. The memory prefetch control method according to claim 9, wherein: After selecting a target standard logical model adapted to the current access pattern from a plurality of standard logical models included in the heterogeneous logical model based on the characteristics of the current access pattern, the memory prefetch control method further includes: Based on the characteristics of the current access mode, model parameters of the heterogeneous logic model are dynamically adjusted to adapt to the current access mode; the model parameters include input sensitivity parameters and historical attenuation parameters.

12. The memory prefetch control method according to claim 11, wherein: Dynamically adjusting model parameters of the heterogeneous logical model based on characteristics of the current access pattern includes: If the current access pattern exhibits periodic characteristics, increasing the historical attenuation parameter by a preset step; If the current access mode exhibits a sudden characteristic, the input sensitivity parameter is increased by a preset step.

13. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the memory prefetch control method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the memory prefetch control method according to any one of claims 1 to 12.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the memory prefetch control method according to any one of claims 1 to 12 are implemented.

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