User state solid-state storage system based on MPSoC

Abstract

The invention discloses an MPSoC-based user mode solid-state storage system, which comprises a software driving module which is arranged in a user mode of an on-chip processor system, realizes reading and writing of a solid-state disk by utilizing a VFIO technology, carries out on-chip processor memory DMA mapping through an SMMU, distributes a continuous programmable logic memory as a buffer area, and transmits the buffer area to the user mode of the on-chip processor system. Frequent switching between a kernel mode and a user mode is avoided, and the read-write efficiency of the solid state disk is improved; and the FPGA hardware module is arranged in the programmable logic part and is used for receiving and analyzing the read-write request from the software driving module, generating a read-write command which can be analyzed by the NVMe host controller, calling the CDMA module to execute data transmission and returning a read-write result to the software driving module. According to the MPSoC-based user mode solid-state storage system, driving is achieved in the user mode, the problems of complexity and low efficiency of kernel mode programming are solved, meanwhile, efficient DMA mapping of the virtual address is achieved through the SMMU, and the flexibility and performance of the system are improved.

Description

Technical Field

[0001] The present invention belongs to the fields of storage technology and FPGA technology, and specifically relates to a user-mode solid-state storage system based on MPSoC. Background Art

[0002] In the prior art, a solid-state storage system based on an MPSoC generally uses a block device driver solution provided by the Linux kernel.

[0003] It has the following disadvantages:

[0004] 1. The Linux block device driver is implemented in kernel mode. It is complex to debug, difficult to program, and has a high probability of failure. If an error such as a memory leak occurs, it may cause the operating system to crash.

[0005] 2. Kernel-mode drivers involve a large number of context switches during use, and data copying between user mode and kernel mode wastes resources and time, resulting in low efficiency.

[0006] 3. Traditional DMA access lacks address isolation between different devices, posing security issues. DMA requires access to a continuous physical address space, so kernel-mode drivers must use software to translate virtual addresses into physical addresses. This process increases storage device I / O overhead and reduces device I / O efficiency, a particularly significant issue in high-performance storage systems based on solid-state media. Summary of the Invention

[0007] The present invention provides a user-mode solid-state storage system based on MPSoC to solve the above-mentioned technical problems, specifically adopting the following technical solutions:

[0008] A user-mode solid-state storage system based on an MPSoC is applied to a Zynq UltraScale+ platform. The platform integrates an on-chip processor system and programmable logic, and the on-chip processor system and programmable logic communicate via an AXI bus. The user-mode solid-state storage system based on the MPSoC includes:

[0009] A software driver module is provided in the user state of the on-chip processor system, and uses VFIO technology to implement reading and writing to the solid-state drive. The software driver module performs DMA mapping of the user state memory through the SMMU and uses IOVA for DMA access;

[0010] The FPGA hardware module is provided in the programmable logic part, and is used to receive and parse the request queue elements from the software driver module, generate read and write commands that can be parsed by the NVMe host controller, execute data transmission, and return the read and write results to the software driver module.

[0011] Furthermore, the software driver module includes a request parsing unit, a request submission unit and an interrupt control unit. The request parsing unit is used to receive and parse the bio data structure sent by the upper-layer interface, extract memory information and disk information, perform necessary address mapping, allocate programmable logic memory, and generate request queue elements; the request submission unit is used to submit the generated request queue elements to the request queue that interacts with the FPGA hardware module, notify the hardware module through the Doorbell register, and call the CDMA module to transfer data between the programmable logic memory and the on-chip processor memory; the interrupt control unit is used to poll the interrupt signal, read the completion queue elements from the completion queue, obtain the completion status of the read and write instructions, and notify the upper-layer application.

[0012] Furthermore, the request parsing unit maps the on-chip processor system memory virtual address with the device virtual address of the device address space through the VFIO_IOMMU_MAP_DMA mapping interface, allocates the programmable logic memory as a read and write buffer, and generates a request queue element containing the mapping address.

[0013] Furthermore, the request submission unit completes IO mapping from the on-chip processor system memory to the relevant register addresses of the FPGA hardware request queue and completion queue through the mmap interface during initialization, so as to control reading and writing of the two queues at runtime.

[0014] Furthermore, the interrupt control unit detects interrupts through the interface provided by VFIO. After detecting the interrupt signal, it disables the interrupt, reads the completion queue elements from the completion queue until the completion queue is empty, and then enables the interrupt, notifies the upper-layer application of the completion status, and releases the allocated programmable logic memory and DMA mapping.

[0015] Furthermore, the FPGA hardware module includes a hardware-software interaction unit and a command generation unit. The hardware-software interaction unit is used to receive and parse request queue elements from the software driver module, connect to the NVMe host controller, and package the read and write results as completion queue elements and return them to the software driver module; the command generation unit is used to convert the information in the request queue elements into a command format recognizable by the NVMe host controller, and execute the read and write tasks of the solid-state drive through the NVMe host controller.

[0016] Furthermore, the hardware-software interaction unit manages the request queue and the completion queue through a ring queue structure, and uses the Doorbell register to achieve synchronous communication with the software driver module. The hardware-software interaction unit is also responsible for calling the CDMA module to perform data transmission between the on-chip processor memory and the programmable logic memory.

[0017] Furthermore, the command generation unit combines the physical address of the programmable logic memory in the request queue element with the read / write flag, the address offset of the disk, and the read / write length information to generate a read / write command for the NVMe host controller.

[0018] Furthermore, after completing all operations on a completion queue element and notifying the upper-layer application, the software driver module releases the DMA mapping of the device address from the on-chip processor system memory to the programmable logic memory contained in the request queue element corresponding to the completion queue element.

[0019] Furthermore, after submitting the request, the software driver module writes the request queue tail pointer to the request queue's Tail Doorbell register through the device identifier provided by VFIO, notifying the hardware module that there is a new request to be processed; after finishing reading the elements in the completion queue, the completion queue head pointer is written to the completion queue's Head Doorbell register in the same way, notifying the hardware that the completion queue element has been processed.

[0020] The present invention is beneficial in that it provides an MPSoC-based user-mode solid-state storage system. By implementing drivers in user mode, it avoids the complexity and inefficiency of kernel-mode programming. It also utilizes the SMMU to achieve efficient DMA mapping of virtual addresses, improving system flexibility and performance. The system is suitable for a variety of high-performance computing and storage scenarios and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0022] Figure 1 This is a schematic diagram of the structure of a user-mode solid-state storage system based on MPSoC in this application;

[0023] Figure 2 This is a schematic diagram of the software driver module structure of this application;

[0024] Figure 3 This is a workflow diagram of the software driver module of this application;

[0025] Figure 4 This is a schematic diagram of the FPGA hardware module structure of this application. DETAILED DESCRIPTION

[0026] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0027] The present invention relates to a user-state solid-state storage system based on MPSoC (Multi-Processor System on Chip), which is particularly suitable for the Zynq UltraScale+ platform. The platform integrates an on-chip processor system (PS, Processing System, running an ARM Linux operating system) and programmable logic (PL, Programmable Logic). The core of the present invention is to realize the reading and writing of solid-state drives in user state through VFIO (Virtual Function I / O, virtual function input and output) technology, and utilize SMMU (System Memory Management Unit, system input and output memory management unit) to perform user-state DMA mapping, thereby improving the read and write efficiency of the solid-state drive and enhancing the security of the system.

[0028] like Figure 1 As shown, the user-state solid-state storage system based on MPSoC of the present invention includes: a software driver module and an FPGA hardware module. The software driver module runs in the user state of the on-chip processor system of the Zynq UltraScale+ platform, while the FPGA hardware module is implemented in the programmable logic part. The two communicate through the AXI bus to achieve efficient solid-state hard disk reading and writing. The main functions of the software driver module include: parsing bio (block input / output) requests issued by the upper layer, performing DMA mapping, submitting read and write requests, processing interrupts, and returning read and write results. The main functions of the FPGA hardware module include: receiving and parsing read and write requests from the software module, generating commands that can be parsed by the NVMe host controller, executing read and write operations, and returning the results to the software module.

[0029] The software driver module is located in user mode of the on-chip processor system and utilizes VFIO technology to implement read and write operations to the solid-state drive. The software driver module uses the SMMU (System Memory Management Unit) to perform user-mode DMA mapping, avoiding frequent switching between kernel and user modes and improving SSD read and write efficiency. DMA operations utilize IOVA (IO virtual address) to eliminate the need for physical address continuity and software translation from virtual memory addresses to physical addresses, thereby enhancing system efficiency, flexibility, and security.

[0030] The FPGA hardware module is set in the programmable logic part, which is used to receive and parse read and write requests from the software driver module, generate read and write commands that can be parsed by the NVMe host controller, execute data transmission, call the CDMA (Central Direct Memory Access) module to move data between the operating system memory and the programmable logic memory, and return the read and write results to the software driver module.

[0031] like Figure 2 As shown, in an embodiment of the present application, the software driver module includes a request parsing unit, a request submitting unit and an interrupt control unit. Figure 3 The software driver module first creates three threads, one for receiving bio, one for processing bio, and one for processing completion information.

[0032] The request parsing unit is used to receive and parse the bio data structure sent by the upper-layer interface, extract memory information and disk information, perform necessary address mapping, and generate a request queue element. In an embodiment of the present application, the request parsing unit maps the on-chip processor system memory virtual address to the device address space through the VFIO_IOMMU_MAP_DMA mapping interface and generates a request queue element containing IOVA.

[0033] Specifically, the request parsing unit mainly includes:

[0034] Receiving bio requests: The receiving thread of the request parsing unit continuously receives the bio data structure sent by the upper interface, and places the bio in a first-in-first-out bio waiting queue, waiting for processing by the processing thread.

[0035] Parsing BIO requests: The request parsing unit's processing thread extracts memory and disk information from the BIO wait queue one by one. BIO contains multiple iovecs. Unlike bvecs defined by Linux block device drivers, each iovec contains a virtual start address and memory block length, representing the memory location of data read from or written to the disk. These iovecs can be discontinuous and can be larger than a page in length, representing the BIO's memory information.

[0036] DMA Mapping: For each iovec, the request resolution unit uses the VFIO_IOMMU_MAP_DMA mapping interface provided by the vfio-platform driver to map discontinuous virtual addresses in PS memory to contiguous virtual addresses (IOVA) in the device address space. After the mapping is completed, when a DMA operation accesses the IOVA, the IOMMU automatically locates the corresponding operating system memory address and performs the DMA operation.

[0037] Allocate programmable logic memory: According to the total length of the hard disk to be read and written, allocate enough programmable logic memory to accommodate the corresponding data as a read and write buffer. The hardware and software interaction unit uses the Buddy allocation algorithm to allocate programmable logic memory and manages an address allocation table in the form of a bitmap. This algorithm divides the entire physical memory into 4K byte blocks (one page) and can only allocate 2 at a time. n Page, maximum 2 can be allocated MAX _ ORDER-1 The software interaction unit maintains a linked list array with a length from 0 to MAX_ORDER-1, and the array item with index i points to a size of 2 i The physical address of the memory block of the page. When initialized, all the allocatable memory is in 2 MAX _ ORDER-1 The memory block is stored in the MAX_ORDER-1th item of the linked list array in the form of a byte array. If the array item for the memory length required by iovec does not exist, the next item in the array is checked to see if there is a memory block, until an entry k is found that contains a memory block. The memory block is then split into two equal pieces (these two pieces of memory are called siblings). One piece is further split, and the other piece is added to the k-1th table item until the memory block size is exactly the same as the required memory length (an additional split will result in less than the required memory). If the allocation cannot be made, the error status is directly reported to the upper-layer application.

[0038] Generate SQE: The request parsing unit packages the memory information contained in the BIO (including the IOVA and length of the on-chip processor memory after each iovec is mapped, the starting physical address and length of the allocated programmable logic memory) and disk information (such as read / write operation type, disk sector offset, number of sector blocks, etc.) into an SQE (Submission Queue Element) and hands it over to the request submission unit.

[0039] In this way, the request parsing unit not only parses the BIO request, but also completes the necessary DMA mapping and allocates the necessary programmable logic memory to prepare for subsequent read and write instructions.

[0040] The request submission unit is used to submit generated request queue elements to the request queue of the FPGA hardware module and notify the hardware module through the doorbell register, invoking the CDMA (Central Direct Memory Access) module to move data between the programmable logic memory and the on-chip processor memory. In the embodiment of the present application, the request submission unit completes the IO mapping from the on-chip processor system memory to the relevant registers of the FPGA hardware during initialization and clears this mapping relationship when the program exits.

[0041] The request submission unit mainly includes:

[0042] I / O Mapping Initialization: During thread initialization, the request submission unit uses the mmap system call to map I / O from on-chip processor memory to the relevant registers in the FPGA hardware's Submission Queue (SQ) and Completion Queue (CQ). This allows reads and writes to this memory block to be equivalent to reads and writes to the relevant registers in the FPGA hardware. Submitting the SQE: The request submission unit writes the SQE generated by the request parsing unit to the memory mapped to the registers during initialization, filling the SQ in the FPGA hardware device address space.

[0043] Queue control: The request submission unit uses semaphores to control the empty / full state of the SQ. When the current thread initializes, the semaphore corresponding to the SQ is set to the queue depth. Each time a request is issued, the SQ semaphore is downed. When the SQ is full, the semaphore blocks until the elements in the SQ are read by the FPGA hardware module. Only then can SQEs be written to the SQ.

[0044] Notify the hardware: After the SQE is written, the request submission unit uses the device identifier provided by VFIO to write the current SQ tail pointer position to the Tail Doorbell register corresponding to the SQ, notifying the hardware module that a new request has arrived.

[0045] In this way, the request submission unit ensures that the SQE can be efficiently submitted to the FPGA hardware module while avoiding problems such as queue overflow.

[0046] The interrupt control unit is used to poll interrupt signals, read completion queue elements from the completion queue CQ, obtain the completion status of read and write operations, and notify the upper-layer application. In an embodiment of the present application, the interrupt control unit detects interrupts through the interface provided by VFIO. After detecting the interrupt signal, the interrupt control unit disables interrupts, reads completion queue elements from the CQ until the completion queue is empty, then enables interrupts and notifies the upper-layer application of the completion status. After completing all operations on a completion queue element, the interrupt control unit releases the DMA mapping from the on-chip processor system memory to the programmable logic device address space of the request queue element corresponding to the completion queue element and releases the allocated PLDDR memory block.

[0047] The interrupt control unit mainly includes:

[0048] Interrupt polling: The interrupt control unit polls for interrupt signals through the interrupt interface provided by VFIO. First, it obtains the device identifier through VFIO. Using this device identifier, it registers an interrupt event descriptor using the VFIO_DEVICE_SET_IRQS interface. It then uses the read function to block on the descriptor until a success return is received, indicating an interrupt has occurred.

[0049] Reading the Completion Queue Element (CQE): During initialization, the Completion Queue (CQ) is set to the same depth as the SQ. When an interrupt arrives, the interrupt control unit first disables interrupts and reads the Completion Queue Element (CQE) from the mapped memory corresponding to the Completion Queue (CQ) in the FPGA hardware module until the CQ is empty. Then, the interrupt is enabled.

[0050] Notify the upper layer: Each time a CQE is read, the interrupt control unit notifies the upper layer application of its completion status and performs an up operation on the SQ semaphore so that new requests can enter the request queue.

[0051] Unmapping DMA: After completing all operations on a CQE, the driver needs to unmap the DMA mapping of the on-chip processor memory corresponding to the CQE. Read the IOVA corresponding to the on-chip processor memory from the CQE and call the VFIO_IOMMU_UNMAP_DMA interface to unmap the DMA.

[0052] Deallocate programmable logic memory: Based on the programmable logic memory block address contained in the CQE, calculate its entry k in the linked list array and add the memory block to entry k. If a sibling memory block exists in the entry, merge the two blocks and add the merged larger block to entry k+1 until no sibling memory exists.

[0053] Notify the hardware of completion: After the reading is completed, the interrupt control unit writes the current head pointer position of CQ to the Head Doorbell register corresponding to CQ, notifying the hardware module that the current read and write operation has been completed.

[0054] In this way, the interrupt control unit ensures that the completion status of read and write operations can be fed back to the upper-level application in a timely manner. At the same time, through the management of semaphores and DMA mapping, the efficient operation of the system is guaranteed.

[0055] like Figure 4 As shown, in an embodiment of the present application, the FPGA hardware module includes a software-hardware interaction unit and a command generation unit.

[0056] The hardware-software interaction unit is used to receive and parse request queue elements (SQEs) from the software driver module, connect to the NVMe host controller, and package the read and write results as completion queue elements (CQEs) and return them to the software driver module. In an embodiment of the present application, the hardware-software interaction unit manages the request queue (SQ) and completion queue (CQ) using a ring queue structure, setting the depth of the two queues to the same depth, and using doorbell registers to achieve synchronous communication with the software driver module.

[0057] The software and hardware interaction unit mainly includes:

[0058] Receive Request: The hardware-software interaction unit first waits for the SQ's Tail Doorbell register to be written by the software module. Based on the tail position written by the software module and the head position saved by the hardware, the number of SQEs in the SQ is calculated.

[0059] Parsing SQE: When an SQE exists in the SQ, the hardware and software interaction unit reads the SQE and analyzes the validity of the programmable logic memory address and length. If it is invalid, it is returned to the software driver module in the form of CQE. If it is valid, the SQE is handed over to the command generation unit through the FIFO (first-in-first-out queue).

[0060] Data transfer: When reading the solid-state drive, after receiving the result signal returned by the command generation unit, the hardware and software interaction unit calls the CDMA module to transfer the data that has been read out and cached in the programmable logic memory to the memory block pointed to by the PSDDR virtual address where the IOVA in the corresponding SQE is located. Among them, the source address is the physical address of the allocated programmable logic memory data, and the destination address is the IOVA mapped in the SQE. The CDMA module will transfer the IOVA as a physical address, and the SMMU will translate the IOVA into the corresponding PSDDR address according to the mapping table to ensure the correctness of the transfer location. When writing to the solid-state drive, after parsing the SQE, the hardware and software interaction unit calls the CDMA module to transfer the data pointed to by the IOVA contained in the SQE to the allocated programmable logic memory address block. Among them, the source address is the IOVA contained in the SQE, and the destination address is the allocated programmable logic memory physical address.

[0061] Receiving results: When the NVMe host controller completes the read and write operations, the command generation unit returns the result signal (including valid signal, read and write results, error code, etc.) to the software and hardware interaction unit.

[0062] Generate a CQE: The hardware-software interaction unit packages these result signals and the memory information contained in the corresponding SQE (including the IOVA and length of the on-chip processor memory and the physical address and length of the programmable logic memory) into a CQE. Based on the CQ HeadDoorbell register written by the software module and the CQ tail position saved by the hardware, the unit calculates the number of CQEs in the CQ. If the CQ is not full, the CQE is written to the CQ and an interrupt is generated to notify the software module.

[0063] In this way, the software-hardware interaction unit realizes efficient communication and data transfer between the software module and the hardware module, ensuring the correct processing of read and write requests and timely feedback of results.

[0064] The command generation unit is used to convert the information in the request queue element into a command format recognizable by the NVMe host controller and execute the read and write instructions of the solid-state drive through the NVMe host controller. In an embodiment of the present application, the command generation unit combines disk information such as read / write, disk address offset, read and write length information with memory information such as the starting physical address and length of the allocated programmable logical memory address block to generate a command that the NVMe host can parse.

[0065] The command generation unit mainly includes:

[0066] Reading SQE: The command generation unit reads the SQE from the FIFO and extracts key information, including the programmable logic memory address, read / write operation type, disk address offset, read / write length, etc. It then determines whether the allocated programmable logic memory address and block number are valid. If not, it submits information such as an error code to the software interaction unit.

[0067] Generate command: The command generation unit combines this information into a command data and puts it into the FIFO connected to the NVMe host controller. The NVMe host controller is a host-side IP core that organizes this information and generates NVMe commands.

[0068] Executing read and write operations: The command generation unit controls the NVMe host controller to read data from the SSD to the programmable logic memory, or write data from the programmable logic memory to the SSD according to read and write instructions. The programmable logic memory serves as the NVMe host controller's read and write buffer, temporarily storing data to be read or written.

[0069] Return result: After the read and write operation is completed, the command generation unit returns the result signal (including valid signal, read and write results, error code, etc.) directly to the software and hardware interaction unit.

[0070] In this way, the command generation unit ensures the correct connection between the hardware and software interaction unit and the NVMe host controller, thereby achieving effective operation of the solid-state drive.

[0071] The MPSoC-based user-mode solid-state storage system of the present invention significantly improves the read and write efficiency of solid-state drives and system security through innovative user-mode driver design and hardware acceleration technology. By implementing drivers in user mode, the complexity and inefficiency of kernel-mode programming are avoided. Furthermore, efficient virtual address translation using the SMMU improves system flexibility and performance. The system of the present invention is suitable for a variety of high-performance computing and storage scenarios and has broad application prospects.

[0072] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solutions obtained by equivalent replacement or equivalent transformation fall within the scope of protection of the present invention.

Claims

1. A user-mode solid-state storage system based on MPSoC, applied to the Zynq UltraScale+ platform, wherein the platform integrates an on-chip processor system and programmable logic, and the on-chip processor system and programmable logic communicate via an AXI bus; characterized in that: The user-mode solid-state storage system based on MPSoC includes: A software driver module is provided in the user state of the on-chip processor system, and uses VFIO technology to implement reading and writing to the solid-state drive. The software driver module performs DMA mapping of the user state memory through the SMMU and uses IOVA for DMA access; The FPGA hardware module is provided in the programmable logic part, and is used to receive and parse the request queue elements from the software driver module, generate read and write commands that can be parsed by the NVMe host controller, execute data transmission, and return the read and write results to the software driver module.

2. The user-mode solid-state storage system based on MPSoC according to claim 1, characterized in that: The software driver module includes a request parsing unit, a request submission unit and an interrupt control unit. The request parsing unit is used to receive and parse the bio data structure sent by the upper layer interface, extract memory information and disk information, perform necessary address mapping, allocate programmable logic memory, and generate request queue elements; The request submission unit is used to submit the generated request queue elements to the request queue that interacts with the FPGA hardware module, notify the hardware module through the Doorbell register, and call the CDMA module to move data between the programmable logic memory and the on-chip processor memory; the interrupt control unit is used to poll the interrupt signal, read the completion queue elements from the completion queue, obtain the completion status of the read and write instructions, and notify the upper-layer application.

3. The user-mode solid-state storage system based on MPSoC according to claim 2, characterized in that: The request parsing unit maps the on-chip processor system memory virtual address with the device virtual address of the device address space through the VFIO_IOMMU_MAP_DMA mapping interface, allocates the programmable logic memory as a read and write buffer, and generates a request queue element containing the mapping address.

4. The user-mode solid-state storage system based on MPSoC according to claim 2, characterized in that: The request submission unit completes IO mapping from the on-chip processor system memory to the relevant register addresses of the FPGA hardware request queue and completion queue through the mmap interface during initialization, so as to control the reading and writing of these two queues at runtime.

5. The user-mode solid-state storage system based on MPSoC according to claim 2, characterized in that: The interrupt control unit detects interrupts through the interface provided by VFIO. After detecting the interrupt signal, it disables the interrupt, reads the completion queue elements from the completion queue until the completion queue is empty, then enables the interrupt, notifies the upper-layer application of the completion status, and releases the allocated programmable logic memory and DMA mapping.

6. The user-mode solid-state storage system based on MPSoC according to claim 1, characterized in that: The FPGA hardware module includes a hardware-software interaction unit and a command generation unit. The hardware-software interaction unit is used to receive and parse request queue elements from the software driver module, connect to the NVMe host controller, and package the read and write results as completion queue elements and return them to the software driver module; the command generation unit is used to convert the information in the request queue elements into a command format recognizable by the NVMe host controller and execute the read and write tasks of the solid-state drive through the NVMe host controller.

7. The user-mode solid-state storage system based on MPSoC according to claim 6, characterized in that: The hardware-software interaction unit manages the request queue and the completion queue through a ring queue structure, and uses the doorbell register to achieve synchronous communication with the software driver module. The hardware-software interaction unit is also responsible for calling the CDMA module to perform data transmission between the on-chip processor memory and the programmable logic memory.

8. The user-mode solid-state storage system based on MPSoC according to claim 6, characterized in that: The command generation unit combines the physical address of the programmable logic memory in the request queue element with the read / write flag, the address offset of the disk, and the read / write length information to generate a read / write command for the NVMe host controller.

9. The user-mode solid-state storage system based on MPSoC according to claim 1, characterized in that: After completing all operations on a completion queue element and notifying the upper layer application, the software driver module releases the DMA mapping of the device address from the on-chip processor system memory to the programmable logic memory contained in the request queue element corresponding to the completion queue element.

10. The user-mode solid-state storage system based on MPSoC according to claim 1, characterized in that: After submitting the request, the software driver module writes the request queue tail pointer to the request queue's Tail Doorbell register using the device identifier provided by VFIO, notifying the hardware module that a new request needs to be processed. After finishing reading the elements in the completion queue, the completion queue head pointer is written to the completion queue's Head Doorbell register using the same method, notifying the hardware that the completion queue element has been processed.

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